Dual-path server system and timing control method for dual-path server system

Abstract

The application provides a dual-path server system and a timing control method for the dual-path server system, and relates to the technical field of servers. The system comprises two mainboards with the same hardware configuration, each of which comprises a CPU, a CPLD and an analog switch; the mainboards are interconnected through a connector to form a synchronization signal line and a response signal line, the synchronization signal line is connected to the timing pin of each CPU; the output end of each CPLD is connected to the synchronization signal line through the corresponding analog switch, the response signal line is connected to the open-drain output pin of each CPLD and is connected to the power supply through a pull-up resistor; the CPLD of the first mainboard controls the conduction of the analog switch thereof according to the node identification of the first mainboard to drive the synchronization signal line; the CPLD of the second mainboard controls the non-conduction of the analog switch thereof according to the node identification of the second mainboard; and the CPLD of the first mainboard synchronously sends a timing effective signal to each CPU through the synchronization signal line when the response signal line is monitored to be at a high level, so that the hardware configuration flexibility and the timing synchronization reliability are taken into account.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a dual-socket server system and a timing control method for a dual-socket server system. Background Technology

[0002] A dual-socket server system refers to a server system configured with two Central Processing Units (CPUs) working together to improve computing performance and data processing capabilities. It is widely used in cloud computing, big data analytics, and high-performance computing. As data centers increasingly demand flexibility and cost control in server configuration, how to achieve on-demand configuration of single-socket and dual-socket servers at a lower cost and with greater flexibility has become a key technical challenge in this field.

[0003] In related technologies, conventional dual-socket server systems typically employ specially designed dual-socket motherboards, with two CPUs integrated on the same board. Timing control relies on a Complex Programmable Logic Device (CPLD) and dedicated timing signal lines on the motherboard. For example, synchronization signals sent to the CPUs are coordinated and synchronized via the CPLD to ensure strict consistency in the startup and shutdown timings of the two CPUs. However, this approach lacks hardware configuration flexibility. Some solutions attempt to interconnect two single-socket motherboards to form a dual-socket system, but these suffer from difficulties in timing synchronization and require differentiated hardware bills of materials. In summary, existing solutions struggle to balance hardware configuration flexibility with reliable timing synchronization. Summary of the Invention

[0004] This application provides a dual-processor server system and a timing control method for the dual-processor server system, in order to improve the problem that the solutions in related technologies are difficult to balance hardware configuration flexibility and timing synchronization reliability.

[0005] In a first aspect, this application provides a dual-processor server system, including a first motherboard and a second motherboard with identical hardware configurations; both the first motherboard and the second motherboard include a CPU, a CPLD, and an analog switch; the first motherboard and the second motherboard are interconnected by a connector to connect a synchronization signal line and an acknowledge signal line, the synchronization signal line being connected to the timing pins of the two CPUs; the output terminals of the two CPLDs are connected to the synchronization signal line via corresponding analog switches; the acknowledge signal line is connected to the open-drain output pins of the two CPLDs and is connected to the power supply via pull-up resistors;

[0006] The CPLD of the first motherboard is used to determine the control role based on the first node identifier and control the analog switch of the first motherboard to turn on to drive the synchronization signal line.

[0007] The CPLD of the second motherboard is used to determine the non-control role based on the second node identifier and control the analog switch of the second motherboard to turn off.

[0008] The CPLD on the first motherboard is also used to monitor the level of the response signal line. When the level is high, it sends a timing valid signal to the two CPUs through the synchronization signal line to achieve timing synchronization of the dual-processor server system.

[0009] In one possible embodiment, the connector is a Slimsas connector.

[0010] In one possible embodiment, the synchronization signal lines include an S0 power-ready signal line, a processor power-good signal line, and a processor reset signal line.

[0011] In one possible embodiment, the response signal lines include an S0 power-ready response signal line, a processor power-on response signal line, and a processor reset response signal line.

[0012] In one possible embodiment, the first node identifier is set by the level of a first hardware configuration pin on the first motherboard, and the second node identifier is set by the level of a second hardware configuration pin on the second motherboard; the first hardware configuration pin and the second hardware configuration pin are set to different levels.

[0013] In one possible embodiment, when the second motherboard is not in place, the response signal line is held high by a pull-up resistor, and the CPLD of the first motherboard independently performs timing control.

[0014] Secondly, this application provides a timing control method for a dual-socket server system, applied to a CPLD in the first motherboard of the aforementioned dual-socket server system; the timing control method includes:

[0015] Read the first node identifier on the first motherboard to determine that the first motherboard is the control role;

[0016] According to the control role, control the analog switch of the first motherboard to be turned on so that the synchronization signal line is driven by the CPLD of the first motherboard;

[0017] Monitor the level status of the response signal line;

[0018] When a low level is detected, continue to wait until the level changes to a high level;

[0019] When a high level is detected, a timing valid signal is sent synchronously to the CPU of the first motherboard and the CPU of the second motherboard via the synchronization signal line.

[0020] In one possible embodiment, reading the first node identifier on the first motherboard includes:

[0021] Read the voltage level of the first hardware configuration pin on the first motherboard, and determine the first node identifier based on the voltage level.

[0022] In one possible embodiment, the timing control method further includes: when the second motherboard is not in place, the level state is maintained at a high level by the pull-up resistor in the first motherboard, and the CPLD of the first motherboard independently completes the timing control.

[0023] Thirdly, this application provides a timing control device for a dual-socket server system, comprising a CPLD disposed in the first motherboard of the dual-socket server system; the timing control device includes:

[0024] The role determination module is used to read the first node identifier on the first motherboard and determine that the first motherboard is the control role.

[0025] The switch control module is used to control the analog switch of the first motherboard to be turned on according to the control role, so that the synchronization signal line is driven by the CPLD of the first motherboard;

[0026] The monitoring module is used to monitor the voltage level of the response signal line;

[0027] The processing module is used to wait until the level changes to a high level when a low level is detected; when a high level is detected, it sends a timing valid signal to the CPU of the first motherboard and the CPU of the second motherboard through the synchronization signal line.

[0028] This application provides a dual-processor server system and a timing control method for the dual-processor server system. The dual-processor server system includes a first motherboard and a second motherboard with identical hardware configurations. Both the first and second motherboards include a CPU, a CPLD, and analog switches. The first and second motherboards are interconnected via connectors to connect synchronization signal lines and response signal lines. The synchronization signal lines are connected to the timing pins of the two CPUs. The outputs of the two CPLDs are connected to the synchronization signal lines via corresponding analog switches. The response signal lines are connected to the open-drain output pins of the two CPLDs and are connected to the power supply via pull-up resistors. The CPLD of the first motherboard is used to determine a control role based on a first node identifier and control the analog switches of the first motherboard to turn on to drive the synchronization signal lines. The CPLD of the second motherboard is used to determine a non-control role based on a second node identifier and control the analog switches of the second motherboard to turn off. The CPLD of the first motherboard is also used to monitor the level state of the response signal lines. When the level state is high, it sends a timing valid signal to the two CPUs synchronously via the synchronization signal lines to achieve timing synchronization of the dual-processor server system.

[0029] This application establishes a first motherboard and a second motherboard with identical hardware configurations. The CPLD on the first motherboard controls its analog switch to drive the synchronization signal line based on a first node identifier, while the CPLD on the second motherboard controls its analog switch to turn off based on a second node identifier to avoid signal conflicts. Simultaneously, an acknowledgment signal line is connected to the open-drain output pins of both CPLDs and connected to the power supply via pull-up resistors. This ensures that the acknowledgment signal line is pulled high only when both motherboards are ready. The CPLD on the first motherboard monitors the level of this acknowledgment signal line, and when a high level is detected, it sends a timing valid signal to both CPUs via the synchronization signal line, thereby ensuring complete timing synchronization between the two CPUs. Furthermore, since the first and second motherboards have identical hardware configurations, there is no need to develop different motherboards for single-socket and dual-socket configurations. This allows the two identical motherboards to be used independently as a single-socket server or interconnected to form a dual-socket server system, thus balancing hardware configuration flexibility and timing synchronization reliability, while also reducing production costs and inventory management complexity. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0031] Figure 1 A schematic diagram of a dual-socket server system provided as an exemplary embodiment of this application;

[0032] Figure 2 A flowchart illustrating a timing control method for a dual-socket server system provided as an exemplary embodiment of this application;

[0033] Figure 3 A schematic diagram of a timing control device for a dual-path server system provided as an exemplary embodiment of this application.

[0034] In the diagram, 10—Dual-processor server system; 11—First motherboard; 111—CPU of the first motherboard; 112—CPLD of the first motherboard; 113—Analog switch of the first motherboard; 12—Second motherboard; 121—CPU of the second motherboard; 122—CPLD of the second motherboard; 123—Analog switch of the second motherboard; 13—Connector; 14—Synchronization signal line; 15—Response signal line; 30—Timing control device for dual-processor server system; 31—Role determination module; 32—Switch control module; 33—Monitoring module; 34—Processing module.

[0035] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0037] The terms “first,” “second,” etc., used in some aspects of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or apparatus.

[0038] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0039] In related technologies, conventional dual-socket server systems typically employ specially designed dual-socket motherboards. With this design, single-socket and dual-socket server systems must use different motherboard hardware. Upgrading from a single-socket to a dual-socket configuration requires replacing the entire motherboard, resulting in poor system adjustability and configurability, and high hardware costs. Some existing technologies attempt to construct a dual-socket server system by interconnecting two single-socket motherboards. Each single-socket motherboard controls its own CPU timing, and the two motherboards are interconnected via connectors. However, since the CPLDs of the two motherboards independently control their own timing, it is difficult to achieve complete synchronization of critical timing signals, easily leading to timing irregularities. Even if timing synchronization is achieved through software or firmware, the hardware bills of materials for the two motherboards often need to be differentiated (e.g., using different resistor configurations to distinguish master and slave roles), making it impossible to achieve completely identical hardware configurations and increasing the complexity of production management and maintenance.

[0040] In view of this, how to achieve reliable synchronous control of critical timing signals in a dual-socket server system while maintaining identical hardware configurations on both motherboards has become an urgent technical problem to be solved. To address this problem, a dual-socket server system is provided. This system includes a first motherboard and a second motherboard with identical hardware configurations. Both motherboards contain a CPU, a CPLD, and analog switches. They are interconnected via connectors, with synchronization signal lines and acknowledge signal lines. The synchronization signal lines are connected to the timing pins of the two CPUs, and the acknowledge signal lines are connected to the open-drain output pins of the two CPLDs and connected to the power supply via pull-up resistors. In this approach, the CPLD of the first motherboard is identified as having a control role based on a first node identifier and controls the analog switches of the first motherboard to turn on, thereby driving the synchronization signal lines. The CPLD of the second motherboard is identified as having a non-control role based on a second node identifier and controls the analog switches of the second motherboard to turn off, thus preventing both from driving the synchronization signal lines simultaneously. Simultaneously, the CPLD, acting as the control role, monitors the level of the acknowledge signal lines. When the level is high, it sends a timing valid signal to both CPUs synchronously via the synchronization signal lines, thereby achieving timing synchronization of the dual-socket server system. This system architecture, based on node identification, analog switch conduction control, and response signal feedback, enables the establishment of a stable dual-path timing coordination mechanism on a unified hardware platform. This effectively addresses the problem that existing solutions struggle to balance hardware configuration flexibility with timing synchronization reliability.

[0041] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of a dual-processor server system provided as an exemplary embodiment of this application. Figure 1 As shown, the dual-socket server system 10 includes a first motherboard 11 and a second motherboard 12 with identical hardware configurations. The first motherboard 11 includes a CPU 111, a CPLD 112, and an analog switch 113. The second motherboard 12 includes a CPU 121, a CPLD 122, and an analog switch 123. The first motherboard 11 and the second motherboard 12 are interconnected via a connector 13, with a synchronization signal line 14 and an acknowledge signal line 15. The synchronization signal line 14 is connected to the timing pins of the two CPUs. The outputs of the two CPLDs are connected to the synchronization signal line 14 via corresponding analog switches. The acknowledge signal line 15 is connected to the open-drain output pins of the two CPLDs and is connected to the power supply via pull-up resistors.

[0043] The CPLD112 of the first motherboard is used to determine the control role based on the first node identifier and control the analog switch 113 of the first motherboard to be turned on to drive the synchronization signal line 14.

[0044] The CPLD122 on the second motherboard is used to determine the non-control role based on the second node identifier and control the analog switch 123 on the second motherboard to turn off.

[0045] The CPLD112 on the first motherboard is also used to monitor the level of the response signal line 15. When the level is high, it sends a timing valid signal to the two CPUs through the synchronization signal line 14 to achieve timing synchronization of the dual-socket server system 10.

[0046] The first motherboard 11 is a hardware node carrier constituting the dual-processor server system 10. It integrates a CPU 111, a CPLD 112, and an analog switch 113, and is used to carry out timing control and signal interconnection functions related to a single-side processor. The function of the first motherboard 11 is to form a unified dual-node computing platform together with the second motherboard 12, enabling the system to complete the collaborative startup and operation of the two processors while maintaining consistent hardware configuration. Structurally, the first motherboard 11 is typically mounted on the motherboard tray of a server chassis or computing platform, and establishes an electrical connection with the second motherboard 12 through connectors 13, such as board-side connectors, backplane interfaces, or board-to-board connectors. Its communication with other components is mainly achieved through signal lines, ground lines, and power supply networks. In terms of form and material, the first motherboard 11 can be implemented as a multilayer printed circuit board (PCB). Circuit Board (PCB) is a board-like structure. The material can be FR-4 epoxy fiberglass copper-clad board, low-loss high-frequency board, or multi-layer composite substrate to adapt to different signal integrity and heat dissipation requirements. In terms of size and proportion, the external dimensions of the first motherboard 11 can be designed to be the same or approximately the same as those of the second motherboard 12. The connector positions, mounting holes, and signal trace lengths are usually set in a symmetrical or mirrored layout to ensure that the electrical characteristics between the two nodes are consistent.

[0047] The second motherboard 12 refers to another node carrier with the same hardware configuration as the first motherboard 11. It also integrates a CPU 121, CPLD 122 and analog switch 123, and is used to work with the first motherboard 11 to complete processor timing synchronization in the dual-processor server system 10. Its function is to participate in system synchronization control as a non-control side or backup side, so as to maintain the consistency of system structure in the scenario of control role switching or node collaboration. In terms of physical location, the second motherboard 12 can be installed in the same chassis as the first motherboard 11 in parallel, or form a fixed interconnection relationship with the first motherboard 11 through the adapter structure and connecting cable. Its interfaces are set to correspond to those of the first motherboard 11 so that the synchronization signal line 14 and the response signal line 15 can be connected at the connector 13.

[0048] The CPU 111 on the first motherboard and the CPU 121 on the second motherboard refer to the processor execution units located on the first motherboard 11 and the second motherboard 12, respectively. They are used to receive timing valid signals from the synchronization signal line 14 and complete processes such as power-on, initialization, reset release, and entering the working state based on these signals. Their function is to serve as the computing core of the dual-socket server system 10, receiving board-level timing control results and entering the executable state. In terms of location and relationship, each CPU is typically soldered or inserted into the central area of ​​the motherboard and connected to the synchronization signal line through timing pins, reset pins, power-good pins, or processor start control pins. They also work in conjunction with the power supply module, memory, and peripheral controllers on the board. In terms of form and material, each CPU can be a Land Grid Array (LGA) processor or a Ball Grid Array (BGA) processor. A CPU (BGA) is a type of processor or socket-type processor module. Its packaging substrate can be made of organic packaging substrate, ceramic substrate or composite heat dissipation substrate. In terms of size and proportion, the package size of each CPU is usually matched with the processor socket or pad area on the motherboard. The number and function definition of its timing pins should meet the synchronization, ready and reset coordination required for dual-channel control.

[0049] CPLD112 on the first motherboard and CPLD122 on the second motherboard refer to the logic control units located on the first motherboard 11 and the second motherboard 12, respectively. They are used to determine roles based on node identifiers and to perform logic control and status monitoring on the corresponding analog switches and response signal lines 15. Their function is to implement timing management, signal gating, and node collaborative control at the motherboard level to avoid conflicts caused by two nodes simultaneously driving the same synchronization signal path. In terms of location and relationship, each CPLD is typically positioned near connector 13 or the signal convergence area to shorten the signal path and reduce propagation delay. Its input terminals can receive node identifiers, board-level status, power monitoring signals, or status quantities from other control circuits, while its output terminals connect to the corresponding analog switch control terminals and response signal monitoring terminals. In terms of form and material, each CPLD can be a Quad Flat Package (QFP), BGA, or Thin Quad Flat Package. CPLD (TQFP) devices use programmable logic arrays and state machine structures inside the chip to implement customized control logic. In terms of size and proportion, the package size of the CPLD should be adapted to the motherboard layout space, and its input and output pin configuration usually corresponds to the synchronous control requirements to reduce external adapters and additional wiring.

[0050] The analog switch 113 on the first motherboard and the analog switch 123 on the second motherboard are respectively controlled signal switching devices installed on each motherboard. Their output terminals are connected to the synchronization signal line 14 via corresponding connection paths, and are used to selectively turn on or off the signal path under the control of the CPLD. Their function is to ensure that only the motherboard designated as the control unit drives the synchronization signal line 14, thereby avoiding level interference, bus contention, or drive conflicts caused by simultaneous output from both sides. In terms of position and relationship, each analog switch is generally located between the CPLD and the connector 13. The input terminal receives timing drive signals from the CPLD or related control circuits, and the output terminal is connected to the synchronization signal line 14. In the off state, this side presents a high impedance to the synchronization signal line 14. In terms of shape and material, each analog switch can be a complementary metal-oxide-semiconductor (CMOS) device. Oxide Semiconductor (CMOS) analog switch chips, solid-state relay switches, or integrated multiplexed switches typically use MOS switching transistors or equivalent on / off units inside the device to achieve low crosstalk switching. In terms of size and proportion, the number of channels of each analog switch is matched with the number of synchronization signal lines, and its on-resistance should be as small as possible relative to the signal path impedance to maintain timing edge integrity and reduce voltage drop.

[0051] Connector 13 is an interface component used to achieve electrical interconnection between the first motherboard 11 and the second motherboard 12. It is used to connect the synchronization signal line 14 and the acknowledgment signal line 15 across the boards, so that the two motherboards can still form a unified timing control link when physically separated. Its function is to provide a stable and removable interconnection channel, which facilitates motherboard assembly, maintenance and replacement, and system expansion. In terms of location and relationship, connector 13 is usually arranged on the adjacent edges, mating edges, or backplane interconnection areas of the two motherboards, and precisely matches with the corresponding sockets, pads, or pin headers on the two motherboards to ensure reliable connection of the synchronization signal line, acknowledgment signal line, and necessary reference ground line. In terms of form and material, connector 13 can be a board-to-board connector, a wire-to-board connector, or a high-speed differential interconnection connector. Its housing can be made of engineering plastic or high-temperature heat-resistant plastic, and the contacts can be made of gold-plated copper alloy. In terms of size and proportion, the pin pitch, terminal length, and mating height of connector 13 need to be coordinated with the thickness of the motherboard and the layout of the components, and meet the integrity requirements of the transmitted control signals.

[0052] Synchronization signal line 14 refers to a shared control line connected to the timing pins of two CPUs. It is used to transmit timing valid signals to both CPUs simultaneously under the drive of the control motherboard, thereby coordinating the two processors to enter the target working state at the same or controlled time. Its function is to serve as a key timing channel of the dual-socket server system 10, directly linking the board-level control logic with the processor startup logic. In terms of location and relationship, synchronization signal line 14 can be connected by connector 13 to the corresponding lines on the two motherboards and extend to the timing pins of their respective CPUs, while also connecting to the analog switch output to form a controlled transmission path. In terms of form and material, synchronization signal line 14 can be a PCB trace, a conductor in a flexible ribbon cable, or a single signal line in a shielded cable. Its copper foil layer, insulation layer, and impedance design can be configured according to the signal speed and the distance between boards. In terms of size and proportion, the line width, line spacing, and length of synchronization signal line 14 are usually matched with the edge speed it carries, and the two paths should be kept as symmetrical as possible to reduce phase difference and propagation delay differences.

[0053] The response signal line 15 is a status feedback line connected to the open-drain output pins of two CPLDs. It is used to form a monitorable logic level under the action of pull-up resistors and to feed back the preparation status of the subordinate node or common link to the control role's motherboard. Its function is to provide the control role with a judgment basis, so that the control role can output a timing valid signal only after confirming that the bus or peer status meets the conditions. In terms of position and relationship, the response signal line 15 is connected across the two motherboards through connector 13 and is connected to the open-drain output terminal of each CPLD. Multiple open-drain output terminals can share the same feedback network electrically. The pull-up resistor is connected to the power supply to provide a default high-level state. In terms of form and material, the response signal line can be composed of in-board traces, wire harnesses, or flexible interconnect conductors. The pull-up resistor can be a surface-mount resistor, an array resistor, or an integrated pull-up network. In terms of size and proportion, the wiring length of the response signal line 15 should be as short as possible and avoid areas with strong interference. The pull-up resistor value can be selected according to the power supply voltage, open-drain drive capability, and required rise speed to balance anti-interference capability and response speed.

[0054] Additionally, the first node identifier refers to logical flag information used to distinguish the role attributes of the first motherboard. It can be provided to the CPLD112 of the first motherboard during power-on initialization via hardware jumpers, resistor encoding, DIP switches, memory configuration bits, or firmware preset parameters. Its function is to enable the CPLD112 of the first motherboard to determine the control status of this node in the dual-path system, thereby deciding whether to turn on the analog switch 113 of the first motherboard on this side and participate in the synchronization signal drive. The second node identifier refers to logical flag information used to distinguish the role attributes of the second motherboard. It can correspond to the first node identifier and is used to enable the CPLD122 of the second motherboard to determine that it has a non-control role and to shut down the second motherboard. The analog switch 123 serves to provide a clear role division basis for dual-motherboard collaboration, preventing the two nodes from competing for the synchronous signal driving right at the source. In terms of position and relationship, the second node identifier can also be placed in the configuration area of ​​the second motherboard 12 and connected to the identification input terminal of the CPLD 122 of the second motherboard so as to complete the role determination when the system is powered on. In terms of form and material, the first node identifier and the second node identifier can be represented as solder pad jumpers, pluggable jumper caps, resistance value encoding networks or logic configuration storage units. In terms of size and proportion, the placement area of ​​the first node identifier and the second node identifier is usually small, only needing to meet the requirement that the CPLD can stably read within the startup window. Open-drain output pins refer to the electrical interfaces used by CPLDs to output response signals. When turned on, they pull the response signal line low, and when turned off, pull-up resistors restore the line to high. Their function is to enable wired-AND functionality for multiple nodes to share signals, allowing multiple CPLDs to participate in status feedback without push-pull conflicts. In terms of location and relationship, this pin is directly located on the external port of the CPLD and connected to the common feedback network via a connector and the response signal line. In terms of form and material, it corresponds to the metal pins, solder balls, or pads on the CPLD package, and the material is usually tin-plated copper alloy or gold-plated copper alloy. In terms of size and proportion, the number of open-drain output pins corresponds to the feedback signal function, and the electrical characteristics of the pins should meet the requirements of low power consumption and high-reliability switching.A pull-up resistor is a biasing element connected between the response signal line 15 and the power supply. It is used to maintain the response signal line at a high level when all open-drain outputs are in the released state, thereby forming a determinable default feedback state. Its function is to provide a stable level reference for the control role, enabling the CPLD to identify the link readiness status by detecting changes in high and low levels. In terms of location and relationship, the pull-up resistor can be set in the common feedback area near the first motherboard 11, the second motherboard 12, or the connector 13, and form a fixed connection with the response signal line 15 and the power network. In terms of form and material, the pull-up resistor can be a surface mount resistor, an array resistor, or an integrated bias network, and the resistive material can be a thick film, thin film, or metal oxide film structure. In terms of size and proportion, its resistance value should be selected according to the load of the response signal line, the power supply voltage, and the required switching speed to ensure reliable high-level establishment without excessively increasing static power consumption.

[0055] Based on the above analysis, it can be seen that in the dual-path server system 10 provided in this application embodiment, when the system starts up, the first motherboard 11 and the second motherboard 12 first read the node identifier in their respective CPLDs and then complete the role determination. The CPLD 112 of the first motherboard determines itself as the control role according to the first node identifier and puts the analog switch 113 of the first motherboard on the conducting state, so that its output path establishes a controlled connection with the synchronization signal line 14. The CPLD 122 of the second motherboard determines itself as the non-control role according to the second node identifier and keeps the analog switch 123 of the second motherboard on the conducting state, so that the second motherboard presents a high impedance state to the synchronization signal line 14. Subsequently, the two CPLDs coordinate their states with the response signal line 15 via open-drain output pins. Under the action of pull-up resistors, the response signal line 15 is at a high level by default. The CPLD 112 of the control motherboard (i.e., the first motherboard) detects that the system has entered a ready state for synchronous control and then simultaneously outputs a timing valid signal to both CPUs via the synchronization signal line 14. This allows both CPUs to receive key signals such as power-on permission, readiness confirmation, or reset release at the same electrical moment, thus entering the working state according to the predetermined timing. Since the synchronization signal line 14 is driven only by the conducting side of the analog switch 113 of the control motherboard (i.e., the first motherboard), and the other side is always in an isolated state, level contention, drive conflicts, or signal distortion caused by two motherboards simultaneously driving the same line can be avoided. Furthermore, since the response signal line 15 uses open-drain output and forms a shared feedback network through pull-up resistors, the control system can directly determine whether the common link meets the synchronization conditions without introducing additional complex handshake circuits, thereby improving the determinism and timing consistency of system startup. Therefore, while keeping the hardware configuration of the two motherboards the same, this embodiment establishes a unified timing coordination mechanism suitable for dual-processor server systems by dividing control relationships through node identification, selecting signal paths through analog switches, and implementing status feedback through open-drain response and pull-up bias. This not only helps to reduce the degree of difference in motherboard design and reduce spare parts and verification costs, but also improves the synchronization stability and overall operational reliability during the dual-processor startup process.

[0056] The dual-socket server system provided in this application embodiment uses a first motherboard and a second motherboard with identical hardware configurations. The CPLD of the first motherboard controls its analog switch to turn on based on a first node identifier to drive the synchronization signal line, while the CPLD of the second motherboard controls its analog switch to turn off based on a second node identifier to avoid signal conflicts. Simultaneously, the response signal line is connected to the open-drain output pins of both CPLDs and connected to the power supply via pull-up resistors. This ensures that the response signal line is pulled high only when both motherboards are ready. The CPLD of the first motherboard monitors the level of this response signal line, and when a high level is detected, it sends a timing valid signal to both CPUs through the synchronization signal line, thereby ensuring complete timing synchronization between the two CPUs. Furthermore, since the first and second motherboards have identical hardware configurations, there is no need to develop different motherboards for single-socket and dual-socket configurations. This allows the two identical motherboards to be used independently as a single-socket server or interconnected to form a dual-socket server system, thus balancing hardware configuration flexibility and timing synchronization reliability, while also reducing production costs and inventory management complexity.

[0057] In some embodiments, the connector is a Slimsas connector.

[0058] Slimsas connectors are high-speed, miniaturized interconnects between motherboards or circuit boards. Their function is to provide a stable physical transmission channel for synchronization and acknowledgment signal lines, enabling reliable coupling and transmission of timing control information between the first and second motherboards. The connector is installed in the corresponding interface areas of the first and second motherboards, electrically connecting them via a plug-in connection and interconnecting the synchronization and acknowledgment signal lines across boards. During system operation, its interface pins serve as power references, ground references, and signal path fixation, ensuring signal integrity and assembly consistency. In terms of form and material, Slimsas connectors are typically available as through-hole board-side connectors, horizontal surface-mount connectors, or pluggable connectors with locking mechanisms. The housing material can be high-temperature thermoplastic engineering plastics, liquid crystal polymers (LCP), or heat-resistant nylon. Conductive terminals can be phosphor bronze, beryllium copper, or gold-plated copper alloys to improve conductivity reliability and mating resistance. In terms of size and proportions, this connector generally features a small terminal pitch and high integration density. Its width and height must be adapted to the edge space of the server motherboard. The number of pins matches the number of synchronization signal lines, acknowledgment signal lines, and necessary reference ground lines. The mating depth meets standardized mechanical fit requirements with the board thickness. In terms of operation, the Slimsas connector itself does not perform active movement, but mechanical mating actions occur during assembly, mating, and removal; it maintains a static connection state during operation. As for alternatives, the connector can be replaced with MiniSAS, board-to-board high-speed connectors, flexible printed circuit boards (FPCs), flexible flat cables (FFCs), or other interconnect devices that meet signal rate and mechanical reliability requirements. It should be understood that the above examples are for illustrative purposes only and are not limiting.

[0059] In one possible embodiment, the Slimsas connector can be understood as a high-density differential or single-ended signal interconnect interface, primarily used to carry synchronization control signals and response feedback signals required for cross-motherboard transmission, while also meeting the requirements of assembly compactness, maintainability, and connection reliability in server platforms. This connector is typically located in the edge region or predetermined mating area of ​​the first and second motherboards, and is fixed to the motherboards by soldering, reflow soldering, or edge clipping, and electrically connected to the trace pads on the motherboards, thereby leading the synchronization signal lines and response signal lines to the cross-board connection path. Since dual-socket server systems typically require the two motherboards to maintain a stable relative position after mechanical assembly, the connector can also be structurally integrated with guide grooves, positioning posts, or locking structures to reduce mating misalignment and prevent poor contact under conditions of vibration, thermal expansion and contraction, or prolonged insertion and removal. Its conductive terminals can use spring-loaded contacts or pin-type contacts, and the surface can be plated with gold, nickel, or multi-layer composite plating to reduce contact resistance and improve oxidation resistance. Its shell can be made of high-temperature resistant, flame-retardant, and dimensionally stable engineering plastics, such as LCP, polybutylene terephthalate (PBT), or high-temperature nylon, to withstand the high ambient temperatures and long-term thermal cycling conditions during server operation. In terms of shape, Slimsas connectors can be rectangular strips, low-profile horizontal structures, or vertical structures. The width of the mating port is usually coordinated with the arrangement space at the edge of the motherboard. The pin pitch can be set to a small spacing to simultaneously arrange synchronization signal lines, acknowledgment signal lines, and reference ground lines within a limited area. Shielding pins can also be reserved if necessary to suppress crosstalk. Its length and number of pins can be configured according to the number of signal channels, generally meeting the requirements for short-distance, high-reliability connections between server motherboards. The mating depth should be matched with the motherboard thickness and connector locking travel to ensure that the contact pressure after mating is within a reasonable range.

[0060] During operation, once the first and second motherboards complete mechanical alignment and establish an electrical connection via the Slimsas connector, a stable cross-board channel is formed between them using the synchronization and response signal lines. The CPLD of the first motherboard can output and transmit timing control information through this channel, while the CPLD of the second motherboard can provide feedback on its response status or receive synchronization constraints through the connector. Because the Slimsas connector offers high contact reliability and a short signal path, it maintains signal integrity with low insertion loss and low reflection, making synchronization timing and response feedback more suitable for scenarios such as server startup, reset, and role coordination. Based on this connection, when the system starts up, cross-board timing information can be stably transmitted via this connector, reducing timing jitter caused by unstable connector contact, signal crosstalk, or line misalignment, and making it easier to maintain consistent control relationships between the two motherboards.

[0061] In this embodiment of the application, by using Slimsas connectors, not only can miniaturized, high-density and high-reliability interconnection between motherboards be achieved, but also the stability and assembly consistency of dual-channel timing synchronization can be improved without changing the overall hardware configuration. This helps to reduce the complexity of system integration and improve the convenience of subsequent maintenance and replacement.

[0062] In some embodiments, the synchronization signal lines include an S0 power-ready signal line, a processor power-good signal line, and a processor reset signal line.

[0063] The synchronization signal line is a set of signal transmission lines used to transmit critical timing control information of the processor between two identical motherboards, the first and second motherboards. Its function is to coordinate the states of power-ready, processor power-stable, and reset-release stages, ensuring that the two CPUs enter the working state according to the same timing and maintain operational consistency. Based on the above analysis, this synchronization signal line is not a single control line, but a timing channel composed of the S0 power-ready signal line (S0_PWROK), the processor power-good signal line (CPU_PWRGD), and the processor reset signal line (CPU_RESET). The S0 power-ready signal line indicates that the system is in or about to enter the S0 working state; the processor power-good signal line indicates that the CPU power supply voltage has reached a preset stable threshold; and the processor reset signal line releases the reset control synchronously for both CPUs after the aforementioned conditions are met. The synchronization signal line is typically routed along the connector path between the first and second motherboards, for example, via a Slimsas connector. It connects to the timing pins of the two CPUs and the output ports of the relevant control logic, so that the timing signals are synchronously transmitted to the two processors after the CPLD of the control motherboard (the first motherboard) is turned on by an analog switch. Because this set of signals involves frequent low-level and high-level switching, it is usually routed separately from the response signal line to ensure signal integrity and timing consistency, and to minimize crosstalk and reflection effects between adjacent traces.

[0064] In one possible embodiment, the S0 power-ready signal line is used to transmit power status information to the control logic on both motherboards when the system power is in standby to operating state, enabling the control logic to determine whether the preconditions for subsequent processor power supply and reset control are met. The processor power-good signal line is used to monitor the processor power rail and output a stable status indication to ensure that the two CPUs only enter the next timing stage after the core voltage, auxiliary voltage, and related bias voltages all reach the allowable range. The processor reset signal line is used to synchronously apply or release the reset level to the two CPUs after the aforementioned conditions are met, so that the two CPUs start executing the initialization process at the same time. These three types of signals generally correspond to independent conductor lines or independent wiring channels, and are electrically connected to the CPLD control terminals and CPU timing pins on the two motherboards through connectors, and then the timing output is driven by the control motherboard.

[0065] When the system starts, the CPLD on the control motherboard (the CPLD of the first motherboard) first determines its control status based on the node identifier. After confirming the status on the response signal line, it sends out control levels on the S0 power ready signal line, the processor power good signal line, and the processor reset signal line by turning on the analog switch of the first motherboard. This allows the two CPUs to sequentially complete the power supply stability determination, reset hold, and reset release processes under the same power ready criteria. Simultaneously, the CPLD on the non-control motherboard (the CPLD of the second motherboard) keeps its corresponding analog switch off, thus avoiding level conflicts caused by both sides simultaneously driving the same synchronization channel. During this process, the S0 power ready signal line provides the overall enable condition for subsequent timing, the processor power good signal line ensures that the CPU only accepts the start command after power supply stability, and the processor reset signal line completes the synchronous reset control of the two CPUs, keeping them consistent in clock, power supply, and reset boundary conditions. Therefore, the two CPUs can enter the working state within a unified timing window, reducing startup mismatch problems caused by differences in electrical characteristics between motherboards, path delay differences, or drive conflicts, thereby improving the power-on consistency, reset synchronization, and operational stability of the dual-socket server system.

[0066] Based on the above embodiments, in some embodiments, the response signal line includes an S0 power-ready response signal line, a processor power-on response signal line, and a processor reset response signal line.

[0067] The response signal line is a set of electrical paths used in a dual-processor server system to provide feedback on the status of each key timing stage. Essentially, it transmits status information from the motherboard or node side regarding S0 power readiness, processor power-on, and processor reset to the control-side CPLD, allowing the control side to determine whether to proceed to the next timing stage based on the feedback level. This response signal line, in conjunction with the aforementioned synchronization signal line, forms a closed-loop control relationship of "status feedback, condition judgment, and synchronous drive." This ensures that the CPLD of the first motherboard can only synchronously output a valid timing signal to both CPUs after confirming that the second motherboard or corresponding node has met the predetermined readiness conditions, avoiding timing mismatch caused by premature driving on one side. In terms of location and connection, the S0 power ready acknowledge signal line (S0_PWROK_ACK), the processor power good acknowledge signal line (CPU_PWRGD_ACK), and the processor reset acknowledge signal line (CPU_RESET_ACK) are interconnected between the first and second motherboards via connectors such as Slimsas connectors, and are respectively connected to the open-drain output pins of the two CPLDs. They are also connected to the power supply via pull-up resistors to form a typical open-drain (OD) feedback structure. This open-drain output pin outputs high impedance when the state is ready and low impedance when the state is not ready. The default state is not ready (low level), ensuring the signal remains high unless actively pulled low on either side. When a valid acknowledgement or state change needs to be indicated at a certain node, the signal level is expressed by pulling low, releasing, or maintaining a high impedance state.

[0068] The three types of response signal lines mentioned above correspond to different timing stages. The S0 power ready response signal line is used to indicate the S0 domain power ready status; the processor power good response signal line is used to indicate that the processor power supply has reached the allowable operating conditions; and the processor reset response signal line is used to indicate whether the processor reset control link has been released or held, thus enabling the control logic to confirm key nodes such as power-on, power supply stabilization, and reset release step by step. When the S0 power ready response signal line is high, it indicates that the corresponding motherboard's S0 domain power supply has been successfully powered on; when it is low, it indicates that power-on is not complete and the system needs to wait for the ready status to be reached. It should be understood that the specific number, layout, and material selection of the S0 power ready response signal line, processor power good response signal line, and processor reset response signal line can be adjusted according to motherboard trace space, signal integrity requirements, and product cost, and are not limited here.

[0069] Correspondingly, when the system starts up, the CPLD of the first motherboard first determines its control role based on the first node identifier and turns on the corresponding analog switch. At the same time, the CPLD of the second motherboard maintains its non-control role based on the second node identifier and turns off its corresponding analog switch, thereby avoiding drive conflicts on the synchronization signal line between the two motherboards. Furthermore, the bill of materials (BOM) of the first and second motherboards does not need to be differentiated. Specifically, after the S0 domain power supply of the first motherboard is powered on, the CPLD of the first motherboard outputs a high-impedance state on the open-drain output pin corresponding to its S0 power-ready response signal line and monitors the level of the S0 power-ready response signal line: when a high level is detected, it indicates that the S0 domain power supply of the second motherboard is powered on successfully and the next operation can be performed; when a low level is detected, it indicates that the S0 domain power supply of the second motherboard is not powered on successfully and the system needs to wait for the second motherboard to become ready. Subsequently, the control side continuously monitors the power level of the other node via the S0 power-ready response signal line, the processor power-good response signal line, and the processor reset response signal line. When the S0 power-ready response signal line, the processor power-good response signal line, and the processor reset response signal line are all high, the relevant response levels form a stable logical judgment basis through the open-drain structure and pull-up resistors. This indicates that the corresponding power domains of the second motherboard are ready. Based on this, the control-side CPLD confirms that each stage of the dual-path system has reached the predetermined threshold and further drives the synchronization signal line to output consistent timing valid signals to the two CPUs. Since the three types of response signals correspond to different timing stages, the control logic can release each stage step by step, thereby establishing a clear sequential constraint between power-on, power supply stabilization, and reset release. This ensures that the two CPUs enter the working state under the same conditions, avoiding startup mismatch, state drift, or erroneous reset caused by a node being too early or too late.

[0070] In this embodiment, by refining the response signal lines into an S0 power-ready response signal line, a processor power-on response signal line, and a processor reset response signal line, and configuring them in open-drain output mode with external pull-up resistors, not only is the observability of key timing nodes enhanced, but the accuracy of the control role's judgment of the overall startup process and the reliability of synchronously issuing effective timing signals are also improved. This is conducive to improving the stable startup capability and collaborative control capability of the dual-socket server system under a unified hardware platform.

[0071] In some embodiments, the first node identifier is set by the level of a first hardware configuration pin on the first motherboard, and the second node identifier is set by the level of a second hardware configuration pin on the second motherboard; the first hardware configuration pin and the second hardware configuration pin are set to different levels.

[0072] The first and second hardware configuration pins are both hardware configuration terminals used to provide board role identification information to the CPLD. Essentially, they are input units that characterize the node identifier of the motherboard in a dual-processor server system through preset level states. Their function is to establish differentiated identity determination criteria for two motherboards with identical hardware configurations, enabling the CPLD to distinguish the first and second motherboards as different roles during the power-on initialization phase, thereby preventing both motherboards from simultaneously entering control mode during synchronization signal driving. In terms of location and relationship, the first hardware configuration pin is typically located near the CPLD on the first motherboard, and the second hardware configuration pin is located near the CPLD on the second motherboard. Both are electrically connected to the CPLD configuration input terminals on their respective motherboards and can be fixed to different levels using pull-up resistors, pull-down resistors, jumpers, DIP switches, pad shorting, or resistor encoding to maintain a stable identification state after the motherboards are assembled. In terms of form and material, hardware configuration pins can be implemented using gold finger contacts, pin headers, solder pads, or soldered jumper terminals. The conductor portion can be made of gold-plated copper alloy, tin-plated copper alloy, or stainless steel spring structure, while the insulating support portion can be made of FR-4, LCP, or high-temperature engineering plastics. Combined with surface-mount resistors, thin-film resistors, or thick-film resistors, they form a stable level setting network. Regarding size and proportion, the pins are typically arranged in a single-point or dual-point identification structure. Their electrical spacing and wiring length should meet the CPLD input threshold requirements, and the level states of the first and second hardware configuration pins must be clearly distinguishable, such as one high and one low, two complementary sets, or a recognizable binary difference formed by resistor encoding. The wiring length is generally controlled to be as short as possible to reduce the impact of crosstalk and noise coupling on node identification. Based on the above analysis, it can be seen that this hardware configuration pin can complete the node role definition without relying on complex software configuration, thus providing a simple and reliable identification basis during manufacturing, assembly, and maintenance. It should be understood that the above example is for demonstration purposes only and is not limiting.

[0073] When the system starts up, the first hardware configuration pin on the first motherboard and the second hardware configuration pin on the second motherboard first output their respective preset different levels. After reading the corresponding configuration input, the CPLD can establish a node identifier and determine the control or non-control role of its own board, thus completing the identity division between the two motherboards before entering the synchronization control stage. Since the two motherboards have the same hardware structure, but form distinguishable node identifiers through hardware configuration pins with different levels, the control logic can reliably identify which side should be responsible for driving the synchronization signal line and which side should remain in a controlled or disabled driving state, thereby avoiding both sides from competing for the same synchronization link at the same time. This process enables the motherboards to maintain a unified and predictable role allocation during the timing stages of power-on, reset, and operation switching, reducing synchronization conflicts, timing offsets, or signal driving anomalies caused by unclear roles, and is beneficial to improving the maintainability and consistency of the dual-socket server system in batch deployment, board replacement, and fault recovery scenarios.

[0074] Based on the above embodiments, in some embodiments, when the second motherboard is not in place, the response signal line is kept at a high level by a pull-up resistor, and the CPLD of the first motherboard independently completes the timing control.

[0075] In this embodiment, when the second motherboard is not in place due to maintenance or other reasons, the response signal line is kept at a high level by the pull-up resistor. The CPLD of the first motherboard independently completes the timing control. This is a fault-tolerant control feature for scenarios where nodes are missing. Its function is to provide a default high level through the pull-up resistor when the second motherboard is not installed, disconnected, or fails, so that the state of the S0 power ready response signal line, the processor power good response signal line, and the processor reset response signal line is consistent with the state of the first motherboard. Therefore, the power-on and power-off timing control can be completed independently without waiting for the response of the second motherboard, and is not affected by the presence of the second motherboard.

[0076] In one possible embodiment, the pull-up resistor is located near the first motherboard or the Slimsas connector to maintain the response signal line at a predetermined level when the second motherboard is not plugged in or its corresponding open-drain output terminal does not form an effective pull-down path, thus avoiding misjudgment caused by floating. When the second motherboard is not in place, the response port on the Slimsas connector corresponding to the second motherboard is floating, the CPLD of the second motherboard does not participate in the pull-down control, and the pull-up resistor continuously pulls each response signal line to a high level.

[0077] Correspondingly, when the system starts up, if the second motherboard is not installed, the response port on the Slimsas connector corresponding to the second motherboard is in a floating state. The CPLD and its open-drain output pins of the second motherboard do not participate in the pull-down control of the response signal lines. At this time, the preset pull-up resistors on the first motherboard side continuously pull each response signal line to a high level. Since the level state of the response signal line is consistent with the state of the first motherboard itself, the CPLD of the first motherboard samples this high-level state after power-on initialization and determines that the current feedback link is in a single-motherboard working mode without contention on the other side. It then exits the cooperative control process of waiting for confirmation from the second motherboard and, unaffected by the presence of the second motherboard, directly and independently completes the determination and output of timing signals such as S0 power ready, processor power good, and processor reset. Since there is no low-level pull and timing feedback from the second motherboard at this time, the first motherboard can directly drive the synchronization signal line to send a timing valid signal to the CPU on its own side according to the preset timing window, and continuously monitor and retransmit the relevant outputs when necessary, thereby ensuring that the processor can still complete a stable startup even without the second motherboard.

[0078] In this embodiment, when the second motherboard is not in place, a pull-up resistor keeps the response signal line at a high level, ensuring the response signal state is consistent with the first motherboard. The CPLD of the first motherboard can then independently complete timing control without waiting for a response from the other end. Therefore, the system can still start normally in scenarios such as node maintenance, removal, or failure, avoiding startup blockage caused by waiting for a non-existent response. It also eliminates the level uncertainty caused by floating signal lines, further improving the fault tolerance and on-site maintenance flexibility of the dual-socket server system.

[0079] The above embodiments illustrate the implementation of a dual-socket server system. The following specific embodiments will be used to illustrate the application of a dual-socket server system.

[0080] Figure 2 This is a flowchart illustrating a timing control method for a dual-socket server system provided as an exemplary embodiment of this application. The timing control method for a dual-socket server system provided in this embodiment is applied to a CPLD in the first motherboard of the aforementioned dual-socket server system. Figure 2 As shown, the timing control method includes the following steps:

[0081] S201. Read the first node identifier on the first motherboard to determine that the first motherboard is the control role.

[0082] In this embodiment, the first motherboard and the second motherboard have identical hardware configurations (i.e., identical BOMs), and both are equipped with node identification pins. Upon system startup, the CPLD of the first motherboard determines its role in the dual-path system by reading the level state of the first node identification pin on the first motherboard. Specifically, when the first node identification pin is set to a first preset level (e.g., grounded via a pull-down resistor), the CPLD of the first motherboard determines itself to be in a control role (i.e., motherboard N0); correspondingly, the node identification pin of the second motherboard is set to the opposite level (e.g., connected to the power supply via a pull-up resistor), causing its CPLD to determine itself to be in a non-control role (i.e., motherboard N1). Through this hardware identification method, the two identical motherboards can automatically complete the master-slave role allocation without software intervention, laying the foundation for timing synchronization control.

[0083] S202. According to the control role, control the analog switch of the first motherboard to be turned on so that the synchronization signal line is driven by the CPLD of the first motherboard.

[0084] For example, see reference Figure 1 Once the CPLD on the first motherboard determines its control role, it outputs an enable signal to control the analog switch on the first motherboard to be in the conducting state. Since the output of the CPLD on the first motherboard is connected to the synchronization signal line via the first analog switch, when the analog switch is on, the synchronization signal line is connected to the output of the CPLD on the first motherboard, thus driving the synchronization signal line. Simultaneously, the CPLD on the second motherboard, according to its non-control role, controls the analog switch on the second motherboard to be in the off state, disconnecting its output from the synchronization signal line, thereby preventing electrical conflicts caused by both CPLDs simultaneously driving the same signal line. Therefore, the driving control of the synchronization signal line is entirely in the hands of the CPLD in the control role, ensuring that subsequent timing signals are issued uniformly.

[0085] S203, Monitor the level status of the response signal line.

[0086] For example, still refer to Figure 1The first and second motherboards are connected by response signal lines, including the S0 power-ready response signal line (S0_PWROK_ACK), the processor power-on response signal line (CPU_PWRGD_ACK), and the processor reset response signal line (CPU_RESET_ACK). These response signal lines are connected to the open-drain output pins of the two CPLDs and to the power supply via external pull-up resistors. When the first motherboard completes the S0 domain power-on, its CPLD outputs a high-impedance state on its S0 power-ready response signal pin, indicating that the board is ready, and simultaneously begins monitoring the response signal line level. Due to the use of open-drain output mode, the level of the response signal line is determined by the output state of the two CPLDs and the pull-up resistors: only when both CPLDs output high impedance (i.e., both are ready) will the pull-up resistors pull the signal line high; otherwise, the signal line will be pulled low.

[0087] S204. When the detected level is low, continue to wait until the level changes to high.

[0088] Accordingly, when the CPLD of the first motherboard detects a low level on the response signal line, it indicates that the second motherboard has not yet completed the corresponding power-on or state readiness. For example, after the first motherboard completes the power-on of the S0 domain, it outputs a high impedance on the S0 power-ready response signal line. If the second motherboard has not yet completed the power-on of the S0 domain, its CPLD will still output a low level, causing the response signal line to be pulled low. After detecting the low level, the CPLD of the first motherboard determines that the second motherboard is not ready and does not execute the next operation. Instead, it continues to cyclically monitor the level of the response signal line until it becomes high. This waiting mechanism ensures that both motherboards have reached the ready state before entering the next timing stage, avoiding timing mismatch caused by premature action on one side.

[0089] S205. When a high level is detected, a timing valid signal is sent synchronously to the CPU of the first motherboard and the CPU of the second motherboard through the synchronization signal line.

[0090] Correspondingly, when the CPLD of the first motherboard detects a high level on the response signal line, it indicates that the second motherboard has also completed power-on of the corresponding power domain and is in a ready state (i.e., both CPLDs output high impedance, and pull-up resistors pull the signal lines high). At this time, the CPLD of the first motherboard sets the corresponding synchronization signal (e.g., the S0 power ready signal S0_PWROK) to a high level through the conducting analog switch and Slimsas connector. This high level is simultaneously transmitted to both CPUs, ensuring that the corresponding timing pins of the two CPUs receive the timing valid signal at the same time. The processor power good signal (CPU_PWRGD) and the processor reset signal (CPU_RESET) are sent synchronously in the same manner. Thus, the two motherboards with identical hardware achieve complete synchronization of critical timing signals.

[0091] In this embodiment, timing synchronization of a dual-socket server system can be achieved by using two motherboards with identical hardware configurations, without the need to develop a dedicated dual-socket motherboard, which significantly improves the flexibility of hardware configuration. At the same time, by monitoring the level of the response signal line and using a waiting mechanism, it is ensured that the two CPUs receive the valid timing signal at the same time, avoiding timing asynchrony problems, thus balancing hardware configuration flexibility and timing synchronization reliability.

[0092] In some embodiments, reading the first node identifier on the first motherboard includes: reading the level of a first hardware configuration pin on the first motherboard, and determining the first node identifier based on the level.

[0093] For example, a first hardware configuration pin on the first motherboard is set to a first preset level by grounding via a pull-down resistor or connecting to the power supply via a pull-up resistor. A second hardware configuration pin on the second motherboard is set to a second preset level opposite to that of the first hardware configuration pin, thus forming a differentiated identity determination basis. The CPLD of the first motherboard samples the first hardware configuration pin through its input port. When the first preset level (e.g., low level) is detected, the low level is mapped to the corresponding first node identifier, determining that the first motherboard is a control role (i.e., N0 motherboard). When the second preset level (e.g., high level) is detected, the high level is mapped to the corresponding second node identifier, determining that the first motherboard is a non-control role (i.e., N1 motherboard).

[0094] The hardware configuration pins can be implemented using gold finger contacts, pin header terminals, solder pad test points, or soldered jumper terminals. The level setting can be fixed using pull-up resistors, pull-down resistors, jumper caps, DIP switches, pad shorting, or resistor encoding to maintain a stable identification state after motherboard assembly. The pin level reading can be completed during power-on initialization or after the motherboard connection is established and the external circuit outputs a stable signal, thus ensuring the reliability of the identification determination. The CPLD can internally preset the correspondence between the level and the node identifier, using this correspondence to complete the identifier conversion. In practical applications, other models of this component can also be selected; this application embodiment does not limit this.

[0095] By setting the first and second hardware configuration pins to different levels on two identical motherboards, the CPLD can distinguish between control and non-control roles during power-on initialization without requiring differentiation in the motherboard bill of materials. This prevents both motherboards from simultaneously entering control mode during synchronization signal driving. The first motherboard does not need additional identification circuitry; it can determine the node identifier based on the level of the hardware configuration pins and provide this identifier to the control logic. This method ensures a consistent identification mechanism for the first motherboard across different installation configurations, reducing configuration complexity and improving the accuracy and stability of motherboard role determination in dual-socket server systems.

[0096] Based on the above embodiments, in some embodiments, the timing control method further includes: when the second motherboard is not in place, the level state is kept high by the pull-up resistor in the first motherboard, and the CPLD of the first motherboard independently completes the timing control.

[0097] For example, when the second motherboard is not in place, the response port on the Slimsas connector corresponding to the second motherboard is left floating, and the CPLD of the second motherboard does not participate in the pull-down control of the response signal lines. The pull-up resistors on the first motherboard side continuously pull the S0 power ready response signal line, the processor power good response signal line, and the processor reset response signal line to a high level, making the level state of the above response signal lines consistent with the state of the first motherboard itself. Correspondingly, after the CPLD of the first motherboard samples a high level, it does not need to wait for the response of the second motherboard and directly and independently completes the determination and output of the S0 power ready signal, the processor power good signal, and the processor reset signal, unaffected by the presence of the second motherboard. Thus, the first motherboard can automatically adapt between dual-motherboard collaborative mode and single-motherboard independent mode, avoiding timing waits or control blockages caused by the absence of the second motherboard.

[0098] In this embodiment, when the second motherboard is not in place, a pull-up resistor is used to keep the response signal line at a high level, ensuring that the response signal state is consistent with that of the first motherboard. The CPLD of the first motherboard can then independently complete timing control without waiting for a response from the other end. Therefore, the system can still start normally when the second motherboard is not in place due to maintenance, removal, or failure, avoiding startup blockage caused by waiting for a non-existent response. It also eliminates the level uncertainty caused by a floating signal line, further improving the fault tolerance and on-site maintenance flexibility of the dual-processor server system.

[0099] In summary, this application has at least the following advantages: By setting up a first motherboard and a second motherboard with identical hardware configurations, using node identifiers to distinguish between control and non-control roles, and having the CPLD of the control role uniformly drive the synchronization signal line, and connecting the response signal line to the open-drain output pins of both CPLDs and to the power supply via pull-up resistors, the response signal line is only pulled high when both motherboards are ready. This ensures that the CPLD of the control role synchronously sends a timing valid signal to both CPUs when it detects a high level. Therefore, this application achieves complete synchronization of critical timing signals while ensuring that the hardware of the two single-channel motherboards is completely identical. This effectively improves the problem of balancing hardware configuration flexibility and timing synchronization reliability in related technologies, reduces system cost and maintenance complexity, and supports single-node fault-tolerant operation, significantly enhancing system maintainability.

[0100] Figure 3 This is a schematic diagram of a timing control device for a dual-processor server system provided as an exemplary embodiment of this application. The timing control device for a dual-processor server system provided in this embodiment is disposed in the CPLD of the first motherboard in the aforementioned dual-processor server system. Figure 3 As shown, the timing control device 30 for a dual-path server system includes a role determination module 31, a switch control module 32, a monitoring module 33, and a processing module 34. Wherein:

[0101] The role determination module 31 is used to read the first node identifier on the first motherboard and determine that the first motherboard is the control role.

[0102] The switch control module 32 is used to control the analog switch of the first motherboard to be turned on according to the control role, so that the synchronization signal line is driven by the CPLD of the first motherboard.

[0103] Monitoring module 33 is used to monitor the level status of the response signal line;

[0104] The processing module 34 is used to continue waiting until the level changes to a high level when the level is detected to be low; when the level is detected to be high, it sends a timing valid signal to the CPU of the first motherboard and the CPU of the second motherboard through the synchronization signal line.

[0105] In one possible embodiment, the role determination module 31 may be specifically used to: read the first node identifier on the first motherboard, including: reading the level of the first hardware configuration pin on the first motherboard, and determining the first node identifier based on the level.

[0106] In one possible embodiment, the processing module 34 may be specifically used to: when the second motherboard is not in place, the level state is kept high by the pull-up resistor in the first motherboard, and the CPLD of the first motherboard independently completes the timing control.

[0107] The timing control device for a dual-processor server system provided in this application embodiment can execute the technical solution shown in the above-described timing control method embodiment for a dual-processor server system. Its implementation principle and beneficial effects are similar, and will not be repeated here.

[0108] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a processing module can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as program code in the device's memory, and its functions can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0109] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a System-On-a-Chip (SOC).

[0110] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Video Discs, DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0111] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0112] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A dual-processor server system, characterized in that, The system includes a first motherboard and a second motherboard with identical hardware configurations; both the first motherboard and the second motherboard include a central processing unit (CPU), a complex programmable logic device (CPLD), and analog switches; the first motherboard and the second motherboard are interconnected via a connector to connect synchronization signal lines and acknowledge signal lines, the synchronization signal lines being connected to the timing pins of the two CPUs; the outputs of the two CPLDs are connected to the synchronization signal lines via corresponding analog switches; the acknowledge signal lines are connected to the open-drain output pins of the two CPLDs and are connected to the power supply via pull-up resistors. The CPLD of the first motherboard is used to determine the control role based on the first node identifier and control the analog switch of the first motherboard to turn on to drive the synchronization signal line; The CPLD of the second motherboard is used to determine the non-control role based on the second node identifier, and control the analog switch of the second motherboard to turn off, so that the second motherboard is in a high impedance state to the synchronization signal line; The CPLD of the first motherboard is also used to monitor the level of the response signal line. When the level is high, it sends a timing valid signal to the two CPUs through the synchronization signal line to achieve timing synchronization of the dual-processor server system. When the second motherboard is not in place, the response signal line is kept at a high level by the pull-up resistor, and the CPLD of the first motherboard independently completes the timing control.

2. The dual-processor server system according to claim 1, characterized in that, The connector is a Slimsas connector.

3. The dual-processor server system according to claim 1, characterized in that, The synchronization signal lines include the S0 power ready signal line, the processor power good signal line, and the processor reset signal line.

4. The dual-processor server system according to claim 1, characterized in that, The response signal lines include the S0 power ready response signal line, the processor power good response signal line, and the processor reset response signal line.

5. The dual-processor server system according to any one of claims 1 to 4, characterized in that, The first node identifier is set by the level of the first hardware configuration pin on the first motherboard, and the second node identifier is set by the level of the second hardware configuration pin on the second motherboard; the first hardware configuration pin and the second hardware configuration pin are set to different levels.

6. A timing control method for a dual-processor server system, characterized in that, A complex programmable logic device (CPLD) used in the first motherboard of a dual-socket server system as described in any one of claims 1 to 5; The timing control method includes: Read the first node identifier on the first motherboard to determine that the first motherboard is a control role; According to the control role, the analog switch of the first motherboard is turned on so that the synchronization signal line is driven by the CPLD of the first motherboard; Monitor the level status of the response signal line; When the detected level is low, continue to wait until the level changes to high. When the level is detected to be high, a timing valid signal is sent synchronously to the CPU of the first motherboard and the CPU of the second motherboard through the synchronization signal line. When the second motherboard is not in place, the voltage level is maintained at a high level by the pull-up resistor in the first motherboard, and the CPLD of the first motherboard independently performs timing control.

7. The timing control method for a dual-processor server system according to claim 6, characterized in that, The step of reading the first node identifier on the first motherboard includes: Read the level of the first hardware configuration pin on the first motherboard, and determine the first node identifier based on the level.

8. A timing control device for a dual-processor server system, characterized in that, A complex programmable logic device (CPLD) is disposed in the first motherboard of the dual-socket server system as described in any one of claims 1 to 5; The timing control device includes: The role determination module is used to read the first node identifier on the first motherboard and determine that the first motherboard is a control role. A switch control module is used to control the analog switch of the first motherboard to be turned on according to the control role, so that the synchronization signal line is driven by the CPLD of the first motherboard. The monitoring module is used to monitor the voltage level of the response signal line; The processing module is configured to wait until the level changes to a high level when the level is detected to be low; and to send a timing valid signal to the CPU of the first motherboard and the CPU of the second motherboard through the synchronization signal line when the level is detected to be high. The processing module is specifically used to maintain the voltage level at a high level by the pull-up resistor in the first motherboard when the second motherboard is not in place, and the CPLD of the first motherboard independently performs timing control.

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