Capacitive isolated driver demodulation circuit

Abstract

The application provides a capacitive isolation driver demodulation circuit, and belongs to the technical field of signal modulation. The capacitive isolation driver demodulation circuit comprises a first envelope detection circuit, a second envelope detection circuit and a logic processing circuit. The input end of the first envelope detection circuit and the input end of the second envelope detection circuit are respectively used for connecting a modulated carrier differential signal. The circuit structures of the first envelope detection circuit and the second envelope detection circuit are the same, and the circuit parameters are different. The output ends of the first envelope detection circuit and the second envelope detection circuit are respectively connected to two input ends of the logic processing circuit. The logic processing circuit is configured to: when a to-be-modulated signal is a high level, the output signal of the first envelope detection circuit is latched and output; and when the to-be-modulated signal is a low level, the output signal of the second envelope detection circuit is latched and output. The application can improve the common-mode transient immunity of the capacitive isolation driver without increasing the circuit delay.

Description

Technical Field

[0001] This application relates to the field of signal modulation technology, and in particular to a capacitor-type isolation driver demodulation circuit. Background Technology

[0002] Capacitive isolation drivers are based on a capacitive isolation architecture and on-off keying (OOK) modulation. Their working principle involves using the input TTL signal to modulate the amplitude of a high-frequency carrier wave. The modulated signal is transmitted through an isolation capacitor to form an attenuated signal. This attenuated signal is then amplified and demodulated to restore the original TTL signal, which is finally passed through the driver circuit to obtain the final output signal. With the large-scale application of third-generation semiconductor devices, challenges such as nanosecond-level switching times and ultra-high dV / dt values ​​have arisen, leading to severe common-mode transient (CMT) interference. Low common-mode transient immunity (CMTI) can easily cause fatal failures such as false triggering of power devices and shoot-through current. Therefore, improving CMTI is crucial for the reliability of isolation drivers. Currently, the main method to improve CMTI is to add RC filter capacitors in the demodulation back-end circuit, but this approach significantly increases circuit delay, making it unsuitable for applications with low latency requirements. Summary of the Invention

[0003] This application provides a demodulation circuit for a capacitive isolation driver to solve the problem that existing methods for improving CMTI increase the circuit delay of the capacitive isolation driver.

[0004] This application provides a capacitor-isolated driver demodulation circuit, including: a first envelope detection circuit, a second envelope detection circuit, and a logic processing circuit; The input terminals of the first envelope detection circuit and the second envelope detection circuit are respectively used to connect to the modulated carrier differential signal; wherein, the modulated carrier differential signal is obtained by amplitude modulation of the signal to be modulated; The first envelope detection circuit and the second envelope detection circuit have the same circuit structure but different circuit parameters, such that: when the signal to be modulated is high, the common-mode transient immunity of the first envelope detection circuit is greater than that of the second envelope detection circuit; and when the signal to be modulated is low, the common-mode transient immunity of the second envelope detection circuit is greater than that of the first envelope detection circuit. The output terminal of the first envelope detection circuit is connected to the first input terminal of the logic processing circuit, and the output terminal of the second envelope detection circuit is connected to the second input terminal of the logic processing circuit. The logic processing circuit is configured to: latch and output the output signal of the first envelope detection circuit when the signal to be modulated is high; and latch and output the output signal of the second envelope detection circuit when the signal to be modulated is low.

[0005] In one embodiment of this application, the modulated carrier differential signal includes a first differential signal and a second differential signal. When the signal to be modulated is at a high level, the amplitude of the first differential signal is greater than the amplitude of the second differential signal. When the signal to be modulated is at a low level, the amplitudes of the first differential signal and the second differential signal are equal. The first envelope detection circuit includes a first envelope comparison branch, a second envelope comparison branch, and a first comparison circuit; the first differential signal is connected to the differential input terminal of the first envelope comparison branch, the second differential signal is connected to the differential input terminal of the second envelope comparison branch, the output terminal of the first envelope comparison branch and the output terminal of the second envelope comparison branch are respectively connected to the two input terminals of the first comparison circuit, and the output terminal of the first comparison circuit is the output terminal of the first envelope detection circuit; The second envelope detection circuit includes a third envelope comparison branch, a fourth envelope comparison branch, and a second comparison circuit; the first differential signal is also connected to the differential input terminal of the third envelope comparison branch, the second differential signal is also connected to the differential input terminal of the fourth envelope comparison branch, the output terminals of the third and fourth envelope comparison branches are respectively connected to the two input terminals of the second comparison circuit, and the output terminal of the second comparison circuit is the output terminal of the second envelope detection circuit; The first envelope comparison branch includes transistor M1, transistor M2, resistor R1, and current source I. 11 With capacitor C1, the gates of transistor M1 and M2 are the differential input terminals of the first envelope comparator branch. The drains of transistor M1 and M2 are connected to a DC power supply. The sources of transistor M1 and M2 are connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the current source I. 11 The second terminal of the resistor R1 is also grounded through the capacitor C1; The second envelope comparison branch includes transistor M3, transistor M4, and current source I. 12 And capacitor C2; the gates of transistor M3 and transistor M4 are the differential input terminals of the second envelope comparator branch, the drains of transistor M3 and transistor M4 are connected to the DC power supply, and the sources of transistor M3 and transistor M4 are connected to the current source I. 12The first end, the current source I 12 The second terminal is grounded, and the source of transistor M3 and the source of transistor M4 are also grounded through capacitor C2; The third envelope comparison branch includes transistor M11, transistor M12, resistor R4, and current source I. 13 With capacitor C3, the gates of transistors M11 and M12 are the differential input terminals of the third envelope comparator branch. The drains of transistors M11 and M12 are connected to a DC power supply, and the sources of transistors M11 and M12 are connected to the first terminal of resistor R4. The second terminal of resistor R4 is connected to the current source I. 13 The second terminal of the resistor R4 is also grounded through the capacitor C3; The fourth envelope comparison branch includes transistor M13, transistor M14, and current source I. 14 And capacitor C4; the gates of transistor M13 and M14 are the differential input terminals of the fourth envelope comparator branch; the drains of transistor M13 and M14 are connected to a DC power supply; and the sources of transistor M13 and M14 are connected to the current source I. 14 The first end, the current source I 14 The second terminal is grounded, and the source of transistor M13 and the source of transistor M14 are also grounded through capacitor C4; The resistance value of resistor R1 is less than the resistance value of resistor R4.

[0006] In one embodiment of this application, the first comparison circuit includes a first comparator, a second comparator, and a first decision output circuit connected in sequence; the second comparison circuit includes a third comparator, a fourth comparator, and a second decision output circuit connected in sequence. The first comparator includes transistor M5, transistor M6, and current source I. 21 Resistors R2 and R3, the gates of transistors M5 and M6 respectively serve as the two input terminals of the first comparator circuit, and the sources of transistors M5 and M6 are connected to the current source I. 21 The first end, the current source I 21 The second terminal is connected to a DC power supply. The drain of transistor M5 is grounded through resistor R2, and the drain of transistor M6 is grounded through resistor R3. The second comparator includes transistor M7, transistor M8, and current source I. 22Transistors M9 and M10 are connected. The drain of transistor M6 is connected to the gate of transistor M7, and the drain of transistor M5 is connected to the gate of transistor M8. The sources of transistors M7 and M8 are connected to the current source I. 22 The first end, the current source I 22 The second terminal is connected to a DC power supply. The drain of transistor M7 is connected to the drain of transistor M9. The drain of transistor M8 is connected to the drain of transistor M10. The gates of transistor M9 and M10 are connected to the drain of transistor M9. The sources of transistor M9 and M10 are both grounded. The first decision output circuit includes transistor M21 and current source I. 31 The drain of transistor M10 is connected to the gate of transistor M21, the source of transistor M21 is grounded, and the drain of transistor M21 is connected to the current source I. 31 The first end, the current source I 31 The second terminal is connected to a DC power supply, and the drain of the transistor M21 is the output terminal of the first comparator circuit; The third comparator includes transistor M15, transistor M16, and current source I. 23 Resistors R5 and R6 are used. The gates of transistors M15 and M16 serve as the two input terminals of the second comparator circuit, respectively. The sources of transistors M15 and M16 are connected to the current source I. 23 The first end, the current source I 23 The second terminal is connected to a DC power supply. The drain of transistor M15 is grounded through resistor R5, and the drain of transistor M16 is grounded through resistor R6. The fourth comparator includes transistor M17, transistor M18, and current source I. 24 Transistors M19 and M20 are used. The drain of transistor M16 is connected to the gate of transistor M17, and the drain of transistor M15 is connected to the gate of transistor M18. The sources of transistors M17 and M18 are connected to the current source I. 24 The first end, the current source I 24 The second terminal is connected to a DC power supply. The drain of transistor M17 is connected to the drain of transistor M19. The drain of transistor M18 is connected to the drain of transistor M20. The gates of transistor M19 and M20 are both connected to the drain of transistor M19. The sources of transistor M19 and M20 are both grounded. The second decision output circuit includes transistor M22 and current source I. 32 The drain of transistor M20 is connected to the gate of transistor M22, the source of transistor M22 is grounded, and the drain of transistor M22 is connected to the current source I. 32 The first end, the current source I 32 The second terminal is connected to a DC power supply, and the drain of the transistor M22 is the output terminal of the second comparator circuit.

[0007] In one embodiment of this application, the resistance value of resistor R2 is less than the resistance value of resistor R3, the aspect ratio of transistor M9 is greater than the aspect ratio of transistor M10, and the resistance value of resistor R5 is equal to the resistance value of resistor R3. The resistance value of resistor R6 is equal to the resistance value of resistor R2, the width-to-length ratio of transistor M9 is equal to the width-to-length ratio of transistor M20, and the width-to-length ratio of transistor M10 is equal to the width-to-length ratio of transistor M19.

[0008] In one embodiment of this application, the logic processing circuit includes a Schmitt trigger U1, a Schmitt trigger U2, an inverter U3, a NAND gate U4, and a NAND gate U5; The input terminal of the Schmitt trigger U1 is connected to the output terminal of the first envelope detection circuit, and the input terminal of the Schmitt trigger U2 is connected to the output terminal of the second envelope detection circuit. The output of Schmitt trigger U1 is connected to the first input of NAND gate U4, the output of NAND gate U4 is connected to the first input of NAND gate U5, the output of Schmitt trigger U2 is connected to the second input of NAND gate U5 through inverter U3, the output of NAND gate U5 is connected to the second input of NAND gate U4, and the output of NAND gate U4 is the output of the logic processing circuit.

[0009] In one embodiment of this application, the logic processing circuit further includes an inverter U6; The output of the NAND gate U4 is connected to the input of the inverter U6, and the output of the inverter U6 is the output of the logic processing circuit.

[0010] The beneficial effects of the capacitor-isolated driver demodulation circuit provided in this application embodiment are as follows: In this embodiment, the signal to be modulated can be a TTL signal input to the modulation circuit. After the signal to be modulated is input to the modulation circuit, it can first undergo amplitude modulation to obtain a modulated carrier differential signal. The first envelope detection circuit and the second envelope detection circuit are respectively used to extract the envelope, amplify the differential signal, and demodulate the modulated carrier differential signal. The first envelope detection circuit and the second envelope detection circuit have the same circuit structure but different circuit parameters, so that when the signal to be modulated is high, the common-mode transient immunity of the first envelope detection circuit is greater than that of the second envelope detection circuit, and when the signal to be modulated is low, the common-mode transient immunity of the second envelope detection circuit is greater than that of the first envelope detection circuit.

[0011] Based on this, the output of the first envelope detection circuit is connected to the first input of the logic processing circuit, and the output of the second envelope detection circuit is connected to the second input of the logic processing circuit. When the signal to be modulated is high, the output signal of the first envelope detection circuit is latched and output; when the signal to be modulated is low, the output signal of the second envelope detection circuit is latched and output. That is, after logic processing, the outputs of the two envelope detection circuits ultimately retain the high CMTI signal of the first envelope detection circuit (the signal corresponding to the high-level period of the signal to be modulated) and the high CMTI signal of the second envelope detection circuit (the signal corresponding to the low-level period of the signal to be modulated) as the final output signal, thereby improving the common-mode transient immunity of the capacitive isolation driver without increasing circuit delay. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic block diagram of the demodulation circuit of the capacitor isolation driver provided in the embodiment of this application; Figure 2 This is a schematic diagram of the dual-envelope detection circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the logic processing circuit provided in the embodiments of this application; Figure 4 This is a waveform diagram of a key node in the demodulation circuit of the capacitor-isolated driver provided in the embodiments of this application; Figure 5 This is a simulation waveform diagram of the key nodes of the capacitor isolation driver demodulation circuit under 150V / ns CMT provided in the embodiments of this application. Detailed Implementation

[0014] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0015] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0016] The implementation of this application will be described in detail below with reference to the specific accompanying drawings: Reference Figures 1-2 The demodulation circuit of the capacitor isolation driver includes a first envelope detection circuit, a second envelope detection circuit, and a logic processing circuit. The input terminals of the first envelope detector circuit and the second envelope detector circuit are respectively used to connect to the modulated carrier differential signal; wherein, the modulated carrier differential signal is obtained by amplitude modulation of the signal to be modulated, and the modulated carrier differential signal includes a first differential signal and a second differential signal. When the signal to be modulated is at a high level, the amplitude of the first differential signal is greater than the amplitude of the second differential signal. When the signal to be modulated is at a low level, the amplitudes of the first differential signal and the second differential signal are equal. The first envelope detector circuit and the second envelope detector circuit have the same circuit structure but different circuit parameters, so that: when the signal to be modulated is high level, the low common-mode transient immunity of the first envelope detector circuit is greater than that of the second envelope detector circuit; when the signal to be modulated is low level, the low common-mode transient immunity of the second envelope detector circuit is greater than that of the first envelope detector circuit. The output of the first envelope detection circuit is connected to the first input of the logic processing circuit, and the output of the second envelope detection circuit is connected to the second input of the logic processing circuit. The logic processing circuit is configured to: latch and output the output signal of the first envelope detection circuit when the signal to be modulated is high; and latch and output the output signal of the second envelope detection circuit when the signal to be modulated is low.

[0017] In this embodiment, the signal to be modulated can be a TTL signal input to the modulation circuit. After the signal to be modulated is input to the modulation circuit, it can first undergo amplitude modulation to obtain a modulated carrier differential signal. The first envelope detection circuit and the second envelope detection circuit are respectively used to extract the envelope, amplify the differential signal, and demodulate the modulated carrier differential signal. The first envelope detection circuit and the second envelope detection circuit have the same circuit structure but different circuit parameters, so that when the signal to be modulated is high, the common-mode transient immunity of the first envelope detection circuit is greater than that of the second envelope detection circuit, and when the signal to be modulated is low, the common-mode transient immunity of the second envelope detection circuit is greater than that of the first envelope detection circuit.

[0018] Based on this, the output of the first envelope detection circuit is connected to the first input of the logic processing circuit, and the output of the second envelope detection circuit is connected to the second input of the logic processing circuit. When the signal to be modulated is high, the output signal of the first envelope detection circuit is latched and output; when the signal to be modulated is low, the output signal of the second envelope detection circuit is latched and output. That is, after logic processing, the outputs of the two envelope detection circuits ultimately retain the high CMTI signal of the first envelope detection circuit (the signal corresponding to the high-level period of the signal to be modulated) and the high CMTI signal of the second envelope detection circuit (the signal corresponding to the low-level period of the signal to be modulated) as the final output signal, thereby improving the common-mode transient immunity of the capacitive isolation driver without increasing circuit delay.

[0019] In one embodiment of this application, the modulated carrier differential signal includes a first differential signal and a second differential signal. When the signal to be modulated is at a high level, the amplitude of the first differential signal is greater than the amplitude of the second differential signal. When the signal to be modulated is at a low level, the amplitudes of the first differential signal and the second differential signal are equal. The first envelope detection circuit includes a first envelope comparison branch, a second envelope comparison branch, and a first comparison circuit; a first differential signal is connected to the differential input terminal of the first envelope comparison branch, a second differential signal is connected to the differential input terminal of the second envelope comparison branch, the output terminal of the first envelope comparison branch and the output terminal of the second envelope comparison branch are respectively connected to the two input terminals of the first comparison circuit, and the output terminal of the first comparison circuit is the output terminal of the first envelope detection circuit; The second envelope detection circuit includes a third envelope comparison branch, a fourth envelope comparison branch, and a second comparison circuit; the first differential signal is also connected to the differential input terminal of the third envelope comparison branch, the second differential signal is also connected to the differential input terminal of the fourth envelope comparison branch, the output terminals of the third envelope comparison branch and the fourth envelope comparison branch are respectively connected to the two input terminals of the second comparison circuit, and the output terminal of the second comparison circuit is the output terminal of the second envelope detection circuit; The first envelope comparison branch includes transistor M1, transistor M2, resistor R1, and current source I. 11 With capacitor C1, the gates of transistors M1 and M2 form the differential input terminals of the first envelope comparator branch. The drains of transistors M1 and M2 are connected to a DC power supply, and the sources of transistors M1 and M2 are connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to current source I. 11 The resistor R1 is grounded, and the second terminal of the resistor R1 is also grounded through the capacitor C1. The second envelope comparison branch includes transistor M3, transistor M4, and current source I. 12 With capacitor C2; the gates of transistors M3 and M4 are the differential input terminals of the second envelope comparator branch, the drains of transistors M3 and M4 are connected to the DC power supply, and the sources of transistors M3 and M4 are connected to the current source I. 12 The first terminal, current source I 12 The second terminal is grounded, and the source of transistor M3 and the source of transistor M4 are also grounded through capacitor C2; The third envelope comparison branch includes transistor M11, transistor M12, resistor R4, and current source I. 13 Along with capacitor C3, the gates of transistors M11 and M12 form the differential input terminals of the third envelope comparator branch. The drains of transistors M11 and M12 are connected to the DC power supply, and the sources of transistors M11 and M12 are connected to the first terminal of resistor R4. The second terminal of resistor R4 is connected to current source I. 13 The resistor R4 is grounded, and the second terminal of the resistor R4 is also grounded through capacitor C3. The fourth envelope comparator branch includes transistor M13, transistor M14, and current source I. 14 With capacitor C4; the gates of transistors M13 and M14 are the differential input terminals of the fourth envelope comparator branch; the drains of transistors M13 and M14 are connected to the DC power supply; and the sources of transistors M13 and M14 are connected to the current source I. 14 The first terminal, current source I 14 The second terminal is grounded, and the source of transistor M13 and the source of transistor M14 are also grounded through capacitor C4; The resistance of resistor R1 is less than the resistance of resistor R4.

[0020] In this embodiment, as Figure 2 As shown, the first differential signal is V. bigger+ and V bigger- The second differential signal is V smaller+ and V smaller-V bigger+ V bigger- V smaller+ V smaller- This is obtained after amplitude modulation of the signal to be modulated. When the input signal to be modulated is low, V... bigger+ =V bigger- =V smaller+ =V smaller- And all are DC levels; when the signal to be modulated is high, V bigger+ V bigger- V smaller+ V smaller- Both are AC signals similar to sine waves, and V bigger+ V bigger- They are opposites, V smaller+ V smaller- They are opposites, V bigger+ The amplitude is equal to V bigger- The amplitude, V smaller+ The amplitude is equal to V smaller- The amplitude, V bigger+ The amplitude is greater than V smaller+ The amplitude.

[0021] The first envelope detector circuit (i.e.) Figure 2 The A-channel envelope detection circuit includes a first envelope comparison branch, a second envelope comparison branch, and a first comparison circuit. The first envelope comparison branch performs differential sampling and envelope extraction on the first differential signal, outputting a first envelope detection voltage SF1_A. The second envelope comparison branch performs differential sampling and envelope extraction on the second differential signal, outputting a second envelope detection voltage SF2_A. The first comparison circuit performs differential comparison, level determination, and signal amplification on the two envelope detection voltages, outputting a first envelope detection signal A. OUT .

[0022] In the first envelope comparison branch, transistors M1 and M2 form a source-coupled differential pair. Based on the amplitude difference of the input first differential signal, a corresponding current change is generated, which is converted into a voltage signal by resistor R1. Then, capacitor C1 filters out the high-frequency carrier component, extracting and outputting a stable envelope voltage. Furthermore, a constant current source I is connected in series at the tail side of the source-coupled differential pair. 11 It can provide a stable bias for source-coupled differential pairs.

[0023] In the second envelope comparator branch, transistors M3 and M4 form a source-coupled differential pair. Based on the amplitude difference of the input second differential signal, they generate corresponding current changes, which are converted into voltage signals by the equivalent load (transistor parasitic impedance). High-frequency carrier components are then filtered out by capacitor C2, extracting and outputting a stable envelope voltage. Furthermore, a constant current source I is connected in series at the tail side of the source-coupled differential pair.13 It can provide a stable bias for source-coupled differential pairs.

[0024] When the signal to be modulated is high, the amplitude of the first differential signal is greater than that of the second differential signal. Therefore, the first envelope detection voltage SF1_A is greater than the second envelope detection voltage SF2_A, and the difference between the two envelope detection voltages is SF1_A - SF2_A. When the signal to be modulated is low, the amplitude of the first differential signal is equal to that of the second differential signal. Due to the presence of resistor R1, the first envelope detection voltage SF1_A is less than that of the second envelope detection voltage SF2_A, and the difference between the two envelope detection voltages is SF2_A - SF1_A.

[0025] The second envelope detector circuit (i.e.) Figure 2 The circuit structure of the B-channel envelope detection circuit in the second envelope detection circuit is the same as that of the first envelope detection circuit. The difference is that the resistor R1 in the first envelope comparison branch is smaller than the resistor R4 in the third envelope comparison branch. For ease of description, the envelope detection voltage output by the third envelope comparison branch in the second envelope detection circuit is referred to as the third envelope detection voltage, and the envelope detection voltage output by the fourth envelope comparison branch is referred to as the fourth envelope detection voltage.

[0026] When the signal to be modulated is high, the resistance of resistor R1 decreases, the first envelope detection voltage SF1_A increases, and the difference between the first and second envelope detection voltages SF1_A-SF2_A increases. This strengthens the differential-mode signal output by the first envelope detection circuit, thereby increasing its common-mode rejection ratio (CMRR) and improving its common-mode transient immunity when the signal to be modulated is high. When the signal to be modulated is low, the resistance of resistor R4 increases, the third envelope detection voltage SF1_B decreases, and the difference between the fourth and third envelope detection voltages SF2_B and SF1_B (SF2_B-SF1_B) increases. This strengthens the differential-mode signal output by the second envelope detection circuit, further increasing its CMRR and improving its common-mode transient immunity when the signal to be modulated is low.

[0027] In one embodiment of this application, the first comparison circuit includes a first comparator, a second comparator, and a first decision output circuit connected in sequence; the second comparison circuit includes a third comparator, a fourth comparator, and a second decision output circuit connected in sequence. The first comparator includes transistor M5, transistor M6, and current source I. 21Resistors R2 and R3, the gates of transistors M5 and M6 serve as the two input terminals of the first comparator circuit, and the sources of transistors M5 and M6 are connected to the current source I. 21 The first terminal, current source I 21 The second terminal is connected to a DC power supply. The drain of transistor M5 is grounded through resistor R2, and the drain of transistor M6 is grounded through resistor R3. The second comparator includes transistor M7, transistor M8, and current source I. 22 Transistors M9 and M10, the drain of transistor M6 is connected to the gate of transistor M7, the drain of transistor M5 is connected to the gate of transistor M8, and the sources of transistors M7 and M8 are connected to current source I. 22 The first terminal, current source I 22 The second terminal is connected to a DC power supply. The drain of transistor M7 is connected to the drain of transistor M9, the drain of transistor M8 is connected to the drain of transistor M10, the gate of transistor M9 and the gate of transistor M10 are both connected to the drain of transistor M9, and the source of transistor M9 and the source of transistor M10 are both grounded. The first decision output circuit includes transistor M21 and current source I. 31 The drain of transistor M10 is connected to the gate of transistor M21, the source of transistor M21 is grounded, and the drain of transistor M21 is connected to current source I. 31 The first terminal, current source I 31 The second terminal is connected to a DC power supply, and the drain of transistor M21 is the output terminal of the first comparator circuit; The third comparator includes transistor M15, transistor M16, and current source I. 23 Resistors R5 and R6, the gates of transistors M15 and M16 respectively serve as the two input terminals of the second comparator circuit, and the sources of transistors M15 and M16 are connected to the current source I. 23 The first terminal, current source I 23 The second terminal is connected to a DC power supply. The drain of transistor M15 is grounded through resistor R5, and the drain of transistor M16 is grounded through resistor R6. The fourth comparator includes transistor M17, transistor M18, and current source I. 24 Transistors M19 and M20, the drain of transistor M16 is connected to the gate of transistor M17, the drain of transistor M15 is connected to the gate of transistor M18, and the sources of transistors M17 and M18 are connected to current source I. 24 The first terminal, current source I 24The second terminal is connected to a DC power supply. The drain of transistor M17 is connected to the drain of transistor M19. The drain of transistor M18 is connected to the drain of transistor M20. The gates of transistor M19 and M20 are connected to the drain of transistor M19. The sources of transistor M19 and M20 are both grounded. The second decision output circuit includes transistor M22 and current source I. 32 The drain of transistor M20 is connected to the gate of transistor M22, the source of transistor M22 is grounded, and the drain of transistor M22 is connected to current source I. 32 The first terminal, current source I 32 The second terminal is connected to a DC power supply, and the drain of transistor M22 is the output terminal of the second comparator circuit.

[0028] In this embodiment, in the first comparator, transistors M5 and M6 form a differential pair, with the first envelope detection voltage SF1_A and the second envelope detection voltage SF2_A as differential inputs, in conjunction with the tail current source I. 21 With load resistors R2 and R3, differential amplification is performed on the two envelope detection voltages to initially amplify the voltage difference and suppress common-mode interference, outputting differential signals COMP1_A and COMP2_A.

[0029] Furthermore, transistor M7, transistor M8, and current source I... 22 Transistor M9 and transistor M10 form a second comparator, which is used to receive the differential signals COMP1_A and COMP2_A from the previous stage, perform secondary differential amplification and level shaping, further enhance the differential signal, compress common-mode noise, and convert the weak voltage difference into a single-channel normalized level COMP_A.

[0030] Finally, the single-channel normalized level COMP_A is connected to the gate of transistor M21, and then connected to the constant current source I. 31 This structure forms a single-ended amplifier output, performs level conversion and drive buffering, and finally outputs the first envelope detection signal A. OUT .

[0031] Similarly, in the third comparator, transistors M15 and M16 form a differential pair, using the third envelope detection voltage SF1_B and the fourth envelope detection voltage SF2_B as differential inputs, in conjunction with the tail current source I. 23 With load resistors R5 and R6, differential amplification is performed on the two envelope detection voltages to initially amplify the voltage difference and suppress common-mode interference, outputting differential signals COMP1_B and COMP2_B.

[0032] Transistor M17, Transistor M18, Current Source I 24, the transistor M19 and the transistor M20 form a fourth comparator, which is used to receive the pre-stage differential signals COMP1_B and COMP2_B, perform secondary differential amplification and level shaping, further strengthen the differential-mode signal, compress the common-mode noise, and convert the weak pressure difference into a single regular level COMP_B.

[0033] Finally, connect the single regular level COMP_B to the gate of the transistor M22, and form a single-ended amplified output structure with the constant current source I 32 to complete the level conversion and drive buffering, and finally output the second envelope detection signal B OUT .

[0034] In an embodiment of the present application, the resistance value of the resistor R2 is less than the resistance value of the resistor R3, the aspect ratio of the transistor M9 is greater than the aspect ratio of the transistor M10, the resistance value of the resistor R5 is equal to the resistance value of the resistor R3, the resistance value of the resistor R6 is equal to the resistance value of the resistor R2, the aspect ratio of the transistor M9 is equal to the aspect ratio of the transistor M20, and the aspect ratio of the transistor M10 is equal to the aspect ratio of the transistor M19.

[0035] In this embodiment, on the basis of setting the resistor R1 in the first envelope comparison branch to be less than the resistor R4 in the third envelope comparison branch, set the resistance value of the resistor R2 to be less than the resistance value of the resistor R3, the resistance value of the resistor R5 to be equal to the resistance value of the resistor R3, and the resistance value of the resistor R6 to be equal to the resistance value of the resistor R2. Compared with a completely symmetric circuit structure, R2<R3 can effectively increase the circuit gain when the signal to be modulated is at a high level (SF1_A>SF2_A), and the value of COMP2_A-COMP1_A increases, thereby improving the CMTI ability; R5>R6 can effectively increase the circuit gain when the signal to be modulated is at a low level (SF1_B<SF2_B), and the value of COMP1_B-COMP2_B increases, thereby improving the CMTI ability.

[0036] Furthermore, set the aspect ratio of the transistor M9 to be greater than the aspect ratio of the transistor M10, the aspect ratio of the transistor M9 to be equal to the aspect ratio of the transistor M20, and the aspect ratio of the transistor M10 to be equal to the aspect ratio of the transistor M19. Compared with a completely symmetric circuit structure, M9>M10 can effectively increase the circuit gain when the signal to be modulated is at a high level (SF1_A>SF2_A), thereby improving the CMTI ability; M19<M20 can effectively increase the circuit gain when the signal to be modulated is at a low level (SF1_B<SF2_B), thereby improving the CMTI ability. In summary, the high-level CMTI ability of the first envelope detection circuit is enhanced, and the low-level CMTI ability of the second envelope detection circuit is enhanced.

[0037] Refer to Figure 3, in an embodiment of the present application, the logic processing circuit includes a Schmitt trigger U1, a Schmitt trigger U2, an inverter U3, a NAND gate U4, and a NAND gate U5; The input terminal of the Schmitt trigger U1 is connected to the output terminal of the first envelope detection circuit, and the input terminal of the Schmitt trigger U2 is connected to the output terminal of the second envelope detection circuit; The output terminal of the Schmitt trigger U1 is connected to the first input terminal of the NAND gate U4, the output terminal of the NAND gate U4 is connected to the first input terminal of the NAND gate U5, the output terminal of the Schmitt trigger U2 is connected to the second input terminal of the NAND gate U5 through the inverter U3, the output terminal of the NAND gate U5 is connected to the second input terminal of the NAND gate U4, and the output terminal of the NAND gate U4 is the output terminal of the logic processing circuit.

[0038] In this embodiment, when the signal to be modulated is at a high level, the amplitude of the first differential signal is greater than that of the second differential signal. Therefore, the first envelope detection voltage SF1_A is greater than the second envelope detection voltage SF2_A, the third envelope detection voltage SF1_B is greater than the fourth envelope detection voltage SF2_B, and the output A OUT of the first envelope detection circuit, and OUT the output B OUT of the second envelope detection circuit OUT are both at a high level; when the signal to be modulated is at a low level, the amplitude of the first differential signal is equal to that of the second differential signal. Due to the existence of the resistor R1 and the resistor R4, SF1_A < SF2_A, SF1_B < SF2_B, and the output A

[0039] of the first envelope detection circuit, OUT and the output B OUT of the second envelope detection circuit OUT are both at a low level. OUT On this basis, the output A OUT of the first envelope detection circuit is connected to the Schmitt trigger U1, the output B OUT of the second envelope detection circuit is connected to the Schmitt trigger U2, and the Schmitt trigger U1 and the Schmitt trigger U2 respectively shape and debounce the two output signals of A OUT and B; OUT The NAND gate U4 and the NAND gate U5 are cross-connected to form an RS latch. The first input terminal of the NAND gate U4 is equivalent to the set terminal (S) of the RS latch, and the second input terminal of the NAND gate U5 is equivalent to the reset terminal R of the RS latch. When the signal to be modulated is at a high level, A OUT and B OUT are both at a high level. The set terminal of the RS latch is at a low level and the reset terminal is at a high level. The RS latch performs a set operation and locks the high-level state; when the signal to be modulated is at a low level, A OUT and B OUTBoth are low levels. The set terminal of the RS latch is at a high level and the reset terminal is at a low level. The latch performs a reset action and locks the low level state.

[0040] Therefore, by using the above logic processing circuit, it can be realized that when the signal to be modulated is at a high level, the output signal A of the first envelope detection circuit OUT is latched and output; when the signal to be modulated is at a low level, the output signal B of the second envelope detection circuit OUT is latched and output.

[0041] In an embodiment of the present application, the logic processing circuit further includes an inverter U6; The output terminal of the NAND gate U4 is connected to the input terminal of the inverter U6, and the output terminal of the inverter U6 is the output terminal of the logic processing circuit.

[0042] In this embodiment, according to actual needs, an inverter U6 can be set at the output terminal of the NAND gate U4, and the output signal of the inverter U6 is used as the final output signal.

[0043] In summary, this embodiment uses a dual-channel envelope detection circuit. First, by optimizing the asymmetry of the parameters of the two-channel envelope detection circuit, the CMTI performance of the signal to be modulated at high and low levels is respectively improved; then, by logically processing the output signals of the two-channel envelope detection, the CMTI ability of the driver is effectively improved, and the circuit delay is not increased.

[0044] As Figure 4 shown is the waveform of the key nodes of the demodulation circuit of the present invention. When the signal to be modulated is at a high level, the value of SF1_A - SF2_A > the value of SF1_B - SF2_B, and the value of COMP2_A - COMP1_A > the value of COMP2_B - COMP1_B. Therefore, when a CMT event occurs, each node of the first envelope detection circuit has a greater voltage margin and stronger CMTI ability. When the signal to be modulated is at a low level, the value of SF2_A - SF1_A < the value of SF2_B - SF1_B, and the value of COMP1_A - COMP2_A < the value of COMP1_B - COMP2_B. Therefore, when a CMT event occurs, each node of the second envelope detection circuit has a greater voltage margin and stronger CMTI ability. After the outputs of the two-channel envelope detection circuits are logically processed, the high-level signal of the first envelope detection circuit and the low-level signal of the second envelope detection circuit are finally retained as the final output OUT.

[0045] As Figure 5As shown, the simulation waveforms of key nodes in the demodulation circuit of the capacitor-isolated driver with high CMTI capability are displayed when the CMT is 150V / ns. It can be determined from the figure that under this CMT, the voltage of each node in the first envelope detector circuit and the second envelope detector circuit still has a large voltage margin. The present invention has a CMTI capability of more than 150V / ns.

[0046] Compared with existing technologies, the circuit achieves high CMTI without increasing circuit delay; the circuit structure is simple, easy to implement, does not require a very high carrier frequency, has low delay, can be widely used in capacitive isolation drivers, and has high reliability.

[0047] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A capacitor-type isolated driver demodulation circuit, characterized in that, include: The circuit consists of a first envelope detector circuit, a second envelope detector circuit, and a logic processing circuit. The input terminals of the first envelope detection circuit and the second envelope detection circuit are respectively used to connect to the modulated carrier differential signal; wherein, the modulated carrier differential signal is obtained by amplitude modulation of the signal to be modulated; The first envelope detection circuit and the second envelope detection circuit have the same circuit structure but different circuit parameters, such that: when the signal to be modulated is high, the common-mode transient immunity of the first envelope detection circuit is greater than that of the second envelope detection circuit; and when the signal to be modulated is low, the common-mode transient immunity of the second envelope detection circuit is greater than that of the first envelope detection circuit. The output terminal of the first envelope detection circuit is connected to the first input terminal of the logic processing circuit, and the output terminal of the second envelope detection circuit is connected to the second input terminal of the logic processing circuit. The logic processing circuit is configured to: latch and output the output signal of the first envelope detection circuit when the signal to be modulated is high; and latch and output the output signal of the second envelope detection circuit when the signal to be modulated is low.

2. The capacitor-isolated driver demodulation circuit as described in claim 1, characterized in that, The modulated carrier differential signal includes a first differential signal and a second differential signal. When the signal to be modulated is at a high level, the amplitude of the first differential signal is greater than the amplitude of the second differential signal. When the signal to be modulated is at a low level, the amplitudes of the first differential signal and the second differential signal are equal. The first envelope detection circuit includes a first envelope comparison branch, a second envelope comparison branch, and a first comparison circuit; the first differential signal is connected to the differential input terminal of the first envelope comparison branch, the second differential signal is connected to the differential input terminal of the second envelope comparison branch, the output terminal of the first envelope comparison branch and the output terminal of the second envelope comparison branch are respectively connected to the two input terminals of the first comparison circuit, and the output terminal of the first comparison circuit is the output terminal of the first envelope detection circuit; The second envelope detection circuit includes a third envelope comparison branch, a fourth envelope comparison branch, and a second comparison circuit; the first differential signal is also connected to the differential input terminal of the third envelope comparison branch, the second differential signal is also connected to the differential input terminal of the fourth envelope comparison branch, the output terminals of the third and fourth envelope comparison branches are respectively connected to the two input terminals of the second comparison circuit, and the output terminal of the second comparison circuit is the output terminal of the second envelope detection circuit; The first envelope comparison branch includes transistor M1, transistor M2, resistor R1, and current source I. 11 With capacitor C1, the gates of transistor M1 and M2 are the differential input terminals of the first envelope comparator branch. The drains of transistor M1 and M2 are connected to a DC power supply. The sources of transistor M1 and M2 are connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the current source I. 11 The second terminal of the resistor R1 is also grounded through the capacitor C1; The second envelope comparison branch includes transistor M3, transistor M4, and current source I. 12 And capacitor C2; the gates of transistor M3 and transistor M4 are the differential input terminals of the second envelope comparator branch, the drains of transistor M3 and transistor M4 are connected to the DC power supply, and the sources of transistor M3 and transistor M4 are connected to the current source I. 12 The first end, the current source I 12 The second terminal is grounded, and the source of transistor M3 and the source of transistor M4 are also grounded through capacitor C2; The third envelope comparison branch includes transistor M11, transistor M12, resistor R4, and current source I. 13 With capacitor C3, the gates of transistors M11 and M12 are the differential input terminals of the third envelope comparator branch. The drains of transistors M11 and M12 are connected to a DC power supply, and the sources of transistors M11 and M12 are connected to the first terminal of resistor R4. The second terminal of resistor R4 is connected to the current source I. 13 The second terminal of the resistor R4 is also grounded through the capacitor C3; The fourth envelope comparison branch includes transistor M13, transistor M14, and current source I. 14 And capacitor C4; the gates of transistor M13 and M14 are the differential input terminals of the fourth envelope comparator branch; the drains of transistor M13 and M14 are connected to a DC power supply; and the sources of transistor M13 and M14 are connected to the current source I. 14 The first end, the current source I 14 The second terminal is grounded, and the source of transistor M13 and the source of transistor M14 are also grounded through capacitor C4; The resistance value of resistor R1 is less than the resistance value of resistor R4.

3. The capacitor-isolated driver demodulation circuit as described in claim 2, characterized in that, The first comparison circuit includes a first comparator, a second comparator, and a first decision output circuit connected in sequence; the second comparison circuit includes a third comparator, a fourth comparator, and a second decision output circuit connected in sequence. The first comparator includes transistor M5, transistor M6, and current source I. 21 Resistors R2 and R3, the gates of transistors M5 and M6 respectively serve as the two input terminals of the first comparator circuit, and the sources of transistors M5 and M6 are connected to the current source I. 21 The first end, the current source I 21 The second terminal is connected to a DC power supply. The drain of transistor M5 is grounded through resistor R2, and the drain of transistor M6 is grounded through resistor R3. The second comparator includes transistor M7, transistor M8, and current source I. 22 Transistors M9 and M10 are connected. The drain of transistor M6 is connected to the gate of transistor M7, and the drain of transistor M5 is connected to the gate of transistor M8. The sources of transistors M7 and M8 are connected to the current source I. 22 The first end, the current source I 22 The second terminal is connected to a DC power supply. The drain of transistor M7 is connected to the drain of transistor M9. The drain of transistor M8 is connected to the drain of transistor M10. The gates of transistor M9 and M10 are connected to the drain of transistor M9. The sources of transistor M9 and M10 are both grounded. The first decision output circuit includes transistor M21 and current source I. 31 The drain of transistor M10 is connected to the gate of transistor M21, the source of transistor M21 is grounded, and the drain of transistor M21 is connected to the current source I. 31 The first end, the current source I 31 The second terminal is connected to a DC power supply, and the drain of the transistor M21 is the output terminal of the first comparator circuit; The third comparator includes transistor M15, transistor M16, and current source I. 23 Resistors R5 and R6 are used. The gates of transistors M15 and M16 serve as the two input terminals of the second comparator circuit, respectively. The sources of transistors M15 and M16 are connected to the current source I. 23 The first end, the current source I 23 The second terminal is connected to a DC power supply. The drain of transistor M15 is grounded through resistor R5, and the drain of transistor M16 is grounded through resistor R6. The fourth comparator includes transistor M17, transistor M18, and current source I. 24 Transistors M19 and M20 are used. The drain of transistor M16 is connected to the gate of transistor M17, and the drain of transistor M15 is connected to the gate of transistor M18. The sources of transistors M17 and M18 are connected to the current source I. 24 The first end, the current source I 24 The second terminal is connected to a DC power supply. The drain of transistor M17 is connected to the drain of transistor M19. The drain of transistor M18 is connected to the drain of transistor M20. The gates of transistor M19 and M20 are both connected to the drain of transistor M19. The sources of transistor M19 and M20 are both grounded. The second decision output circuit includes transistor M22 and current source I. 32 The drain of transistor M20 is connected to the gate of transistor M22, the source of transistor M22 is grounded, and the drain of transistor M22 is connected to the current source I. 32 The first end, the current source I 32 The second terminal is connected to a DC power supply, and the drain of the transistor M22 is the output terminal of the second comparator circuit.

4. The capacitor-isolated driver demodulation circuit as described in claim 3, characterized in that, The resistance value of resistor R2 is less than the resistance value of resistor R3, and the aspect ratio of transistor M9 is greater than the aspect ratio of transistor M10. The resistance value of resistor R5 is equal to the resistance value of resistor R3, the resistance value of resistor R6 is equal to the resistance value of resistor R2, the aspect ratio of transistor M9 is equal to the aspect ratio of transistor M20, and the aspect ratio of transistor M10 is equal to the aspect ratio of transistor M19.

5. The capacitor-isolated driver demodulation circuit as described in claim 1, characterized in that, The logic processing circuit includes a Schmitt trigger U1, a Schmitt trigger U2, an inverter U3, a NAND gate U4, and a NAND gate U5; The input terminal of the Schmitt trigger U1 is connected to the output terminal of the first envelope detection circuit, and the input terminal of the Schmitt trigger U2 is connected to the output terminal of the second envelope detection circuit. The output of Schmitt trigger U1 is connected to the first input of NAND gate U4, the output of NAND gate U4 is connected to the first input of NAND gate U5, the output of Schmitt trigger U2 is connected to the second input of NAND gate U5 through inverter U3, the output of NAND gate U5 is connected to the second input of NAND gate U4, and the output of NAND gate U4 is the output of the logic processing circuit.

6. The capacitor-isolated driver demodulation circuit as described in claim 5, characterized in that, The logic processing circuit also includes an inverter U6; The output of the NAND gate U4 is connected to the input of the inverter U6, and the output of the inverter U6 is the output of the logic processing circuit.

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