A driving circuit for a power device

Abstract

This invention discloses a driving circuit for a power device, including a negative voltage capacitor circuit, a pre-charge module, a power output stage, and a charging pull-down module. The negative voltage capacitor circuit provides a negative voltage for turning off the gate of the power device when the received unipolar output drive signal is a turn-off signal. The pre-charge module pre-charges the negative voltage capacitor circuit. The power output stage outputs a unipolar output drive signal to the negative voltage capacitor circuit according to the input signal. The charging pull-down module pulls the gate voltage of the power device to ground during pre-charging and replenishes the charge of the output capacitor when the power output stage outputs the unipolar output drive signal. This invention, while ensuring a simple, reliable, low-pin-count, and low-power structure, can effectively generate a negative voltage turn-off signal, ensuring the power device topology's anti-interference capability against voltage spikes under high-speed switching and improving the reliability of driving the power device topology.

Description

Technical Field

[0001] This invention belongs to the field of power integrated circuit technology, and specifically relates to a driving circuit for a power device. Background Technology

[0002] With the rapid development of wide-bandgap semiconductor power devices, represented by silicon carbide and gallium nitride, power electronics technology is undergoing a profound transformation towards high frequency, high efficiency, and high power density. Wide-bandgap semiconductor devices, with their superior material properties such as high breakdown field strength, high electron saturation drift velocity, and high thermal conductivity, have brought revolutionary performance improvements to various power conversion topologies—including but not limited to half-bridge, full-bridge, LLC resonant, and totem-pole PFC—leading to their widespread application in high-performance fields such as new energy vehicles, photovoltaic energy storage, industrial drives, and data center power supplies.

[0003] However, while wide-bandgap semiconductor devices offer significant advantages, they also place more stringent demands on the design of their drive circuits. Compared to traditional silicon-based devices, wide-bandgap semiconductor devices have two key characteristics: first, extremely fast switching speeds (extremely high dV / dt and dI / dt); and second, typically low gate threshold voltages and limited allowable negative withstand voltages. These characteristics collectively lead to a significant challenge in complex topologies such as bridge circuits—the risk of mis-enabling due to gate crosstalk.

[0004] For example, in a bridge circuit, when the switch in one arm is turned off at high speed, its rapidly changing drain-source voltage generates a significant displacement current through the inherent parasitic capacitance between the upper and lower arms (such as Miller capacitance). This current couples into the gate circuit of the turn-off arm, inducing a voltage spike across its gate and source. For wide-bandgap semiconductor devices with low threshold voltages, this coupled voltage spike can easily exceed its turn-on threshold, causing the device to be accidentally "mistakenly turned on," resulting in a momentary shoot-through between the upper and lower arms, generating huge short-circuit currents and heat, seriously threatening the reliability of the circuit.

[0005] To fundamentally suppress gate crosstalk and the risk of false turn-on caused by extremely high switching speeds, negative gate turn-off drive technology has become a key safeguard for the application of wide-bandgap semiconductor devices. Applying a negative gate voltage during turn-off provides a reliable turn-off voltage margin, enhancing the circuit's anti-interference capability. Furthermore, negative gate drive can accelerate turn-off speed and reduce turn-off losses. In summary, negative gate turn-off drive circuits can fully leverage the high-frequency and high-efficiency advantages of wide-bandgap semiconductor devices and ensure the safe and reliable operation of advanced topologies such as bridge circuits in high-performance applications.

[0006] A typical application of a power device drive circuit is as follows: Figure 1As shown, the driver circuit receives logic control signals and generates valid drive signals, which are transmitted to the gate of the power device to drive its turn-on and turn-off. If a conventional unipolar positive voltage drive is used, the high-speed switching of the half-bridge topology causes a sharp change in the drain voltage of the lower transistor. The HS node generates a very high voltage change dV / dt, which is coupled to the gate through the parasitic capacitance of the power device, generating a significant crosstalk voltage spike. This spike may cause the gate-source voltage of the power device to exceed its threshold voltage, leading to mis-turn-on of the upper bridge arm, resulting in a shoot-through short circuit between the upper and lower bridge arms, generating huge loss current and heat, threatening circuit reliability. Furthermore, the slight oscillation of the gate-source voltage difference near 0V also increases turn-off losses. Therefore, to fundamentally suppress mis-turn-on, improve switching robustness, and fully utilize the high-frequency performance advantages of wide-bandgap semiconductor devices, it is necessary to use a drive scheme with negative voltage turn-off capability.

[0007] Existing publicly available embodiments (patent authorization announcement number: CN108539964B), such as Figure 2 As shown, its negative pressure generation relies on an additional negative pressure charge pump circuit, which makes the chip structure more complex and the static power consumption greater.

[0008] Therefore, there is an urgent need for a simple, reliable, low-pin-count, and low-power integrated circuit solution to achieve negative voltage drive of semiconductor power devices. Summary of the Invention

[0009] The purpose of this invention is to provide a driving circuit for power devices that, while ensuring a simple, reliable structure, low pin count, and low power consumption, can effectively generate a negative voltage turn-off signal, ensuring the power device topology's ability to resist voltage spikes during high-speed switching and improving the reliability of driving the power device topology.

[0010] To achieve the above objectives, the solution of the present invention is:

[0011] A driving circuit for a power device includes a negative voltage capacitor circuit, a pre-charge module, a power output stage, and a charging pull-down module;

[0012] The output terminal of the negative voltage capacitor circuit is connected to the gate of the power device, and is used to provide a negative voltage to the gate of the power device to turn off the power device when the received unipolar output drive signal is a turn-off signal.

[0013] The pre-charging module is used to pre-charge the negative voltage capacitor circuit.

[0014] The power output stage is used to output a unipolar output drive signal to the negative voltage capacitor circuit according to the input signal;

[0015] The charging pull-down module is used to pull down the gate voltage of the power device to ground when the pre-charging module pre-charges the negative voltage capacitor circuit, and to replenish the charge of the negative voltage capacitor circuit when the power output stage outputs a unipolar output drive signal to the negative voltage capacitor circuit.

[0016] The aforementioned pre-charge module includes a power-on signal generation unit, a second inverter, and a second high-voltage resistant thick-gate NMOS transistor. The power-on signal generation unit is connected to the power signal of the low / high voltage domain power rail and is used to generate a power-on signal during the power-on process of the power signal. The input terminal of the second inverter is connected to the output terminal of the power-on signal generation unit, and its output terminal is connected to the gate of the second high-voltage resistant thick-gate NMOS transistor. The second inverter is powered by a clamping control input signal. The drain of the second high-voltage resistant thick-gate NMOS transistor is connected to the power signal of the high voltage domain power rail, and its source is connected to a negative voltage capacitor circuit.

[0017] The aforementioned power-on signal generation unit includes a first resistor, a first capacitor, a first Schmitt trigger, a first PMOS transistor, a first NMOS transistor, and a first inverter. The source of the first PMOS transistor is connected to the power signal of the low / high voltage power rail, its gate is connected to ground, and its drain is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the drain of the first NMOS transistor, the first terminal of the first capacitor, and the input terminal of the first Schmitt trigger. The gate and source of the first NMOS transistor are both connected to ground, and the second terminal of the first capacitor is connected to ground. The output terminal of the first Schmitt trigger is connected to the input terminal of the first inverter, and the output terminal of the first inverter serves as the output terminal of the power-on signal generation unit, connected to the input terminal of the second inverter.

[0018] The aforementioned charging pull-down module includes a first diode, a series diode array, a first pull-down switch, and a third high-voltage thin-gate NMOS transistor. The series diode array consists of several diodes connected in series in the same direction. The gate of the third high-voltage thin-gate NMOS transistor is used to connect a logic control signal to adjust the charging time of the negative voltage capacitor circuit. The source of the third high-voltage thin-gate NMOS transistor is connected to ground, and its drain is connected to the cathode of the first diode and the anode of the series diode array, respectively. The cathode of the series diode array and the anode of the first diode are used to output a negative voltage output signal to the negative voltage capacitor circuit. The first pull-down switch is connected to the anode of the first diode and, based on the output signal of the power-on signal generation unit, pulls the output port level of the charging pull-down module low to ground during the pre-charging process.

[0019] The aforementioned driving circuit also includes a feedback control module; wherein the feedback control module is used to generate logic control signals, including a first comparator, a third inverter, a second AND gate, a first NAND gate, and a third buffer, wherein the input terminal of the first comparator is connected to the output terminal of the pre-charge module, and its output terminal is connected to the first input terminal of the second AND gate; the input terminal of the third inverter is connected to the input signal, and its output terminal is connected to the second input terminal of the second AND gate; the output terminal of the second AND gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the output terminal of the power-on signal generation unit, and its output terminal is connected to the input terminal of the third buffer, and the output terminal of the third buffer is connected to the input terminal of the charging pull-down module.

[0020] The aforementioned power output stage includes a first high-voltage resistant thin-gate NMOS transistor and a high-voltage resistant PMOS transistor. The source of the high-voltage resistant PMOS transistor is connected to the power signal of the high-voltage power rail, and its drain is connected to the drain of the first high-voltage resistant thin-gate NMOS transistor, serving as the output terminal of the power output stage and connected to the negative voltage capacitor circuit. The high-voltage resistant PMOS transistor conducts when the power device is turned on according to the input signal. The source of the first high-voltage resistant thin-gate NMOS transistor is grounded to the input signal, and conducts when the input signal is a pull-down signal.

[0021] The aforementioned high-voltage PMOS transistor is connected to the input signal through a first OR gate and a first buffer. The first input terminal of the first OR gate is connected to the input signal, the second input terminal is connected to the output terminal of the power-on signal generation unit, the output terminal of the first OR gate is connected to the input terminal of the first buffer, and the output terminal of the first buffer is connected to the gate of the high-voltage PMOS transistor.

[0022] A level shifting circuit is also connected between the first OR gate and the first buffer. The power supply terminal of the level shifting circuit is connected to the power signal of the high-voltage power rail, and its ground terminal is connected to the ground signal. It is used to convert the input level from the low-voltage domain to the high-voltage domain.

[0023] The aforementioned first high-voltage resistant thin-gate NMOS transistor is connected to the input signal through a first AND gate and a second buffer. The first input terminal of the first AND gate is connected to the input signal, the second input terminal is connected to the output terminal of the power-on signal generation unit, and the output terminal of the first AND gate is connected to the gate of the first high-voltage resistant thin-gate NMOS transistor.

[0024] The aforementioned negative voltage capacitor circuit includes a gate resistor and an output capacitor. The first end of the gate resistor is connected to the output terminal of the power output stage, the second end of the gate resistor is connected to the first end of the output capacitor, the second end of the output capacitor is connected to the gate of the power device, and the second end of the output capacitor is also connected to the output terminal of the charging pull-down module.

[0025] After adopting the above scheme, the input terminal of the present invention receives the input signal and outputs the corresponding unipolar output drive signal at the unipolar output port through the internal power output structure of the drive circuit; the circuit is provided with a unipolar output port and a negative voltage output port, and the two output ports are connected by a negative voltage capacitor circuit; the negative voltage capacitor circuit is used to provide a negative voltage for turning off the power device to the first electrode when the unipolar output drive signal is a turn-off signal.

[0026] Compared with the prior art, the main differences and effects of the present invention are as follows:

[0027] (1) A negative voltage turn-off signal is generated to ensure that the power device will not be mis-turned on due to crosstalk voltage spikes, thereby improving the drive signal's ability to resist voltage spike crosstalk.

[0028] (2) It can precharge the output capacitor in the negative voltage capacitor circuit during the power-on process of the circuit to ensure the rapid establishment of the negative voltage shutdown function.

[0029] (3) It can control the charging level of the output capacitor by setting the clamp control input signal, so as to prevent the output capacitor from being overcharged.

[0030] (4) When the power device starts to conduct, one end of the output capacitor can be connected to ground, and the output capacitor can be briefly charged by the power output stage to maintain its charge. No additional negative voltage charge pump is required. The structure is simple and the power consumption is low.

[0031] (5) The negative voltage value of the power device can be adjusted by changing the number of series-connected anti-backflow diodes in the charging pull-down module.

[0032] (6) The power device gate can be pulled down to ground during the pre-charging process by the initial pull-down switch in the charging pull-down module, so as to ensure that the power device will not be turned on by mistake. Attached Figure Description

[0033] Figure 1 This is a typical application diagram of a driving circuit for an existing power device;

[0034] Figure 2 This is a schematic diagram of an embodiment of a drive circuit with negative pressure drive function given in the prior art;

[0035] Figure 3 This is a block diagram of a driving circuit for a power device according to an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a driving circuit for a power device according to an embodiment of the present invention;

[0037] Figure 5This is a specific example diagram of a driving circuit for a power device provided according to an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the operating waveform of a driving circuit for a power device according to an embodiment of the present invention;

[0039] Figure 7 This is a timing diagram of the feedback control module and its control logic in a drive circuit of a power device according to an embodiment of the present invention. Detailed Implementation

[0040] In the following description, numerous technical details are provided to facilitate the reader's understanding of this application. However, those skilled in the art will understand that the technical solutions claimed in the claims of this application can be implemented even without these technical details and with various variations and modifications based on the following embodiments.

[0041] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0042] The first embodiment of the present invention relates to a driving circuit for a power device. Figure 3 This is a block diagram of the drive circuit of the power device.

[0043] Specifically, such as Figure 3 As shown, this drive circuit, combined with the negative voltage capacitor circuit 006, can achieve negative voltage shutdown. Internally, it includes a power output stage 001 controlled by the input signal, a pre-charge module 002, a charging pull-down module 004, and a feedback control module 005. This circuit can pre-charge the output capacitor within the negative voltage capacitor circuit through the pre-charge module and the charging pull-down module, solving the problem of slow establishment of the negative voltage shutdown function upon initial power-on. When the power device is turned on, the charging pull-down module connects one end of the output capacitor to ground, and the power output stage provides charge to the output capacitor to generate a negative voltage when the power device is turned off.

[0044] The pre-charge module of this circuit includes a clamp control input signal (Vclamp) to address the issue of overcharging of the output capacitor.

[0045] The pre-charge module of this circuit includes a power-on signal generation unit. The generated power-on signal is output to the charging pull-down module for pre-charging the output capacitor and ensuring that the power devices remain off when the drive circuit is initially powered on.

[0046] The charging pull-down module of this circuit includes a switching device controlled by a feedback control module, a series array of diodes to prevent reverse current from flowing in and out, and an initial pull-down switch.

[0047] The number of anti-backflow diodes in the series array of the charging pull-down module of this circuit is determined by the required turn-off negative voltage; the higher the absolute voltage, the more diodes are connected in series.

[0048] The circuit's charging pull-down module includes an initial pull-down switch that is only activated during pre-charging, and there is no body diode between the two terminals of this switch. For example, this switch could be a P-channel JFET device.

[0049] Figure 4 This is a schematic diagram of a driving circuit for a power device according to an embodiment of the present invention. Figure 4 As shown, the input port of the driving circuit receives the driving signal, and through the internal power output stage of the driving circuit, outputs the corresponding unipolar output driving signal at the unipolar output port OUT. The circuit has a unipolar output port OUT and a negative voltage output port NegOUT, connected by an output capacitor C2. The output capacitor C2 and the gate resistor RG together constitute the negative voltage capacitor circuit 406 of this embodiment. The output capacitor C2 is used to provide a negative voltage to the first electrode of the power device to turn off the power device when the unipolar output driving signal is a turn-off signal. Besides the negative voltage capacitor circuit 406 outside the IC integrated circuit, the internal driving circuit of the power device includes: a pre-charge module 402, a level shifting circuit, a buffer, a power output stage 401, a charging pull-down module 404, a feedback control module 405, and a logic control unit.

[0050] Output capacitor C2 is used to generate a negative voltage output signal at the negative voltage generation port NegOUT;

[0051] The precharge module 402 includes a power-on signal generation unit 403, which is used to generate a power-on signal during the power-on process of the power signal VDD of the low-voltage domain power rail.

[0052] The pre-charge module 402 pre-charges the output capacitor C2 of the negative voltage capacitor circuit during the power-on process of the power signal VDD of the low voltage domain power rail, based on the power-on signal generated by the internal power-on signal generation unit 403.

[0053] Level shifting circuits are used to convert the level of input drive signals from the low voltage domain (VSS ~ VDD) to the high voltage domain (VSS ~ VCC);

[0054] The buffer is used to drive the large-size MOSFETs in the power output stage and the large-size MOSFETs in the charging pull-down module;

[0055] The power output stage is used to receive the input control signal from the front stage and convert the input control signal into a unipolar output drive signal;

[0056] The charging pull-down module 404 is used to receive charging control signals and control the charging process of the output capacitor;

[0057] The feedback control module 405 is used to receive the negative voltage drive signal from the negative voltage output port and generate a charging control signal for the output capacitor C2.

[0058] The logic control unit is used for related logic control.

[0059] The core part is that the circuit forms a negative voltage generation topology through the negative voltage capacitor circuit 406, the pre-charge module 402, the charging pull-down module 404, and the feedback control module 405. This topology can generate a negative voltage drive signal at the negative voltage output port.

[0060] For ease of understanding, the negative voltage generation topology can be further divided into a pre-charging topology and a feedback pull-down topology. The pre-charging topology includes the initial pull-down switch of the pre-charging module 402 and the charging pull-down module 404. Its function is to pre-charge the output capacitor C2 inside the negative voltage capacitor circuit 406 during power-on, ensuring that the output capacitor C2 stores a certain amount of charge, thus solving the problem of slow establishment of the negative voltage shutdown function upon initial power-on.

[0061] In addition, the feedback pull-down topology includes other structures such as the feedback control module 405 and the charging pull-down module 404. Its function is to detect the circuit status in real time, generate a negative voltage clamping level at the negative voltage output port NegOUT when the unipolar output is low, and briefly charge the output capacitor C2 when the power device is turned on to maintain the charge of the output capacitor C2 for generating a negative voltage when the power device is turned off.

[0062] The above describes the circuit modules involved in the core idea of ​​this invention. To further illustrate the technical solution of this invention, Figure 5 A specific example diagram of a driving circuit for a power device provided in an embodiment of the present invention is shown.

[0063] like Figure 5As shown, in one embodiment of the present invention, the power-on signal generation unit 503 in the pre-charge module 502 includes: a first resistor R1, a first capacitor C1, a first Schmitt trigger ST1, a first PMOS transistor PM1, a first NMOS transistor NM1, and a first inverter INV1. The branch formed by the first resistor R1 and the first capacitor C1 connected in series determines the duration of the generated power-on signal. The first PMOS transistor PM1 acts as a current limiter, and the first NMOS transistor NM1 remains off, making the upper plate of the first capacitor C1 have a high resistance to ground. The first Schmitt trigger ST1 flips when the voltage level at the upper plate of the first capacitor C1 rises to the trigger threshold, outputting a power-on signal. The first inverter INV1 receives this power-on signal and outputs an inverted power-on signal.

[0064] The power-on signal generation unit 503 is connected as follows: the source of the first PMOS transistor PM1 is connected to the power signal VDD of the low-voltage domain power rail, the gate is connected to the ground signal VSS, and the drain is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the first capacitor C1 and the input of the first Schmitt trigger ST1. The other end of the first capacitor C1 is connected to the ground signal VSS. The output of the first Schmitt trigger ST1 is connected to the input of the first inverter INV1 and the input of other modules. The output of the first inverter INV1 is connected to the input of other modules.

[0065] In one embodiment of the present invention, the pre-charge module 502, in addition to the power-on signal generation unit 503, also includes: a second inverter INV2 and a second high-voltage resistant thick-gate NMOS transistor HMN2. The module turns on the second high-voltage resistant thick-gate NMOS transistor HMN2 during the power-on process according to the power-on signal generated by the power-on signal generation unit 503, and pre-charges the output capacitor C2.

[0066] The precharge module 502 is connected as follows: the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output is connected to the gate of the second high-voltage thick-gate NMOS transistor HMN2; the second inverter INV2 is powered by the clamp control input signal (Vclamp); the drain of the second high-voltage thick-gate NMOS transistor HMN2 is connected to the power signal VCC of the high-voltage power rail, the source is connected to the chip output port OUT and one end of the gate resistor RG, and the other end of the gate resistor RG is connected to one end of the output capacitor C2.

[0067] In one embodiment of the present invention, the charging pull-down module 504 includes: a first diode D1, a series diode array consisting of a second diode to an Nth diode (D2 ~ DN) connected in series, a first pull-down switch K1 (which can be a P-channel JFET device), and a third high-voltage thin-gate NMOS transistor HMN3. The third high-voltage thin-gate NMOS transistor HMN3 receives a logic control signal to control the charging time of the output capacitor C2. The first diode D1 and the series diode array consisting of the second diode to the Nth diode (D2 ~ DN) together form a reverse-current protection diode series array, which not only ensures effective charging and discharging of the output capacitor C2, but also clamps the negative voltage output level of the negative voltage output port NegOUT, ensuring a stable output negative voltage level. The diagram shows the second diode to the Nth diode (D2 ~ DN) connected in series. The number of diodes in the series diode array (DN) is determined by the required turn-off negative voltage. The higher the absolute voltage of the required turn-off negative voltage, the more series diodes are required. The first pull-down switch K1 serves as the initial pull-down switch in the charging pull-down module. It is only turned on during the pre-charging process to ensure that the output level of the NegOUT port is pulled down to VSS during the pre-charging process, and will not output an erroneous high-level drive signal. It also provides a pre-charging ground path for the output capacitor C2. Since there is no body diode between the two terminals of the first pull-down switch K1, it will not affect the negative voltage output level of the negative voltage output port NegOUT during normal operation.

[0068] The connection relationship of the charging pull-down module 504 is as follows: the cathode of the second diode D2 and the anode of the first diode D1 are connected to the negative voltage output port NegOUT of the chip and the other end of the output capacitor C2; the anode of the second diode D2 is connected to the cathode of the series diode, and the series diode array maintains the series connection relationship of anode to cathode until it is connected to the cathode of the Nth diode DN; the anode of the Nth diode DN is connected to the cathode of the first diode D1 and the drain of the third high voltage resistant thin-gate NMOS transistor HMN3; the gate of the third high voltage resistant thin-gate NMOS transistor HMN3 is connected to the output of the third buffer BUF3, and the source is connected to the ground signal VSS; one terminal of the first pull-down switch K1 is connected to the ground signal VSS, and the other terminal is connected to the negative voltage output port NegOUT of the chip.

[0069] In one embodiment of the present invention, the feedback control module 505 includes: a first comparator COMP1, a third inverter INV3, a second AND gate AND2, a first NAND gate AND2, and a third buffer BUF3. The first comparator COMP1 receives the output signal from the chip output port OUT, compares it with a threshold set by the comparator, generates a comparison signal, and inputs it to the logic circuit composed of the third inverter INV3 and the second AND gate AND2 to generate a logic signal for controlling the third high-voltage thin-gate NMOS transistor HMN3 in the charging pull-down module. When the power-on process ends, the first AND gate NAND1 allows the logic signal to pass through, and the logic signal is then used by the third buffer BUF3 to control the conduction and turn-off of HMN3, thereby controlling the charging and discharging process of the output capacitor C2.

[0070] The feedback control module 505 is connected as follows: the input of the first comparator COMP1 is connected to the chip output port OUT, and the output is connected to one input of the second AND gate AND2; the other input of the second AND gate AND2 is connected to the output of the third inverter INV3; the output of the second AND gate AND2 is connected to one input of the first NAND gate; the power-on signal is connected to the other input of the first NAND gate; the output of the first NAND gate is connected to the third buffer BUF3; the output of the third buffer BUF3 is connected to the gate of the third high-voltage thin-gate NMOS transistor HMN3; and the input of the third inverter INV3 is connected to the input port IN.

[0071] Combination Figure 4 and Figure 5 The working principle of a driving circuit for a power device provided in this embodiment of the invention is described in detail below. The driving circuit for a power device provided in this embodiment of the invention, combined with an output capacitor, can achieve negative voltage shutdown.

[0072] The power device driving circuit provided in this embodiment of the invention, compared to a traditional unipolar power device driving circuit, adds a pre-charge module 402 (including a power-on signal generation unit 403), a charging pull-down module 404, a feedback control module 405, a negative voltage capacitor circuit 406, and corresponding logic units (inverter, OR gate, AND gate). The working principle is as follows: The specific implementation of the power-on signal generation unit 403 in the pre-charge module 402 is as follows: Figure 5As shown in Figure 503, the circuit consists of a resistor R1, a capacitor C1, a first Schmitt trigger ST1, a first PMOS transistor PM1, a first NMOS transistor NM1, and a first inverter INV1. The power-on signal generation unit outputs a power-on signal VPOR that remains low for a certain period of time, then transitions to a high level. This high level signal is then inverted by the inverter INV1 to generate an inverted power-on signal VN. The duration of the low level is related to the rise rate of the voltage across the upper plate of capacitor C1. Adjusting the resistance of resistor R1 and the capacitance of capacitor C1 can change the duration of the low level of the power-on signal VPOR. This power-on signal is used to control the pre-charging process. When the power-on signal VPOR is low, it controls the high-voltage thick-gate NMOS transistor HMN2 to conduct via the inverter INV2, pre-charging the output capacitor C2. Furthermore, this signal controls the first pull-down switch K1 to conduct, thereby pulling down the output level of the negative voltage output port NegOUT to VSS during the pre-charging phase. This prevents the power device from being mis-energized and provides a pre-charging path for the output capacitor C2.

[0073] Specific implementation of pre-charge module 402, for example Figure 5 As shown, the circuit consists of a power-on signal generation unit 503, an inverter INV2, and a high-voltage thick-gate NMOS transistor HMN2. The inverter INV2 is powered by a clamping control input signal (Vclamp) to ensure its output voltage equals a high level of Vclamp, used for pre-charge clamping. When the pre-charge module receives a low-level signal from the power-on signal generation unit, the inverter INV2 outputs a high level equivalent to Vclamp, driving the high-voltage thick-gate NMOS transistor HMN2 to conduct. The source of the high-voltage thin-gate NMOS transistor HMN2 is clamped at the level of the clamping control input signal minus the on-state voltage drop of the second high-voltage thick-gate NMOS transistor HMN2, i.e., (Vclamp - Vth), pre-charging the output capacitor C2 until the output signal of the power-on signal generation unit switches, turning off the high-voltage thick-gate NMOS transistor HMN2, marking the end of the pre-charge process. The significance of the clamping control input signal is to ensure that the output capacitor C2 is not overcharged during the pre-charge process.

[0074] Specific implementation of charging pull-down module 404, for example Figure 5As shown in Figure 504, it consists of diodes D1-DN, a high-voltage resistant thin-gate NMOS transistor HMN3, and a first pull-down switch K1. During the pre-charging phase, the power-on signal generation unit generates a power-on signal, which controls the first pull-down switch K1 to remain on during the pre-charging process, thereby pulling the level of NegOUT down to VSS and preventing the output of an erroneous high-level drive signal, thus preventing the power device from being mis-energized. In addition, during the pre-charging process, there is a charging path from the power signal VCC of the high-voltage domain power rail through the high-voltage resistant thick-gate NMOS transistor HMN2, the output capacitor C2, the first pull-down switch K1 to ground, which can effectively pre-charge the output capacitor C2.

[0075] During normal operation, whenever the power device is turned on, a short pulse signal is generated through the feedback control module 505 and related logic units to briefly turn on the high-voltage NMOS transistor HMN3. At the same time, the high-voltage PMOS transistor HMP1 in the output stage is also turned on by the input signal. At this time, there is a charging path from the power signal VCC of the high-voltage power rail through the high-voltage PMOS transistor HMP1, the output capacitor C2, the diode D1, the high-voltage thin-gate NMOS transistor HMN3 to ground, which briefly charges the output capacitor C2, thereby maintaining the charge of the output capacitor C2.

[0076] When a pull-down signal is input to the IN port, the high-voltage thin-gate NMOS transistor HMN1 is turned on by the preceding drive logic. The unipolar output port OUT is pulled down to ground VSS by the high-voltage thin-gate NMOS transistor HMN1, meaning the upper plate of the output capacitor C2 is pulled down to ground VSS. Since the voltage drop across the capacitor cannot change abruptly, the level of the lower plate of the output capacitor C2, i.e., the negative voltage output port of the circuit, is also pulled down to a negative voltage, thus generating a negative voltage output at the negative voltage output port NegOUT. At the same time, there is a path from the body diode of the high-voltage thin-gate NMOS transistor HMN3 through the second diode to the Nth diode (D2 ~ DN) connected in series to the negative voltage output port NegOUT. This path has a clamping effect, ensuring the stability of the output negative voltage level.

[0077] Specific implementation of feedback control module 405, for example Figure 5As shown in Figure 505, this module consists of comparator COMP1, inverter INV3, AND gate AND2, NAND gate AND1, and buffer BUF3. This module is mainly used during normal operation to control the brief conduction time of the high-voltage thin-gate NMOS transistor HMN3 in the charging pull-down module 504. During normal operation, the start-on time of the high-voltage thin-gate NMOS transistor HMN3 is determined by the input signal at the input port IN: when the input signal at the input port IN changes from high to low, since the initial state of the unipolar output port signal is low, comparator COMP1 outputs a high level. Simultaneously, the input signal passes through inverter INV3 and outputs a high level. These two high levels enter the second AND gate AND2, which outputs a high-level signal, causing the high-voltage thin-gate NMOS transistor HMN3 to start conducting, and the output capacitor C2 is briefly charged to maintain its charge.

[0078] During normal operation, the turn-off time of the high-voltage thin-gate NMOS transistor HMN3 is determined by the output of comparator COMP1: when the input signal at input port IN changes from high to low, the output stage high-voltage thin-gate NMOS transistor HMN1 turns off, and the high-voltage PMOS transistor HMP1 turns on. The level of the unipolar output port OUT gradually increases. When the level of this port is pulled high enough to exceed the internal threshold Vneg_ref set by the comparator, the output of comparator COMP1 flips to low, causing the output of AND gate AND2 to become low. Through buffer BUF3, the high-voltage NMOS transistor HMN3 is turned off. The circuit can briefly charge the output capacitor C2 in each switching cycle to maintain its charge. The clamping structure formed by the body diode of the high-voltage thin-gate NMOS transistor HMN3 and the series connection of diodes D2-DN ensures that the turn-off signal output at the negative voltage output port NegOUT can be clamped at a relatively stable negative voltage level, and this negative voltage level is changed by adjusting the number of diodes in the series connection of the D2-DN array.

[0079] Figure 6 This is a schematic diagram of the operating waveform of a driving circuit for a power device provided in an embodiment of the present invention. Figure 6As shown, after the circuit is powered on for a period of time, the input signal IN becomes a fixed-frequency, 50% duty cycle, voltage range of VSS ~ VDD input drive signal. Since the power-on signal generated by the power-on signal generation unit is still at a low level at this time, the circuit is still in the pre-charging stage. Therefore, neither the unipolar output OUT nor the negative voltage output NegOUT will respond to the input drive signal. Only when the power-on signal changes from low to high level will the unipolar output OUT and the negative voltage output NegOUT begin to respond to the input signal. The unipolar output port OUT outputs a drive signal with a voltage range of VSS ~ VCC, and the negative voltage output port NegOUT outputs a drive signal with a voltage range of (set negative voltage) ~ (VCC – ΔV).

[0080] Figure 7 This is a timing diagram of the feedback control module and its control logic in a power device drive circuit according to an embodiment of the present invention. As analyzed above, the turn-on time of the high-voltage thin-gate NMOS transistor HMN3 is determined by the input signal at the input port IN. When the input signal at the input port IN changes from high to low, after a circuit logic response delay of up to t1, the gate voltage of the high-voltage thin-gate NMOS transistor HMN3 in the pull-down clamping module becomes high. As analyzed above, the turn-off time of the high-voltage thin-gate NMOS transistor HMN3 is determined by the output of comparator COMP1. The input of comparator COMP1 is the output signal of the unipolar output port OUT. When the output of the unipolar output port OUT rises to the internal threshold Vneg_ref set by the comparator, the output of comparator COMP1 flips from high to low after a response time t3. This low-level signal, after a circuit logic response delay of up to t2, pulls down the gate voltage of the high-voltage thin-gate NMOS transistor HMN3 in the pull-down clamping module to a low level. Therefore, at the falling edge of the input in each cycle, the high-voltage thin-gate NMOS transistor HMN3 is briefly turned on, thereby moderately and briefly charging the output capacitor C2 to maintain the charge of the output capacitor C2.

[0081] A driving circuit for a power device according to an embodiment of the present invention has a negative voltage shutdown function. The input terminal of the driving circuit receives a driving signal, and through the internal power output structure of the driving circuit, outputs a corresponding unipolar output driving signal at a unipolar output port. The circuit has a unipolar output port and a negative voltage output port, which are connected by a negative voltage capacitor circuit. The negative voltage capacitor circuit provides a negative voltage to the first electrode of the power device for shutting down the power device when the unipolar output driving signal is a shutdown signal. The driving circuit includes a pre-charge module and a charging pull-down module, which can pre-charge the output capacitor in the negative voltage capacitor circuit during initial power-on, thereby solving the problem of slow establishment of the negative voltage shutdown function. The driving circuit for the power device of the present invention can provide a stable shutdown negative voltage for the power device.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0084] Although the invention has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A driving circuit for a power device, characterized in that: Includes a negative voltage capacitor circuit, a pre-charge module, a power output stage, and a charging pull-down module; The output terminal of the negative voltage capacitor circuit is connected to the gate of the power device, and is used to provide a negative voltage to the gate of the power device to turn off the power device when the received unipolar output drive signal is a turn-off signal. The pre-charging module is used to pre-charge the negative voltage capacitor circuit. The power output stage is used to output a unipolar output drive signal to the negative voltage capacitor circuit according to the input signal; The charging pull-down module is used to pull down the gate voltage of the power device to ground when the pre-charging module pre-charges the negative voltage capacitor circuit, and to replenish the charge of the negative voltage capacitor circuit when the power output stage outputs a unipolar output drive signal to the negative voltage capacitor circuit.

2. The driving circuit as described in claim 1, characterized in that: The pre-charge module includes a power-on signal generation unit, a second inverter, and a second high-voltage thick-gate NMOS transistor. The power-on signal generation unit is connected to the power signal of the low / high voltage domain power rail and is used to generate a power-on signal during the power-on process. The input terminal of the second inverter is connected to the output terminal of the power-on signal generation unit, and its output terminal is connected to the gate of the second high-voltage thick-gate NMOS transistor. The second inverter is powered by a clamping control input signal. The drain of the second high-voltage thick-gate NMOS transistor is connected to the power signal of the high voltage domain power rail, and its source is connected to a negative voltage capacitor circuit.

3. The driving circuit as described in claim 2, characterized in that: The power-on signal generation unit includes a first resistor, a first capacitor, a first Schmitt trigger, a first PMOS transistor, a first NMOS transistor, and a first inverter. The source of the first PMOS transistor is connected to the power signal of the low / high voltage power rail, its gate is connected to ground, and its drain is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the drain of the first NMOS transistor, the first terminal of the first capacitor, and the input terminal of the first Schmitt trigger. The gate and source of the first NMOS transistor are both connected to ground, and the second terminal of the first capacitor is connected to ground. The output terminal of the first Schmitt trigger is connected to the input terminal of the first inverter, and the output terminal of the first inverter serves as the output terminal of the power-on signal generation unit, connected to the input terminal of the second inverter.

4. The driving circuit as described in claim 2, characterized in that: The charging pull-down module includes a first diode, a series diode array, a first pull-down switch, and a third high-voltage thin-gate NMOS transistor. The series diode array consists of several diodes connected in series in the same direction. The gate of the third high-voltage thin-gate NMOS transistor is used to connect a logic control signal to adjust the charging time of the negative voltage capacitor circuit. The source of the third high-voltage thin-gate NMOS transistor is connected to ground, and its drain is connected to the cathode of the first diode and the anode of the series diode array. The cathode of the series diode array and the anode of the first diode are used to output a negative voltage output signal to the negative voltage capacitor circuit. The first pull-down switch is connected to the anode of the first diode and pulls the output port level of the charging pull-down module low to ground during the pre-charging process according to the output signal of the power-on signal generation unit.

5. The driving circuit as described in claim 4, characterized in that: The driving circuit further includes a feedback control module; wherein the feedback control module is used to generate logic control signals, including a first comparator, a third inverter, a second AND gate, a first NAND gate, and a third buffer, wherein the input terminal of the first comparator is connected to the output terminal of the pre-charge module, and its output terminal is connected to the first input terminal of the second AND gate; the input terminal of the third inverter is connected to the input signal, and its output terminal is connected to the second input terminal of the second AND gate; the output terminal of the second AND gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the output terminal of the power-on signal generation unit, and its output terminal is connected to the input terminal of the third buffer, and the output terminal of the third buffer is connected to the input terminal of the charging pull-down module.

6. The driving circuit as described in claim 5, characterized in that: The power output stage includes a first high-voltage thin-gate NMOS transistor and a high-voltage PMOS transistor. The source of the high-voltage PMOS transistor is connected to the power signal of the high-voltage power rail, and its drain is connected to the drain of the first high-voltage thin-gate NMOS transistor, serving as the output terminal of the power output stage and connected to the negative voltage capacitor circuit. The high-voltage PMOS transistor conducts when the power device is turned on according to the input signal. The source of the first high-voltage thin-gate NMOS transistor is grounded, and it conducts when the input signal is a pull-down signal according to the input signal.

7. The driving circuit as described in claim 6, characterized in that: The high-voltage PMOS transistor is connected to the input signal through a first OR gate and a first buffer. The first input terminal of the first OR gate is connected to the input signal, the second input terminal is connected to the output terminal of the power-on signal generation unit, the output terminal of the first OR gate is connected to the input terminal of the first buffer, and the output terminal of the first buffer is connected to the gate of the high-voltage PMOS transistor.

8. The driving circuit as described in claim 7, characterized in that: A level shifting circuit is also connected between the first OR gate and the first buffer. The power supply terminal of the level shifting circuit is connected to the power signal of the high-voltage power rail, and its ground terminal is connected to the ground signal. It is used to convert the input level from the low-voltage domain to the high-voltage domain.

9. The driving circuit as described in claim 6, characterized in that: The first high-voltage resistant thin-gate NMOS transistor is connected to the input signal through a first AND gate and a second buffer. The first input terminal of the first AND gate is connected to the input signal, the second input terminal is connected to the output terminal of the power-on signal generation unit, and the output terminal of the first AND gate is connected to the gate of the first high-voltage resistant thin-gate NMOS transistor.

10. The driving circuit as described in claim 1, characterized in that: The negative voltage capacitor circuit includes a gate resistor and an output capacitor. The first end of the gate resistor is connected to the output terminal of the power output stage, the second end of the gate resistor is connected to the first end of the output capacitor, the second end of the output capacitor is connected to the gate of the power device, and the second end of the output capacitor is also connected to the output terminal of the charging pull-down module.

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