Ferroelectric field effect transistor integrated chip and method for manufacturing the same

Abstract

This application provides a ferroelectric field-effect transistor (FFET) integrated chip and its fabrication method, relating to the field of electronic component technology, aiming to improve the integration density and design flexibility of the FFET integrated chip. The FFET integrated chip includes a substrate, and multiple gate conductive layers, multiple first isolation layers, a ferroelectric layer, an oxide semiconductor layer, a second isolation layer, a source, and a drain layer stacked on the substrate. The ferroelectric layer, the oxide semiconductor layer, and the second isolation layer are all disposed within a first trench, a second trench, and a third trench, with the ferroelectric layer at least partially covering the inner walls of the first trench, the second trench, and the third trench. The oxide semiconductor layer includes multiple channel regions, one channel region being at least partially opposite to a gate conductive layer in a second direction. Among the multiple gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

Description

Technical Field

[0001] This application relates to the field of electronic components technology, and in particular to a ferroelectric field-effect transistor integrated chip and its fabrication method. Background Technology

[0002] With the rapid development of information technology and the explosive growth of generative artificial intelligence and big data applications, unprecedented demands have been placed on the density, energy efficiency, and reliability of memory. The market urgently needs a high-density, low-power, and high-endurance non-volatile memory solution to support the continuous evolution of data-intensive computing architectures. Ferroelectric field-effect transistors (FETs), as an emerging non-volatile memory device, have become a strong candidate for next-generation embedded memory and 3D stacked memory due to their low operating voltage, nanosecond-level read / write speeds, and high compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes.

[0003] Among them, ferroelectric field-effect transistors (FETs) using oxide semiconductors as the channel material exhibit significant advantages in improving reliability and integration density due to their higher durability and superior three-dimensional integration flexibility. Achieving flexible and precise threshold voltage control is a key technology for improving the performance of FET memory arrays, ensuring compatibility with peripheral circuit designs, and realizing voltage domain partitioning and power consumption optimization.

[0004] However, improving the integration density and design flexibility of ferroelectric field-effect transistor integrated chips remains a problem to be solved in the field. Summary of the Invention

[0005] This application proposes a ferroelectric field-effect transistor integrated chip and its fabrication method, aiming to improve the integration level and design flexibility of the ferroelectric field-effect transistor integrated chip.

[0006] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0007] On one hand, embodiments of this application provide a ferroelectric field-effect transistor (FET). The FET integrated chip includes a substrate, multiple gate conductive layers, multiple first isolation layers, a ferroelectric layer, an oxide semiconductor layer, a second isolation layer, a source, and a drain. The substrate includes a first surface and a second surface disposed opposite to each other. The substrate also includes a first trench extending from the first surface into the substrate. Multiple gate conductive layers are sequentially stacked on the first surface. Along a first direction perpendicular to the substrate, the gate conductive layers include a through-hole second trench. Multiple first isolation layers are disposed on the first surface. Along the first direction, the first isolation layers are disposed between adjacent gate conductive layers. Each first isolation layer includes a through-hole third trench. The orthographic projection of the third trench onto the substrate at least partially overlaps with the orthographic projections of the first trench and the second trench onto the substrate. A ferroelectric layer, an oxide semiconductor layer, and a second isolation layer are all disposed within a first trench, a second trench, and a third trench. The ferroelectric layer at least partially covers the inner walls of the first trench, the second trench, and the third trench. Along a second direction parallel to the substrate, the oxide semiconductor layer is disposed on the side of the ferroelectric layer away from the gate conductive layer, and the second isolation layer is disposed on the side of the oxide semiconductor layer away from the ferroelectric layer. The oxide semiconductor layer includes multiple channel regions, one channel region being at least partially opposite to a gate conductive layer in the second direction. The source and drain electrodes are both disposed on the side of the oxide semiconductor layer away from the substrate. Among the multiple gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

[0008] The ferroelectric field-effect transistor integrated chip provided in the embodiments of this application includes a substrate, multiple gate conductive layers, multiple first isolation layers, a ferroelectric layer, an oxide semiconductor layer, a second isolation layer, a source, and a drain. A gate conductive layer and a first isolation layer are sequentially stacked on the substrate. A first trench is formed in the substrate, a through second trench is formed in the gate conductive layer, and a through third trench is formed in the first isolation layer. At least a portion of the ferroelectric layer, the oxide semiconductor layer, and the second isolation layer are all disposed in the first trench, the second trench, and the third trench, and the ferroelectric layer is in contact with the gate conductive layer through the second trench. The source and drain are both disposed on the side of the oxide semiconductor layer away from the substrate and are electrically connected to at least a portion of the oxide semiconductor layer, respectively.

[0009] Understandably, multiple ferroelectric field-effect transistors (FETs) in a FET integrated chip are integrated and stacked along a direction perpendicular to the substrate, and these FETs utilize the same oxide semiconductor layer as a channel, thereby reducing the planar size of the integrated chip. Furthermore, the shared source and drain of multiple FETs effectively reduces the operating voltage of the vertically stacked FETs, improving their durability, thus facilitating the realization of highly integrated, low-power, and highly reliable FET integrated chips.

[0010] Furthermore, the oxide semiconductor layer includes multiple channel regions, one channel region being at least partially opposite to a gate conductive layer in a second direction, and in the multiple gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

[0011] Understandably, multiple channel regions can be formed in the oxide semiconductor layer through thermal annealing. During thermal annealing, the gate conductive layer expands at high temperatures, generating stress. This stress is conducted through the ferroelectric layer to the oxide semiconductor layer, causing localized tensile stress in the oxide semiconductor layer. This tensile stress will affect the grain size and oxygen vacancy distribution in the channel region, thereby altering the carrier concentration and mobility in the channel region, and ultimately affecting the threshold voltage of the ferroelectric field-effect transistor.

[0012] Therefore, by setting the materials of at least two gate conductive layers to have different coefficients of thermal expansion and different Young's moduli, the above-mentioned thermal annealing process can be used to conduct different stresses to the corresponding channel regions of the at least two gate conductive layers, so that the ferroelectric field-effect transistors in the at least two gate conductive layers have different threshold voltages. Thus, the threshold voltages of different ferroelectric field-effect transistors in the same vertical channel can be independently modulated without increasing the process flow, thereby improving the integration density and design flexibility of ferroelectric field-effect transistor integrated chips.

[0013] In some embodiments, in the plurality of gate conductive layers, the coefficient of thermal expansion of the material of each gate conductive layer is different, and the Young's modulus of the material of each gate conductive layer is different.

[0014] In some embodiments, among multiple gate conductive layers, the larger the coefficient of thermal expansion and Young's modulus of the gate conductive layer material, the larger the threshold voltage of the ferroelectric field-effect transistor device under the same metal work function.

[0015] In some embodiments, the plurality of gate conductive layers further includes a first gate conductive layer and a second gate conductive layer. The difference between the coefficient of thermal expansion of the material of the first gate conductive layer and the coefficient of thermal expansion of the material of the second gate conductive layer is greater than or equal to 2 × 10⁻⁶. -6 / K.

[0016] In some embodiments, the ratio of the thickness of the gate conductive layer in the first direction to the thickness of the channel region in the second direction ranges from 0.25 to 100.

[0017] In some embodiments, the ratio of the thickness of the ferroelectric layer in the second direction to the thickness of the channel region in the second direction ranges from 1.25 to 20.

[0018] In some embodiments, the lanthanum element has a mass fraction of 5% to 20% in the ferroelectric layer material. Alternatively, the thickness of the ferroelectric layer along the second direction ranges from 5 nm to 20 nm. Alternatively, the lanthanum element has a mass fraction of 5% to 20%, and the thickness of the ferroelectric layer along the second direction ranges from 5 nm to 20 nm.

[0019] In some embodiments, the orthographic projections of the first trench on the substrate, the second trench on the substrate, and the third trench on the substrate all coincide.

[0020] On the other hand, embodiments of this application also provide a method for fabricating a ferroelectric field-effect transistor integrated chip, the method comprising: Multiple gate conductive layers and multiple first isolation layers are formed on a substrate, and the first isolation layer is disposed between two adjacent gate conductive layers along a first direction perpendicular to the substrate. A substrate, multiple gate conductive layers, and multiple first isolation layers are etched to form a first trench, a second trench, and a third trench. The substrate includes a first surface and a second surface disposed opposite to each other. The first trench extends from the first surface into the substrate. The second trench penetrates the gate conductive layer. The third trench penetrates the first isolation layer. The orthographic projection of the third trench on the substrate at least partially overlaps with the orthographic projection of the first trench on the substrate and the orthographic projection of the second trench on the substrate. A ferroelectric material layer and an oxide semiconductor material layer are sequentially formed in the first trench, the second trench and the third trench, wherein at least part of the ferroelectric material layer covers the inner wall of the first trench, the inner wall of the second trench and the inner wall of the third trench. A second isolation layer is formed in the first trench, the second trench and the third trench, and the second isolation layer is located on the side of the oxide semiconductor material layer away from the ferroelectric layer; The source and drain are formed on the side of the oxide semiconductor material layer away from the substrate; A thermal annealing process is used to form an oxide semiconductor layer and a ferroelectric layer, and multiple channel regions are formed in the oxide semiconductor layer. Along a second direction parallel to the substrate, one channel region is at least partially opposite to a gate conductive layer. Among the multiple gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

[0021] The method for fabricating a ferroelectric field-effect transistor integrated chip provided in the embodiments of this application includes forming multiple gate conductive layers and multiple first isolation layers on a substrate. The substrate, the multiple gate conductive layers, and the multiple first isolation layers are etched to form a first trench, a second trench, and a third trench. A ferroelectric material layer, an oxide semiconductor material layer, and a second isolation layer are sequentially formed in the first trench, the second trench, and the third trench, with the ferroelectric layer contacting the gate conductive layer through the second trench. A source and a drain are formed on the side of the oxide semiconductor material layer away from the substrate.

[0022] Understandably, multiple ferroelectric field-effect transistors (FETs) in a FET integrated chip are integrated and stacked along a direction perpendicular to the substrate, and these FETs utilize the same oxide semiconductor layer as a channel, thereby reducing the planar size of the integrated chip. Furthermore, the shared source and drain of multiple FETs effectively reduces the operating voltage of the vertically stacked FETs, improving their durability, thus facilitating the realization of highly integrated, low-power, and highly reliable FET integrated chips.

[0023] Furthermore, the above-mentioned preparation method also includes using a thermal annealing process to form an oxide semiconductor layer and a ferroelectric layer, and forming multiple channel regions in the oxide semiconductor layer, wherein one channel region is at least partially opposite to a gate conductive layer in a second direction, and in the multiple gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

[0024] Understandably, multiple channel regions can be formed in the oxide semiconductor layer through thermal annealing. During thermal annealing, the gate conductive layer expands at high temperatures, generating stress. This stress is conducted through the ferroelectric layer to the oxide semiconductor layer, causing localized tensile stress in the oxide semiconductor layer. This tensile stress will affect the grain size and oxygen vacancy distribution in the channel region, thereby altering the carrier concentration and mobility in the channel region, and ultimately affecting the threshold voltage of the ferroelectric field-effect transistor.

[0025] Therefore, by setting the materials of at least two gate conductive layers to have different coefficients of thermal expansion and different Young's moduli, the above-mentioned thermal annealing process can be used to conduct different stresses to the corresponding channel regions of the at least two gate conductive layers, so that the ferroelectric field-effect transistors in the at least two gate conductive layers have different threshold voltages. Thus, the threshold voltages of different ferroelectric field-effect transistors in the same vertical channel can be independently modulated without increasing the process flow, thereby improving the integration density and design flexibility of ferroelectric field-effect transistor integrated chips.

[0026] In some embodiments, the thermal annealing process includes a heating stage, a holding stage, and a cooling stage. During the heating stage, the peak temperature ranges from 300°C to 700°C. During the holding stage, the holding time ranges from 10 s to 3600 s. During the cooling stage, the cooling rate is less than or equal to 10°C / s. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0028] Figure 1 A schematic diagram of the structure of a ferroelectric field-effect transistor integrated chip provided for an embodiment of this application; Figure 2 for Figure 1 A magnified view of the integrated chip at point M; Figure 3 A flowchart illustrating the fabrication method of a ferroelectric field-effect transistor integrated chip provided in the embodiments of this application; Figures 4-8 Schematic diagrams illustrating the steps of the preparation method provided for embodiments of this application; Figures 9-12 The simulation experiment diagrams provided for the embodiments of this application. Detailed Implementation

[0029] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0030] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0031] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0032] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0033] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0034] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0035] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0036] With the rapid development of information technology and the explosive growth of generative artificial intelligence and big data applications, unprecedented demands have been placed on the density, energy efficiency, and reliability of memory. The market urgently needs a high-density, low-power, and high-endurance non-volatile memory solution to support the continuous evolution of data-intensive computing architectures. Ferroelectric field-effect transistors (FeFETs), as an emerging non-volatile memory device, have become a strong candidate for 3D stacked memory due to their low operating voltage, nanosecond-level read / write speeds, and high compatibility with standard CMOS (Complementary Metal Oxide Semiconductor) processes.

[0037] Ferroelectric field-effect transistors (FeFETs) are novel semiconductor devices formed by replacing the gate insulating layer of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) with a ferroelectric material with a high dielectric constant. Their core principle utilizes the spontaneous polarization characteristics of ferroelectric materials to control the resistance state of the semiconductor channel through gate voltage, combining non-volatile storage with field-effect modulation capabilities. They are primarily used in ultra-high-speed integrated circuits and novel memory applications.

[0038] Furthermore, introducing oxide semiconductors (such as IGZO and IZO) as channel materials into FeFETs not only offers higher durability and greater flexibility in 3D integration fabrication, but also demonstrates significant advantages in improving reliability and integration density. In NAND flash memory, ferroelectric field-effect transistor integrated chips using this structure are expected to achieve substantial performance improvements. NAND flash memory is a non-volatile storage technology based on the NAND logic gate structure. It stores charge through floating-gate transistors or charge traps, achieving high-capacity, low-cost, erasable and rewritable data storage, making it a core storage medium for mobile phones, USB flash drives, and data centers.

[0039] In vertically stacked memory structures such as 3D NAND, the channel is typically deposited in the entire via at once, running through all transistors on the entire vertical array. Unlike planar devices, it cannot achieve differentiated control of the threshold voltage (Vth) of transistors at different locations through partitioning. Existing threshold voltage control methods, such as ion implantation, in-situ doping, or multiple channel deposition, all have significant limitations in oxide semiconductor channel FeFETs. Specifically, ion implantation can damage the channel lattice and interface quality, reducing mobility and durability. In-situ doping and multiple deposition not only increase process complexity and cost but also introduce inter-region interface inconsistencies, affecting array yield and consistency.

[0040] Since mainstream channel film deposition technologies such as atomic layer deposition (ALD) and physical vapor deposition (PVD) are all full-wafer growth processes, they cannot achieve spatially selective control in the vertical direction, resulting in all transistors on the same channel having the same absolute threshold voltage.

[0041] However, in practical arrays, memory cells and select transistors (such as serial select transistors and word line select transistors) have significantly different requirements for threshold voltage positions due to their different functions. This differentiated requirement is difficult to achieve under single-channel deposition process conditions, resulting in the use of bulk silicon transistors as control transistors, which restricts the array design in terms of integration density and design flexibility.

[0042] Therefore, on the one hand, embodiments of this application provide an integrated chip for a ferroelectric field-effect transistor. Figure 1 This is a schematic diagram of the structure of a ferroelectric field-effect transistor integrated chip provided for an embodiment of this application.

[0043] See Figure 1 The ferroelectric field-effect transistor integrated chip 10 includes a substrate 1, multiple gate conductive layers 2, multiple first isolation layers 7, a ferroelectric layer 3, an oxide semiconductor layer 4, a second isolation layer 8, a source 5, and a drain 6.

[0044] For example, the ferroelectric field-effect transistor integrated chip 10 can be a three-dimensional stacked NAND memory array.

[0045] For example, the ferroelectric field-effect transistor integrated chip 10 also includes multiple ferroelectric field-effect transistors 100. The ferroelectric field-effect transistors 100 can be used as memory chips in the fields of ultra-high-speed integrated circuits and novel memory. Ferroelectric field-effect transistors have a programmable gate (PRG) state and an eraser state (ESR), and these two different states have different threshold voltages (Vth) and conductivity characteristics. For example, in a three-dimensional stacked NAND memory array, the ferroelectric field-effect transistors 100 can be select transistors, reference cells, or memory cells, etc.

[0046] The threshold voltage of the ferroelectric field-effect transistor 100 is a core parameter distinguishing its cutoff and conduction regions, playing a crucial role in the switching of the ferroelectric field-effect transistor 100's operating states, performance optimization, circuit design adaptation, and stability assurance. The threshold voltage is the critical voltage value that allows the ferroelectric field-effect transistor 100 to switch from "off" to "on". When the gate voltage is below the threshold voltage, no conductive channel is formed in the oxide semiconductor layer 4, the ferroelectric field-effect transistor 100 is in the cutoff state, and the drain current 6 is extremely small. When the gate voltage reaches or exceeds the threshold voltage, strong inversion occurs in the oxide semiconductor layer 4, forming a conductive channel, the ferroelectric field-effect transistor 100 turns on, and the drain current 6 increases significantly.

[0047] See also Figure 1 The substrate 1 includes a first surface 101 and a second surface 102 disposed opposite to each other. The substrate 1 also includes a first trench 11 extending from the first surface 101 into the substrate 1.

[0048] For example, the material of substrate 1 can be silicon or other semiconductor materials, such as a wafer.

[0049] Multiple gate conductive layers 2 are sequentially stacked on the first surface 101. Along a first direction Z perpendicular to the substrate 1, the gate conductive layer 2 includes a through second trench 12. It is understood that one through second trench 12 is provided in one gate conductive layer 2, and exemplaryly, the orthographic projections of the multiple second trenches 12 on the substrate 1 coincide.

[0050] For example, the material of the gate conductive layer 2 can be a metal such as titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), titanium (Ti), tungsten (W), ruthenium (Ru), or an alloy of the above metal materials.

[0051] See also Figure 1 Multiple first isolation layers 7 are disposed on the first surface 101 along the first direction Z, and the first isolation layers 7 are disposed between two adjacent gate conductive layers 2. It can be understood that the first isolation layers 7 are used to achieve electrical isolation between two adjacent gate conductive layers 2, thereby preventing electrical crosstalk between two adjacent ferroelectric field-effect transistors 100.

[0052] For example, the material of the first isolation layer 7 includes silicon oxide or silicon nitride. Along the Z direction, the thickness of the first isolation layer 7 ranges from 10 nm to 100 nm.

[0053] The first isolation layer 7 includes a through third trench 13. The orthographic projection of the third trench 13 onto the substrate 1 at least partially overlaps with the orthographic projections of the first trench 11 and the second trench 12 onto the substrate 1. It is understood that a through third trench 13 is disposed in one first isolation layer 7, and the third trench 13 exposes at least a portion of the second trench 12. Exemplarily, the orthographic projections of multiple third trenches 13 onto the substrate 1 coincide.

[0054] See also Figure 1 A ferroelectric layer 3 is disposed within the first trench 11, the second trench 12, and the third trench 13, and at least a portion of the ferroelectric layer 3 covers the inner walls of the first trench 11, the second trench 12, and the third trench 13. It is understood that the ferroelectric layer 3 is in contact with each gate conductive layer 2, thereby enabling stress transmission from the gate conductive layer 2 to the ferroelectric layer 3. Exemplarily, the ferroelectric layer 3 includes portions located within the first trench 11, the second trench 12, and the third trench 13, and a portion located on the side of the third trench 13 away from the substrate 1.

[0055] For example, the ferroelectric layer 3 can serve as the gate insulating layer of the ferroelectric field-effect transistor 100, electrically isolating the gate conductive layer 2 from the oxide semiconductor layer 4. Furthermore, the ferroelectric layer 3 can also enable the ferroelectric field-effect transistor 100 to possess key performance characteristics such as non-volatile storage, threshold voltage regulation, low power consumption operation, and high switching ratio through its unique ferroelectric properties, such as spontaneous polarization, polarization reversal, and hysteresis loop.

[0056] For example, the material of the ferroelectric layer 3 may include hafnium oxide. For instance, the material of the ferroelectric layer 3 may be a pure hafnium oxide thin film, or a hafnium oxide thin film doped with silicon, zirconium, aluminum, lanthanum, gallium, or yttrium. The embodiments of this application illustrate the use of hafnium oxide (HfO2) as the material of the ferroelectric layer 3.

[0057] See also Figure 1 The oxide semiconductor layer 4 is disposed in the first trench 11, the second trench 12 and the third trench 13, and along the second direction X parallel to the substrate 1, the oxide semiconductor layer 4 is disposed on the side of the ferroelectric layer 3 away from the gate conductive layer 2.

[0058] It is understood that the oxide semiconductor layer 4 is in contact with and covers the ferroelectric layer 3. Exemplarily, the oxide semiconductor layer 4 includes portions located within the first trench 11, the second trench 12, and the third trench 13, and a portion located on the side of the ferroelectric layer 3 away from the substrate 1. The portion of the oxide semiconductor layer 4 located on the side of the ferroelectric layer 3 away from the substrate 1 covers the ferroelectric layer 3 in the Z direction and extends along the X direction to opposite sides of the third trench 13.

[0059] For example, the material of the oxide semiconductor layer 4 includes an n-type semiconductor material. For instance, the material of the oxide semiconductor layer 4 can be a monolithic oxide semiconductor material, such as titanium oxide, tin oxide, zinc oxide, indium oxide, gallium oxide, or cerium oxide. Alternatively, the material of the oxide semiconductor layer 4 can also be a binary oxide or a multi-component oxide material composed of the aforementioned metal elements, such as indium-doped zinc oxide (binary oxide), indium gallium zinc oxide (ternary oxide), indium gallium zinc tin oxide (quaternary oxide), etc.

[0060] The second isolation layer 8 is disposed within the first trench 11, the second trench 12, and the third trench 13, and is disposed on the side of the oxide semiconductor layer 4 away from the ferroelectric layer 3. It can be understood that, along direction X, the portion of the oxide semiconductor layer 4 located on the side of the ferroelectric layer 3 away from the substrate 1 is electrically connected to the source electrode 5 and the drain electrode 6, respectively. By providing the second isolation layer 8, electrical isolation between the source electrode 5 and the drain electrode 6 can be achieved.

[0061] For example, the material of the second isolation layer 8 includes silicon oxide or silicon nitride.

[0062] Figure 2 for Figure 1 A magnified view of the integrated chip at point M.

[0063] See Figure 2 The oxide semiconductor layer 4 includes multiple channel regions 41, one of which is at least partially opposite to a gate conductive layer 2 in the second direction X. The gate conductive layer 2 can apply an electric field to the channel region 41 through the ferroelectric layer 3, thereby controlling the conductivity of the channel region 41 and thus controlling the switching state of the ferroelectric field-effect transistor 10. Therefore, the channel region 41 can be referred to as a "gate-controlled channel".

[0064] For example, after forming the oxide semiconductor layer 4, a rapid thermal annealing (RTA) process can be used to form the channel region 41 in the oxide semiconductor layer 4. It is understood that during the thermal annealing process, a portion of the material in the oxide semiconductor layer 4 can be transformed from an amorphous state to a polycrystalline state under high temperature, and the portion transformed into the polycrystalline state is the channel region 41.

[0065] For example, the rapid thermal annealing stage includes a heating stage, a holding stage, and a cooling stage. During the heating and holding stages, partial crystallization reactions occur in the ferroelectric layer 3 and the oxide semiconductor layer 4, and the gate conductive layer 2 simultaneously undergoes thermal expansion at high temperatures. During the cooling stage, the gate conductive layer 2, the ferroelectric layer 3, and the oxide semiconductor layer 4 all undergo cooling contraction. Since the materials of the ferroelectric layer 3 and the gate conductive layer 2 are different, their coefficients of thermal expansion are different. This difference in coefficients of thermal expansion creates a stress difference between them. This stress difference is conducted through the ferroelectric layer 3 to the oxide semiconductor layer 4, resulting in localized tensile stress on the oxide semiconductor layer 4. This stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 10.

[0066] See also Figure 1 The source electrode 5 and the drain electrode 6 are both disposed on the side of the oxide semiconductor layer 4 away from the substrate 1.

[0067] For example, the oxide semiconductor layer 4 also includes source-drain contact regions 42, with the source 5 and drain 6 respectively contacting different source-drain contact regions 42. Since multiple ferroelectric field-effect transistors 100 in the ferroelectric field-effect transistor integrated chip 10 can all be controlled by the same source 5 and drain 6, the operating voltage of the vertical channel ferroelectric field-effect transistors 100 can be effectively reduced, and durability can be improved, so as to realize a highly integrated, low-power, and highly reliable three-dimensional NAND memory.

[0068] For example, the source 5 and the drain 6 are made of the same material, and the positions of the source 5 and the drain 6 can be interchanged. For instance, the source 5 and the drain 6 can be conductive materials such as titanium nitride, tantalum nitride, molybdenum, titanium, tungsten, ruthenium, or indium tin oxide, which form ohmic contacts with the oxide semiconductor layer 4 and are process-compatible.

[0069] Among the multiple gate conductive layers 2, at least two gate conductive layers 2 have different coefficients of thermal expansion (CTE) and different Young's modulus (YM).

[0070] For example, the material of the gate conductive layer 2 can be a combination of metal materials such as TiN / W, Mo / Ru, or TiN / Ru. The thermal expansion coefficient and Young's modulus of the gate conductive layer 2 can also be adjusted by changing the proportion of different metal elements in it. By rationally configuring the material of the gate conductive layer 2, a wide range of precise threshold voltage control can be achieved, meeting the operational requirements of ferroelectric field-effect transistors 100 with different functions.

[0071] Furthermore, by selecting different gate conductive layer 2 materials in the memory cell, select transistor, reference cell, and other locations, a threshold voltage adjustment range far exceeding that provided by the difference in metal work function can be obtained, thereby realizing the integration of multi-threshold voltage devices under the conditions of one channel deposition and one annealing process.

[0072] For example, by setting the thermal expansion coefficients and Young's moduli of the materials of at least two gate conductive layers 2 to be different, during the cooling stage of the thermal annealing process, due to the thermal mismatch between the stack of the gate conductive layer 2 and the ferroelectric layer 3 and the oxide semiconductor layer 4, the gate conductive layers 2 at different positions will generate stresses of different magnitudes and directions in the local area of ​​the oxide semiconductor layer 4, thereby applying controllable stress to the channel region 41 corresponding to the at least two gate conductive layers 2, thereby regulating the crystallization state and oxygen vacancy distribution of the polycrystalline oxide in the channel region 41, so that the at least two ferroelectric field effect transistors 100 have different threshold voltages.

[0073] The ferroelectric field-effect transistor integrated chip 10 provided in the embodiments of this application includes a substrate 1, a plurality of gate conductive layers 2, a plurality of first isolation layers 7, a ferroelectric layer 3, an oxide semiconductor layer 4, a second isolation layer 8, a source 5, and a drain 6. A gate conductive layer 2 and a first isolation layer 7 are sequentially stacked on the substrate. A first trench 11 is formed in the substrate 1, a through second trench 12 is formed in the gate conductive layer 2, and a through third trench 13 is formed in the first isolation layer 7. At least a portion of the ferroelectric layer 3, the oxide semiconductor layer 4, and the second isolation layer 8 are all disposed within the first trench 11, the second trench 12, and the third trench 13, and the ferroelectric layer 3 is in contact with the gate conductive layer 2 through the second trench 12. The source 5 and the drain 6 are both disposed on the side of the oxide semiconductor layer 4 away from the substrate 1, and are electrically connected to at least a portion of the oxide semiconductor layer 4, respectively.

[0074] Understandably, the multiple ferroelectric field-effect transistors 100 in the ferroelectric field-effect transistor integrated chip 10 are integrated and stacked along a direction Z perpendicular to the substrate 1, and the multiple ferroelectric field-effect transistors 100 utilize the same oxide semiconductor layer 4 as a channel, thereby reducing the planar size of the integrated chip 10. Furthermore, the multiple ferroelectric field-effect transistors 100 share the same source 5 and drain 6, which can effectively reduce the operating voltage of the vertically stacked ferroelectric field-effect transistors 100 and improve their durability, thus facilitating the realization of a highly integrated, low-power, and highly reliable ferroelectric field-effect transistor integrated chip 10.

[0075] Furthermore, the oxide semiconductor layer 4 includes a plurality of channel regions 41, one channel region 41 being at least partially opposite to a gate conductive layer 2 in the second direction X. Among the plurality of gate conductive layers 4, at least two gate conductive layers 4 have different coefficients of thermal expansion and different Young's moduli.

[0076] Understandably, multiple channel regions 41 can be formed in the oxide semiconductor layer 4 through a thermal annealing process. During the thermal annealing process, the gate conductive layer 4 expands at high temperature, thereby generating stress. This stress is conducted to the oxide semiconductor layer 4 through the ferroelectric layer 3, resulting in localized tensile stress in the oxide semiconductor layer 4. This tensile stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 100.

[0077] Therefore, by setting the materials of at least two gate conductive layers 4 to have different coefficients of thermal expansion and different Young's moduli, the above-mentioned thermal annealing process can be used to conduct different stresses to the corresponding channel regions 41 through the at least two gate conductive layers 4, so that the ferroelectric field-effect transistors 100 in which the at least two gate conductive layers 4 are located have different threshold voltages. Thus, the threshold voltages of different ferroelectric field-effect transistors 100 in the same vertical channel can be independently modulated without increasing the process flow, thereby improving the integration density and design flexibility of the ferroelectric field-effect transistor integrated chip 10.

[0078] In some embodiments, see Figure 1 The orthographic projections of the first trench 11, the second trench 12, and the third trench 13 on the substrate 1 all coincide.

[0079] It is understandable that during the fabrication of the ferroelectric field-effect transistor integrated chip 10, the first trench 11, the second trench 12, and the third trench 13 can be formed simultaneously, thereby reducing process steps and lowering process costs. The first trench 11, the second trench 12, and the third trench 13 together form a vertical trench, and the oxide semiconductor layer 4 is disposed within the aforementioned vertical trench. This is beneficial for improving the control performance of the source 5 and the drain 6 over the channel of the oxide semiconductor layer 4, thereby improving the performance and lifespan of each ferroelectric field-effect transistor 100 in the integrated chip 10.

[0080] In some embodiments, see Figure 1 In the multiple gate conductive layers 2, the coefficient of thermal expansion of the material of each gate conductive layer 2 is different, and the Young's modulus of the material of each gate conductive layer 2 is different.

[0081] It is understandable that, through the above settings, each gate conductive layer 4 can conduct different stresses to the corresponding channel region 41, so that each ferroelectric field-effect transistor 100 in which the gate conductive layer 4 is located has a different threshold voltage. Thus, without increasing the process flow, the threshold voltage of each ferroelectric field-effect transistor 100 in the same vertical channel can be independently modulated, thereby further improving the integration and design flexibility of the ferroelectric field-effect transistor integrated chip 10.

[0082] For example, ferroelectric field-effect transistors 100 with different gate conductive layers 2 have different functions. For example, ferroelectric field-effect transistors 100 can be used as selection transistors, reference cells or memory cells, etc., to improve the functional diversity of ferroelectric field-effect transistor integrated chip 10.

[0083] In some embodiments, see Figure 1In the multiple gate conductive layers 2, the larger the coefficient of thermal expansion and Young's modulus of the material of the gate conductive layer 2, the larger the threshold voltage of the ferroelectric field-effect transistor device 10 under the same metal work function.

[0084] It is understandable that when the gate conductive layer 2 is made of a material with high Young's modulus and high coefficient of thermal expansion, the greater the tensile stress generated in the gate conductive layer 2 during the cooling stage of the thermal annealing process, the greater the tensile stress on the channel region 41, and the higher the threshold voltage of the ferroelectric field-effect transistor 100 where the gate conductive layer 2 is located. Conversely, when the gate conductive layer 2 is made of a material with low Young's modulus and low coefficient of thermal expansion, the smaller the tensile stress generated in the gate conductive layer 2 during the cooling stage of the thermal annealing process, the smaller the tensile stress on the channel region 41, and the lower the threshold voltage of the ferroelectric field-effect transistor 100 where the gate conductive layer 2 is located. Through these established rules, the threshold voltage of the ferroelectric field-effect transistor 100 at different locations can be more precisely controlled, thereby further improving the design flexibility of the ferroelectric field-effect transistor integrated chip 10.

[0085] In some embodiments, see Figure 1 The plurality of gate conductive layers 2 also includes a first gate conductive layer 21 and a second gate conductive layer 22. The difference between the coefficient of thermal expansion of the material of the first gate conductive layer 21 and the coefficient of thermal expansion of the material of the second gate conductive layer 22 is greater than or equal to 2 × 10⁻⁶. -6 / K.

[0086] It is understandable that, by setting the first gate conductive layer 21 and the second gate conductive layer 22, the difference in the coefficient of thermal expansion of their materials is greater than or equal to 2 × 10⁻⁶. -6 / K can generate a sufficient stress difference between the first gate conductive layer 21 and the second gate conductive layer 22 during the cooling stage, so that the ferroelectric field-effect transistor 100 where the first gate conductive layer 21 is located has a sufficient threshold voltage difference with the ferroelectric field-effect transistor 100 where the second gate conductive layer 22 is located.

[0087] For example, the ferroelectric field-effect transistor 100 where the first gate conductive layer 21 is located can be a high threshold voltage transistor, which can suppress leakage current and improve storage stability. The ferroelectric field-effect transistor 100 where the second gate conductive layer 22 is located can be a low threshold voltage transistor, which can reduce the operating voltage and improve read / write speed.

[0088] In some embodiments, see Figure 2The ratio of the thickness d1 of the gate conductive layer 2 in the first direction Z to the thickness d2 of the channel region 41 in the second direction X ranges from 0.25 to 100. For example, the value of d1:d2 can be 0.25, 25, 50, 75, or 100. It is understood that by setting d1:d2 within the range of 0.25 to 100, stress transmission matching between the gate conductive layer 2 and the channel region 41 can be achieved, meaning that the stress required by the gate conductive layer 2 under different threshold voltages can be more precisely controlled.

[0089] For example, d1 can range from 10nm to 100nm, and d2 can range from 1nm to 40nm. By setting the range of d1, the gate conductive layer 2 can effectively control the opening and closing of the channel region 41, thereby enabling data readout and modulating the polarization direction of the ferroelectric layer 3, thereby enabling the writing of the ferroelectric field-effect transistor 100.

[0090] Furthermore, the range of d1 is preferably 5nm~50nm, which allows for more precise control of the stress generated in the gate conductive layer 2 during the cooling stage, enabling the ferroelectric field-effect transistor 100 to have a wider threshold voltage modulation range.

[0091] In some embodiments, see Figure 1 The ratio of the thickness d3 of the ferroelectric layer 3 in the second direction X to the thickness d2 of the channel region 41 in the second direction X ranges from 1.25 to 20. For example, the value of d3:d2 can be 1.25, 5, 10, 15, or 20. This setting allows for better matching between the channel region 41 and the ferroelectric layer 3, thereby improving the semiconductor characteristics of the oxide semiconductor layer 4.

[0092] In some embodiments, see Figure 1 The ferroelectric layer 3 is made of hafnium oxide and lanthanum doped in the hafnium oxide, wherein the mass fraction of lanthanum is 5% to 20%. Alternatively, the thickness of the ferroelectric layer 3 along the second direction X ranges from 5 nm to 20 nm. Alternatively, the mass fraction of lanthanum is 5% to 20%, and the thickness d3 of the ferroelectric layer 3 along the second direction X ranges from 5 nm to 20 nm. For example, the mass fraction of lanthanum in the material of the ferroelectric layer 3 can be 5%, 9%, 12.5%, 17%, or 20%. The value of d3 can be 5 nm, 9 nm, 12.5 nm, 17 nm, or 20 nm.

[0093] It is understandable that, through the above settings, the ferroelectric layer 3 can have better ferroelectricity and lower leakage current, thereby improving the performance of the ferroelectric field-effect transistor 100, and further improving the performance of the ferroelectric field-effect transistor integrated chip 10.

[0094] On the other hand, embodiments of this application also provide a method for fabricating a ferroelectric field-effect transistor integrated chip 10. Figure 3 A flowchart illustrating the fabrication method of a ferroelectric field-effect transistor integrated chip provided in the embodiments of this application; Figures 4-8 The diagram shows the steps of the preparation method provided in the embodiments of this application.

[0095] See Figure 3 The preparation method includes the following steps S1 to S6: Step S1: See Figure 4 A plurality of gate conductive layers 2 and a plurality of first isolation layers 7 are formed on a substrate 1. The first isolation layers 7 are disposed between two adjacent gate conductive layers 2 along a first direction Z perpendicular to the substrate 1. Among the plurality of gate conductive layers 2, at least two gate conductive layers 2 have different coefficients of thermal expansion and different Young's moduli.

[0096] For example, a gate conductive layer 2 and a first isolation layer 7 can be alternately formed on a substrate 1 by a deposition process. One gate conductive layer 2 corresponds to one ferroelectric field-effect transistor 100, and gate conductive layers 2 made of different materials correspond to ferroelectric field-effect transistors 100 with different functions.

[0097] For example, the material of the gate conductive layer 2 can be a metal such as titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), titanium (Ti), tungsten (W), ruthenium (Ru), or an alloy of the above metal materials.

[0098] Deposition processes are key technologies used in many fields, including semiconductor manufacturing, to form uniform thin films on substrate surfaces. Through specific physical or chemical means, the materials constituting the thin film migrate from the source material to the substrate surface in the form of atoms, molecules, or ions, gradually depositing and growing on the substrate to ultimately form a continuous thin film with specific thickness, composition, and properties. Common deposition processes include physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD uses physical methods such as high temperature and high-energy particle bombardment to evaporate or sublimate the source material before depositing it on the substrate. CVD utilizes gaseous chemicals to react on the substrate surface, generating solid thin film materials. These processes allow for precise control of the film's thickness, uniformity, and composition.

[0099] For example, in the embodiments of this application, the deposition process can be physical vapor deposition, chemical vapor deposition, or any other film formation process.

[0100] Step S2: See Figure 5The substrate 1, multiple gate conductive layers 2, and multiple first isolation layers 7 are etched to form a first trench 11, a second trench 12, and a third trench 13. The substrate 1 includes a first surface 101 and a second surface 102 disposed opposite to each other. The first trench 11 extends from the first surface 101 into the substrate 1. The second trench 12 penetrates the gate conductive layer 2. The third trench 13 penetrates the first isolation layer 7. The orthographic projection of the third trench 13 on the substrate 1 at least partially overlaps with the orthographic projection of the first trench 11 on the substrate 1 and the orthographic projection of the second trench 12 on the substrate 1.

[0101] For example, a first trench 11, a second trench 12, and a third trench 13 can be simultaneously formed by etching a substrate 1, multiple gate conductive layers 2, and multiple first isolation layers 7 using photolithography. The first trench 11, the second trench 12, and the third trench 13 together form a vertical trench, forming a vertical surrounding via in the stacked structure composed of the substrate 1, multiple gate conductive layers 2, and multiple first isolation layers 7, thereby reducing process steps and lowering process costs.

[0102] Step S3: See Figure 6 Ferroelectric material layer 30 and oxide semiconductor material layer 40 are sequentially formed in the first trench 11, the second trench 12 and the third trench 13. At least a portion of the ferroelectric material layer 30 covers the inner wall of the first trench 11, the inner wall of the second trench 12 and the inner wall of the third trench 13.

[0103] The first trench 11, the second trench 12, and the third trench 13 together form a vertical trench. The oxide semiconductor layer 4 is disposed in the vertical trench, which is beneficial to improving the control performance of the source 5 and the drain 6 on the channel of the oxide semiconductor layer 4, thereby improving the performance and lifespan of each ferroelectric field-effect transistor 100 in the subsequently formed integrated chip 10.

[0104] For example, an atomic layer deposition process can be used to sequentially form a ferroelectric material layer 30 and an oxide semiconductor material layer 40 in a first trench 11, a second trench 12 and a third trench 13. The ferroelectric material layer 30 is in contact with the gate conductive layer 2 through the second trench 12, and the oxide semiconductor material layer 40 can receive the stress conducted by the gate conductive layer 2 through the ferroelectric material layer 30.

[0105] Step S4: See Figure 7 A second isolation layer 8 is formed in the first trench 11, the second trench 12 and the third trench 13. The second isolation layer 8 is located on the side of the oxide semiconductor material layer 40 away from the ferroelectric material layer 30.

[0106] For example, the second isolation layer 8 can be formed by a deposition process. For instance, the second isolation layer 8 can fill the remaining portions of the first trench 11, the second trench 12, and the third trench 13. It is understood that, along the X direction, the portion of the oxide semiconductor material layer 40 located on the side of the ferroelectric layer 3 away from the substrate 1 is used for electrical connection with the source 5 and the drain 6, respectively. By providing the second isolation layer 8, electrical isolation of the oxide semiconductor material layers 40 with different functions can be achieved.

[0107] Step S5: See Figure 8 A source electrode 5 and a drain electrode 6 are formed on the side of the oxide semiconductor material layer 40 away from the substrate 1.

[0108] For example, a full-surface source / drain electrode layer can be formed by deposition, and then the source / drain electrode layer can be etched by photolithography to form the source 5 and drain 6. Next, the oxide semiconductor material layer 40 and the ferroelectric material layer 30 are etched to define their positions. For instance, during the etching of the source / drain electrode layer and the etching of the oxide semiconductor material layer 40 and the ferroelectric layer 30, etching can be performed through an opening in the same mask, thereby further reducing fabrication costs.

[0109] Step S6: See Figure 1 A thermal annealing process is used to crystallize the oxide semiconductor layer 4 and the ferroelectric layer 3 to form a ferroelectric layer 3 with ferroelectric properties, and a plurality of channel regions 41 with semiconductor properties are formed in the oxide semiconductor layer 4. One channel region 41 is at least partially opposite to a gate conductive layer 2 in the second direction X.

[0110] Understandably, during the thermal annealing process, a portion of the material in the oxide semiconductor layer 4 can transform from an amorphous state to a polycrystalline state under high temperature, and the portion that transforms into a polycrystalline state is the channel region 41. Furthermore, the ferroelectric material layer 30 crystallizes under high temperature, thereby forming the ferroelectric layer 3.

[0111] Since the materials of the ferroelectric layer 3 and the gate conductive layer 2 are different, their coefficients of thermal expansion are different. The difference in their coefficients of thermal expansion will cause a stress difference between them. This stress difference will be conducted through the ferroelectric layer 3 to the oxide semiconductor layer 4, thereby causing the oxide semiconductor layer 4 to be subjected to localized tensile stress. This stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 10.

[0112] In some embodiments, the thermal annealing process includes a heating stage, a holding stage, and a cooling stage. During the heating stage, the peak temperature ranges from 300°C to 700°C. For example, the peak temperature can be 300°C, 400°C, 500°C, 600°C, or 700°C. During the holding stage, the holding time ranges from 10s to 3600s. For example, the holding time can be 10s, 20s, 35s, 50s, 60s, 1000s, 2000s, or 3600s. During the cooling stage, the cooling rate is less than or equal to 10°C / s.

[0113] It is understandable that by setting the process parameters of the above-mentioned thermal annealing process within this range, the stress generated by the gate conductive layer 2 can be effectively conducted to the channel region 41 through the ferroelectric layer 3, and the ferroelectricity and interface integrity of the ferroelectric layer 3 can also be guaranteed.

[0114] For example, the process parameters for each stage of the above-mentioned thermal annealing process can also be as follows: the heating rate in the heating stage is greater than or equal to 10 K / s; the holding temperature range in the holding stage is 400℃~800℃, and the holding time is 5s~600s; the cooling rate in the cooling stage is greater than or equal to 50 K / s. These settings help to improve the ferroelectricity of the ferroelectric layer 3, enhance the semiconductor properties of the oxide semiconductor layer 4, and promote the effect of stress on the threshold voltage of the gate conductive layer 2.

[0115] For example, the material of the gate conductive layer 2 can be a combination of metal materials such as TiN / W, Mo / Ru, or TiN / Ru. The thermal expansion coefficient and Young's modulus of the gate conductive layer 2 can also be adjusted by changing the proportion of different metal elements in it. By rationally configuring the material of the gate conductive layer 2, a wide range of precise threshold voltage control can be achieved, meeting the operational requirements of ferroelectric field-effect transistors 100 with different functions.

[0116] Furthermore, by selecting different gate conductive layer 2 materials in the memory cell, select transistor, reference cell, and other locations, a threshold voltage adjustment range far exceeding that provided by the difference in metal work function can be obtained, thereby realizing the integration of multi-threshold voltage devices under the conditions of one channel deposition and one annealing process.

[0117] The method for fabricating a ferroelectric field-effect transistor integrated chip 10 provided in the embodiments of this application includes forming a plurality of gate conductive layers 2 and a plurality of first isolation layers 7 on a substrate 1. The substrate 1, the plurality of gate conductive layers 2, and the plurality of first isolation layers 7 are etched to form a first trench 11, a second trench 12, and a third trench 13. A ferroelectric material layer 30, an oxide semiconductor material layer 40, and a second isolation layer 8 are sequentially formed in the first trench 11, the second trench 12, and the third trench 13, with the ferroelectric layer 30 contacting the gate conductive layer 2 through the second trench 12. A source electrode 5 and a drain electrode 6 are formed on the side of the oxide semiconductor material layer 40 away from the substrate 1.

[0118] Understandably, the multiple ferroelectric field-effect transistors 100 in the ferroelectric field-effect transistor integrated chip 10 are integrated and stacked along a direction Z perpendicular to the substrate 1, and the multiple ferroelectric field-effect transistors 100 utilize the same oxide semiconductor layer 4 as a channel, thereby reducing the planar size of the integrated chip 10. Furthermore, the multiple ferroelectric field-effect transistors 100 share the same source 5 and drain 6, which can effectively reduce the operating voltage of the vertically stacked ferroelectric field-effect transistors 100 and improve their durability, thus facilitating the realization of a highly integrated, low-power, and highly reliable ferroelectric field-effect transistor integrated chip 10.

[0119] Furthermore, the above preparation method also includes using a thermal annealing process to form an oxide semiconductor layer 4 and a ferroelectric layer 3, and forming a plurality of channel regions 41 in the oxide semiconductor layer 4. One channel region 41 is at least partially opposite to a gate conductive layer 2 in the second direction X. Among the plurality of gate conductive layers 4, at least two gate conductive layers 4 have different coefficients of thermal expansion and different Young's moduli.

[0120] Understandably, multiple channel regions 41 can be formed in the oxide semiconductor layer 4 through a thermal annealing process. During the thermal annealing process, the gate conductive layer 4 expands at high temperature, thereby generating stress. This stress is conducted to the oxide semiconductor layer 4 through the ferroelectric layer 3, resulting in localized tensile stress in the oxide semiconductor layer 4. This tensile stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 100.

[0121] Therefore, by setting the materials of at least two gate conductive layers 4 to have different coefficients of thermal expansion and different Young's moduli, the above-mentioned thermal annealing process can be used to conduct different stresses to the corresponding channel regions 41 through the at least two gate conductive layers 4, so that the ferroelectric field-effect transistors 100 in which the at least two gate conductive layers 4 are located have different threshold voltages. Thus, the threshold voltages of different ferroelectric field-effect transistors 100 in the same vertical channel can be independently modulated without increasing the process flow, thereby improving the integration density and design flexibility of the ferroelectric field-effect transistor integrated chip 10.

[0122] This application also provides an experiment for controlling the threshold voltage of a ferroelectric field-effect transistor. Figures 9-12 The simulation experiment diagrams provided are for embodiments of this application. Wherein, Figure 9 This is a sample diagram of the structural parameters of a ferroelectric field-effect transistor in a simulation experiment. Figure 10 for Figure 9 A schematic diagram showing the temperature change over time of the sample during the thermal annealing process. Figure 11 for Figure 9 A schematic diagram illustrating the expansion and contraction of a portion of the membrane layer in the sample. Figure 12 This diagram illustrates the effect of different gate conductive layers on the threshold voltage in a ferroelectric field-effect transistor.

[0123] See Figure 9 (1) The ferroelectric field-effect transistor comprises a stacked substrate (Si substrate), a gate conductive layer (stress layer), a ferroelectric layer (material HfO2), and an oxide semiconductor layer (material TiO2). The gate conductive layer has a thickness of 40 nm, the ferroelectric layer has a thickness of 8 nm, and the oxide semiconductor layer has a thickness of 6 nm. A stress probe is provided at the interface between the ferroelectric layers, i.e., at the interface between HfO2 and TiO2, to measure the stress at the interface during the thermal annealing process, i.e., the stress experienced by the oxide semiconductor layer.

[0124] Furthermore, the coefficients of thermal expansion (CTE) of TiO2 and HfO2 are 5 × 10⁻⁶ and 5 × 10⁻⁶, respectively. -5 / K and 7×10 -6 The Young's modulus (YM) of TiO2 and HfO2 are 150 GPa and 166 GPa, respectively. The Poisson's ratio (ν) of TiO2 and HfO2 are 0.27 and 0.25, respectively. Poisson's ratio is a dimensionless physical quantity that describes the relationship between transverse strain and axial strain when a material is subjected to stress. It is defined as the ratio of transverse strain to axial strain.

[0125] See Figure 9 (2) The horizontal axis represents the Young's modulus (YM) of the material, the left vertical axis represents the coefficient of thermal expansion (CTE) of the material, and the right vertical axis represents the tensile stress detected by the stress probe, i.e., the tensile stress subjected to the oxide semiconductor layer. The unit of tensile stress is "GPa". At an annealing temperature of 250℃, the coefficient of thermal expansion of titanium nitride (TiN) is approximately 9µm / (m·K) = 9×10 -6 The Young's modulus is approximately 200 GPa. The coefficient of thermal expansion of molybdenum (Mo) is approximately 4.9 µm / (m·K) = 4.9 × 10⁻⁶. -6 The Young's modulus of ruthenium (Ru) is approximately 350 GPa. The coefficient of thermal expansion of ruthenium (Ru) is approximately 9.5 µm / (m·K) = 9.5 × 10⁻⁶. -6 / K, with a Young's modulus of approximately 450 GPa. It is known that titanium nitride (TiN), molybdenum (Mo), and ruthenium (Ru) can all be used as materials for the gate conductive layer.

[0126] It is understandable that the coefficients of thermal expansion and Young's modulus gradually increase in titanium nitride (TiN), molybdenum (Mo), and ruthenium (Ru).

[0127] See Figure 10 The horizontal axis represents time (t), and the vertical axis represents temperature. Figure 10 As can be seen, the hot annealing process can be divided into a heating stage, a holding stage, and a cooling stage. In the diagram, the left side of the dashed line represents the heating and holding stages, while the right side of the dashed line represents the cooling stage.

[0128] See Figure 11 , Figure 11 (1) A schematic diagram of the expansion of the stacked structure of the gate conductive layer 2, the ferroelectric layer 3 and the oxide semiconductor layer 4 before the channel region is formed in the oxide semiconductor layer 4 by adopting the thermal annealing process. Figure 11 (2) is a schematic diagram of the expansion of the stacked structure of the gate conductive layer 2, the ferroelectric layer 3 and the oxide semiconductor layer 4 during the heating and holding stages of the thermal annealing process. Figure 11 (3) is a schematic diagram of the shrinkage of the stacked structure of the gate conductive layer 2, ferroelectric layer 3 and oxide semiconductor layer 4 during the cooling stage of the thermal annealing process.

[0129] Depend on Figure 10 and Figure 11 It is known that the gate conductive layer 2 is in a state of thermal expansion before the thermal annealing process. During the heating and holding stages, the gate conductive layer 2, the ferroelectric layer 3, and the oxide semiconductor layer 4 all expand. Due to the increase in external temperature, some of the ferroelectric layer 3 and the oxide semiconductor layer 4 undergo crystallization reactions, and the gate conductive layer 2 simultaneously undergoes thermal expansion at high temperature.

[0130] During the cooling phase, both the ferroelectric layer 3 and the oxide semiconductor layer 4 shrink. Under the stress generated by the gate conductive layer 2, the grain properties and size of some materials in the oxide semiconductor layer 4, as well as the oxygen vacancy distribution, change. The altered portion constitutes the channel region 41. The grain size and oxygen vacancy distribution of the channel region 41 can change the carrier concentration and mobility of the channel region 41, thereby affecting the threshold voltage of the ferroelectric field-effect transistor 100.

[0131] It is understandable that gate conductive layers 2 made of different materials have different coefficients of thermal expansion and different Young's moduli. During the cooling stage of the thermal annealing process, gate conductive layers 2 made of different materials can apply different and controllable stresses to the channel region 41, thereby regulating the crystallization state and oxygen vacancy distribution of the polycrystalline oxide in the channel region 41, and achieving precise adjustment of the threshold voltage.

[0132] See Figure 12 , Figure 12 (1) For three ferroelectric field-effect transistors with titanium nitride (TiN), molybdenum (Mo), and ruthenium (Ru) as gate conductive layer materials, respectively, their drain current (I) D ) and gate voltage (V G The characteristic relationship curves of ferroelectric field-effect transistors are shown in the figure. Since ferroelectric field-effect transistors have programmed (PRG) and erased (ESR) states, the ferroelectric field-effect transistors in these two different states have different threshold voltages (Vth) and conductivity characteristics. Therefore, the ferroelectric field-effect transistors corresponding to each set of sample parameters have two different characteristic curves.

[0133] Figure 12 (2) for Figure 12 (1) is a line graph showing the relationship between the threshold voltages of the three ferroelectric field-effect transistors in the programmed state (PRG) and erased state (ESR). The horizontal axis represents tensile stress, i.e., the tensile stress exerted on the oxide semiconductor layer, measured in GPa. The vertical axis represents voltage (V). T -WF / e(V), refers to the threshold voltage (V). T Subtract the work function (WF), divide by the electron charge (e), and then divide by the current gate voltage (V). T -WF / e(V) can be used to extract the interfacial trap density of different materials. T-PRG "V" refers to the threshold voltage corresponding to the programmed state. T-ESR "Refers to the threshold voltage corresponding to the erase state."

[0134] Depend on Figure 12It is known that the threshold voltage of a ferroelectric field-effect transistor using titanium nitride (TiN) as the gate conductive layer material is lower than that of a ferroelectric field-effect transistor using molybdenum (Mo) as the gate conductive layer material, and the threshold voltage of both of the above ferroelectric field-effect transistors is lower than that of a ferroelectric field-effect transistor using ruthenium (Ru) as the gate conductive layer material.

[0135] In other words, due to the increasing coefficients of thermal expansion and Young's modulus of titanium nitride (TiN), molybdenum (Mo), and ruthenium (Ru), the tensile stress in the channel region gradually increases with the increasing coefficients of thermal expansion and Young's modulus of the gate conductive layer material. Consequently, the threshold voltage of the ferroelectric field-effect transistor, including the gate conductive layer, gradually increases. Furthermore, the threshold voltage of the ferroelectric field-effect transistor in both the programming and erasing states also gradually increases.

[0136] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ferroelectric field effect transistor integrated chip, characterized by, include: The substrate includes a first surface and a second surface disposed opposite to each other; the substrate also includes a first trench extending from the first surface into the substrate. Multiple gate conductive layers are sequentially stacked on the first surface; Along a first direction perpendicular to the substrate, the gate conductive layer includes a through-type second trench; Multiple first isolation layers are disposed on the first surface; along the first direction, the first isolation layer is disposed between two adjacent gate conductive layers, and the first isolation layer includes a through third trench, the orthographic projection of the third trench on the substrate at least partially overlapping the orthographic projection of the first trench on the substrate and the orthographic projection of the second trench on the substrate. A ferroelectric layer is disposed in the first trench, the second trench and the third trench, and the ferroelectric layer at least partially covers the inner wall of the first trench, the inner wall of the second trench and the inner wall of the third trench; An oxide semiconductor layer is disposed in the first trench, the second trench, and the third trench along a second direction parallel to the substrate, and the oxide semiconductor layer is disposed on the side of the ferroelectric layer away from the gate conductive layer; the oxide semiconductor layer includes a plurality of channel regions, and one channel region is at least partially opposite to a gate conductive layer in the second direction; A second isolation layer is disposed within the first trench, the second trench, and the third trench, and is disposed on the side of the oxide semiconductor layer away from the ferroelectric layer; Both the source and drain electrodes are disposed on the side of the oxide semiconductor layer away from the substrate; Among the plurality of gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

2. The ferroelectric field effect transistor integrated chip of claim 1, wherein, In the plurality of gate conductive layers, the coefficient of thermal expansion of the material of each gate conductive layer is different, and the Young's modulus of the material of each gate conductive layer is different.

3. The ferroelectric field effect transistor integrated chip of claim 2, wherein, Among the plurality of gate conductive layers, the larger the coefficient of thermal expansion and Young's modulus of the material of the gate conductive layer, the larger the threshold voltage of the ferroelectric field-effect transistor device under the same metal work function.

4. The ferroelectric field effect transistor integrated chip of claim 1, wherein, The plurality of gate conductive layers further includes a first gate conductive layer and a second gate conductive layer; The difference between the coefficient of thermal expansion of the material of the first gate conductive layer and the coefficient of thermal expansion of the material of the second gate conductive layer is greater than or equal to 2x10 -6 / K.

5. The ferroelectric field effect transistor integrated chip of claim 1, wherein, The ratio of the thickness of the gate conductive layer in the first direction to the thickness of the channel region in the second direction ranges from 0.25 to 100.

6. The ferroelectric field effect transistor integrated chip of claim 1, wherein, The ratio of the thickness of the ferroelectric layer in the second direction to the thickness of the channel region in the second direction ranges from 1.25 to 20.

7. The ferroelectric field effect transistor integrated chip of claim 1, wherein, The ferroelectric layer material contains 5% to 20% lanthanum by mass, and / or the thickness of the ferroelectric layer along the second direction ranges from 5 nm to 20 nm.

8. The ferroelectric field effect transistor integrated chip of claim 1, wherein, The orthographic projections of the first trench, the second trench, and the third trench on the substrate all coincide.

9. A method for fabricating a ferroelectric field-effect transistor integrated chip, characterized in that, include: Multiple gate conductive layers and multiple first isolation layers are formed on a substrate, and the first isolation layer is disposed between two adjacent gate conductive layers along a first direction perpendicular to the substrate; The substrate, the plurality of gate conductive layers, and the plurality of first isolation layers are etched to form a first trench, a second trench, and a third trench; the substrate includes a first surface and a second surface disposed opposite to each other, the first trench extends from the first surface into the substrate, the second trench penetrates the gate conductive layer, the third trench penetrates the first isolation layer, and the orthographic projection of the third trench on the substrate at least partially overlaps with the orthographic projection of the first trench on the substrate and the orthographic projection of the second trench on the substrate; A ferroelectric material layer and an oxide semiconductor material layer are sequentially formed in the first trench, the second trench, and the third trench; A second isolation layer is formed in the first trench, the second trench and the third trench, the second isolation layer being located on the side of the oxide semiconductor material layer away from the ferroelectric layer; A source and a drain are formed on the side of the oxide semiconductor material layer away from the substrate; An oxide semiconductor layer and a ferroelectric layer are formed using a thermal annealing process, and a plurality of channel regions are formed in the oxide semiconductor layer. Along a second direction parallel to the substrate, one channel region is at least partially opposite to a gate conductive layer. Among the plurality of gate conductive layers, at least two gate conductive layers have different coefficients of thermal expansion and different Young's moduli.

10. The method of claim 9, wherein, The hot annealing process includes a heating stage, a holding stage, and a cooling stage; During the heating phase, the peak temperature ranges from 300℃ to 700℃; during the heat preservation phase, the heat preservation time ranges from 10s to 3600s; and during the cooling phase, the cooling rate ranges from less than or equal to 10℃ / s.

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