Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate, a first transistor, a second transistor and a first gate layer. The first transistor comprises a first semiconductor layer, a first gate and a second gate. The first semiconductor layer is arranged on one side of the substrate, and a channel of the first transistor is located in the first semiconductor layer. The second transistor comprises a second semiconductor layer, a third gate and a fourth gate. The second semiconductor layer is arranged on one side of the substrate, and a channel of the second transistor is located in the second semiconductor layer. The first gate layer is arranged on the side, away from the substrate, of the first semiconductor layer and the second semiconductor layer. The first gate and the third gate are arranged in the first gate layer in the same layer and are spaced apart. The application arranges the gates of the first transistor and the second transistor in the same layer, thereby reducing the number of masks and lowering the manufacturing cost.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and its manufacturing method, and a display panel. Background Technology

[0002] With the development of display technology, consumers are placing increasingly higher demands on display panels for high refresh rates, high resolutions, and low power consumption. Currently, LTPO (Low Temperature Polycrystalline Oxide) backplane technology is widely used in display panels. However, the LTPO backplane structure typically requires multiple metal layers to serve as gates for different types of thin-film transistors. Additionally, the plates for the storage capacitors also require separate metal layers. The formation of these metal layers necessitates patterning with individual photomasks, resulting in a large number of photomasks and a complex manufacturing process for the entire backplane. Summary of the Invention

[0003] To overcome the technical problems mentioned in the above background, embodiments of this application provide an array substrate, including: a substrate; a first transistor including a first semiconductor layer, a first gate, and a second gate, wherein the first semiconductor layer is disposed on one side of the substrate, and the channel of the first transistor is located in the first semiconductor layer; a second transistor including a second semiconductor layer, a third gate, and a fourth gate, wherein the second semiconductor layer is disposed on one side of the substrate, and the channel of the second transistor is located in the second semiconductor layer; and a first gate layer disposed on the side of the first semiconductor layer and the second semiconductor layer away from the substrate; wherein the first gate and the third gate are on the same layer and spaced apart in the first gate layer.

[0004] Furthermore, the first gate serves as the top gate of the first transistor, and the third gate serves as the top gate of the second transistor.

[0005] Furthermore, the array substrate also includes: a second gate layer disposed on the side of the first semiconductor layer and the second semiconductor layer near the substrate, wherein the second gate and the fourth gate are disposed on the same layer and spaced apart in the second gate layer; wherein the second gate serves as the bottom gate of the first transistor and the fourth gate serves as the bottom gate of the second transistor.

[0006] Furthermore, the orthographic projection of the first gate onto the substrate at least partially overlaps with the orthographic projection of the first semiconductor layer onto the substrate; the orthographic projection of the second gate onto the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer onto the substrate; the orthographic projection of the third gate onto the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer onto the substrate; and the orthographic projection of the fourth gate onto the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer onto the substrate. It should be noted that there may be a typo in the projection relationship between the second and third gates here. According to the technical essence, the second gate should be considered the bottom gate of the first transistor, and its projection should overlap with the first semiconductor layer; the third gate should be considered the top gate of the second transistor, and its projection should overlap with the second semiconductor layer.

[0007] Furthermore, the first semiconductor layer and the second semiconductor layer are disposed on the same layer but spaced apart.

[0008] Furthermore, the material of the first semiconductor layer includes a low-temperature polycrystalline silicon semiconductor, and the material of the second semiconductor layer includes a metal oxide semiconductor; or, the material of the first semiconductor layer includes a metal oxide semiconductor, and the material of the second semiconductor layer includes a low-temperature polycrystalline silicon semiconductor.

[0009] Furthermore, the array substrate also includes: a capacitor, the first electrode of which is reused as a first gate; a second electrode disposed on the side of the first electrode facing away from the substrate; and a dielectric layer disposed between the first electrode and the second electrode, wherein the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap.

[0010] Furthermore, the array substrate further includes: an interlayer dielectric layer located on the side of the dielectric layer away from the substrate; a first source / drain electrode disposed on the interlayer dielectric layer and connected to the first semiconductor layer; and a second source / drain electrode disposed on the interlayer dielectric layer and connected to the second semiconductor layer; wherein the first source / drain electrode and the second source / drain electrode are on the same layer and spaced apart.

[0011] The present invention also provides a display panel comprising an array substrate according to any of the above.

[0012] The present invention also provides a method for manufacturing an array substrate, comprising the following steps: providing a substrate; forming a second gate layer on the substrate and patterning a second gate of a first transistor and a fourth gate of a second transistor; forming a buffer layer on the second gate layer; forming a first semiconductor layer and a second semiconductor layer spaced apart on the buffer layer; forming a gate insulating layer on the first semiconductor layer and the second semiconductor layer; forming a first gate layer on the gate insulating layer and patterning a first gate of the first transistor and a third gate of the second transistor, wherein the first gate is multiplexed as a first electrode of a capacitor; forming a dielectric layer on the first gate layer; and forming a second electrode of a capacitor on the dielectric layer.

[0013] Compared with existing technologies, this invention achieves shared use of the top and bottom gate layers by using the first gate layer as the top gate of both the first and second transistors simultaneously, and the second gate layer as the bottom gate of both the first and second transistors simultaneously. Compared to fabricating the gates of two types of transistors separately, this invention reduces at least two photomask processes, significantly simplifying the process and lowering production costs. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of an array substrate according to one embodiment of this application;

[0016] Figure 2 This is a schematic diagram of an array substrate according to one embodiment of this application; Figure 3 This is a schematic diagram of a capacitor according to one embodiment of this application; Figure 4 This is a top view of a capacitor according to one embodiment of this application; Figure 5 This is a flowchart of an array substrate manufacturing method according to one embodiment of this application; Figure 6 This is a schematic diagram of an array substrate according to one embodiment of this application.

[0017] Explanation of reference numerals in the attached figures: 1000, array substrate; 100, substrate; 110, the first transistor; 111, First semiconductor layer; 120, the second transistor; 121, Second semiconductor layer; 200, second gate layer; 210, second gate; 220, fourth gate; 300, buffer layer; 400, gate insulating layer; 500, first gate layer; 510, first gate; 520, third gate; 600, dielectric layer; 700, interlayer dielectric layer; 800, planarization layer; 810, first source / drain; 820, second source / drain; 900, anode layer; 910, pixel-limited layer; 920, support column; C1, the first electrode plate (i.e., 510); C2, the second electrode plate. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0021] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0022] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0023] Figure 1 This application describes an array substrate 1000 according to one embodiment. The array substrate 1000 includes a substrate 100, a first transistor 110 and a second transistor 120 disposed above the substrate 100, and a first gate layer 500.

[0024] It should be noted that the substrate 100 is used to support the entire array substrate 1000. The material of the substrate 100 can be a rigid material such as glass or a flexible material such as polyimide (PI). When used for flexible display panels, polyimide is preferably used as the substrate 100 to give the array substrate the property of being bendable.

[0025] Furthermore, the first transistor 110 includes a first semiconductor layer 111, a first gate 510, and a second gate 210. The first semiconductor layer 111 is disposed on one side of the substrate 100, and the channel of the first transistor 110 is located in the first semiconductor layer 111.

[0026] Further, the second transistor 120 includes a second semiconductor layer 121, a third gate 520, and a fourth gate 220. The second semiconductor layer 121 is disposed on one side of the substrate 100 and on the same side as the first semiconductor layer 111, and the channel of the second transistor 120 is located in the second semiconductor layer 121. The first semiconductor layer 111 and the second semiconductor layer 121 can be made of the same or different semiconductor materials. In this embodiment, the material of the first semiconductor layer 111 is low-temperature polycrystalline silicon (LTPS), and the material of the second semiconductor layer 121 is metal oxide semiconductor, preferably indium gallium zinc oxide (IGZO), and the two materials can be interchanged.

[0027] Furthermore, the first gate layer 500 is disposed on the side of the first semiconductor layer 111 and the second semiconductor layer 121 facing away from the substrate 100. The material of the first gate layer 500 is preferably metallic molybdenum (Mo), which is formed by sputtering (SPT) deposition and patterning processes such as photolithography and etching. The first gate 510 and the third gate 520 are disposed on the same layer and spaced apart from each other in the first gate layer 500.

[0028] Specifically, the first gate 510 is located directly above the first semiconductor layer 111, and their orthogonal projections on the substrate 100 at least partially overlap. The first gate 510 serves as the top gate of the first transistor 110 and is used to control the switching of the first transistor 110. The third gate 520 is located directly above the second semiconductor layer 121, and their orthogonal projections on the substrate 100 at least partially overlap. The third gate 520 serves as the top gate of the second transistor 120 and is used to control the switching of the second transistor 120. The first gate 510 and the third gate 520 are spaced apart from each other in the horizontal direction to avoid electrical interference.

[0029] With the above structure, the top gates of the first transistor 110 and the second transistor 120, namely the first gate 510 and the third gate 520, are disposed on the first gate layer 500 at intervals in the same layer, thus eliminating the need to fabricate separate top gate metal layers for the two types of transistors. This design can save one or more photomask processes, significantly reducing manufacturing costs and process complexity.

[0030] In one embodiment, continue to refer to Figure 1 The first gate 510 serves as the top gate of the first transistor 110, and the third gate 520 serves as the top gate of the second transistor 120. The first gate 510 is disposed directly above the first semiconductor layer 111, with a gate insulating layer 400 disposed between them. When an appropriate voltage is applied to the first gate 510, the electric field penetrates through the gate insulating layer 400 to induce a conductive channel (for enhancement-mode devices) or deplete existing carriers (for depletion-mode devices) in the channel region of the first semiconductor layer 111, thereby controlling the current switching between the source and drain of the first transistor 110. Similarly, the third gate 520 is disposed directly above the second semiconductor layer 121, and the two are also isolated by the gate insulating layer 400. The third gate 520 controls the channel region of the second semiconductor layer 121 through an electric field, thereby realizing the switching control of the second transistor 120.

[0031] Furthermore, the materials of the first gate 510 and the third gate 520 are preferably molybdenum (Mo), which is deposited by sputtering and patterned by photolithography. The first gate 510 and the third gate 520 are disposed on the same layer and spaced apart on the first gate layer 500. They share the same photolithography process, which reduces manufacturing costs and ensures the performance advantages of top gate control for two different types of transistors.

[0032] In one embodiment, continue to refer to Figure 1The array substrate 1000 further includes a second gate layer 200. The second gate layer 200 is disposed on the side of the first semiconductor layer 111 and the second semiconductor layer 121 near the substrate 100. The material of the second gate layer 200 is preferably molybdenum (Mo), which is formed by sputtering (SPT) deposition and patterning processes such as photolithography and etching. The second gate 210 and the fourth gate 220 are disposed on the same layer and spaced apart from each other on the second gate layer 200.

[0033] Specifically, the second gate 210 is located directly below the first semiconductor layer 111, and their orthogonal projections on the substrate 100 at least partially overlap, with the second gate 210 serving as the bottom gate of the first transistor 110; the fourth gate 220 is located directly below the second semiconductor layer 121, and their orthogonal projections on the substrate 100 at least partially overlap, with the fourth gate 220 serving as the bottom gate of the second transistor 120. The second gate 210 and the fourth gate 220 are spaced apart from each other in the horizontal direction to prevent electrical interference.

[0034] In this embodiment, the second gate 210 serves as the bottom gate of the first transistor 110, forming a dual-gate structure of the first transistor 110 together with the first gate 510. When the second transistor 120 uses a metal-oxide-semiconductor (MODS) transistor, the fourth gate 220 serves as the bottom gate of the second transistor 120 and is a conventional control electrode for MODS TFTs. When an appropriate voltage is applied to the fourth gate 220, a conductive channel can be induced in the channel region of the second semiconductor layer 121, controlling the switching of the transistor. Simultaneously, the fourth gate 220 also acts as a light-shielding layer, effectively suppressing photo-induced leakage current and the NBTIS effect caused by light exposure in the IGZO material, ensuring the stability of the second transistor 120 in strong outdoor light environments.

[0035] Furthermore, the first semiconductor layer 111 and the second semiconductor layer 121 are co-located on the side of the second gate layer 200 facing away from the substrate 100. Both are located on the same horizontal plane, and the orthogonal projections of the first semiconductor layer 111 and the second semiconductor layer 121 on the substrate 100 do not overlap; they are spaced apart to avoid signal crosstalk. The first semiconductor layer 111 at least partially overlaps with the second gate 210 in a direction perpendicular to the substrate 100, and the second semiconductor layer 121 at least partially overlaps with the fourth gate 220 in a direction perpendicular to the substrate 100. The first semiconductor layer 111 is made of low-temperature polycrystalline silicon (LTPS), and its formation process includes depositing amorphous silicon (a-Si), crystallizing it into polycrystalline silicon through excimer laser annealing (ELA), and then forming a pattern through photolithography etching. The second semiconductor layer 121 is made of metal oxide semiconductor, preferably indium gallium zinc oxide (IGZO), and is formed by sputtering (SPT) deposition and photolithography etching. It should be noted that the materials of the first semiconductor layer 111 and the second semiconductor layer 121 can be interchanged, that is, the first semiconductor layer 111 can be made of metal oxide semiconductor and the second semiconductor layer 121 can be made of low temperature polycrystalline silicon, which also applies to this embodiment.

[0036] In one embodiment, the second gate layer 200 is a back shielding metal layer (BSM). The second gate layer 200 simultaneously functions as a back shielding metal layer (BSM), which can block mobile ions (such as Na+) from the substrate 100. + K + The back shielding metal layer diffuses into the upper active semiconductor region and blocks ambient light incident from the back of the substrate 100, suppressing photo-induced leakage current in the semiconductor material. The preferred material for the back shielding metal layer is molybdenum (Mo). The back shielding metal layer serves as the second gate 210 and the fourth gate 220, respectively controlling the channel switching of the first semiconductor layer 111 and the second semiconductor layer 121. Furthermore, it also acts as a shield and light blocker. In flexible display panels, the polyimide (PI) substrate 100 inevitably contains mobile ions. The back shielding metal layer can prevent these ions from migrating into the active semiconductor region under the influence of an electric field, thereby suppressing threshold voltage drift and improving device reliability. Simultaneously, the back shielding metal layer is an opaque metal, effectively blocking ambient light incident from the back of the substrate 100, preventing photogenerated carriers from causing photo-induced leakage current in the semiconductor channel. Especially for photosensitive oxide semiconductor materials, this light-blocking effect can significantly improve NBTIS (negative bias temperature photo-stress) characteristics.

[0037] In one embodiment, reference Figure 1 and Figure 2The orthographic projection of the first gate 510 on the substrate 100 at least partially overlaps with the orthographic projection of the first semiconductor layer 111 on the substrate 100; the orthographic projection of the third gate 520 on the substrate 100 at least partially overlaps with the orthographic projection of the second semiconductor layer 121 on the substrate 100; the orthographic projection of the second gate 210 on the substrate 100 at least partially overlaps with the orthographic projection of the first semiconductor layer 111 on the substrate 100; and the orthographic projection of the fourth gate 220 on the substrate 100 at least partially overlaps with the orthographic projection of the second semiconductor layer 121 on the substrate 100.

[0038] Furthermore, the first gate 510 is located directly above the first semiconductor layer 111 and at least covers the main portion of the active region of the first semiconductor layer 111. This overlapping projection relationship allows a conductive channel to be induced in the active region of the first semiconductor layer 111 when an appropriate gate voltage is applied to the first gate 510, thereby controlling the current switching between the source and drain. If the projections do not overlap, the first gate 510 cannot generate effective electric field control over the first semiconductor layer 111, and the transistor will not function properly. Similarly, the third gate 520 is located directly above the second semiconductor layer 121, and its projection at least partially overlaps with the active region of the second semiconductor layer 121 to ensure that the third gate 520 can effectively control the turn-on and turn-off of the second semiconductor layer 121.

[0039] Furthermore, the second gate 210 is located directly below the first semiconductor layer 111, and the projection area of ​​the second gate 210 on the substrate 100 at least covers the active region of the first semiconductor layer 111. This overlapping relationship allows the second gate 210 to apply effective electric field control to the first semiconductor layer 111: when an appropriate gate voltage is applied to the second gate 210, a conductive channel (for enhancement-mode devices) or a depletion channel (for depletion-mode devices) can be induced in the active region of the first semiconductor layer 111, thereby controlling the switching state of the transistor. If the projections do not overlap, the second gate 210 cannot generate an effective electric field on the first semiconductor layer 111, and the transistor will not function properly.

[0040] Furthermore, the first semiconductor layer 111 is made of low-temperature polycrystalline silicon (LTPS), and the second gate 210 serves not only as a bottom gate electrode control channel but also as a back shielding metal layer (BSM). In this case, the projection of the second gate 210 at least partially overlaps with the projection of the first semiconductor layer 111, ensuring that the second gate 210 effectively blocks mobile ions from the substrate 100 from diffusing upwards into the active region of the first semiconductor layer 111, thereby suppressing threshold voltage drift and improving the long-term reliability of the device. Simultaneously, the opaque second gate 210 also blocks ambient light incident from the back of the substrate, reducing photo-induced leakage current.

[0041] Furthermore, the second semiconductor layer 121 is made of metal-oxide-semiconductor (e.g., IGZO) material, and the fourth gate 220 serves as both the bottom gate electrode of the second semiconductor layer 121 and a light-shielding layer. The projection of the fourth gate 220 at least partially overlaps with the projection of the second semiconductor layer 121. On the one hand, this ensures that the fourth gate 220 can effectively control the opening and closing of the IGZO channel; on the other hand, as an opaque metal layer, the fourth gate 220 can block light incident from the back of the substrate, preventing the IGZO channel from generating additional electron-hole pairs due to light exposure. This significantly suppresses photo-induced leakage current and the NBTIS (negative bias temperature photo-stress) effect, ensuring the stability of the oxide semiconductor TFT in strong outdoor light environments.

[0042] In one embodiment, reference Figure 1 and Figure 2 The orthographic projection of the first semiconductor layer 111 on the substrate 100 and the orthographic projection of the second semiconductor layer 121 on the substrate 100 do not overlap, and the first semiconductor layer 111 and the second semiconductor layer 121 are arranged at intervals in the same layer.

[0043] Specifically, the projection area of ​​the first semiconductor layer 111 onto the surface of the substrate 100 in a direction perpendicular to the substrate 100 does not overlap with the projection area of ​​the second semiconductor layer 121 in the same direction. The first semiconductor layer 111 and the second semiconductor layer 121 maintain a certain gap in the planar direction of the substrate 100, avoiding electrical interference that may occur from direct contact or excessive proximity between two different types of semiconductor materials, such as lateral leakage, parasitic channel effects, or impurity cross-diffusion between LTPS and IGZO. By ensuring that the projections do not overlap, the active regions of each thin-film transistor are separated and operate independently, thereby improving the stability and reliability of the pixel circuit. Simultaneously, the first semiconductor layer 111 and the second semiconductor layer 121 are co-located and formed on the upper surface of the buffer layer 300. This co-location allows the first semiconductor layer 111 and the second semiconductor layer 121 to be patterned simultaneously through the same photolithography and etching process, or at least patterned in the same plane, thereby simplifying the manufacturing process and reducing the number of photomasks.

[0044] Furthermore, the first semiconductor layer 111 is a low-temperature polycrystalline silicon (LTPS) pattern, and the second semiconductor layer 121 is a metal-oxide-semiconductor (e.g., IGZO) pattern. A gap of at least 1 to 5 micrometers is maintained between the two patterns in their projection areas on the substrate 100. The size of this gap can be adjusted according to lithographic precision and electrical isolation requirements. This co-layer arrangement and non-overlapping projections allow TFTs made of two different materials to be integrated within the same pixel circuit area, saving layout area and avoiding mutual interference, thus providing favorable conditions for the design of high-resolution display panels.

[0045] Furthermore, the first semiconductor layer 111 is made of low-temperature polycrystalline silicon (LTPS), and the second semiconductor layer 121 is made of metal-oxide-semiconductor (MODS). LTPS has high electron mobility, making it suitable for use as a driving transistor or switching transistor in pixel circuits, providing high charging rates and fast response. MODS is preferably indium gallium zinc oxide (IGZO), which has extremely low off-state leakage current, making it suitable for use as a compensation transistor or initialization transistor, capable of maintaining the voltage in the storage capacitor for extended periods, thereby supporting low-frequency refresh rates (e.g., 1Hz) and always-on display (AoD) functions, and reducing the dynamic power consumption of the display panel.

[0046] Alternatively, the first semiconductor layer 111 may be made of metal-oxide-semiconductor (MODS) and the second semiconductor layer 121 may be made of low-temperature polycrystalline silicon (LTPS), meaning the two semiconductor materials can be interchanged. In this alternative, the first semiconductor layer 111 may use MODS (such as IGZO), and the second semiconductor layer 121 may use LTPS. This combination of materials also achieves the complementary advantages of high mobility and low leakage current, and the choice can be made based on the ease of pixel circuit layout and process integration. For example, placing the MODS in the first semiconductor layer 111 and the LTPS in the second semiconductor layer 121 can also constitute a hybrid thin-film transistor array substrate, and the back shielding metal layer can also provide bottom gate control and light shielding for both. Regardless of which material combination is used, it does not depart from the scope of this invention. This embodiment, by integrating LTPS and IGZO into the same array substrate, can fully utilize the advantages of both materials, achieving a balance between high performance and low power consumption.

[0047] In one embodiment, reference Figures 2 to 4 The array substrate 1000 also includes a capacitor C (not shown in the figure). The first electrode C1 (i.e., the lower electrode of the capacitor) of the capacitor C is reused as a first gate 510. The first gate 510 serves as the top gate electrode of the first semiconductor layer 111 and also extends as an electrode plate of the capacitor. This reuse design eliminates the need to fabricate a separate first electrode plate for the capacitor, thereby saving the number of photomasks and process steps.

[0048] Furthermore, the array substrate 1000 also includes a second electrode C2, i.e., the upper electrode of the capacitor, which is disposed on the side of the first electrode C1 facing away from the substrate 100. The second electrode C2 is located above the first gate 510. The material of the second electrode C2 is preferably a metal, such as molybdenum (Mo) or a titanium / aluminum / titanium stack, which is deposited by sputtering and patterned by photolithography and etching. The orthographic projection of the second electrode C2 on the substrate 100 at least partially overlaps with the orthographic projection of the first electrode C1 on the substrate 100 to ensure that effective capacitive coupling can be formed between them.

[0049] Further, refer to Figure 2 The array substrate 1000 also includes a dielectric layer 600 disposed between the first electrode C1 and the second electrode C2. The dielectric layer 600 can be made of silicon nitride, silicon oxide, silicon oxynitride, or a high dielectric constant material (such as Al2O3 or HfO2), and is formed by chemical vapor deposition or atomic layer deposition. The thickness of the dielectric layer 600 is designed according to the required capacitance value. The dielectric layer 600 covers the upper surface of the first electrode C1 and electrically isolates the first electrode C1 from the second electrode C2, while also serving as the dielectric layer of the capacitor. The first gate 510, the dielectric layer 600, and the second electrode C2 together constitute a parallel-plate capacitor. Capacitor C is typically used as a storage capacitor in pixel circuits to maintain the gate voltage of the driving transistor during the frame cycle, thereby ensuring stable light emission of the OLED. Since the first gate 510 already exists in the array substrate, reusing it as the first electrode of the capacitor eliminates the need for additional photomasks or metal layers, further reducing manufacturing costs and decreasing the area of ​​the pixel circuit, which is beneficial for achieving high-resolution displays.

[0050] Furthermore, the first electrode C1 is made of molybdenum (Mo), the dielectric layer 600 is made of silicon nitride, and the second electrode C2 is made of a titanium / aluminum / titanium stack, wherein the aluminum layer provides low resistance and the titanium layer provides good ohmic contact and barrier properties. The projection of the second electrode C2 onto the substrate 100 covers the projection area of ​​the first electrode C1 to ensure maximum capacitance density.

[0051] In one embodiment, continue to refer to Figure 2 The array substrate 1000 also includes an interlayer dielectric layer 700, a first source / drain electrode 810, and a second source / drain electrode 820. The interlayer dielectric layer 700 is located on the side of the dielectric layer 600 facing away from the substrate 100. That is, the interlayer dielectric layer 700 covers the dielectric layer 600 and the second electrode C2. The material of the interlayer dielectric layer 700 is typically silicon oxide, silicon nitride, or a stack thereof, and it is formed by chemical vapor deposition (CVD). The interlayer dielectric layer 700 is used to protect the underlying gate structure, capacitor structure, and semiconductor channel from damage and impurity contamination in subsequent processes, while providing a planarized surface to create a good interface for the formation of the source / drain electrode; furthermore, contact holes (i.e., lap holes) are formed in the dielectric layer 700 to enable electrical connection between the source / drain electrode and the underlying semiconductor active region.

[0052] Furthermore, the first source / drain 810 is disposed on the interlayer dielectric layer 700 and connected to the first semiconductor layer 111. Specifically, through-hole contact holes are formed in the interlayer dielectric layer 700 and the underlying gate insulating layer 400 through photolithography and etching processes to expose the source and drain regions of the first transistor 110. Then, a metal layer is deposited and patterned to form the first source / drain 810, which is electrically connected to the source and drain regions of the first transistor 110 through the contact holes. The material of the first source / drain 810 is preferably a titanium / aluminum / titanium three-layer stack structure, wherein the aluminum layer provides low resistance and the titanium layer provides good ohmic contact and barrier effect; metals such as molybdenum (Mo) or copper (Cu) can also be used.

[0053] Furthermore, the second source / drain 820 is disposed on the interlayer dielectric layer 700 and connected to the second semiconductor layer 121. Similarly, the source and drain regions of the second semiconductor layer 121 are exposed through the same or separate contact hole etching process, and then a metal layer is deposited and patterned to form the second source / drain 820, which is electrically connected to the source and drain regions of the second semiconductor layer 121 through contact holes. The material of the second source / drain 820 is the same as that of the first source / drain 810, preferably a titanium / aluminum / titanium (Ti / Al / Ti) stack.

[0054] In this design, the first source / drain 810 and the second source / drain 820 are disposed on the same layer. The pattern is formed simultaneously through the same metal deposition and photolithography etching processes, eliminating the need to fabricate separate source / drain metal layers for the first and second semiconductors. This reduces one or more photomask processes, lowering manufacturing costs and process complexity. Furthermore, the co-layer arrangement facilitates wiring connections between the source and drain electrodes, making pixel circuit integration easier.

[0055] Furthermore, firstly, an interlayer dielectric layer 700 is deposited, and then contact holes leading to the source / drain regions of the first semiconductor layer 111 and the second semiconductor layer 121 are simultaneously formed through a single photolithography and etching process. Next, a Ti / Al / Ti multilayer metal is sputtered and deposited, and then the patterns of the first source / drain electrode 810 and the second source / drain electrode 820 are simultaneously formed through a single photolithography and etching process. This process uses only one source / drain metal photomask to fabricate the source / drain electrodes of two different semiconductor TFTs, significantly simplifying the process flow. This feature reflects a further optimization of the present invention in terms of cost reduction.

[0056] In one embodiment, continue to refer to Figure 2The array substrate 1000 further includes a buffer layer 300 and a gate insulating layer 400. The buffer layer 300 is located on one side of the substrate 100 and is disposed between the first semiconductor layer 111 and the second gate layer 200, and between the second semiconductor layer 121 and the second gate layer 200. Specifically, the buffer layer 300 covers the second gate layer 200, while the first semiconductor layer 111 and the second semiconductor layer 121 are formed on the upper surface of the buffer layer 300. Therefore, the buffer layer 300 is located between the second gate layer 200 and the first semiconductor layer 111, and also between the second gate layer 200 and the second semiconductor layer 121, in a direction perpendicular to the substrate 100. The material of the buffer layer 300 is typically silicon oxide, silicon nitride, or a multilayer stack thereof, and it is formed by chemical vapor deposition (CVD). The buffer layer 300 serves to provide a flat surface, facilitating the formation of subsequent semiconductor layers, and further preventing mobile ions and moisture in the substrate 100 from diffusing upwards into the active region of the semiconductor. It also provides thermal uniformity during laser annealing (ELA), promoting uniform crystallization of amorphous silicon into polycrystalline silicon. Since the buffer layer 300 is disposed between the second gate layer 200 and the semiconductor layer, it also acts as an electrical insulator, preventing unnecessary short circuits or leakage between the second gate layer 200 and the semiconductor layer.

[0057] Furthermore, the gate insulating layer 400 is located on the side of the buffer layer 300 facing away from the substrate 100, and is disposed between the first semiconductor layer 111 and the first gate layer 500, and between the second semiconductor layer 121 and the first gate layer 500. The gate insulating layer 400 covers the first semiconductor layer 111 and the second semiconductor layer 121. Specifically, the gate insulating layer 400 is deposited on the buffer layer 300 and covers the upper surface and side surface of the first semiconductor layer 111 and the second semiconductor layer 121. The first gate layer 500 is formed on the upper surface of the gate insulating layer 400. Therefore, the gate insulating layer 400 is located between the first semiconductor layer 111 and the first gate 510 in a direction perpendicular to the substrate 100, and also between the second semiconductor layer 121 and the third gate 520. The material of the gate insulating layer 400 is typically silicon oxide, silicon oxynitride, or a high dielectric constant material, and is formed by chemical vapor deposition or atomic layer deposition.

[0058] Furthermore, the gate insulating layer 400 serves as the gate dielectric layer in the top gate structure. When a voltage is applied to the first gate 510, the gate insulating layer 400 transmits an electric field to the active region of the first semiconductor layer 111, thereby controlling the switching of the transistor. Similarly, the third gate 520 controls the channel of the second semiconductor layer 121 through the gate insulating layer 400. In addition, the gate insulating layer 400 also protects the underlying semiconductor layer from plasma damage and impurity contamination in subsequent processes (such as source / drain deposition and etching).

[0059] Specifically, the buffer layer 300 adopts a three-layer stacked structure of SiO2 / SiNx / SiO2, in which the silicon nitride layer provides good ion blocking capability, and the upper and lower silicon oxide layers provide stress matching and interface optimization. The gate insulating layer 400 adopts a single layer of SiO2, which is formed by plasma-enhanced chemical vapor deposition (PECVD).

[0060] In one embodiment, reference Figure 5 The present invention also provides a method for manufacturing an array substrate.

[0061] S1: Provide a substrate, form a second gate layer 200 on the substrate 100, and pattern the second gate 210 of the first transistor 110 and the fourth gate 220 of the second transistor 120.

[0062] First, a substrate 100 is provided. The substrate 100 can be a rigid glass substrate or a flexible polyimide (PI) substrate. A metal material, preferably molybdenum (Mo), is deposited on the substrate 100 by sputtering. Then, the metal layer is patterned using photolithography (coating, exposure, development) and etching (wet etching or dry etching) processes to form a second gate 210 and a fourth gate 220 spaced apart. The second gate 210 serves as the bottom gate of a subsequently formed first transistor 110, and the fourth gate 220 serves as the bottom gate of a subsequently formed second transistor 120. The second gate layer 200 also serves as a back shielding metal layer (BSM), capable of blocking mobile ions and moisture in the substrate during subsequent processes and providing light-shielding protection for the semiconductor channel.

[0063] S2: A buffer layer 300 is formed on the second gate layer 200.

[0064] A buffer layer 300 is formed on the second gate layer 200 and the exposed substrate 100 by chemical vapor deposition (CVD). The material of the buffer layer 300 is typically silicon oxide, silicon nitride, or a stack thereof (e.g., SiO2 / SiNx / SiO2). The buffer layer 300 covers the entire substrate and serves to planarize, block impurity ions, and provide thermal uniformity for subsequent laser annealing.

[0065] S3: A first semiconductor layer 111 and a second semiconductor layer 121 are formed on the buffer layer 300 at intervals.

[0066] A first semiconductor layer 111 and a second semiconductor layer 121 are formed on the buffer layer 300. Specifically, for the first semiconductor layer 111 (taking low-temperature polycrystalline silicon (LTPS) as an example), an amorphous silicon (a-Si) layer is first deposited by chemical vapor deposition. Then, the amorphous silicon is converted into polycrystalline silicon using an excimer laser annealing (ELA) process. Next, the polycrystalline silicon is patterned by photolithography and etching to form the first semiconductor layer 111. The first semiconductor layer 111 at least partially overlaps with the underlying second gate 210 in a direction perpendicular to the substrate 100. For the second semiconductor layer 121 (taking metal-oxide-semiconductor (IGZO) as an example): an IGZO thin film is deposited by sputtering. Then, the IGZO is patterned by photolithography and etching (wet etching) to form the second semiconductor layer 121. The second semiconductor layer 121 at least partially overlaps with the underlying fourth gate 220 in a direction perpendicular to the substrate 100.

[0067] The first semiconductor layer 111 and the second semiconductor layer 121 are disposed on the upper surface of the buffer layer 300 in the same layer, and their orthogonal projections on the substrate 100 do not overlap to avoid electrical interference. It should be noted that the materials of the first semiconductor layer 111 and the second semiconductor layer 121 can be interchanged, that is, the first semiconductor layer 111 can be made of IGZO and the second semiconductor layer 121 can be made of LTPS, which is also applicable to this method.

[0068] S4: A gate insulating layer 400 is formed on the first semiconductor layer 111 and the second semiconductor layer 121.

[0069] A gate insulating layer 400 is formed by chemical vapor deposition on top of the buffer layer 300, the first semiconductor layer 111, and the second semiconductor layer 121. The material of the gate insulating layer 400 is preferably silicon oxide or silicon oxynitride. The gate insulating layer 400 covers the first semiconductor layer 111 and the second semiconductor layer 121, serving as the gate dielectric layer for the subsequent top gate, while also protecting the semiconductor channel.

[0070] S5: A first gate layer 500 is formed on the gate insulating layer 400, and a first gate 510 and a third gate 520 are patterned, wherein the first gate 510 is multiplexed as the first plate C1 of the capacitor.

[0071] A first gate layer 500, preferably made of molybdenum (Mo), is deposited on top of the gate insulating layer 400 by sputtering. Then, the first gate layer 500 is patterned using photolithography and etching processes to form a first gate 510 and a third gate 520 spaced apart. The first gate 510 is located directly above the first semiconductor layer 111, and their orthogonal projections on the substrate 100 at least partially overlap, with the first gate 510 serving as the top gate of the first semiconductor layer 111. The third gate 520 is located directly above the second semiconductor layer 121, and their orthogonal projections on the substrate 100 at least partially overlap, with the third gate 520 serving as the top gate of the second semiconductor layer 121. Simultaneously, the first gate 510 extends to serve as the first electrode C1 of the capacitor (i.e., the lower electrode of the capacitor), eliminating the need for a separate lower electrode fabrication and thus saving a photomask.

[0072] S6: A dielectric layer 600 is formed above the first gate layer 500.

[0073] A dielectric layer 600 is formed on the first gate layer 500 by chemical vapor deposition or atomic layer deposition. The material of the dielectric layer 600 can be silicon nitride, silicon oxide, or a high dielectric constant material. The dielectric layer 600 covers the first electrode C1 of the capacitor, serving as the dielectric layer of the capacitor.

[0074] S7: The second plate C2 of the capacitor is formed above the dielectric layer 600.

[0075] A metal layer, preferably molybdenum (Mo) or titanium / aluminum / titanium (Ti / Al / Ti) stack, is deposited on top of the dielectric layer 600 by sputtering. This metal layer is then patterned using photolithography and etching processes to form the second electrode C2 of the capacitor. The orthographic projection of the second electrode C2 onto the substrate 100 at least partially overlaps with the orthographic projection of the first electrode C1 onto the substrate 100, thereby forming the storage capacitor C together with the dielectric layer 600 and the first electrode C1.

[0076] In one embodiment, reference Figure 6 Furthermore, according to actual needs, structures such as planarization layer 800, anode 900, pixel limiting layer 910, and support pillar 920 can be further formed. Through the above manufacturing method, the first gate layer (top gate) and the second gate layer (bottom gate) can be shared, and the first top gate can be reused as the lower electrode plate of the capacitor, which greatly reduces the number of photomasks, lowers production costs, and at the same time ensures the performance reliability of two different types of thin film transistors.

[0077] In some possible embodiments, this application also provides a display panel, which includes the array substrate 1000 described in this application. In some possible embodiments, this application also provides a display device, which includes the display panel described in this application. The display device may include a device with image processing capabilities, such as a mobile phone, desktop computer, laptop computer, tablet computer, automotive display, wearable device, etc. Because the display device includes the display panel described in this application, the reliability of the electronic device is higher.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized by, include: Substrate; The first transistor includes a first semiconductor layer, a first gate, and a second gate. The first semiconductor layer is disposed on one side of the substrate, and the channel of the first transistor is located in the first semiconductor layer. The second transistor includes a second semiconductor layer, a third gate, and a fourth gate. The second semiconductor layer is disposed on one side of the substrate, and the channel of the second transistor is located in the second semiconductor layer. A first gate layer is disposed on the side of the first semiconductor layer and the second semiconductor layer that is away from the substrate; The first gate and the third gate are disposed on the same layer and spaced apart from each other in the first gate layer.

2. The array substrate of claim 1, wherein, The first gate serves as the top gate of the first transistor, and the third gate serves as the top gate of the second transistor.

3. The array substrate of claim 1, wherein, Also includes: The second gate layer is disposed on the side of the first semiconductor layer and the second semiconductor layer near the substrate, and the second gate and the fourth gate are disposed on the same layer and spaced apart in the second gate layer; Wherein, the second gate serves as the bottom gate of the first transistor, and the fourth gate serves as the bottom gate of the second transistor.

4. The array substrate according to claim 1, characterized in that, The orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the first semiconductor layer on the substrate; The orthographic projection of the second gate onto the substrate at least partially overlaps with the orthographic projection of the first semiconductor layer onto the substrate; The orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate; The orthogonal projection of the fourth gate onto the substrate at least partially overlaps with the orthogonal projection of the second semiconductor layer onto the substrate.

5. The array substrate of claim 1, wherein, The first semiconductor layer and the second semiconductor layer are on the same layer and spaced apart.

6. The array substrate of claim 1, wherein, The material of the first semiconductor layer includes low-temperature polycrystalline silicon semiconductor, and the material of the second semiconductor layer includes metal oxide semiconductor; or, the material of the first semiconductor layer includes metal oxide semiconductor, and the material of the second semiconductor layer includes low-temperature polycrystalline silicon semiconductor.

7. The array substrate of claim 1, wherein, Also includes: A capacitor, wherein the first plate of the capacitor is reused as the first gate; The second electrode plate is disposed on the side of the first electrode plate that is away from the substrate; as well as, A dielectric layer is disposed between the first electrode and the second electrode, wherein the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap.

8. The array substrate of claim 7, wherein, Also includes: An interlayer dielectric layer is located on the side of the dielectric layer opposite to the substrate; First source / drain; It is disposed on the interlayer dielectric layer and connected to the first semiconductor layer; The second source and drain are disposed on the interlayer dielectric layer and connected to the second semiconductor layer; The first source and drain electrodes are on the same layer as the second source and drain electrodes and are spaced apart.

9. A display panel, characterized by, The array substrate includes any one of claims 1 to 8.

10. A manufacturing method of an array substrate, characterized by, Includes the following steps: A substrate is provided, on which a second gate layer is formed, and a second gate of a first transistor and a fourth gate of a second transistor are patterned. A buffer layer is formed on the second gate layer; A first semiconductor layer and a second semiconductor layer are formed on the buffer layer at intervals; A gate insulating layer is formed on the first semiconductor layer and the second semiconductor layer; A first gate layer is formed on the gate insulating layer, and a first gate of the first transistor and a third gate of the second transistor are patterned thereon, wherein the first gate is multiplexed as the first plate of a capacitor; A dielectric layer is formed on the first gate layer; The second plate of the capacitor is formed on the dielectric layer.

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