Display panel and driving method thereof

Abstract

The application discloses a display panel and a driving method thereof. The display panel comprises a driving unit, a gating circuit and at least two types of data signal lines. Each type of data signal line is connected with a sub-pixel of the same light-emitting color. An input end of the gating circuit is connected with an output channel of the driving unit. The gating circuit has at least two output ends. At least two adjacent output ends are connected with the same type of data signal line. In a row period, the driving unit is used for controlling the gating circuit to sequentially gate the input end and an output end, and sequentially provide driving signals corresponding to data signal lines connected with different output ends through the same output channel. In different data voltages provided by the same output channel, at least two adjacent data voltages are data voltages corresponding to sub-pixels of the same color. The difference between the at least two adjacent data voltages is reduced, so that the voltage jump when the output channel outputs different data voltages in time division can be reduced, and the power consumption of a display driving chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and its driving method. Background Technology

[0002] With the increase in display panel resolution (e.g., from FHD to 4K / 8K) and the growing demand for narrow bezels, the number of output channels (Source drivers, SOPs) of display driver ICs (DDICs) has increased dramatically. To reduce transmission latency and trace count between the DDIC and the display panel, and to effectively reduce module costs, a time-division multiplexing circuit is typically introduced between the SOP and the data lines, time-division multiplexing one SOP to multiple rows of data lines. In existing technologies, when the time-division multiplexing circuit outputs different data voltages at different times, the difference in data voltage is large, resulting in significant variations in the output voltage provided by the SOP, leading to high power consumption of the DDIC. Summary of the Invention

[0003] This invention provides a display panel and its driving method, which can reduce the power consumption of the display driver chip.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a driving unit, a gating circuit, and at least two types of data signal lines; each type of data signal line is connected to a sub-pixel of the same emitting color; The input terminal of the gating circuit is connected to an output channel of the driving unit. The gating circuit has at least two output terminals, and at least two adjacent output terminals are connected to the same type of data signal lines. During the row cycle, the driving unit controls the gating circuit to sequentially select its input terminal and an output terminal, and sequentially provides driving signals corresponding to the data signal lines connected to different output terminals through the same output channel.

[0005] Optionally, the gating circuit includes multiple output terminals; the multiple output terminals of the gating circuit include at least three types of output terminals selected sequentially; each type of output terminal is connected to a type of data signal line; the voltage difference provided by the driving unit for two adjacent selected types of output terminals is less than the voltage difference provided by the driving unit for two separated selected types of output terminals.

[0006] Optionally, the display panel includes multiple sub-pixels arranged in an array; in different row cycles, the output terminal of the driving unit that is last selected in the previous row cycle and the output terminal of the first selected in the next row cycle are of the same type.

[0007] Optionally, at least two gating circuits constitute a gating unit; within the gating unit, the input terminal of each gating circuit is connected to an output channel of the driving unit, all output terminals of each gating circuit are connected to the same type of data signal line, and the output terminals of different gating circuits within the gating unit are respectively connected to different types of data signal lines; the same output channel of the driving unit sequentially provides driving signals corresponding to the same type of data signal lines.

[0008] Optionally, the timing of the drive signals provided by different output channels of the drive unit is the same.

[0009] Optionally, at least two adjacent output terminals of each gating circuit are connected to adjacent data signal lines of the same type; the output terminals of different gating circuits in the same gating unit are connected to different types of data signal lines, and the different types of data signal lines are arranged adjacent to each other.

[0010] Optionally, the row cycle includes multiple driving stages, and the driving unit is used to provide a driving signal corresponding to a data signal line in each driving stage; the duration of the multiple driving stages is equal.

[0011] Optionally, the duration for which the gating circuit selects its input and an output is longer than the duration for which the driving unit provides a driving signal.

[0012] Optionally, the display panel also includes at least two types of connecting lines; one end of each type of connecting line is connected to a type of data signal line, and the other end of each type of connecting line is connected to a sub-pixel of the same luminous color.

[0013] Optionally, the data signal line is disposed on a different layer from at least one connection line, and / or at least two types of connection lines are disposed on different layers.

[0014] Optionally, the sub-pixels with different emission colors include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the data signal lines include a first type of data signal line, a second type of data signal line, and a third type of data signal line; the gating unit includes a first gating circuit, a second gating circuit, and a third gating circuit. At least two adjacent outputs of the first gating circuit are respectively connected to at least two first-class data signal lines, and each first-class data signal line is connected to a column of first sub-pixels; at least two adjacent outputs of the second gating circuit are respectively connected to at least two second-class data signal lines, and each second-class data signal line is connected to a column of second sub-pixels; at least two adjacent outputs of the third gating circuit are respectively connected to at least two third-class data signal lines, and each third-class data signal line is connected to a column of third sub-pixels.

[0015] Secondly, embodiments of the present invention provide a driving method for a display panel, used to drive the display panel of the first aspect; the driving method for the display panel includes: During the row cycle, the control gating circuit sequentially selects its input terminal and one output terminal; The same output channel sequentially provides drive signals corresponding to the data signal lines connected to different output terminals.

[0016] The technical solution of this invention involves connecting at least two adjacent output terminals of a gating circuit to the same type of data signal lines. During a row cycle, the driving unit controls the gating circuit to sequentially select an input terminal and an output terminal, and sequentially provides driving signals corresponding to the data signal lines connected to different output terminals through the same output channel. This ensures that among the different data voltages provided by the same output channel, at least two adjacent data voltages correspond to the data voltages of the same color sub-pixels, reducing the difference between at least two adjacent data voltages. This reduces voltage jumps when the output channel outputs different data voltages in a time-division multiplexing manner, thereby lowering the power consumption of the display driver chip.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of a display panel provided for related technologies; Figure 2 for Figure 1 The timing diagram of the data voltage output by one of the output channels corresponding to the provided display panel; Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 5 for Figure 4 The provided display panel includes a timing diagram of the data voltage output from the first output channel. Figure 6 for Figure 4 A timing diagram of the driving signals for a display panel is provided. Figure 7 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention; Figure 8 A cross-sectional structural diagram of another display panel provided in an embodiment of the present invention; Figure 9 A cross-sectional structural diagram of another display panel provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 11 This is a flowchart illustrating a method for driving a display panel according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 A schematic diagram of a display panel structure provided for related technologies. For example... Figure 1 As shown, the display panel includes multiple time-division multiplexing circuits (MUXs) and an array of pixels P. The input of each MUX is connected to an output channel SOP' of the DDIC. The multiple outputs of each MUX are connected to a column of pixels P via a data line (data). In this case, an output channel SOP' needs to provide data voltage to different columns of pixels P in a time-division multiplexing manner. When the data voltage differences between the different columns of pixels P connected to the multiple outputs of a MUX are relatively large, the voltage jump when an output channel SOP' provides the data voltage corresponding to different pixels P in a time-division multiplexing manner is relatively large, resulting in high power consumption of the DDIC. For example, as... Figure 1As shown, the array of pixels P includes red pixel P1, green pixel P2 and blue pixel P3 arranged sequentially along the row direction. Each time-division multiplexing circuit MUX includes 6 output terminals, which are connected to red pixel P1, green pixel P2 and blue pixel P3 sequentially through data signal lines data. Figure 2 for Figure 1 The provided diagram shows the timing of the data voltage output from one of the output channels of the display panel. R1 represents the data voltage of the first column of red sub-pixels P1, connected to the first output terminal of the time-division multiplexing circuit MUX; G1 represents the data voltage of the first column of green sub-pixels P2, connected to the second output terminal of the time-division multiplexing circuit MUX; B1 represents the data voltage of the first column of blue sub-pixels P3, connected to the third output terminal of the time-division multiplexing circuit MUX; R2 represents the data voltage of the second column of red sub-pixels P1, connected to the fourth output terminal of the time-division multiplexing circuit MUX; G2 represents the data voltage of the second column of green sub-pixels P2, connected to the fifth output terminal of the time-division multiplexing circuit MUX; and B2 represents the data voltage of the second column of blue sub-pixels P3, connected to the sixth output terminal of the time-division multiplexing circuit MUX. Figure 2 It is known that when the output channel SOP' outputs different data voltages in a time-division multiplexing manner, the data voltages of two adjacent data voltages correspond to the data voltages of different emission color sub-pixels, meaning that the difference between two adjacent data voltages is relatively large. This results in large voltage jumps when the output channel SOP' outputs different data voltages in a time-division multiplexing manner, leading to high power consumption of the DDIC.

[0023] To address the aforementioned technical problems, embodiments of the present invention provide a display panel. Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 3 As shown, the display panel includes a driving unit 110, a gating circuit 120, and at least two types of data signal lines D; each type of data signal line D is connected to a sub-pixel P of the same luminous color; the input terminal of the gating circuit 120 is connected to an output channel SOP of the driving unit 110, and the gating circuit 120 has at least two output terminals T, with at least two adjacent output terminals T connected to the same type of data signal line D; within a row cycle, the driving unit 110 controls the gating circuit 120 to sequentially select its input terminal and an output terminal T, and sequentially provides driving signals corresponding to the data signal lines D connected to different output terminals T through the same output channel SOP.

[0024] Specifically, Figure 3The illustration exemplifies three types of luminescent sub-pixels P in a display panel: red sub-pixels PR, green sub-pixels PG, and blue sub-pixels PB. Data signal lines D are divided into three categories: first-category data signal lines D1, second-category data signal lines D2, and third-category data signal lines D3. Each first-category data signal line D1 is connected to a column of red sub-pixels PR, each second-category data signal line D2 is connected to a column of green sub-pixels PG, and each third-category data signal line D3 is connected to a column of blue sub-pixels PB. The driving unit 110 can be a display driver chip (DDIC) with multiple output channels SOP for providing data voltage to each column of sub-pixels P. The display panel includes multiple gating circuits 120, each gating circuit 120 having an input connected to one output channel SOP of the driving unit 110, and at least two outputs T of each gating circuit 120 connected to a data signal line D. The line period of the display panel is the duration required to drive one row of pixels. One frame duration of the display panel may include multiple line periods, each line period used to drive one row of sub-pixels P. When the gating circuit 120 includes at least two output terminals T, the row cycle can include multiple driving stages. In each driving stage, the gating circuit 120 selects one output terminal T and one input terminal, thereby sequentially selecting one row of sub-pixels P within the row cycle, ensuring the normal display of one row of sub-pixels P. During the stage where the driving unit 110 selects one of the output terminals T and one of the input terminals, the driving unit 110 provides the data voltage required by the sub-pixel P connected to that output terminal T, enabling the driving unit 110 to provide corresponding data voltages for sub-pixels P in different columns, ensuring that the sub-pixels P are displayed normally according to the data voltage.

[0025] In the same gating circuit 120, at least two adjacent output terminals T are connected to the same type of data signal line D. Therefore, when the driving unit 110 provides data voltages to different data signal lines D through a time-division multiplexing output channel SOP, at least two adjacent data voltages correspond to the data voltages of the same color sub-pixels P, reducing the difference between at least two adjacent data voltages. This reduces voltage jumps when SOP outputs different data voltages in a time-division multiplexing manner, thus lowering the power consumption of the display driver chip.

[0026] For example, such as Figure 3As shown, the gating circuit 120 includes six output terminals T, from the first to the last, namely the first output terminal T1 to the sixth output terminal T6. When at least two adjacent output terminals T are connected to the same type of data signal line D, the first output terminal T1 and the second output terminal T2 can be connected to the first type of data signal line D1, the third output terminal T3 and the fourth output terminal T4 can be connected to the second type of data signal line D2, and the fifth output terminal T5 and the sixth output terminal T6 can be connected to the third type of data signal line D3. When the gating circuit 120 sequentially selects the first output terminal T1 with the input terminal... and the sixth output terminal T6 with the input terminal, and an output channel SOP provides different data voltages for the gating circuit 120 in a time-division manner, the data voltage provided in the first stage of the selection between the first output terminal T1 and the input terminal, and the data voltage provided in the second stage of the selection between the second output terminal T2 and the input terminal, are both the data voltage corresponding to the red sub-pixel PR, and the difference between the two data voltages is relatively small. This allows for a very small voltage jump when the output channel SOP sequentially outputs the data voltages corresponding to the two red sub-pixels PR, reducing the power consumption of the display driver chip. Similarly, the data voltages provided in the third stage of the selection between the third output terminal T3 and the input terminal, and the data voltages provided in the fourth stage of the selection between the fourth output terminal T4 and the input terminal, are both the data voltages corresponding to the green sub-pixel PG, with a relatively small voltage difference between them. This allows for a very small voltage jump when the output channel SOP sequentially outputs the data voltages corresponding to the two green sub-pixels PG, reducing the power consumption of the display driver chip. Similarly, the data voltages provided in the fifth stage of the selection between the fifth output terminal T5 and the input terminal, and the data voltages provided in the sixth stage of the selection between the sixth output terminal T6 and the input terminal, are both the data voltages corresponding to the blue sub-pixel PB, with a relatively small voltage difference between them. This allows for a very small voltage jump when the output channel SOP sequentially outputs the data voltages corresponding to the two blue sub-pixels PB, reducing the power consumption of the display driver chip.

[0027] It should be noted that, Figure 3The example shown illustrates a gating circuit 120 having multiple output terminals T, with only two adjacent output terminals T connected to the same type of data signal line D. In other embodiments, the gating circuit 120 may have multiple output terminals T, with multiple adjacent output terminals T (the number of which may be less than or equal to the number of output terminals T in the gating circuit 120) connected to the same type of data signal line D, and other output terminals T connected to other types of data signal lines D, without limitation. For example, the gating circuit 120 may have six output terminals T, with the first output terminal T1 to the fourth output terminal T4 connected to the first type of data signal line D1, and the fifth output terminal T5 and the sixth output terminal T6 connected to the second type of data signal line D2. Alternatively, the fifth output terminal T5 and the sixth output terminal T6 may be connected to the third type of data signal line D3. Alternatively, the fifth output terminal T5 and the sixth output terminal T6 may be connected to the second type of data signal line D2 and the third type of data signal line D3, respectively.

[0028] The technical solution of this embodiment connects at least two adjacent output terminals of the gating circuit to the same type of data signal lines. During a row cycle, the driving unit controls the gating circuit to sequentially select an input terminal and an output terminal, and sequentially provides driving signals corresponding to the data signal lines connected to different output terminals through the same output channel. This ensures that among the different data voltages provided by the same output channel, at least two adjacent data voltages correspond to the data voltages of the same color sub-pixels, reducing the difference between at least two adjacent data voltages. This reduces voltage jumps when the output channel outputs different data voltages in a time-division multiplexing manner, thereby lowering the power consumption of the display driver chip.

[0029] Continue to refer to Figure 3 The gating circuit 120 includes multiple output terminals T; the multiple output terminals T of the gating circuit 120 include at least three types of output terminals selected sequentially; each type of output terminal is connected to a type of data signal line D; the voltage difference provided by the driving unit 110 for two adjacent selected output terminals is less than the voltage difference provided by the driving unit 110 for two separated selected output terminals.

[0030] Specifically, the display panel includes multiple sub-pixels P with different emitting colors. Each emitting color sub-pixel P corresponds to a type of data signal line D. Therefore, the display panel includes multiple types of data signal lines D. The gating circuit 120 includes multiple output terminals T, which are divided into at least three types of output terminals according to the category of the connected data signal lines D. Each type of output terminal includes at least two adjacent output terminals T. The output terminal of one type selected in the previous stage and the output terminal of the next stage selected by the gating circuit 120 are two adjacent types of output terminals. Therefore, two types of output terminals selected separately have at least one other type of output terminal between the gating stage of one type of output terminal and the gating stage of the other type of output terminal. For example, as shown... Figure 3As shown, the gating circuit 120 includes six sequentially selected output terminals T. The first output terminal T1 and the second output terminal T2 are first-type output terminals, the third output terminal T3 and the fourth output terminal T4 are second-type output terminals, and the fifth output terminal T5 and the sixth output terminal T6 are third-type output terminals. Therefore, the first-type and second-type output terminals are adjacent to each other, while the first-type and third-type output terminals are alternately selected.

[0031] At least three types of output terminals of the selection circuit 120 are sequentially selected, and the driving unit 110 sequentially provides driving signals to the different types of output terminals. By setting the voltage difference provided by the driving unit 110 to two adjacent selected output terminals to be less than the voltage difference provided by the driving unit 110 to two separated selected output terminals, the voltage difference can be made relatively small when the driving unit 110 outputs driving signals corresponding to different types of data signal lines D sequentially. This results in a small voltage jump when the driving unit 110 outputs different driving signals, further reducing the power consumption of the driving unit 110. For example, in Figure 3 In this configuration, the selection circuit 120 sequentially selects the first output terminal T1 through the sixth output terminal T6. When the selection circuit 120 selects the first output terminal T1 and the second output terminal T2, the driving unit 110 provides the driving signal corresponding to the first type of data signal line D1. When the selection circuit 120 selects the third output terminal T3 and the fourth output terminal T4, the driving unit 110 provides the driving signal corresponding to the second type of data signal line D2. When the selection circuit 120 selects the fifth output terminal T5 and the sixth output terminal T6, the driving unit 110 provides the driving signal corresponding to the third type of data signal line D3. The voltage difference between the drive signal corresponding to the first type of data signal line D1 and the drive signal corresponding to the second type of data signal line D2 provided by the drive unit 110 is less than the voltage difference between the drive signal corresponding to the first type of data signal line D1 and the drive signal corresponding to the third type of data signal line D3 provided by the drive unit 110. This can reduce the voltage jump when the drive unit 110 switches from the drive signal corresponding to the first type of data signal line D1 to the drive signal corresponding to the second type of data signal line D2, thereby further reducing the power consumption of the drive unit 110.

[0032] Continue to refer to Figure 3 The display panel includes multiple sub-pixels P arranged in an array; in different row cycles, the output terminal of the driving unit 110 that is last selected in the previous row cycle and the output terminal that is first selected in the next row cycle are of the same type.

[0033] Specifically, the driving unit 110 can provide a driving signal for a row of sub-pixels P in each row cycle. When multiple output terminals T of the same gating circuit 120 are connected to different types of data signal lines D, the driving unit 110 can sequentially provide driving signals corresponding to different types of data signal lines D within a row cycle. Within different row cycles, if the last type of output terminal selected by the driving unit 110 in the previous row cycle and the first type of output terminal selected in the next row cycle are of the same type, then the driving signal last provided by the driving unit 110 in the previous row cycle and the driving signal first provided in the next row cycle are driving signals corresponding to the same type of data signal line D. That is, the driving signals provided by the driving unit 110 before and after switching between row cycles are driving signals corresponding to the same luminous color sub-pixel P, thereby reducing the voltage jump of the driving unit 110 before and after row cycle switching, further reducing the power consumption of the display driving chip. For example, as shown... Figure 3 As shown, the gating circuit 120 includes three types of output terminals selected sequentially. The first type of output terminal can be connected to the first type of data signal line D1 to provide a driving signal for the red sub-pixel PR. The second type of output terminal can be connected to the second type of data signal line D2 to provide a driving signal for the green sub-pixel PG. The third type of output terminal can be connected to the third type of data signal line D3 to provide a driving signal for the blue sub-pixel PB. During the previous row cycle, the gating circuit 120 sequentially selects the first, second, and third type of output terminals, and the driving unit 110 sequentially provides the gating circuit 120 with the driving signals corresponding to the red sub-pixel PR, the green sub-pixel PG, and the blue sub-pixel PB. During the next row cycle, the gating circuit 120 sequentially selects the third type of output terminal, the first type of output terminal, and the second type of output terminal, and the driving unit 110 sequentially provides the gating circuit 120 with the driving signals corresponding to the blue sub-pixel PB, the red sub-pixel PR, and the green sub-pixel PG. The driving unit 110 can provide the driving signal corresponding to the blue sub-pixel PB before and after the row cycle switching, which reduces the voltage jump of the driving unit 110 and further reduces the power consumption of the display driving chip.

[0034] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 4 As shown, at least two gating circuits 120 constitute a gating unit 10; within the gating unit 10, the input terminal of each gating circuit 120 is connected to an output channel SOP of the driving unit 110, all output terminals T of each gating circuit 120 are respectively connected to the same type of data signal line D, and the output terminals T of different gating circuits 120 within the gating unit 10 are respectively connected to different types of data signal lines D; the same output channel SOP of the driving unit 110 sequentially provides driving signals corresponding to the same type of data signal line D.

[0035] Specifically, the number of gating circuits 120 within the gating unit 10 is the same as the number of emission colors of the sub-pixel P. For example, such as... Figure 4 As shown, sub-pixels P include sub-pixels P with three different emission colors. Therefore, the gating unit 10 consists of three gating circuits 120. The output terminal T of each gating circuit 120 is connected to the same type of data signal line D. The output terminals T of different gating circuits 120 are connected to different types of data signal lines D. This allows the data voltage provided by the same output channel SOP in a time-division manner to be the data voltage corresponding to the sub-pixel P with the same emission color, reducing the difference in data voltage within the row period. This further reduces the voltage jump when the SOP outputs different data voltages in a time-division manner, and reduces the power consumption of the display driver chip.

[0036] For example, such as Figure 4 As shown, sub-pixels P of different emission colors include a first sub-pixel, a second sub-pixel, and a third sub-pixel; data signal lines D include a first type of data signal line D1, a second type of data signal line D2, and a third type of data signal line D3; gating unit 10 includes a first gating circuit 121, a second gating circuit 122, and a third gating circuit 123; at least two adjacent output terminals T of the first gating circuit 121 are respectively connected to at least two first type of data signal lines D1, and each first type of data signal line D1 is connected to a column of first sub-pixels; at least two adjacent output terminals T of the second gating circuit 122 are respectively connected to at least two second type of data signal lines D2, and each second type of data signal line D2 is connected to a column of second sub-pixels; at least two adjacent output terminals T of the third gating circuit 123 are respectively connected to at least two third type of data signal lines D3, and each third type of data signal line D3 is connected to a column of third sub-pixels.

[0037] For example, the first sub-pixel can be a red sub-pixel PR, the second sub-pixel can be a green sub-pixel PG, and the third sub-pixel can be a blue sub-pixel PB. The gating unit 10 includes three gating circuits 120, each with six output terminals T. The input terminal of the first gating circuit 121 is connected to the first output channel SOP1 of the driving unit 110, and its six output terminals T are respectively connected to six Class 1 data signal lines D1. The input terminal of the second gating circuit 122 is connected to the second output channel SOP2 of the driving unit 110, and its six output terminals T are respectively connected to six Class 2 data signal lines D2. The input terminal of the third gating circuit 123 is connected to the third output channel SOP3 of the driving unit 110, and its six output terminals T are respectively connected to six Class 3 data signal lines D2. Within the line cycle, the data voltage output by the first output channel SOP1 in a time-division manner is the data voltage corresponding to the six red sub-pixels PR, reducing the difference in data voltage between different driving stages of the first output channel SOP1 within the line cycle, thereby reducing voltage jumps when the first output channel SOP1 outputs different data voltages in a time-division manner. Specifically, Figure 5 for Figure 4 The provided display panel provides a timing diagram of the data voltage output from the first output channel. R1' to R6' correspond to the data voltages of the six columns of red sub-pixels PR connected to the six output terminals T of the first gating circuit 120, respectively. Figure 5 It can be seen that the different data voltages output by the first output channel SOP1 in a time-division manner are all the data voltages corresponding to the red sub-pixels PR, and the voltage difference is relatively small, thereby reducing the voltage jump caused by the different data voltages output by the first output channel SOP1 in a time-division manner. Similarly, the data voltages output by the second output channel SOP2 in a time-division manner are the data voltages corresponding to the 6 green sub-pixels PG, reducing the difference in data voltages of the second output channel SOP2 in different driving stages within the row cycle, and thus reducing the voltage jump when the second output channel SOP2 outputs different data voltages in a time-division manner. The data voltages output by the third output channel SOP3 in a time-division manner are the data voltages corresponding to the 6 blue sub-pixels PB, reducing the difference in data voltages of the third output channel SOP3 in different driving stages within the row cycle, and thus reducing the voltage jump when the third output channel SOP3 outputs different data voltages in a time-division manner. This reduces the power consumption of the display driver chip. For example, Table 1 is a power consumption comparison table of a display panel in different display modes provided by an embodiment of the present invention. Among them, case 1 is Figure 1 The power consumption of the provided display panel under different display modes, case 2 is... Figure 4The power consumption of the provided display panel under different display modes is shown in Table 1. The power consumption reduction ratio is the ratio of the power consumption of case 2 to that of case 1 under the same display mode, and the average power consumption reduction ratio is the average of the power consumption reduction ratios under different display modes. As can be seen from Table 1, the power consumption of the display panel provided in this application is significantly reduced under different display modes compared to the display panels provided in related technologies, and the average power consumption under different display modes can be optimized by more than 48%. Continue to refer to Figure 4 At least two adjacent output terminals T of each gating circuit 120 are connected to adjacent data signal lines D of the same type; the output terminals T of different gating circuits 120 in the same gating unit 10 are connected to different types of data signal lines D, and the different types of data signal lines D are arranged adjacent to each other.

[0038] Specifically, the data signal lines D are arranged along the row direction of the sub-pixel arrangement and extend along the column direction of the sub-pixel arrangement. Along the row direction of the sub-pixel arrangement, the arrangement order of different types of data signal lines D is the same as the order of the data signal lines D connected to different output channels SOP. At this time, different types of data signal lines D can be arranged as repeating units based on the number of data signal lines connected to the gating unit 10. Within the repeating units of the data signal line arrangement, data signal lines D of the same type are arranged adjacently. After the arrangement of one type of data signal line D is completed, other types of data signal lines D continue to be arranged. At this time, each gating circuit 120 can be connected to adjacent data signal lines D of the same type. Different gating circuits 120 in the same gating unit 10 are respectively connected to adjacent data signal lines D of different types. This ensures that the same output channel SOP provides a driving signal for sub-pixels P of the same color, allowing for a one-to-one correspondence between the data signal lines D and the output terminals T of the gating circuit 120, simplifying the connection between the data signal lines D and the gating circuit 120. For example, as... Figure 4As shown, the gating unit 10 includes three gating circuits 120, each of which includes six output terminals T. Along the row direction of the sub-pixel arrangement, the repeating units of the data signal lines D are: the first first-class data signal line D1, the second first-class data signal line D1...the sixth first-class data signal line D1, the first second-class data signal line D2, the second second-class data signal line D2...the sixth second-class data signal line D2, and the first third-class data signal line D3, the second third-class data signal line D3...the sixth third-class data signal line D3. The first gating circuit 121 can be connected to the first type 1 data signal line D1, the second type 1 data signal line D1...the sixth type 1 data signal line D1, the second gating circuit 122 can be connected to the first type 2 data signal line D2, the second type 2 data signal line D2...the sixth type 2 data signal line D2, and the first gating circuit 121 can be connected to the first type 3 data signal line D3, the second type 3 data signal line D3...the sixth type 3 data signal line D3.

[0039] In some embodiments, the timing of the drive signals provided by different output channels SOP of the drive unit 110 is the same.

[0040] Specifically, the timing of the drive signals provided by the output channel SOP is the timing of the drive signals provided by the output channel SOP within the row cycle. Different output channel SOPs are connected to different gating circuits 120, and each gating circuit 120 has the same number of output terminals T. When the timing of the drive signals provided by different output channel SOPs is the same, the order of the output terminals T of the gating circuits 120 corresponding to the drive signals output by each output channel SOP in the same driving stage is the same, and the duration of each output channel SOP in the same driving stage is the same. This allows different output channel SOPs to output drive signals in parallel, and simplifies the timing settings of the drive signals output by different output channel SOPs, which helps to reduce the performance requirements of the display driver chip, thereby helping to reduce the cost of the display panel. For example, when the gating unit 10 includes three gating circuits 120, and each gating circuit 120 includes 6 output terminals T, the timing of the drive signals is explained using three gating circuits 120 in one gating unit 10 as an example. Figure 6 for Figure 4A timing diagram of driving signals for a display panel is provided, wherein the first stage 1 to the sixth stage 6 are six driving stages in which the gating circuit 120 sequentially selects the first output terminal T1 and input terminal to the sixth output terminal T6 and input terminal within the row cycle. S1 is the emission color corresponding to the driving signal output by the first gating circuit 120 in the first stage 1 to the sixth stage 6 after being output to the sub-pixel P, S2 is the emission color corresponding to the driving signal output by the second gating circuit 120 in the first stage 1 to the sixth stage 6 after being output to the sub-pixel P, and S3 is the emission color corresponding to the driving signal output by the third gating circuit 120 in the first stage 1 to the sixth stage 6 after being output to the sub-pixel P. M1 to M6 are the timing diagrams of the driving signals output by the first output terminal T1 to the sixth output terminal T6 of each gating circuit 120 in the first stage 1 to the sixth stage 6. DATA1 to DATA6 are the data voltages output by the first output terminal T1 to the sixth output terminal T6 of each gating circuit 120 in the first stage 1 to the sixth stage 6. For example, the data voltage DATA1 corresponding to the first output terminal T1 of the first gating circuit 121 is the data voltage corresponding to the first column red sub-pixel PR; the data voltage DATA1 corresponding to the first output terminal T1 of the second gating circuit 122 is the data voltage corresponding to the first column green sub-pixel PG; the data voltage DATA1 corresponding to the first output terminal T1 of the third gating circuit 123 is the data voltage corresponding to the first column blue sub-pixel PB, and so on. Figure 6 As shown, when the timing of the driving signals output from the first output channel SOP1 to the third output channel SOP3 is the same, the first gating circuit 120 to the third gating circuit 120 can all provide driving signals for sub-pixels P of different emitting colors according to the first stage 1 to the sixth stage 6, and the duration of the first stage 1 to the sixth stage 6 of the first gating circuit 120 to the third gating circuit 120 is equal. At this time, the first gating circuit 120 to the third gating circuit 120 simultaneously output the driving signals corresponding to the sub-pixels P of different emitting colors, driving the sub-pixels P of different emitting colors.

[0041] It should be noted that the voltage value of the driving signal is the data voltage of the sub-pixel P connected to the output terminal T of the gating circuit 120 in the current driving stage. In each driving stage from the first stage 1 to the sixth stage 6, the voltage values ​​of the driving signals provided by different output channels SOP are different to ensure that different sub-pixels P can be written with matching data voltages.

[0042] Continue to refer to Figure 6 The line cycle includes multiple driving stages, and the driving unit 110 is used to provide a driving signal corresponding to a data signal line D in each driving stage; the duration of the multiple driving stages is equal.

[0043] Specifically, the number of driving stages is the same as the number of output terminals T of the gating circuit 120. Within each driving stage, the driving unit 110 controls the gating circuit 120 to select one output terminal T and one input terminal, providing a corresponding driving signal to a data signal line D. Within a row cycle, the durations of multiple driving stages can be set to be equal, ensuring that the driving unit 110 controls the gating circuit 120 to select each output terminal T and input terminal for an equal duration. This guarantees that the driving unit 110 provides a driving signal to each data signal line D for an equal duration. Given the limited duration of the row cycle, the accuracy of the driving signal written to each data signal line D can be guaranteed.

[0044] Continue to refer to Figure 6 The duration for which the gating circuit 120 selects its input and an output T is greater than the duration for which the driving unit 110 provides a driving signal.

[0045] Specifically, the duration for which the gating circuit 120 selects its input and one output terminal T is the duration of the driving phase. For example, in Figure 6 In this configuration, the selection circuit 120 selects its input and an output terminal T for a duration equal to the duration of any one of the driving stages from the first stage 1 to the sixth stage 6. The driving unit 110 provides the driving signal corresponding to the output terminal T for a duration equal to the duration of the driving signal output by the driving unit 110 within the driving stage. For example, in... Figure 6 In the first stage (1) to the sixth stage (6), each driving stage has an output channel SOP that outputs a driving signal with a duration ST. By setting the duration of the input and output terminal T of the gating circuit 120 to be greater than the duration of the driving signal corresponding to the output terminal T provided by the driving unit 110, it can be ensured that when the driving unit 110 outputs a driving signal, the output terminal T and the input terminal corresponding to the driving signal are in a gating state, thereby ensuring the writing duration of the driving signal and ensuring the writing accuracy of the driving signal.

[0046] Continue to refer to Figure 4 The display panel also includes at least two types of connection lines L; one end of each type of connection line L is connected to a type of data signal line D, and the other end of each type of connection line L is connected to a sub-pixel P of the same luminous color.

[0047] Specifically, the number of categories of connection line L is the same as the number of categories of data signal line D. For example, when data signal line D includes a first-category data signal line D1, a second-category data signal line D2, and a third-category data signal line D3, connection line L includes a first-category connection line L1, a second-category connection line L2, and a third-category connection line L3. The display panel can have different pixel arrangements. For example, such as... Figure 4As shown, the display panel uses an RGB pixel arrangement, meaning each row of pixels is arranged in a repeating pattern of red sub-pixels PR, green sub-pixels PG, and blue sub-pixels PB. When sub-pixels P of different colors do not match data signal lines D of different classes in the column direction of the sub-pixel arrangement, each color sub-pixel P can be connected to the corresponding class of data signal line D through a connection line L, thus enabling a connection between a data signal line D and a sub-pixel P of a specific color.

[0048] For example, such as Figure 4 As shown, the arrangement of sub-pixels P in a row is a repetitive arrangement of red sub-pixels PR, green sub-pixels PG, and blue sub-pixels PB. The arrangement of data signal lines D is a repetitive arrangement of the first to sixth type 1 data signal lines D1, the first to sixth type 2 data signal lines D2, and the first to sixth type 3 data signal lines D3. The first to sixth type 1 data signal lines D1 are connected to the first to sixth red sub-pixels PR via six type 1 connecting lines L1. The first to sixth red sub-pixels PR are located in the first, fourth, seventh, tenth, thirteenth, and sixteenth columns of the row of sub-pixels P, respectively. The first to sixth type 2 data signal lines D2 are connected to the first to sixth green sub-pixels PG via six type 2 connecting lines L2. The first to sixth green sub-pixels PG are located in the second, fifth, eighth, eleventh, fourteenth, and seventeenth columns of the row of sub-pixels P, respectively. The first to sixth Class 3 data signal lines D3 are connected to the first to sixth blue sub-pixels PB via the third connecting line L2. The first to sixth blue sub-pixels PB are located in the third, sixth, ninth, twelfth, fifteenth, and eighteenth columns of a row of sub-pixels P, respectively.

[0049] It should be noted that, Figure 4 An RGB pixel arrangement is illustrated as an example. In other embodiments, the display panel may also employ other pixel arrangements, which are not limited here, as long as a type of data signal line D is connected to a sub-pixel P of the same color through a type of connection line L.

[0050] Figure 7 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. Figure 7 As shown, the data signal line D and at least one connection line L are arranged on different layers.

[0051] Specifically, the number of data signal lines D and connecting lines L is relatively large, while the display panel area is relatively small. When the data signal line D is connected to the sub-pixel P through the connecting line L, the data signal line D and at least one connecting line L can be set to be on different layers. This can reduce the number of wirings on the same conductive layer, thereby reducing the wiring difficulty of the display panel. For example, as shown... Figure 7 As shown, the data signal line D is on a different layer than all the connection lines L.

[0052] In other embodiments, Figure 8 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention. Figure 8 As shown, at least two types of connecting lines L are arranged in different layers.

[0053] Specifically, when data signal connection line D is connected to sub-pixel P via connection line L, connection line L has a portion extending along the row direction of the sub-pixel arrangement and crossing other connection lines L. In this case, setting at least two types of connection lines L in different layers avoids short circuits due to contact between different connection lines L, ensuring the reliability of the connection between data signal line D and sub-pixel P. For example, as shown... Figure 4 As shown, when the second first-type connection line L1 connects to the second red sub-pixel PR in the fourth column, and the first second-type connection line L2 connects to the first green sub-pixel PG in the second column, the second first-type connection line L1 and the first second-type connection line L2 intersect horizontally. In this case, the first-type connection line L1 and the second-type connection line L2 can be set to different layers to avoid short circuits. Similarly, when the first third-type connection line L3 connects to the first blue sub-pixel PB in the third column, the second first-type connection line L1 and the first third-type connection line L3 intersect horizontally. Again, the first-type connection line L1 and the third-type connection line L3 can be set to different layers to avoid short circuits. For example, in... Figure 8 In this configuration, the first type of connecting line L1, the second type of connecting line L2, and the third type of connecting line L3 are all arranged in different layers.

[0054] Figure 9 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention. Figure 9 As shown, the data signal line D, the first type connection line L1, the second type connection line L2, and the third type connection line L3 can also be set to different layers, which is not limited here.

[0055] In other embodiments, the data signal line D includes a first end and a second end. The first end is connected to the sub-pixel P, and the second end is connected to the output terminal T of the gating circuit 120. When the data signal line D provides driving signals for different sub-pixels P, a column of data signal lines D can also be configured to connect to the same column of sub-pixels P, and the second end of the data signal line D can be connected across the output terminal T of the gating circuit 120, so that the same gating circuit 120 provides driving signals for sub-pixels P of the same emission color. For example, Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 10 As shown, along the row direction of the sub-pixel arrangement, the arrangement of different types of data signal lines D is the same as that of sub-pixels P, so that the nth data signal line D is directly connected to the nth column of sub-pixels P, simplifying the wiring design of the display panel display area. Here, n is an integer greater than or equal to 1. The second end of the data signal line D is connected to the output terminal T of the corresponding selection circuit 120 through a jumper. When the output terminal T of the selection circuit 120 sequentially outputs the driving signals corresponding to the sub-pixels P of the same luminous color, the display panel can be driven normally. Specifically, as shown... Figure 10 As shown, the six output terminals T of the first gating circuit 121 are connected sequentially to the first type I data signal line D1 to the sixth type I data signal line D1, the six output terminals T of the second gating circuit 122 are connected sequentially to the first type II data signal line D2 to the sixth type II data signal line D2, and the six output terminals T of the third gating circuit 123 are connected sequentially to the first type III data signal line D3 to the sixth type III data signal line D3.

[0056] This invention also provides a method for driving a display panel, used to drive the display panel provided in any embodiment of this invention. Figure 11 This is a schematic flowchart illustrating a driving method for a display panel according to an embodiment of the present invention. Figure 11 As shown, the driving method for this display panel includes: S11. During the row cycle, the control gating circuit sequentially selects its input terminal and one output terminal.

[0057] S12. Drive signals corresponding to data signal lines connected to different output terminals are provided sequentially through the same output channel.

[0058] The technical solution of this embodiment controls the selection circuit to sequentially select the input terminal and an output terminal, and sequentially provides the driving signals corresponding to the data signal lines connected to different output terminals through the same output channel. This ensures that among the different data voltages provided by the same output channel, at least two adjacent data voltages are the data voltages corresponding to the same color sub-pixels, reducing the difference between at least two adjacent data voltages. This reduces the voltage jump when the output channel outputs different data voltages in a time-division manner, thereby reducing the power consumption of the display driver chip.

[0059] In some embodiments, at least two gating circuits 120 constitute a gating unit 10; within the gating unit 10, the input terminal of each gating circuit 120 is connected to an output channel SOP of the driving unit 110, and at least two output terminals T of each gating circuit 120 are respectively connected to the same type of data signal line D. The driving method for the display panel further includes: Drive signals for the same type of data signal lines are provided sequentially through the same output channel.

[0060] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, It includes a driving unit, a gating circuit, and at least two types of data signal lines; each type of data signal line is connected to a sub-pixel of the same emission color; The input terminal of the gating circuit is connected to an output channel of the driving unit. The gating circuit has at least two output terminals, and at least two adjacent output terminals are connected to the same type of data signal lines. During a row cycle, the driving unit controls the gating circuit to sequentially select its input terminal and an output terminal, and sequentially provides driving signals corresponding to the data signal lines connected to different output terminals through the same output channel.

2. The display panel according to claim 1, characterized in that, The gating circuit includes a plurality of output terminals; the plurality of output terminals of the gating circuit includes at least three types of output terminals selected sequentially; each type of output terminal is connected to a type of data signal line; the voltage difference provided by the driving unit for two adjacent selected types of output terminals is less than the voltage difference provided by the driving unit for two separated selected types of output terminals.

3. The display panel according to claim 2, characterized in that, The display panel includes a plurality of sub-pixels arranged in an array; in different row cycles, the output terminal of the driving unit that was last selected in the previous row cycle and the output terminal of the first selected in the next row cycle are of the same type.

4. The display panel according to claim 1, characterized in that, At least two of the aforementioned gating circuits constitute a gating unit; within the gating unit, the input terminal of each of the aforementioned gating circuits is connected to one of the output channels of the driving unit, all the output terminals of each of the aforementioned gating circuits are connected to the same type of data signal lines, and the output terminals of different of the aforementioned gating circuits within the gating unit are respectively connected to different types of data signal lines; the same output channel of the driving unit sequentially provides driving signals corresponding to the same type of data signal lines.

5. The display panel according to claim 4, characterized in that, The timing of the drive signals provided by the different output channels of the drive unit is the same.

6. The display panel according to claim 4, characterized in that, At least two adjacent output terminals of each of the gating circuits are respectively connected to adjacent data signal lines of the same type; the output terminals of different gating circuits in the same gating unit are respectively connected to different types of data signal lines, and the different types of data signal lines are arranged adjacent to each other.

7. The display panel according to claim 1, characterized in that, The row cycle includes multiple driving stages, and the driving unit is used to provide a driving signal corresponding to a data signal line in each driving stage; the duration of the multiple driving stages is equal.

8. The display panel according to claim 1, characterized in that, The duration for which the gating circuit selects its input and output terminals is greater than the duration for which the driving unit provides a driving signal.

9. The display panel according to any one of claims 1-7, characterized in that, It also includes at least two types of connecting lines; one end of each type of connecting line is connected to one type of data signal line, and the other end of each type of connecting line is connected to the sub-pixel of the same luminous color.

10. The display panel according to claim 9, characterized in that, The data signal line is disposed on a different layer from at least one of the connection lines, and / or at least two types of the connection lines are disposed on different layers.

11. The display panel according to claim 4, characterized in that, The sub-pixels with different emission colors include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the data signal lines include a first type of data signal line, a second type of data signal line, and a third type of data signal line; the gating unit includes a first gating circuit, a second gating circuit, and a third gating circuit. At least two adjacent output terminals of the first gating circuit are respectively connected to at least two first-type data signal lines, and each first-type data signal line is connected to a column of first sub-pixels; at least two adjacent output terminals of the second gating circuit are respectively connected to at least two second-type data signal lines, and each second-type data signal line is connected to a column of second sub-pixels; at least two adjacent output terminals of the third gating circuit are respectively connected to at least two third-type data signal lines, and each third-type data signal line is connected to a column of third sub-pixels.

12. A method for driving a display panel, used to drive the display panel according to any one of claims 1-11; characterized in that, The driving method for the display panel includes: During the row cycle, the control gating circuit sequentially selects its input terminal and one output terminal; Drive signals corresponding to the data signal lines connected to different output terminals are provided sequentially through the same output channel.

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