A matrix-integrable structure for a high-speed InGaAs PD detector chip and its fabrication method

Abstract

The application relates to the technical field of semiconductor optoelectronic devices, in particular to a matrix-integrable structure of a high-speed InGaAs PD detection chip and a preparation method thereof. The structure comprises a semi-insulating InP substrate, a first n-InP layer, an intrinsic InGaAs layer and a p+ InP layer which are sequentially formed on the substrate, a photosensitive surface region is arranged in the p+ InP layer, the p+ InP layer outside the photosensitive surface region is removed, and the intrinsic InGaAs layer is exposed, a second n-InP layer is formed on the exposed intrinsic InGaAs layer through secondary epitaxy, and the second n-InP layer is electrically connected with the first n-InP layer. The application limits the PN junction in the photosensitive surface through secondary epitaxy, significantly reduces the capacitance to 0.05 pF, the dark current is less than 50 pA, the responsivity is higher than 0.95 A / W, and the matrix integration is easy to realize, and the application is suitable for high-speed optical communication above 50G.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, specifically to a matrix-integrable structure of a high-speed InGaAs PD detector chip and its fabrication method. Background Technology

[0002] InGaAs materials are widely used in fiber optic communication, lidar, and photoelectric detection due to their excellent photoelectric response in the 1000nm~2600nm wavelength range. Traditional high-speed InGaAs digital devices (PDs) typically employ diffusion methods to form pn junctions, such as Zn3P2 diffusion or MOCVD doping of Zn to form the p+ region. However, diffusion methods suffer from difficulties in precisely controlling diffusion depth and width, and inhomogeneous doping concentration, resulting in large device capacitance (typically >0.1pF@5V), which is insufficient to meet the <0.1pF capacitance requirement of 50G and above high-speed communication systems. This also affects the device's dark current and yield. Furthermore, the traditional structure is not conducive to array integration, limiting its application in high-density optical interconnects and array receivers.

[0003] Therefore, how to further reduce the junction capacitance of InGaAs PD, improve process controllability, and simultaneously achieve device matrix integration while ensuring high responsivity and low dark current is a technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a matrix-integrable structure for a high-speed InGaAs PD detector chip and its fabrication method.

[0005] The technical solution of this invention is implemented as follows: In a first aspect, the present invention proposes a matrix-integrable structure for a high-speed InGaAs PD detector chip, comprising a semi-insulating InP substrate; A first n-InP layer, an intrinsic InGaAs layer, and a p+InP layer are sequentially formed on the substrate; The p+InP layer has a photosensitive surface region. The p+InP layer outside the photosensitive surface region is removed to expose the intrinsic InGaAs layer. A second n-InP layer is formed on the exposed intrinsic InGaAs layer by secondary epitaxy. The second n-InP layer is electrically connected to the first n-InP layer. An insulating dielectric layer covers the p+InP layer and the second n-InP layer, and has a first electrode window exposing the p+InP layer and a second electrode window exposing the back side of the substrate; The p electrode is disposed within the first electrode window and electrically connected to the p+InP layer; The n-electrode is disposed on the back side of the substrate.

[0006] Preferably, the photosensitive surface is circular or rectangular, with a diameter or side length of 5μm to 40μm.

[0007] Preferably, the insulating dielectric layer comprises a silicon nitride layer with a refractive index of 1.8 to 2.0 and a thickness of 180 nm to 220 nm.

[0008] Preferably, the materials of the p electrode and n electrode include one or more of Ti, Pt, Au, Ni, and Al.

[0009] Preferably, the thickness of the p+InP layer is 100nm~1000nm; the thickness of the intrinsic InGaAs layer is 2.0μm~3.0μm; the thickness of the first n-InP layer is 0.4μm~0.6μm; and the thicknesses of the second n-InP layer and the p+InP layer are equal.

[0010] Preferably, multiple matrix-integrable structures are arranged in an array on the same substrate.

[0011] In a second aspect, the present invention provides a method for fabricating a matrix-integrable structure as described in the first aspect, comprising the following steps: S1. A first n-InP layer, an intrinsic InGaAs layer, and a p+InP layer are epitaxially grown sequentially on a semi-insulating InP substrate. S2. Remove the p+InP layer outside the photosensitive surface region to expose the intrinsic InGaAs layer; S3. A second n-InP layer is grown on the exposed intrinsic InGaAs layer by secondary epitaxy, and phosphorus-containing precursor and indium-containing precursor are introduced during the secondary epitaxy process. S4. Protect the photosensitive surface and its sidewalls to form a portion of the second n-InP layer, and etch the remaining portion to the semi-insulating substrate; S5. Deposit an insulating dielectric layer and create openings to expose the p+InP layer and the back side of the substrate; S6, forming p and n electrodes.

[0012] Preferably, the secondary epitaxial process parameters in step S3 include: a temperature of 550℃~650℃, a reaction chamber pressure of 45mbar~55mbar, a carrier gas of H2, a phosphorus-containing precursor including PH3 with a flow rate of 900sccm~1100sccm, and an indium-containing precursor including TMIn with a flow rate of 40sccm~60sccm.

[0013] Preferably, in step S2, dry etching is used to remove the p+InP layer, and the etching gas includes a mixture of Cl2, CH4 and H2, with an etching depth of 100nm~1000nm.

[0014] More preferably, the width distance of the portion of the second n-InP layer in step S4 is 10~20μm.

[0015] Thirdly, the present invention provides an optoelectronic device comprising a matrix-integrable structure as described in the first aspect and a laser, wherein the matrix-integrable structure is integrated with the laser.

[0016] Compared with the prior art, the advantages of the present invention are as follows: (1) The present invention forms n-InP sidewalls through secondary epitaxy, which strictly limits the pn junction to the photosensitive surface area, greatly reducing the junction capacitance. The measured capacitance can be as low as 0.05pF@5V, which is suitable for high-speed detection above 50G.

[0017] (2) The present invention avoids the problems of uneven doping and uncontrollable depth in traditional diffusion processes by using dry etching combined with secondary epitaxy, and the dark current can be as low as 50pA or less.

[0018] (3) The integrated structure prepared by the present invention is flat and can be easily integrated with lasers or other optoelectronic devices by photolithography and etching to achieve a high-density matrix array. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a cross-sectional view of the layer structure after the first extension of the present invention; Figure 2 This is a cross-sectional view of the p+InP layer outside the photosensitive surface after dry etching according to the present invention; Figure 3 This is a cross-sectional view of the second n-InP layer after secondary epitaxial growth according to the present invention; Figure 4 This is a cross-sectional view of the portion of the second n-InP layer formed to protect the photosensitive surface and its sidewalls of the present invention, after etching the remaining portion to the semi-insulating substrate. Figure 5 This is a cross-sectional view of the insulating dielectric layer (silicon nitride) deposited according to the present invention; Figure 6 This is a cross-sectional view of the final structure after the holes are opened and the p-electrode and n-electrode are formed in this invention; Figure 7 This is a cross-sectional view of the layer structure after the first epitaxy using a traditional diffusion process. Figure 8 A cross-sectional view of the photosensitive surface after depositing an insulating layer and etching an opening in the traditional diffusion process; Figure 9 Cross-sectional view of Zn3P2 diffusion to form a p+InP layer using conventional diffusion process; Figure 10 This is a cross-sectional view of the substrate after traditional diffusion etching to isolate the material to a semi-insulating substrate. Figure 11 This is a cross-sectional view of the final structure after the traditional diffusion process deposits an insulating layer, creates pores, and forms electrodes.

[0021] Wherein, 1-semi-insulating InP substrate; 2-first n-InP layer; 3-intrinsic InGaAs layer; 4-p+InP layer; 5-second n-InP layer. Detailed Implementation

[0022] The embodiments of the present invention are described in detail below. These embodiments are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0023] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0024] In this document, the terms “containing,” “comprising,” or “including” are open-ended expressions, meaning they include the contents specified in this invention but do not exclude other aspects.

[0025] In this document, the terms “optional,” “optionally,” or “optional” generally refer to an event or condition that may, but may not, occur, and the description includes both cases in which the event or condition occurs and cases in which the event or condition does not occur.

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0027] Unless otherwise specified, all reagents used in this invention can be purchased from the market.

[0028] Example 1 This embodiment provides a matrix-integrable structure for a high-speed InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 1 The first n-InP layer 2 (thickness 0.5 μm, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate 1 (thickness 350 μm, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer 3 (thickness 2.5 μm, carrier concentration 1 × 10⁻⁶), 15 cm -3 ), p+InP layer 4 (thickness 0.5μm, carrier concentration 1×10), 19 cm -3 ); (2) A photosensitive surface area (circular, 10 μm in diameter) is formed on the p+InP layer 4 by photolithography. The photosensitive surface area is covered and protected by thick photoresist (5 μm thick). The photoresist in the remaining areas is removed by development. (3) Reference Figure 2 The etching was performed using an ICP device with a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively. The ICP power was 75W, the chamber temperature was 100℃, the pressure was 5mTorr, and the etching depth was 500nm. The p+InP layer 4 outside the photosensitive surface was completely removed, exposing the underlying intrinsic InGaAs layer 3. After etching, the p+InP layer 4 in the photosensitive surface region was preserved by photoresist. (4) Reference Figure 3 After removing the remaining photoresist, the wafer is placed in the MOCVD reaction chamber for secondary epitaxy. The specific process is as follows: the reaction chamber pressure is 50 mbar, and the carrier gas is switched from N2 (25 L / min) to H2 (25 L / min) within 7.5~10 min, while the temperature is raised from room temperature (25℃) to 300℃; from 10 to 12.5 min, PH3 is introduced at 300℃ to 1000 sccm, and from 12.5 to 15 min, the temperature is raised to 600℃; from 15 to 27.5 min, TMIn is introduced at 600℃, PH3 at 1000 sccm, and H2 at 25 L / min to 50 sccm, obtaining an n-InP layer with a thickness of 0.5 μm; TMIn is turned off at 27.5 min, the temperature is lowered to 300℃ from 27.5 to 30 min, the temperature is lowered to room temperature and PH3 is turned off from 30 to 33 min, and N2 purging is resumed from 33 to 40 min and the pressure is depressurized to 0 mbar; the second n-InP layer 5 is obtained. (5) Reference Figure 4The second n-InP layer 5, formed by protecting the photosensitive surface and its sidewalls with thick photoresist (5 μm thick) using a photolithography process, retains a width of 15 μm. The photoresist to be etched is removed by exposure and development, exposing the remaining area (including the secondary epitaxial layer and the underlying intrinsic layer). ICP etching is performed using a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively, with a power of 75 W, a chamber temperature of 100 °C, and a pressure of 5 mTorr, etching down to the semi-insulating InP substrate 1 at a rate of 400 nm / min. This step forms deep trench isolation between devices. (6) Reference Figure 5 Silicon nitride (SiN2) was deposited using PECVD as the insulating dielectric layer. The deposition conditions were: temperature 350℃, RF power 50W, reaction chamber pressure 200Pa, and SiH4 / NH3 flow ratio 1100:3300 sccm. The deposited silicon nitride layer was 200nm thick and had a refractive index of 1.9. This insulating layer covered the entire surface, including the photosensitive surface, trench sidewalls, and bottom. (7) Reference Figure 6 The photolithography process was employed, with photoresist (1 μm thick) used for protection. The photoresist was removed from the areas to be etched by exposure and development. Silicon nitride was etched using ICP, with 80 sccm of CF4 and 10 sccm of O2 as the etching gases. The etching rate was 100 nm / min, the power was 50 W, the chamber temperature was 60 °C, and the pressure was 25 mTorr. After etching, the surface of the p+InP layer 4 was exposed. (8) Using photolithography, photoresist is used for protection (thickness 5μm). The area to be plated with metal is developed by exposure and development. The p electrode is drawn from the p+InP layer 4 using an electron gun evaporation machine. The metal is Ti / Pt / Au, and the total thickness is 1μm. The back side of the substrate is thinned to a thickness of 120μm. On the back side of the thinned substrate, the n electrode is fabricated using photolithography and evaporation processes. The metal is AuGeNi / Au, and the total thickness is 0.8μm.

[0029] Example 2 This embodiment provides a matrix-integrable structure for a high-speed InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 1 The first n-InP layer 2 (thickness 0.4 μm, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate 1 (thickness 350 μm, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer 3 (thickness 2.0 μm, carrier concentration 1 × 10⁻⁶), 15 cm -3), p+InP layer 4 (thickness 0.1 μm, carrier concentration 1 × 10⁻⁶) 19 cm -3 ); (2) A photosensitive surface area (circular, 5 μm in diameter) is formed on the p+InP layer 4 by photolithography. The photosensitive surface area is covered and protected by thick photoresist (5 μm thick). The photoresist in the remaining areas is removed by development. (3) Reference Figure 2 The etching was performed using an ICP device with a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively. The ICP power was 75W, the chamber temperature was 100℃, the pressure was 5 mTorr, and the etching depth was 100 nm. The p+InP layer 4 outside the photosensitive surface was completely removed, exposing the underlying intrinsic InGaAs layer 3. After etching, the p+InP layer 4 in the photosensitive surface area was preserved by photoresist. (4) Reference Figure 3 After removing the remaining photoresist, the wafer is placed in the MOCVD reaction chamber for secondary epitaxy. The specific process is as follows: the reaction chamber pressure is 45 mbar, and the carrier gas is switched from N2 (25 L / min) to H2 (25 L / min) within 7.5~10 min, while the temperature is raised from room temperature (25℃) to 300℃; from 10 to 12.5 min, PH3 is introduced at 300℃ to 1000 sccm, and from 12.5 to 15 min, the temperature is raised to 550℃; from 15 to 17.5 min, TMIn is introduced at 550℃, PH3 at 900 sccm, and H2 at 25 L / min for 40 sccm to obtain an n-InP layer with a thickness of 0.1 μm; TMIn is turned off at 17.5 min, the temperature is lowered to 300℃ from 17.5 to 20 min, the temperature is lowered to room temperature and PH3 is turned off from 20 to 23 min, and N2 purging is resumed and the pressure is depressurized to 0 mbar from 23 to 30 min to obtain the second n-InP layer 5; (5) Reference Figure 4 The second n-InP layer 5, formed by protecting the photosensitive surface and its sidewalls with thick photoresist (5 μm thick) using a photolithography process, retains a width of 10 μm. The photoresist to be etched is removed by exposure and development, exposing the remaining area (including the secondary epitaxial layer and the underlying intrinsic layer). ICP etching is performed using a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively, with a power of 75 W, a chamber temperature of 100 °C, and a pressure of 5 mTorr, etching down to the semi-insulating InP substrate 1 at a rate of 400 nm / min. This step forms deep trench isolation between devices. (6) Reference Figure 5Silicon nitride (SiN2) was deposited using PECVD as the insulating dielectric layer. The deposition conditions were: temperature 350℃, RF power 50W, reaction chamber pressure 200Pa, and SiH4 / NH3 flow ratio 1100:3300 sccm. The deposited silicon nitride layer was 180nm thick and had a refractive index of 1.8. This insulating layer covered the entire surface, including the photosensitive surface, trench sidewalls, and bottom. (7) Reference Figure 6 The photolithography process was employed, with photoresist (1 μm thick) used for protection. The photoresist was removed from the areas to be etched by exposure and development. Silicon nitride was etched using ICP, with 80 sccm of CF4 and 10 sccm of O2 as the etching gases. The etching rate was 100 nm / min, the power was 50 W, the chamber temperature was 60 °C, and the pressure was 25 mTorr. After etching, the surface of the p+InP layer 4 was exposed. (8) Using photolithography, photoresist is used for protection (thickness 5μm). The area to be plated with metal is developed by exposure and development. The p electrode is drawn from the p+InP layer 4 using an electron gun evaporation machine. The metal is Ti / Pt / Au, and the total thickness is 1μm. The back side of the substrate is thinned to a thickness of 120μm. On the back side of the thinned substrate, the n electrode is fabricated using photolithography and evaporation processes. The metal is AuGeNi / Au, and the total thickness is 0.8μm.

[0030] Example 3 This embodiment provides a matrix-integrable structure for a high-speed InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 1 The first n-InP layer 2 (thickness 0.6 μm, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate 1 (thickness 350 μm, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer 3 (thickness 3.0 μm, carrier concentration 1 × 10⁻⁶). 15 cm -3 ), p+InP layer 4 (thickness 1.0 μm, carrier concentration 1×10⁻⁶) 19 cm -3 ); (2) A photosensitive area (square, 40 μm in diameter) is formed on the p+InP layer 4 by photolithography. The photosensitive area is covered and protected by thick photoresist (5 μm thick). The photoresist in the remaining areas is removed by development. (3) Reference Figure 2The etching was performed using an ICP device with a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively. The ICP power was 75W, the chamber temperature was 100℃, the pressure was 5 mTorr, and the etching depth was 1000 nm. The p+InP layer 4 outside the photosensitive surface was completely removed, exposing the underlying intrinsic InGaAs layer 3. After etching, the p+InP layer 4 in the photosensitive area was preserved by photoresist. (4) Reference Figure 3 After removing the remaining photoresist, the wafer is placed in the MOCVD reaction chamber for secondary epitaxy. The specific process is as follows: The reaction chamber pressure is 55 mbar. The carrier gas is switched from N2 (25 L / min) to H2 (25 L / min) within 7.5~10 min, while the temperature is raised from room temperature (25℃) to 300℃. From 10 to 12.5 min, PH3 is introduced at 300℃ to 1000 sccm, and from 12.5 to 15 min, the temperature is raised to 650℃. From 15 to 30 min, TMIn is introduced at 650℃, PH3 at 1100 sccm, and H2 at 25 L / min to 60 sccm, obtaining an n-InP layer with a thickness of 1.0 μm. TMIn is turned off after 30 min, the temperature is lowered to 300℃ from 30 to 32.5 min, the temperature is lowered to room temperature and PH3 is turned off from 32.5 to 35 min, and N2 purging is resumed from 35 to 42 min, and the pressure is depressurized to 0 mbar; the second n-InP layer 5 is obtained. (5) Reference Figure 4 The second n-InP layer 5, formed by protecting the photosensitive surface and its sidewalls with thick photoresist (5 μm thick) using a photolithography process, retains a width of 20 μm. The photoresist to be etched is removed by exposure and development, exposing the remaining area (including the secondary epitaxial layer and the underlying intrinsic layer). ICP etching is performed using a mixed gas of Cl2, CH4, and H2 at flow rates of 10 sccm, 8 sccm, and 4 sccm, respectively, with a power of 75 W, a chamber temperature of 100 °C, and a pressure of 5 mTorr, etching down to the semi-insulating InP substrate 1 at a rate of 400 nm / min. This step forms deep trench isolation between devices. (6) Reference Figure 5 Silicon nitride (SiN2) was deposited using PECVD as the insulating dielectric layer. The deposition conditions were: temperature 350℃, RF power 50W, reaction chamber pressure 200Pa, and SiH4 / NH3 flow ratio 1100:3300 sccm. The deposited silicon nitride layer was 220nm thick and had a refractive index of 2.0. This insulating layer covered the entire surface, including the photosensitive surface, trench sidewalls, and bottom. (7) Reference Figure 6The photolithography process was employed, with photoresist (1 μm thick) used for protection. The photoresist was removed from the areas to be etched by exposure and development. Silicon nitride was etched using ICP, with 80 sccm of CF4 and 10 sccm of O2 as the etching gases. The etching rate was 100 nm / min, the power was 50 W, the chamber temperature was 60 °C, and the pressure was 25 mTorr. After etching, the surface of the p+InP layer 4 was exposed. (8) Using photolithography, photoresist is used for protection (thickness 5μm). The area to be plated with metal is developed by exposure and development. The p electrode is drawn from the p+InP layer 4 using an electron gun evaporation machine. The metal is Ti / Pt / Au, and the total thickness is 1μm. The back side of the substrate is thinned to a thickness of 120μm. On the back side of the thinned substrate, the n electrode is fabricated using photolithography and evaporation processes. The metal is AuGeNi / Au, and the total thickness is 0.8μm.

[0031] Comparative Example 1 This comparative example provides a matrix-integrable structure of a conventional InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 7 The first n-InP layer (0.5 μm thick, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate (350 μm thick, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer (thickness 2.5 μm, carrier concentration 1 × 10⁻⁶). 15 cm -3 ), n-InP layer (thickness 0.5 μm, carrier concentration 1 × 10⁻⁶) 15 cm -3 ); (2) See Figure 8 Silicon nitride with a thickness of 200 nm was deposited by PECVD, and the photosensitive surface opening (diameter 10 μm) was etched by ICP. The deposition and etching processes were the same as steps (6) and (7) in Example 1. Then, Zn3P2 was vacuum doped in a furnace tube at a high temperature of 600℃ for 20 min to form a p+InP layer with a carrier concentration of 4×10⁻⁶. 18 cm -3 ; (3) See Figure 9 Photoresist protects the photosensitive surface, and ICP is etched onto the semi-insulating substrate; the process parameters are the same as step (5) in Example 1. (4) See Figure 10 Silicon nitride was deposited by PECVD, with process parameters the same as step (6) in Example 1. (5) Etch the opening and thin the back side to 120μm; and form the p electrode (Ti / Pt / Au 1μm) and n electrode (AuGeNi / Au 0.8μm).

[0032] Comparative Example 2 This comparative example provides a matrix-integrable structure of a conventional InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 7 The first n-InP layer (0.5 μm thick, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate (350 μm thick, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer (thickness 2.5 μm, carrier concentration 1 × 10⁻⁶). 15 cm -3 ), n-InP layer (thickness 0.5 μm, carrier concentration 1 × 10⁻⁶) 15 cm -3 ); (2) See Figure 8 Silicon nitride with a thickness of 200 nm was deposited by PECVD, and the photosensitive surface opening (diameter 10 μm) was etched by ICP. The deposition and etching processes were the same as steps (6) and (7) in Example 1. Then, Zn was doped in the MOCVD high-temperature 550℃ chamber for 60 min to form a p+InP layer with a carrier concentration of 7×10⁻⁶. 18 cm -3 ; (3) See Figure 9 Photoresist protects the photosensitive surface, and ICP is etched onto the semi-insulating substrate; the process parameters are the same as step (5) in Example 1. (4) See Figure 10 Silicon nitride was deposited by PECVD, with process parameters the same as step (6) in Example 1. (5) Etch the opening and thin the back side to 120μm; and form the p electrode (Ti / Pt / Au 1μm) and n electrode (AuGeNi / Au 0.8μm).

[0033] Comparative Example 3 This comparative example provides a matrix-integrable structure of a conventional InGaAs PD detector chip and its fabrication method, including the following steps: (1) Reference Figure 7 The first n-InP layer (0.5 μm thick, carrier concentration 1 × 10⁻⁶) was epitaxially grown sequentially on a semi-insulating InP substrate (350 μm thick, 2 inches) using MOCVD. 16 cm -3 ), intrinsic InGaAs layer (thickness 2.5 μm, carrier concentration 1 × 10⁻⁶). 15 cm -3 ), n-InP layer (thickness 0.5 μm, carrier concentration 1 × 10⁻⁶)15 cm -3 ); (2) See Figure 8 Silicon nitride with a thickness of 200 nm was deposited by PECVD, and the photosensitive surface opening (diameter 10 μm) was etched by ICP. The deposition and etching processes were the same as steps (6) and (7) in Example 1. Then, Zn was doped in the MOCVD high-temperature 520℃ cavity for 70 min to form a p+InP layer with a carrier concentration of 8×10⁻⁶. 18 cm -3 ; (3) See Figure 9 Photoresist protects the photosensitive surface, and ICP is etched onto the semi-insulating substrate; the process parameters are the same as step (5) in Example 1. (4) See Figure 10 Silicon nitride was deposited by PECVD, with process parameters the same as step (6) in Example 1. (5) Etch the opening and thin the back side to 120μm; and form the p electrode (Ti / Pt / Au 1μm) and n electrode (AuGeNi / Au 0.8μm).

[0034] The InGaAs PD detector chip prepared in Example 1 of this invention was tested for electrical performance at room temperature using a semiconductor parameter analyzer. The test results showed that, under a reverse bias of 5V, the device capacitance was 0.05pF and the dark current was less than 50pA; under a reverse current of 10μA, the breakdown voltage was 30~45V; and under zero bias, the responsivity was greater than 0.95A / W.

[0035] The InGaAs PD detector chip prepared in Example 2 has a capacitance of 0.03pF and a dark current of <50pA under a 5V reverse bias; a breakdown voltage of 30~45V under a 10μA reverse current; and a responsivity of >0.95A / W under zero bias.

[0036] The InGaAs PD detector chip prepared in Example 3 has a capacitance of 0.1pF and a dark current of <50pA under a 5V reverse bias; a breakdown voltage of 30~45V under a 10μA reverse current; and a responsivity of >0.95A / W under zero bias.

[0037] As a comparative example 1, the InGaAs PD chip prepared using the traditional Zn3P2 diffusion process showed the following results under the same test conditions: capacitance 0.12~0.20pF, dark current less than 500pA, breakdown voltage 20V~60V, and responsivity greater than 0.95A / W.

[0038] As a comparative example 2, the InGaAs PD chip prepared using the traditional Zn diffusion process showed the following results under the same test conditions: capacitance 0.1~0.18pF, dark current less than 300pA, breakdown voltage 30V~50V, and responsivity greater than 0.95A / W.

[0039] As a comparative example 3, the InGaAs PD chip prepared using the traditional Zn diffusion process showed the following results under the same test conditions: capacitance 0.1~0.15pF, dark current less than 300pA, breakdown voltage 30V~50V, and responsivity greater than 0.95A / W.

[0040] As can be seen from the comparison, the diffusion depth cannot be effectively controlled when using furnace tube or MOCVD diffusion methods, directly affecting the junction capacitance and dark current. This invention, through a surrounding n-InP sidewall structure formed by secondary epitaxy, strictly confines the PN junction to the photosensitive surface region. While maintaining essentially the same dark current, breakdown voltage, and responsivity, it significantly reduces the device junction capacitance to 0.05 pF. The lower capacitance makes the device of this invention more suitable for high-speed optical communication systems above 50G, and the secondary epitaxy process has good uniformity and controllability, which is beneficial for achieving high-density matrix integration.

[0041] The embodiments described above are some, but not all, of the embodiments of the present invention; the detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention; all other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A matrix-integrable structure for a high-speed InGaAs PD detector chip, characterized in that, Including a semi-insulating InP substrate (1); The first n-InP layer (2), the intrinsic InGaAs layer (3) and the p+InP layer (4) are sequentially formed on the substrate. The p+InP layer (4) has a photosensitive surface region. The p+InP layer (4) outside the photosensitive surface region is removed to expose the intrinsic InGaAs layer (3). A second n-InP layer (5) is formed on the exposed intrinsic InGaAs layer (3) by secondary epitaxy. The second n-InP layer (5) is electrically connected to the first n-InP layer (2). An insulating dielectric layer covers the p+InP layer (4) and the second n-InP layer (5), and has a first electrode window exposing the p+InP layer (4) and a second electrode window exposing the back side of the substrate; The p electrode is disposed within the first electrode window and electrically connected to the p+InP layer (4); The n-electrode is disposed on the back side of the substrate.

2. The matrix-integrable structure according to claim 1, characterized in that, The photosensitive surface is circular or rectangular, with a diameter or side length of 5μm to 40μm.

3. The matrix-integrable structure according to claim 1, characterized in that, The insulating dielectric layer includes a silicon nitride layer with a refractive index of 1.8 to 2.0 and a thickness of 180 nm to 220 nm.

4. The matrix-integrable structure according to claim 1, characterized in that, The materials of the p electrode and n electrode include one or more of Ti, Pt, Au, Ni, and Al.

5. The matrix-integrable structure according to claim 1, characterized in that, The thickness of the p+InP layer (4) is 100nm~1000nm; the thickness of the intrinsic InGaAs layer (3) is 2.0μm~3.0μm; the thickness of the first n-InP layer (2) is 0.4μm~0.6μm; the thickness of the second n-InP layer (5) and the p+InP layer (4) are equal.

6. The matrix-integrable structure according to claim 1, characterized in that, Multiple of the matrix-integrable structures are arranged in an array on the same substrate.

7. A method for fabricating a matrix-integrable structure as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. A first n-InP layer (2), an intrinsic InGaAs layer (3) and a p+InP layer (4) are epitaxially grown sequentially on a semi-insulating InP substrate (1). S2. Remove the p+InP layer (4) outside the photosensitive surface area to expose the intrinsic InGaAs layer (3). S3. A second n-InP layer (5) is grown on the exposed intrinsic InGaAs layer (3) by secondary epitaxy. Phosphorus-containing precursor and indium-containing precursor are introduced during the secondary epitaxy process. S4. Protect the photosensitive surface and its sidewalls to form a portion of the second n-InP layer (5), and etch the remaining portion to the semi-insulating substrate; S5. Deposit an insulating dielectric layer and open holes to expose the p+InP layer (4) and the back side of the substrate; S6, forming p and n electrodes.

8. The preparation method according to claim 7, characterized in that, The secondary epitaxial process parameters in step S3 include: a temperature of 550℃~650℃, a reaction chamber pressure of 45mbar~55mbar, a carrier gas of H2, a phosphorus-containing precursor including PH3 with a flow rate of 900sccm~1100sccm, and an indium-containing precursor including TMIn with a flow rate of 40sccm~60sccm.

9. The preparation method according to claim 7, characterized in that, In step S2, the p+InP layer is removed by dry etching (4). The etching gas includes a mixture of Cl2, CH4 and H2, and the etching depth is 100nm~1000nm.

10. An optoelectronic device comprising a matrix-integrable structure as described in any one of claims 1 to 6 and a laser, wherein the matrix-integrable structure is integrated with the laser.

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