A multi-channel test apparatus and test method for semiconductor chips

Abstract

The application aims to provide a kind of multi-channel test equipment and test method for semiconductor chip.The application includes test substrate and carrier, host computer is connected with the test substrate and the carrier, the test substrate includes MCU hardware resource configuration module, the MCU hardware resource configuration module is connected with DMM power supply filtering and communication interface, product power supply circuit, product I2C communication isolation circuit, the DMM power supply filtering and communication interface are connected with multiple product voltage measurement module, multiple product current test module, the product power supply circuit, the product I2C communication isolation circuit are all connected with product power supply control circuit, the product power supply control circuit is connected with first product test signal needle point interface, the multiple product voltage measurement module, the product power supply control circuit, the first product test signal needle point interface are all connected with open short circuit measurement circuit.The application is applied to the technical field of electronic testing.

Description

Technical Field

[0001] This invention relates to the technical field of electronic testing, and in particular to a multi-channel testing device and testing method for semiconductor chips. Background Technology

[0002] Currently, most electronic semiconductor components, electronic products, smartwatches, mobile phones, new energy power supplies, tablets, computers, mobile phones, digital cameras, and other products require circuit, electrical parameter, and defect testing. Existing technologies lack specific testing capabilities for electronic semiconductor products, such as MLB electrical parameter testing, temperature testing, I2C communication testing, liquid detection and alarm circuit board testing, open / short circuit testing, constant temperature environment testing and calibration, current and voltage accuracy testing, and NTC testing for DUT circuit boards (B2B interface DUT, test point interface DUT). Current technologies offer limited testing options for electronic semiconductor products, requiring multiple testing machines to meet product testing needs, resulting in high testing costs and low efficiency. For example, Chinese patent CN216649227U discloses a high-precision self-recovering over-temperature protection circuit, placing a high-precision NTC next to the current-limiting power resistor RS1 of the component requiring temperature testing, and using a traditional temperature switch to sense the RS1 temperature in real time. However, its testing capabilities are limited and difficult to integrate with testing multiple products. Therefore, it is necessary to provide a multi-channel testing device and testing method for semiconductor chips, which adopts a modular design, has strong compatibility, and can be compatible with testing multiple products. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a multi-channel test device and test method for semiconductor chips. It adopts a modular design, has strong compatibility, and can be compatible with the testing of multiple products.

[0004] The technical solution adopted in this invention is as follows: This invention includes a test substrate and a carrier. A host computer is communicatively connected to the carrier via the test substrate. The test substrate includes an MCU hardware resource configuration module. The MCU hardware resource configuration module is connected to a DMM power filter and communication interface, a product power supply circuit, and a product I2C communication isolation circuit. The DMM power filter and communication interface is connected to a multi-channel product voltage measurement module and a multi-channel product current test module. The product power supply circuit and the product I2C communication isolation circuit are both connected to a product power supply control circuit. The product power supply control circuit is connected to a first product test signal pin interface. The multi-channel product voltage measurement module, the product power supply control circuit, and the first product test signal pin interface are all connected to an open / short circuit measurement circuit. The open / short circuit measurement circuit is connected to the carrier via a second product test signal pin interface. As can be seen from the above solution, this application can be widely used for defect testing of circuits and semiconductor chips in all electronic semiconductor components, electronic products, smartwatches, mobile phones, new energy power supplies, tablets, computers, mobile phones, digital cameras, and other products. It adopts a modular design, has strong compatibility, and can be used for testing multiple products. It can perform MLB electrical parameter testing, temperature testing, DUT T12C communication testing, circuit board open / short circuit testing, DUT constant temperature environment testing and calibration, DUT current and voltage testing, and NTC testing.

[0005] In a preferred embodiment, the test substrate further includes a first IO drive circuit, the MCU hardware resource configuration module is connected to the first IO drive circuit, the first IO drive circuit is connected to a second IO drive circuit and a vacuum valve control and detection module for the product placement position, the vacuum valve control and detection module for the product placement position is connected to the carrier, and the second IO drive circuit is connected to the product power supply control circuit and the multi-channel product current test module.

[0006] In a preferred embodiment, the test substrate further includes a power module, which is connected to the DMM power filtering and communication interface and the product power supply circuit.

[0007] A preferred embodiment is that the multi-channel product voltage measurement module includes a multiplexer.

[0008] A preferred embodiment is that the multi-channel product current test module includes a signal relay.

[0009] In a preferred embodiment, the power supply circuit of the product includes a linear regulator.

[0010] In a preferred embodiment, the product's I2C communication isolation circuit includes a level shifter.

[0011] A preferred embodiment is that the testing method includes the following steps: Step A: Open the host computer, place the product on the test fixture of the carrier, read the QR code information of the product, and insert the 16up test fixture into the device; Step B: The test equipment is reset, the equipment performs liquid leakage detection, and the test substrate process is reset; Step C: Perform product arrival detection through test circuit, perform open and short circuit tests on product chip pins, perform product PP1V85 Volt / Curr test, and vacuum the product's waterproof bag; Step D: Product initialization, read the test channel Carrier EEPROM slot, query the type of product to be read, configure the product rate 1 / S, and configure the product sampling mode CS; Step E: Start the test substrate process, read the DUT Temp Data through IIC, stop the test motherboard process, detect the DUT NTC Temp, determine whether the product is normal, and release the vacuum from the product's waterproof bag; Step F: Reset the test equipment, remove the 16up test fixture, and return the test results. Attached Figure Description

[0012] Figure 1 This is a structural block diagram of the present invention; Figure 2 This is a circuit schematic diagram of the test signal pin interface of the first product and the test signal pin interface of the second product; Figure 3 This is the circuit schematic diagram of the power supply module; Figure 4 This is the circuit schematic diagram of the MCU hardware resource configuration module; Figure 5 This is a circuit schematic diagram of the first IO drive circuit and the second IO drive circuit; Figure 6 This is the circuit diagram of the open / short circuit measurement circuit. Figure 7 This is the circuit schematic diagram of the multi-channel product voltage measurement module; Figure 8 This is the circuit schematic diagram of the multi-channel product current test module; Figure 9 This is the circuit diagram of the power supply circuit for the product. Figure 10 This is the circuit diagram of the power supply control circuit for the product. Figure 11 This is the circuit schematic of the I2C communication isolation circuit of the product. Figure 12 This is a circuit schematic diagram of the test signal pin interface of the first product and the test signal pin interface of the second product; Figure 13 This is a circuit diagram of the vacuum valve control and detection module for the product placement position; Figure 14 This is a diagram showing the first test results of the present invention; Figure 15 This is the second test result diagram of the present invention; Figure 16 This is the third test result diagram of the present invention; Figure 17 This is a test flowchart of the present invention. Detailed Implementation

[0013] like Figures 1 to 13As shown, in this embodiment, the present invention includes a test substrate 1 and a carrier 2. A host computer is communicatively connected to the carrier 2 via the test substrate 1. The test substrate 1 includes an MCU hardware resource configuration module 3. The MCU hardware resource configuration module 3 is connected to a DMM power filtering and communication interface 4, a product power supply circuit 5, and a product I2C communication isolation circuit 6. The DMM power filtering and communication interface 4 is connected to a multi-channel product voltage measurement module 7 and a multi-channel product current test module 8. The product power supply circuit 5 and the product I2C communication isolation circuit 6 are both connected to a product power supply control circuit 9. The product power supply control circuit 9 is connected to a first product test signal pin interface 10. The multi-channel product voltage measurement module 7, the product power supply control circuit 9, and the first product test signal pin interface 10 are all connected to an open / short circuit measurement circuit 11. The open / short circuit measurement circuit 11 is connected to the carrier 2 via a second product test signal pin interface 12. This application utilizes the MCU hardware resource configuration module 3, the test substrate 1, the DMM test module, the test electrical control box, and the constant temperature water bath module to perform electrical parameter testing of the DUT semiconductor, DUT liquid detection and alarm circuit. The test substrate 1 collects analog signals, the DMM performs signal processing, and the MCU hardware resource configuration module 3 outputs the test results to the host computer.

[0014] like Figure 5 As shown, in this embodiment, the test substrate 1 further includes a first IO drive circuit 13, the MCU hardware resource configuration module 3 is connected to the first IO drive circuit 13, the first IO drive circuit 13 is connected to a second IO drive circuit 14 and a vacuum valve control and detection module 15 for product placement position, the vacuum valve control and detection module 15 for product placement position is connected to the carrier 2, and the second IO drive circuit 14 is connected to the product power supply control circuit 9 and the multi-channel product current test module 8.

[0015] like Figure 3 As shown, in this embodiment, the test substrate 1 further includes a power module 16, which is connected to the DMM power filtering and communication interface 4 and the product power supply circuit 5.

[0016] like Figure 7 As shown, in this embodiment, the multi-channel product voltage measurement module 7 includes a multiplexer U1801. The multiplexer U1801 is model ADG5409BRUZ.

[0017] like Figure 8 As shown, in this embodiment, the multi-channel product current test module 8 includes a signal relay K2001. The signal relay K2001 is model AGQ200A4H.

[0018] like Figures 1 to 3 As shown, in this embodiment, the product power supply circuit 5 includes a linear regulator U2201. The linear regulator U2201 is model LT3045EMSE#PBF.

[0019] like Figures 1 to 3 As shown, in this embodiment, the product I2C communication isolation circuit 6 includes a level shifter U2701. The level shifter U2701 is model TCA9416DDFR.

[0020] In this embodiment, the product power supply voltage is calculated using the formula: Vout = 100uA * Rset = 1.85V; Product power supply voltage calculation formula: Iout=(150mA*KΩ) / RIout=100mA.

[0021] like Figure 14 As shown, the test substrate 1 sends Add 0x58 to the DUT, but the DUT returns an abnormal value. The test substrate 1 exhibits an abnormal communication waveform with the DUT IIC, making it impossible to retrieve DUT data. For example... Figure 15 As shown, the test substrate 1 sends Add 0x58 to the DUT, and the DUT can return data normally, as shown. Figure 16 As shown, the test substrate 1 successfully communicated with the DUT IIC and obtained DUT data normally.

[0022] like Figure 17 As shown, in this embodiment, the testing method includes the following steps: Step A: Open the host computer, place the product on the test fixture of the carrier 2, read the QR code information of the product, and insert the 16up test fixture into the device; Step B: The test equipment is reset, and the equipment performs liquid leakage detection. The test substrate 1 is reset in process. Step C: Perform product arrival detection through test circuit, perform open and short circuit tests on product chip pins, perform product PP1V85 Volt / Curr test, and vacuum the product's waterproof bag; Step D: Product initialization, read the test channel Carrier EEPROM slot, query the type of product to be read, configure the product rate 1 / S, and configure the product sampling mode CS; Step E: Start the process of the test substrate 1, read the DUT Temp Data through IIC, stop the test motherboard process, detect the DUT NTC Temp, determine whether the product is normal, and release the vacuum from the waterproof bag of the product; Step F: Reset the test equipment, remove the 16up test fixture, and return the test results.

[0023] like Figure 14 As shown in the figure, the DUT test data stabilized at around ±0.02℃ after ten minutes.

[0024] Although the embodiments of the present invention are described with reference to actual solutions, they do not constitute a limitation on the meaning of the present invention. Modifications to the embodiments and combinations with other solutions based on this specification will be obvious to those skilled in the art.

Claims

1. A multi-channel testing device for semiconductor chips, comprising a test substrate (1) and a carrier (2), wherein a host computer is communicatively connected to the carrier (2) via the test substrate (1), characterized in that: The test substrate (1) includes an MCU hardware resource configuration module (3), which is connected to a DMM power filter and communication interface (4), a product power supply circuit (5), and a product I2C communication isolation circuit (6). The DMM power filter and communication interface (4) is connected to a multi-channel product voltage measurement module (7) and a multi-channel product current test module (8). The product power supply circuit (5) and the product I2C communication isolation circuit (6) are both connected to a product power supply control circuit (9). The product power supply control circuit (9) is connected to a first product test signal pin interface (10). The multi-channel product voltage measurement module (7), the product power supply control circuit (9), and the first product test signal pin interface (10) are all connected to an open / short circuit measurement circuit (11). The open / short circuit measurement circuit (11) is connected to the carrier (2) via a second product test signal pin interface (12).

2. The multi-lane test apparatus for semiconductor chips according to claim 1, wherein, The test substrate (1) further includes a first IO drive circuit (13), the MCU hardware resource configuration module (3) is connected to the first IO drive circuit (13), the first IO drive circuit (13) is connected to a second IO drive circuit (14) and a vacuum valve control and detection module (15) for product placement position, the vacuum valve control and detection module (15) for product placement position is connected to the carrier (2), and the second IO drive circuit (14) is connected to the product power supply control circuit (9) and the multi-channel product current test module (8).

3. The multi-lane test apparatus for semiconductor chips according to claim 1, wherein, The test substrate (1) also includes a power module (16), which is connected to the DMM power filtering and communication interface (4) and the product power supply circuit (5).

4. The multi-lane test apparatus for semiconductor chips according to claim 1, wherein, The multi-channel product voltage measurement module (7) includes a multiplexer (U1801).

5. The multi-lane test apparatus for semiconductor chips according to claim 1, wherein, The multi-channel product current test module (8) includes a signal relay (K2001).

6. The multi-lane test apparatus for semiconductor chips according to claim 1, wherein, The product power supply circuit (5) includes a linear regulator (U2201).

7. The multi-channel testing equipment for semiconductor chips according to claim 1, characterized in that, The product's I2C communication isolation circuit (6) includes a level shifter (U2701).

8. A test method including the multi-channel test apparatus for a semiconductor chip according to claim 1, characterized by, The testing method includes the following steps: Step A: Open the host computer, place the product on the test fixture of the carrier (2), read the QR code information of the product, and insert the 16up test fixture into the device; Step B: The test equipment is reset, and the equipment performs liquid leakage detection. The test substrate (1) is reset in process. Step C: Perform product arrival detection through test circuit, perform open and short circuit tests on product chip pins, perform product PP1V85 Volt / Curr test, and vacuum the product's waterproof bag; Step D: Product initialization, read the test channel Carrier EEPROM slot, query the type of product to be read, configure the product rate 1 / S, and configure the product sampling mode CS; Step E: Start the test substrate (1) process, read the DUT Temp Data through IIC, stop the test motherboard process, detect the DUT NTC Temp, determine whether the product is normal, and release the vacuum from the waterproof bag of the product; Step F: Reset the test equipment, remove the 16up test fixture, and return the test results.

Images