Clock generating circuit, half-rate sampling circuit and signal transceiver chip

Abstract

The application relates to a clock generating circuit, a half-rate sampling circuit and a signal transceiver chip, comprising a clock generating module, a signal adjusting module and a phase difference feedback module. The clock generating module generates a first clock signal and a second clock signal, the signal adjusting module adjusts the phase of the first clock signal or the second clock signal according to a delay control voltage, and outputs a first adjusted clock signal and a second adjusted clock signal. The phase difference feedback module adjusts the delay control voltage in real time according to the actual phase difference between the first adjusted clock signal and the second adjusted clock signal and outputs the delay control voltage to the signal adjusting module until the real-time phase difference reaches a target phase difference. By automatically detecting and compensating for the relative phase shift caused by the different capacitive load differences existing between edge sampling and data sampling, a precise and adaptive clock signal pair is provided for the subsequent circuit, so that the data sampling point is aligned with the center of the data eye diagram, and the maximum signal-to-noise ratio is achieved during sampling.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a clock generating circuit, a half-rate sampling circuit, and a signal transceiver chip. Background Technology

[0002] In half-rate clock and data recovery (CDR) circuits, sampling is typically performed using four quadrature clocks. The I-phase clocks (CKIP, CKIM) drive the data decision unit, sampling the valid data values ​​to recover the data. The Q-phase clocks (CKQP, CKQM) drive the edge decision unit, sampling the data transition edges to provide the phase error information needed for clock recovery.

[0003] The quadrature clock pairs required by traditional half-rate sampling circuits are typically generated by circuits such as polyphase filters (PPFs) or quadrature voltage-controlled oscillators (QVCOs). However, in practical circuits, the capacitive loads presented by the clock paths of the data decision unit and the edge decision unit often differ. This load mismatch causes an unexpected relative phase shift between the I-phase clock and the Q-phase clock after transmission, disrupting their ideal quadrature relationship and severely affecting the correct sampling and recovery of data. Summary of the Invention

[0004] Therefore, it is necessary to provide a clock generation circuit, a half-rate sampling circuit, and a signal transceiver chip to address the technical problem of relative phase shift in four-phase quadrature clocks caused by the different capacitive load differences between edge sampling and data sampling.

[0005] A clock generating circuit, comprising:

[0006] A clock generation module is used to generate a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency;

[0007] The signal adjustment module is electrically connected to the clock generation module and is used to adjust the phase of the first clock signal or the second clock signal according to the input delay control voltage, and output the first adjusted clock signal and the second adjusted clock signal.

[0008] The phase difference feedback module is electrically connected to the signal adjustment module and is used to adjust the delay control voltage in real time according to the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and output the adjusted delay control voltage to the signal adjustment module until the real-time phase difference reaches the target phase difference.

[0009] In one embodiment, the phase difference feedback module includes:

[0010] A phase difference detection unit, electrically connected to the signal adjustment module, is used to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and output an error differential voltage in real time based on the actual phase difference.

[0011] An error integration unit, electrically connected to the phase difference detection unit, is used to integrate the error differential voltage and provide the integrated output voltage as the adjusted delay control voltage to the signal adjustment module.

[0012] In one embodiment, the phase difference detection unit includes a multiplier, and the error integration unit includes an integrator;

[0013] The multiplier is used to multiply the input first adjustment clock signal and the second adjustment clock signal to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and output the error differential voltage in real time according to the actual phase difference.

[0014] The integrator is used to integrate the error differential voltage, and the output voltage after integration is proportional to the cosine of the actual phase difference.

[0015] In one embodiment, the first adjustment clock signal is further used to output to the first decision unit of the half-rate sampling circuit to assist the first decision unit in outputting a regenerated data signal based on the input data signal;

[0016] The half-rate sampling circuit further includes a verification unit connected to the first decision unit, the verification unit being used to output the bit error rate of the regenerated data signal relative to the input data signal;

[0017] The phase difference feedback module also includes:

[0018] An error control unit, electrically connected to the error integration unit and the verification unit, is used to provide an input offset voltage to the error integration unit according to the bit error rate;

[0019] The error integration unit is used to integrate the error differential voltage and the input offset voltage, and the integrated output voltage is provided to the signal adjustment module as the adjusted delay control voltage.

[0020] In one embodiment, the error integration unit includes an integrator, which includes at least an operational amplifier;

[0021] The error control unit includes an adjustable current source, which is connected in series between the inverting input terminal and the ground terminal of the operational amplifier, and the adjustment terminal of the adjustable current source is connected to the verification unit.

[0022] In one embodiment, the signal adjustment module includes a first clock driver and a second clock driver;

[0023] The first clock driver is used to receive the first clock signal and adjust the output of the first adjusted clock signal; the second clock driver is used to receive the second clock signal and adjust the output of the second adjusted clock signal.

[0024] The delay control voltage is provided to the delay control terminal of the first clock driver or the second clock driver.

[0025] In one embodiment, the target phase difference is 90°.

[0026] In one embodiment, a half-rate sampling circuit is also provided, including a clock generation circuit, a first decision unit, a second decision unit, and a clock data recovery unit as described in any of the above embodiments;

[0027] The clock generating circuit connects the first decision unit and the second decision unit, and is used to provide a first adjustment clock signal to the first decision unit and a second adjustment clock signal to the second decision unit. Both the first decision unit and the second decision unit are connected to the clock data recovery unit, and the clock data recovery unit is connected to the clock generating circuit.

[0028] The first decision unit is used to output the received input data signal as a regenerated data signal based on the first adjustment clock signal, and to provide the regenerated data signal to the clock data recovery unit;

[0029] The second decision unit is used to output the input data signal as a data edge signal based on the second adjustment clock signal, and to provide the data edge signal to the clock data recovery unit;

[0030] The clock data recovery unit is used to output a phase control voltage to the clock generation circuit based on the edge phase difference between the regenerated data signal and the data edge signal.

[0031] In one embodiment, a verification unit is further included, which is connected to the first decision unit and the clock generation circuit, for outputting the bit error rate of the regenerated data signal relative to the input data signal and providing the bit error rate to the clock generation circuit.

[0032] In one embodiment, a signal transceiver chip is also provided, including a half-rate sampling circuit as described in any of the above embodiments.

[0033] The aforementioned clock generation circuit, half-rate sampling circuit, and signal transceiver chip include a clock generation module, a signal adjustment module, and a phase difference feedback module. The clock generation module generates a first clock signal and a second clock signal, both with the same frequency. The signal adjustment module adjusts the phase of either the first or second clock signal based on the input delay control voltage, outputting a first adjusted clock signal and a second adjusted clock signal. The phase difference feedback module adjusts the delay control voltage in real time based on the actual phase difference between the first and second adjusted clock signals, and outputs the adjusted delay control voltage to the signal adjustment module until the real-time phase difference reaches the target phase difference. By automatically detecting and compensating for the relative phase shift caused by the difference in capacitive load between edge sampling and data sampling, a precisely matched clock signal pair is provided for subsequent circuits, ensuring that the data sampling point is aligned with the center of the data eye diagram, thereby maximizing the signal-to-noise ratio during sampling. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a system block diagram of a half-rate sampling circuit in one embodiment;

[0036] Figure 2 This is a schematic diagram of the sampling timing of a half-rate sampling circuit in one embodiment;

[0037] Figure 3 This is a schematic diagram of a system block diagram of a clock generation circuit in one embodiment;

[0038] Figure 4 This is a schematic diagram of the system block diagram of the clock generation circuit in another embodiment;

[0039] Figure 5 This is a schematic block diagram of the clock generation circuit in one embodiment;

[0040] Figure 6 This is a schematic block diagram of a half-rate sampling circuit in one embodiment;

[0041] Figure 7This is a sampling timing diagram of a half-rate sampling circuit in another embodiment. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. The accompanying drawings illustrate embodiments of this application; however, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0044] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0045] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] As described in the background section, the quadrature clock pairs required by traditional half-rate sampling circuits are generally generated by circuits such as multiphase clock filters (PPFs) or four-phase voltage-controlled oscillators (QVCOs). However, in actual circuits, the capacitive loads presented by the clock paths of the data decision unit and the edge decision unit often differ. This load mismatch causes an unexpected relative phase shift between the I-phase clock and the Q-phase clock after transmission, destroying their ideal quadrature relationship and severely affecting the correct sampling and recovery of data.

[0049] In one exemplary embodiment, refer to Figure 1 A conventional half-rate sampling circuit is provided, including a clock generation circuit 100, a first decision unit 200, a second decision unit 300, and a clock data recovery unit 400.

[0050] Specifically, the clock generation circuit 100 is generally implemented using circuits such as a multiphase clock filter (PPF) or a four-phase voltage-controlled oscillator (QVCO) to generate the quadrature clock pair required by the half-rate sampling circuit, namely, a first clock signal and a second clock signal. The first clock signal can be an I-phase clock (CKI), and the second clock signal can be a Q-phase clock (CKQ). Under ideal conditions, the I-phase clock (CKI) and the Q-phase clock (CKQ) generated by the clock generation circuit 100 have a 90° phase difference. For example, both the I-phase clock (CKI) and the Q-phase clock (CKQ) can be differential clock signals, i.e., the I-phase clock (CKI) includes two phase clocks (CKIP, CKIM), and the Q-phase clock (CKQ) includes two phase clocks (CKQP, CKQM).

[0051] Furthermore, the clock generation circuit 100 is connected to the first decision unit 200 to provide a first clock signal, i.e., an I-phase clock (CKI), to the first decision unit 200. The first decision unit 200 can be a data slicer, used to receive the input data signal data_input, and at the edge of the I-phase clock (CKI), sample and decide on the received input data signal data_input, outputting a first digital bit (0 or 1), which represents the value of the input data signal data_input at that edge. The continuously output bit stream from the data slicer then serves as the recovered original data, i.e., the regenerated data signal data_syn. Exemplarily, the data slicer can sample and decide at the rising edge or the falling edge, depending on the specific design.

[0052] The clock generation circuit 100 is also connected to the second decision unit 300, which provides a second clock signal, namely the Q-phase clock (CKQ), to the second decision unit 300. The second decision unit 300 can be an edge slicer, used to detect the transition edge of the input data signal data_input, so as to provide phase error information to the clock data recovery unit 400. Specifically, the edge slicer receives the input data signal data_input, and samples and decides on the same input data signal data_input at the edge of the Q-phase clock (CKQ), outputting a second digital bit. It can be understood that the second digital bit has a different data meaning from the first digital bit output by the data slicer. It does not directly represent the data signal, but is used to characterize the moment when the data signal may transition. Furthermore, the bit stream continuously output by the edge slicer will serve as a signal related to the transition edge of the input data signal data_input, namely the data edge signal edge_syn.

[0053] Correspondingly, the half-rate sampling circuit also includes a clock data recovery unit 400, whose input side is connected to the first decision unit 200 and the second decision unit 300, and whose output side is connected to the clock generation circuit 100, forming a closed-loop feedback loop. The clock data recovery unit 400 acquires the regenerated data signal data_syn output by the first decision unit 200, and the data edge signal edge_syn output by the second decision unit 300. Using the outputs of these two decision units as raw information, the phase and frequency of the first clock signal and the second clock signal output by the clock generation circuit 100 are dynamically adjusted through its closed-loop feedback loop until they are synchronized with the input data signal data_input.

[0054] The clock data recovery unit 400 may include at least a phase detector and a loop filter.

[0055] The phase detector can acquire the regenerated data signal data_syn and the data edge signal edge_syn, and compare the edge sample value E in the data edge signal edge_syn. n Compared with the data sample value D in the previous regenerated data signal data_syn n-1 The logical relationship. If E n ==D n-1 This indicates that the edge sampling point E n It fell into the previous data sample value D n-1 The flat-top region. This means that the sampling time of the second clock signal (Q-phase clock CKQ) is earlier than the transition edge of the actual input data signal data_input, that is, the phase of the quadrature clock pair is ahead. If E n !=D n-1This indicates that the edge sampling point E n It fell into the next data sample value D n The sampling time is either on the top of the flat region or on the transition edge of the input data signal data_input. This means that the sampling time of the second clock signal (Q-phase clock CKQ) is later than the transition edge of the actual input data signal data_input, i.e., the phase of the quadrature clock pair is lagging. After comparing multiple sampling points in each clock cycle, a sequence of logical values ​​is generated that characterizes whether the phase of the quadrature clock pair leads or lags the phase of the input data signal data_input.

[0056] The loop filter acquires the aforementioned logic value sequence and outputs a control voltage to the clock generation circuit 100 based on this sequence to regulate the quadrature clock pair and achieve phase and frequency alignment with the input data signal data_input. It can be understood that when phase and frequency are aligned, i.e., the clock data recovery unit 400 is in a phase-locked state, the number of values ​​representing phase lead and phase lag in the logic value sequence is statistically roughly equal, and the control voltage output from the loop filter to the clock generation circuit 100 remains stable.

[0057] Correspondingly, refer to Figure 2 Under the ideal state of loop-locked clock data recovery unit 400, after the quadrature clock pair achieves phase and frequency alignment with the input data signal data_input, the sampling point of the first decision unit 200 (determined by the edge timing of CKI) will be aligned with the center of the data eye diagram, i.e., the position where the amplitude of the input data signal data_input is the largest. The sampling point of the second decision unit 300 (determined by the edge timing of CKQ) will be aligned with the intersection of the data eye diagram (i.e., the place where data 0 and 1 are converted). Under this condition, the bit error rate of the regenerated data signal data_syn relative to the input data signal data_input reaches its minimum.

[0058] However, research has revealed that the clock data recovery unit 400 generally assumes that the first clock signal and the second clock signal output by the clock generation circuit 100 are ideally orthogonal. But in actual circuits, the capacitive loads presented by the clock paths of the first decision unit 200 and the second decision unit 300 connected to the clock generation circuit 100 often differ. This load mismatch causes an unexpected relative phase shift between the first and second clock signals after transmission, disrupting their ideal orthogonality. In this case, the data edge signal edge_syn provided by the second decision unit 300 to the clock data recovery unit 400 itself has a phase deviation relative to the regenerated data signal data_syn, and is not ideally orthogonal. This results in the clock data recovery unit 400 reaching phase-locked state, and the regenerated data signal data_syn sampled by the sampling point of the first decision unit 200 is not aligned with the center of the data eye diagram, such as... Figure 2 This may result in a leftward or rightward offset, severely affecting the correct sampling and recovery of data, and causing a significant decrease in the signal-to-noise ratio.

[0059] Based on this, the clock generation circuit 100 is improved in this application embodiment to correct the relative phase shift caused by the difference in capacitive load between edge sampling and data sampling, so as to provide a precisely matched clock signal pair for subsequent circuits, so that the data sampling point is aligned with the center of the data eye diagram, and the maximum signal-to-noise ratio is achieved during sampling.

[0060] In one exemplary embodiment, refer to Figure 3 A clock generation circuit 100 is provided, comprising: a clock generation module 110 for generating a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency; a signal adjustment module 120 electrically connected to the clock generation module 110 for adjusting the phase of the first clock signal or the second clock signal according to an input delay control voltage, and outputting a first adjusted clock signal and a second adjusted clock signal; and a phase difference feedback module 130 electrically connected to the signal adjustment module 120 for adjusting the delay control voltage in real time according to the actual phase difference between the first adjusted clock signal and the second adjusted clock signal, and outputting the adjusted delay control voltage to the signal adjustment module 120 until the real-time phase difference reaches the target phase difference.

[0061] Specifically, the clock generation module 110 is the clock source in the circuit. Its function is to generate a pair of original clock signals with the same frequency but a fixed phase relationship (the initial phase relationship is usually orthogonal), namely, a first clock signal and a second clock signal. Referring to the description above, the first clock signal can be an I-phase clock (CKI), and the second clock signal can be a Q-phase clock (CKQ). Hereinafter, CKI will be used to represent the first clock signal, and CKQ will be used to represent the second clock signal.

[0062] Exemplary examples show that the clock generation module 110 can be implemented using various circuit structures, and this application embodiment is not limited to any particular one. Any circuit known to those skilled in the art capable of generating two clock signals with the same frequency is applicable. In one specific implementation, the clock generation module 110 may include a voltage-controlled oscillator (VCO) and a subsequent multiphase filter (PPF) or frequency divider chain, generating the required two clock signals by performing phase processing on the single output of the VCO. In another implementation, the clock generation module 110 may also be implemented using a quad-phase voltage-controlled oscillator (QVCO), which directly outputs four clock signals with a phase difference of 90°, and selects the two signals with a phase difference of 90° as CKI and CKQ.

[0063] In one example, the first clock signal CKI and the second clock signal CKQ output by the clock generation module 110 have the same frequency, and the frequency is half the frequency of the input data signal data_input.

[0064] Furthermore, the signal adjustment module 120 is a module for performing phase calibration, used to receive a first clock signal CKI and a second clock signal CKQ from the clock generation module 110, and to receive a delay control voltage V from the phase difference feedback module 130. ctrl The signal adjustment module 120 can control the voltage V based on the input delay. ctrl The transmission delay of one of the first clock signal CKI and the second clock signal CKQ is selectively adjusted continuously or in steps, thereby changing the relative phase between the two output clocks. The signals output after adjustment by the signal adjustment module 120 are called the first adjusted clock signal CKI' and the second adjusted clock signal CKQ'.

[0065] For example, the signal conditioning module 120 may include at least a voltage-controlled delay unit. In one specific embodiment, the voltage-controlled delay unit may be a variable delay buffer based on analog voltage control, the delay amount of which varies with the delay control voltage V. ctrl Linear or monotonic variation. For example, an inverter-chained voltage-controlled delay buffer driven by a voltage-controlled current source can be used, with the delay control voltage V... ctrl The charging and discharging current of the inverter is controlled, thereby changing the propagation delay of the signal through the buffer.

[0066] It can be understood that by embedding the voltage-controlled delay unit included in the signal adjustment module 120 into the clock path of the first clock signal or the second clock signal, the back-end sampling and decision circuit can be provided with the first adjusted clock signal CKI' and the second adjusted clock signal CKQ' after correction and adjustment.

[0067] It should be noted that, in this embodiment, the first adjusted clock signal CKI' and the second adjusted clock signal CKQ' are obtained by adjusting the phase of the first clock signal CKI or the second clock signal CKQ. Therefore, only one of the adjusted clock signals is actually a phase-adjusted clock signal; the other adjusted clock signal can be obtained from the original clock signal without phase adjustment. For example, when adjusting the phase of the first clock signal CKI, the first adjusted clock signal CKI' is the phase-adjusted first clock signal CKI, while the second adjusted clock signal CKQ' is output from the second clock signal CKQ without signal adjustment.

[0068] In order to obtain a precise delay control voltage V ctrl The clock generation circuit 100 also includes a phase difference feedback module 130, whose input terminal is electrically connected to the output terminal of the signal adjustment module 120, and whose output terminal is also electrically connected to the control terminal of the signal adjustment module 120, so as to form a phase difference closed-loop feedback circuit.

[0069] Specifically, the input of the phase difference feedback module 130 receives the first adjustment clock signal CKI' and the second adjustment clock signal CKQ' output by the signal adjustment module 120. Then, the phase difference feedback module 130 detects the actual phase difference θ between the first adjustment clock signal CKI' and the second adjustment clock signal CKQ' in real time, and based on the difference between the actual phase difference θ and the target phase difference θ1, generates an error signal related to the target phase difference θ1. Finally, it adjusts the delay control voltage V in real time according to this error signal. ctrl And adjust the delay control voltage V ctrl The feedback is sent to the signal adjustment module 120, forming a negative feedback loop.

[0070] In one specific embodiment, the phase difference feedback module 130 may also include a phase detector and a loop filter. The phase detector may be a trigger-type frequency phase detector or a quadrature phase detection circuit, which detects the position of the edge of the first adjustment clock signal CKI' within the period of the second adjustment clock signal CKQ' to output a pulse signal representing the actual phase difference. The loop filter converts the digital pulse signal output by the phase detector into a smoothed analog delayed control voltage V. ctrl The loop filter can be implemented using a first-order or second-order low-pass filter to filter out high-frequency noise and generate a stable delay control voltage V. ctrl .

[0071] It is understood that the target phase difference θ1 is set by the balance point of the constructed negative feedback loop. In one embodiment, the target phase difference is set to 90°. Correspondingly, when the actual phase difference θ is less than 90°, the delay control voltage V generated by the phase difference feedback module 130...ctrl This allows the signal adjustment module 120 to increase the phase difference between the first clock signal CKI or the second clock signal CKQ. When the actual phase difference θ is greater than 90°, the delay control voltage V generated by the phase difference feedback module 130... ctrl This allows the signal adjustment module 120 to reduce the phase difference between the first clock signal CKI or the second clock signal CKQ.

[0072] The aforementioned clock generation circuit includes a clock generation module, a signal adjustment module, and a phase difference feedback module. The clock generation module generates a first clock signal and a second clock signal, both with the same frequency. The signal adjustment module adjusts the phase of either the first or second clock signal based on the input delay control voltage, outputting a first adjusted clock signal and a second adjusted clock signal. The phase difference feedback module adjusts the delay control voltage in real time based on the actual phase difference between the first and second adjusted clock signals, and outputs the adjusted delay control voltage to the signal adjustment module until the real-time phase difference reaches the target phase difference. By automatically detecting and compensating for the relative phase shift caused by differences in capacitive loads between edge sampling and data sampling, a precisely matched clock signal pair is provided for subsequent circuits, ensuring that the data sampling point is aligned with the center of the data eye diagram, thereby maximizing the signal-to-noise ratio during sampling.

[0073] In one exemplary embodiment, refer to Figure 4 The phase difference feedback module 130 includes: a phase difference detection unit 131, electrically connected to the signal adjustment module 120, used to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and output an error differential voltage in real time according to the actual phase difference; and an error integration unit 132, electrically connected to the phase difference detection unit 131, used to integrate the error differential voltage, and provide the integrated output voltage as the adjusted delay control voltage to the signal adjustment module 120.

[0074] Specifically, the phase difference detection unit 131 can detect the actual phase difference θ between the first adjustment clock signal CKI' and the second adjustment clock signal CKQ', and convert the actual phase difference θ into an analog error differential voltage V. err Error differential voltage V err This consists of a pair of voltage signals with opposite polarities, specifically including V err+ With V err- Error differential voltage V err The magnitude of the amplitude represents the degree to which the actual phase difference θ deviates from the target phase difference θ1, while its positive or negative polarity represents the direction of deviation, i.e., whether the actual phase difference θ is too large or too small.

[0075] For example, the phase difference detection unit 131 can be implemented through various circuit structures. In one specific implementation, the phase difference detection unit 131 can be a Gilbert unit, which takes the first adjustment clock signal CKI' and the second adjustment clock signal CKQ' as the two inputs of a double-balanced mixer, and its output current, after being amplified by transimpedance, generates a pair of error differential voltages V that are proportional to the actual phase difference θ between the two clock signals. err When the actual phase difference θ is the target phase difference θ1 (e.g., 90°), the output error differential voltage V err The output error differential voltage V is zero when the actual phase difference θ deviates from the target phase difference θ1. err The amplitude is directly proportional to the deviation.

[0076] In another implementation, the phase difference detection unit 131 can also include an XOR gate and a low-pass filter. The first adjustment clock signal CKI' and the second adjustment clock signal CKQ' are input to the XOR gate, and its output pulse width is proportional to the actual phase difference θ. The DC component is then extracted by the low-pass filter to obtain the single-ended error voltage. To obtain a differential output, two XOR gates can be used for separate processing. For example, one path uses a direct XOR of the first adjustment clock signal CKI' and the second adjustment clock signal CKQ', and the other path uses an inverse XOR of the first adjustment clock signal CKI' and the second adjustment clock signal CKQ', thereby forming a differential signal and obtaining the error differential voltage V. err .

[0077] Furthermore, the error integration unit 132 receives the error differential voltage V from the phase difference detection unit 131. err The voltage is integrated to output a continuously varying integrated voltage V. out The integrated output voltage is used as the adjusted delay control voltage V. ctrl This continues until the error is completely eliminated, at which point the resulting negative feedback loop reaches steady-state lock-in.

[0078] In a specific implementation, the error integration unit 132 receives the error differential voltage V. err The output voltage V is obtained by integrating it over time. out Assuming the initial condition, the delay control voltage V ctrl The value is 0. If the actual phase difference θ is not equal to the target phase difference θ1, the delay control voltage V increases as the integration progresses. ctrl Will vary with the output voltage V out The voltage increases or decreases linearly until the error differential voltage V err The phase difference becomes zero (i.e., the actual phase difference θ reaches the target phase difference θ1). It can be understood that the integral operation ensures that even when the phase error approaches zero, the delay control voltage V... ctrlIt can also remain stable, thereby locking in the required delay compensation amount.

[0079] The output voltage V after integration by the error integration unit 132 out Used for real-time adjustment of delay control voltage V ctrl And adjust the delay control voltage V ctrl Provided to signal conditioning module 120. Signal conditioning module 120 controls the voltage V based on the delay. ctrl The internal delay unit is adjusted according to the changes in clock signal θ to correct the phase of the first clock signal CKI or the second clock signal CKQ, so that the actual phase difference θ gradually approaches the target phase difference θ1. When the actual phase difference θ is exactly equal to the target phase difference θ1, the error differential voltage V err When the error is zero, the output of the error integration unit 132 remains unchanged, and the resulting negative feedback loop enters a locked state. In the locked state, if the path load changes again due to temperature or voltage variations, causing a slight deviation in the actual phase difference θ, the phase difference detection unit 131 will quickly generate a new non-zero error differential voltage V. err Error integration unit 132 drives delay control voltage V ctrl Compensation is performed to achieve real-time dynamic tracking.

[0080] In one exemplary embodiment, refer to Figure 5 The phase difference detection unit 131 includes a multiplier M, and the error integration unit 132 includes an integrator. The multiplier M is used to multiply the input first adjustment clock signal and the second adjustment clock signal to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and outputs the error differential voltage in real time according to the actual phase difference. The integrator is used to integrate the error differential voltage, and the output voltage after integration is proportional to the cosine of the actual phase difference.

[0081] Specifically, the multiplier M performs a time-domain multiplication operation on the input first adjustment clock signal CKI' and the second adjustment clock signal CKQ', and outputs an error differential voltage V containing phase difference information. err An integrator is a circuit that accumulates the input signal over time. In this embodiment, the integrator receives the error differential voltage V output by the multiplier M. err The voltage is then integrated over continuous time, and the integrated output voltage is used as the adjusted delay control voltage V. ctrl Provided to signal conditioning module 120. The core function of the integrator is to achieve zero steady-state error, that is, the error differential voltage V output by multiplier M. err The output of the integrator is extremely small and close to zero, thus ensuring that the negative feedback loop is stably locked after reaching the target phase difference.

[0082] It is understandable that since the first clock signal CKI or the second clock signal CKQ has the same frequency, the first adjustment clock signal CKI' and the second adjustment clock signal CKQ' also have the same frequency. Mathematically, if the two clock signals are approximated as sine waves (or the fundamental component of a square wave), multiplying two sine signals of the same frequency will result in an output product containing a DC component and a second harmonic component. After the high-frequency component is naturally filtered out by the subsequent integrator, the remaining DC component is the delay control voltage V. ctrl .

[0083] In one example, the multiplier M can be implemented using devices such as a Gilbert multiplier, a switching multiplier, or a passive resistor mixer. In this embodiment, the multiplier M is preferably a Gilbert multiplier because it has high gain, wide bandwidth, low noise, and good common-mode rejection capability, making it suitable for phase detection of high-frequency clock signals (such as tens of GHz).

[0084] For two sinusoidal signals of the same frequency, through mathematical derivation, the output voltage after integration (i.e., the error difference voltage V output by multiplier M) is... err (the DC component), i.e., the delay control voltage V ctrl Cos(θ) is proportional to the cosine of the actual phase difference θ. Correspondingly, when θ = 90°, cos(90°) = 0, V err =0; when θ>90°, cosθ is negative, V err When θ < 90°, cosθ is negative; when θ < 90°, cosθ is positive, V err It is positive. Therefore, V err The polarity and magnitude of the value directly reflect the direction and degree to which the actual phase difference θ deviates from 90°.

[0085] In this embodiment, a cascaded structure of multipliers and integrators is used as the phase difference feedback module. The DC component output by the multiplier is proportional to the cosine of the actual phase difference, enabling highly sensitive orthogonal detection. The introduction of the integrator makes the DC gain of the loop approach infinity, automatically eliminating any static phase deviation and ensuring that the orthogonality after locking is accurate to 90°. Furthermore, both the Gilbert multiplier and the operational amplifier integrator are mature analog integrated circuit basic modules, occupying a small chip area and with controllable power consumption.

[0086] In one exemplary embodiment, refer to Figure 6 The first adjustment clock signal is also used to output to the first decision unit 200 of the half-rate sampling circuit to assist the first decision unit 200 in outputting the regenerated data signal according to the input data signal; the half-rate sampling circuit also includes a verification unit 500 connected to the first decision unit 200, and the verification unit 500 is used to output the bit error rate of the regenerated data signal relative to the input data signal.

[0087] Specifically, in this embodiment, the first adjusted clock signal CKI', after phase correction by the signal adjustment module 120, replaces the original first clock signal CKI and is provided to the first decision unit 200. This allows the first decision unit 200 to sample and decide on the received input data signal data_input based on the first adjusted clock signal CKI', obtaining the regenerated data signal data_syn. Simultaneously, the second adjusted clock signal CKQ', after phase correction by the signal adjustment module 120, also replaces the original second clock signal CKQ and is provided to the second decision unit 300. This allows the second decision unit 300 to sample and decide on the same input data signal data_input based on the second adjusted clock signal CKQ', obtaining the data edge signal edge_syn. Thus, based on the first adjusted clock signal CKI' and the second adjusted clock signal CKQ', the relative phase shift caused by the difference in capacitive load between edge sampling and data sampling is corrected, aligning the data sampling point with the center of the data eye diagram, thereby achieving the maximum signal-to-noise ratio during sampling.

[0088] Furthermore, this embodiment introduces a verification unit 500 connected to the first decision unit 200 in the half-rate sampling circuit. This unit receives the regenerated data signal data_syn output by the first decision unit 200 and performs bit-by-bit verification with the original input data signal data_input, calculating and outputting the bit error rate. The bit error rate is defined as the proportion of erroneous bits to the total number of transmitted bits. This verification result can be used to evaluate the quality of clock recovery and can serve as an additional feedback signal to trigger or fine-tune the locking state of the clock generation circuit 100.

[0089] In one example, the bit error rate (BER) output by the verification unit 500 can be implemented using the built-in self-test (BIST) mode of the half-rate sampling circuit. During system initialization or idle periods, a known pseudo-random bit sequence (PRBS) is injected into the input of the acquired input data signal data_input. The verification unit 500 contains an identical PRBS detector that performs a bit-by-bit XOR comparison between the input data signal data_input and the regenerated data signal data_syn, counts the number of error bits using a counter, and then calculates the BER.

[0090] In one exemplary embodiment, please continue to refer to Figure 6The phase difference feedback module 130 also includes an error control unit 133, which is electrically connected to the error integration unit 132 and the verification unit 500, and is used to provide the input offset voltage to the error integration unit 132 according to the bit error rate; the error integration unit 132 is used to integrate the error differential voltage and the input offset voltage, and provide the integrated output voltage as the adjusted delay control voltage to the signal adjustment module 120.

[0091] Understandable, refer to Figure 7 In certain pre-stage channel response conditions, the point of maximum signal-to-noise ratio (SNR) of the input data signal (data_input) may deviate from the center of the data cycle. Correspondingly, the phase difference between the first clock signal CKI and the second clock signal CKQ may need to be greater than 90° to align the data sampling point with the center of the data eye diagram, thereby achieving maximum SNR during sampling.

[0092] Furthermore, this embodiment introduces an error control unit 133, which serves as an interface between the verification unit 500 and the error integration unit 132. This unit converts the real-time bit error rate into a dynamically adjustable input offset voltage and superimposes it onto the input of the error integration unit 132. In this way, the phase lock point is no longer strictly fixed at the zero-error point of the multiplier output (i.e., 90° orthogonality), but can be slightly offset around 90° based on the actual data recovery quality, thereby searching for and locking onto the optimal phase difference corresponding to the minimum bit error rate.

[0093] Specifically, the error control unit 133 can receive the bit error rate output by the verification unit 500, and generate one or a set of input offset voltages V in real time based on the bit error rate. os This is then injected into the input terminal of the error integration unit 132. The error integration unit 132 is used to measure the error differential voltage V. err and input offset voltage V os The combination of these components is integrated, and the integrated output voltage is used as the adjusted delay control voltage V. ctrl Provided to signal conditioning module 120. It can be understood that the input offset voltage V... os Its function is to artificially bias the equivalent zero error point of the phase difference detection unit 131, forcing the negative feedback loop to lock on a phase difference that is not 90°, thereby compensating for the sampling window offset caused by non-ideal data path (such as inter-symbol interference, clock jitter asymmetry).

[0094] In one exemplary embodiment, refer to Figure 6 The integrator of the error integration unit 132 includes at least an operational amplifier U; the error control unit 133 includes an adjustable current source Is, which is connected in series between the inverting input terminal of the operational amplifier U and the ground terminal, and the adjustment terminal of the adjustable current source Is is connected to the verification unit 500.

[0095] Specifically, the error integration unit 132 is an integrator based on an operational amplifier, and the error control unit 133 is correspondingly specified as an adjustable current source Is. The adjustable current source Is is connected in series between the inverting input terminal of the operational amplifier U and the ground terminal (or power supply reference ground), and its adjustment terminal is directly or indirectly connected to the verification unit 500 to obtain a control signal output based on the bit error rate.

[0096] It can be understood that the adjustable current source Is is a controlled current source, and its output current I... os The magnitude of the error rate is adjusted by the control signal output by the verification unit 500 based on the bit error rate. This is achieved by adjusting the output current I. os The magnitude of the current allows a controllable offset current to be injected into the inverting input of the integrator, which is equivalent to superimposing an input offset voltage V at the input. os This changes the lock-in phase point of the negative feedback loop.

[0097] In one example, please refer to... Figure 6 The verification unit 500 includes at least a PRBS detector 510 and a digital controller 520. The PRBS detector 510 performs a bit-by-bit XOR comparison between the input data signal `data_input` and the regenerated data signal `data_syn`, counts the number of error bits using a counter, and then calculates the bit error rate. The digital controller 520 outputs a control signal based on the bit error rate and provides the control signal to the error control unit 133. In other examples, the verification unit 500 may only include the PRBS detector 510, with the controller integrated into the error control unit 133. After obtaining the bit error rate, the error control unit 133 generates a control signal based on the bit error rate to regulate the adjustable current source `Is`.

[0098] In this embodiment, the traditional phase feedback loop only guarantees clock quadrature, but distortions in the data path (such as bandwidth limitations and reflections) may cause the optimal sampling point to not be precisely located at the center of the eye diagram. This embodiment uses the real-time bit error rate as a direct indicator to dynamically adjust the locking point to the actual minimum bit error rate position, significantly improving the fault tolerance of the half-rate sampling circuit.

[0099] In one exemplary embodiment, refer to Figure 5 or Figure 6 The signal adjustment module 120 includes a first clock driver 121 and a second clock driver 122; the first clock driver 121 is used to receive a first clock signal and adjust and output a first adjusted clock signal; the second clock driver 122 is used to receive a second clock signal and adjust and output a second adjusted clock signal; a delay control voltage is provided to the delay control terminal of the first clock driver 121 or the second clock driver 122.

[0100] Specifically, the first clock driver 121 and the second clock driver 122 are voltage-controlled adjustable delay drivers, which can be derived from the clock signal of the clock generation module 110, and internally adjust according to the voltage signal (e.g., delay control voltage V) received at their delay control terminals. ctrl The clock signal is subject to a controllable delay adjustment, and the output is the adjusted clock signal. This is achieved by controlling the delay voltage V. ctrl The delay control terminal of the first clock driver 121 or the second clock driver 122 is selectively applied to achieve controllable adjustment of the relative phase between the two clock signals.

[0101] In one example, to simplify circuit design, the first clock driver 121 and the second clock driver 122 are typically implemented using the exact same circuit topology. The only difference lies in the connection of the delay control terminal; only one connection has the delay control voltage V. ctrl This can be understood as follows: of the first clock driver 121 and the second clock driver 122, only one path is adjusted, while the other path serves as a fixed reference. This ensures that the phase difference adjustment direction is unique and avoids control ambiguity that may result from adjusting both paths simultaneously.

[0102] In one exemplary embodiment, refer to Figure 6 This application also provides a half-rate sampling circuit, including a clock generation circuit 100, a first decision unit 200, a second decision unit 300, and a clock data recovery unit 400 as described in any of the above embodiments; the clock generation circuit 100 is connected to the first decision unit 200 and the second decision unit 300, and is used to provide a first adjustment clock signal CKI' to the first decision unit 200 and a second adjustment clock signal CKQ' to the second decision unit 300; both the first decision unit 200 and the second decision unit 300 are connected to the clock data recovery unit 400, and the clock data recovery unit 400 is connected to the clock generation circuit 100; the first decision unit 200 is used to perform a clock data recovery based on the first adjustment clock signal CKI'. The clock signal CKI' outputs the received input data signal data_input as a regenerated data signal data_syn, and provides the regenerated data signal data_syn to the clock data recovery unit 400; the second decision unit 300 is used to output the input data signal data_input as a data edge signal edge_syn based on the second adjustment clock signal CKQ', and provide the data edge signal edge_syn to the clock data recovery unit 400; the clock data recovery unit 400 is used to output a phase control voltage to the clock generation circuit 100 according to the edge phase difference between the regenerated data signal data_syn and the data edge signal edge_syn.

[0103] Specifically, in this embodiment, a first adjusted clock signal CKI', after phase correction by the clock generation circuit 100, replaces the original first clock signal CKI and is provided to the first decision unit 200. This unit samples and decides on the received input data signal data_input based on the first adjusted clock signal CKI' to obtain the regenerated data signal data_syn. Simultaneously, a second adjusted clock signal CKQ', after phase correction by the clock generation circuit 100, also replaces the original second clock signal CKQ and is provided to the second decision unit 300. This unit samples and decides on the same input data signal data_input based on the second adjusted clock signal CKQ' to obtain the data edge signal edge_syn. Thus, based on the first adjusted clock signal CKI' and the second adjusted clock signal CKQ', the relative phase shift caused by the difference in capacitive load between edge sampling and data sampling is corrected, aligning the data sampling point with the center of the data eye diagram and achieving the maximum signal-to-noise ratio during sampling.

[0104] In one exemplary embodiment, please continue to refer to Figure 6 The aforementioned half-rate sampling circuit also includes a verification unit 500, which is connected to the first decision unit 200 and the clock generation circuit 100. The verification unit 500 is used to output the bit error rate of the regenerated data signal data_syn relative to the input data signal data_input, and to provide the bit error rate to the clock generation circuit 100.

[0105] Specifically, this embodiment introduces a verification unit 500 connected to the first decision unit 200 in the half-rate sampling circuit. This unit receives the regenerated data signal data_syn output by the first decision unit 200 and performs bit-by-bit verification with the original input data signal data_input, calculating and outputting the bit error rate. The bit error rate is defined as the proportion of erroneous bits to the total number of transmitted bits. This verification result can be used to evaluate the quality of clock recovery and can serve as an additional feedback signal to trigger or fine-tune the locking state of the clock generation circuit 100.

[0106] In one exemplary embodiment, this application also provides a signal transceiver chip, including a half-rate sampling circuit as described in any of the above embodiments.

[0107] It is understood that the solution provided by the above-mentioned half-rate sampling circuit and signal transceiver chip is similar to the solution described in the above-mentioned clock generation circuit. Therefore, the specific limitations of the one or more half-rate sampling circuits and signal transceiver chip embodiments can be found in the limitations of the clock generation circuit above, and will not be repeated here.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock generating circuit, characterized in that, include: A clock generation module is used to generate a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency; The signal adjustment module is electrically connected to the clock generation module and is used to adjust the phase of the first clock signal or the second clock signal according to the input delay control voltage, and output the first adjusted clock signal and the second adjusted clock signal. The first adjustment clock signal is output to the first decision unit of the half-rate sampling circuit to assist the first decision unit in outputting a regenerated data signal based on the input data signal; the half-rate sampling circuit further includes a verification unit connected to the first decision unit, the verification unit being used to output the bit error rate of the regenerated data signal relative to the input data signal; The phase difference feedback module includes a phase difference detection unit, an error integration unit, and an error control unit. The phase difference detection unit is electrically connected to the signal adjustment module and the error integration unit, and the error control unit is electrically connected to the error integration unit and the verification unit. The phase difference detection unit is used to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and outputs the error differential voltage in real time according to the actual phase difference; The error control unit is used to provide an input offset voltage to the error integration unit according to the bit error rate; The error integration unit is used to integrate the error differential voltage and the input offset voltage, and outputs the integrated output voltage as the adjusted delay control voltage to the signal adjustment module until the actual phase difference reaches the target phase difference.

2. The clock generating circuit according to claim 1, characterized in that, The phase difference detection unit includes a multiplier, and the error integration unit includes an integrator. The multiplier is used to multiply the input first adjustment clock signal and the second adjustment clock signal to detect the actual phase difference between the first adjustment clock signal and the second adjustment clock signal, and output the error differential voltage in real time according to the actual phase difference. The integrator is used to integrate the error differential voltage, and the output voltage after integration is proportional to the cosine of the actual phase difference.

3. The clock generating circuit according to claim 2, characterized in that, The integrator includes at least an operational amplifier; The error control unit includes an adjustable current source, which is connected in series between the inverting input terminal and the ground terminal of the operational amplifier, and the adjustment terminal of the adjustable current source is connected to the verification unit.

4. The clock generating circuit according to claim 1, characterized in that, The signal adjustment module includes a first clock driver and a second clock driver; The first clock driver is used to receive the first clock signal and adjust the output of the first adjustment clock signal; The second clock driver is used to receive the second clock signal and adjust the output of the second adjustment clock signal; The delay control voltage is provided to the delay control terminal of the first clock driver or the second clock driver.

5. The clock generating circuit according to claim 1, characterized in that, The target phase difference is 90°.

6. A half-rate sampling circuit, characterized in that, Includes the clock generating circuit, the first decision unit, the second decision unit, and the clock data recovery unit as described in any one of claims 1 to 5; The clock generating circuit connects the first decision unit and the second decision unit, and is used to provide a first adjustment clock signal to the first decision unit and a second adjustment clock signal to the second decision unit. Both the first decision unit and the second decision unit are connected to the clock data recovery unit, and the clock data recovery unit is connected to the clock generating circuit. The first decision unit is used to output the received input data signal as a regenerated data signal based on the first adjustment clock signal, and to provide the regenerated data signal to the clock data recovery unit; The second decision unit is used to output the input data signal as a data edge signal based on the second adjustment clock signal, and to provide the data edge signal to the clock data recovery unit; The clock data recovery unit is used to output a phase control voltage to the clock generation circuit based on the edge phase difference between the regenerated data signal and the data edge signal.

7. The half-rate sampling circuit according to claim 6, characterized in that, It also includes a verification unit, which is connected to the first decision unit and the clock generation circuit, for outputting the bit error rate of the regenerated data signal relative to the input data signal, and providing the bit error rate to the clock generation circuit.

8. A signal transceiver chip, characterized in that, Includes the half-rate sampling circuit as described in claim 6 or 7.

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