A multi-module cascaded solid-state transformer coordinated control method

Abstract

This invention discloses a coordinated control method for a multi-module cascaded solid-state transformer, relating to the field of power electronics technology. The solid-state transformer includes multiple power conversion units, each employing a combined topology of front-end and rear-end conversion modules. Through the synergy of front-end voltage build-up control and rear-end optimal trajectory soft-start control, a phased and controllable soft-start strategy is constructed. First, the front-end actively builds up and equalizes the input buses at each stage, boosting and stabilizing the bus voltage within a safe operating range for startup, providing approximately constant input conditions for the rear-end stages. The rear-end stages employ an optimal trajectory control strategy, constraining the evolution paths of resonant current and capacitor voltage to achieve controlled power delivery, reducing problems such as overshoot, current surges, and excessive device stress during startup. Simultaneously, on the output side, phased control and a smooth transition mechanism ensure that the output voltage gradually builds up along a predetermined trajectory. After the system enters the steady-state operation stage, a post-stage steady-state optimization control method is proposed. The allocation coefficients of each module are used as unified optimization variables. The optimal allocation result is solved by a resource-aware distributed differential evolution algorithm. The allocation result is mapped to specific control inputs through the local controllers of each module, thereby optimizing the adaptive and coordinated operation mechanism of the post-stage system.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a coordinated control method for multi-module cascaded solid-state transformers. Background Technology

[0002] Solid-state transformers, as a novel power conversion device, possess technological advantages such as high-frequency isolation, active regulation, and high power density, and can be widely used in smart grids, rail transit, and new energy power generation. However, traditional solid-state transformers typically consist of multiple cascaded power conversion units and high-frequency isolation stages, resulting in tight energy coupling and complex dynamic behavior within the system. Especially during startup, significant timing mismatches exist between voltage establishment and energy transfer at each stage, easily leading to problems such as input current surges, DC bus voltage overshoot, and output voltage fluctuations, severely impacting system startup stability and the operational reliability of power devices.

[0003] In existing technologies, various solutions have been proposed for the startup problem of solid-state transformers, but all have significant limitations. For example, soft-start methods based on specific topologies, such as utilizing the constant voltage gain characteristics of resonant units, can suppress startup shocks, but are limited by the topology and difficult to extend to other architectures. While multi-level cooperative control schemes can optimize the startup process, their high control complexity reduces system robustness. A particularly prominent problem is that most current methods rely on preset startup timing sequences or fixed parameters, making it difficult to adapt to dynamic operating conditions such as wide-range input voltages and sudden load changes, thus increasing the risk of startup failure. Summary of the Invention

[0004] In view of this, the present invention provides a coordinated control method for multi-module cascaded solid-state transformers, which can achieve stable establishment of bus voltage and smooth switching of soft-start mode, while also taking into account the current sharing performance optimization of downstream parallel modules.

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] This invention provides a coordinated control method for multi-module cascaded solid-state transformers, wherein the topology of the solid-state transformer includes multiple modules composed of front-end circuits and back-end circuits; the method includes: Pre-stage proactive pressure building; When the voltage of the current stage bus reaches the first start-up threshold of the subsequent stage, the current stage switches to a holding state, and the subsequent stage uses a phased collaborative control method based on optimal trajectory control to achieve soft start. The phased collaborative control method based on optimal trajectory control includes: Stage 1 uses asymmetric current limiting to establish the track, with the goal of first positioning the resonant cavity on a suitable trajectory; Stage 2 uses symmetric current limiting to deliver energy, with the goal of effectively delivering energy to the output terminal under current limiting constraints, and then outputting the switching frequency; Stage 3 reduces the frequency to approach the target output, with the goal of gradually reducing the switching frequency until the output reaches the target value. Determine whether the output bus voltage has reached the second start-up threshold. If it has, switch the subsequent stage from the start-up control state to the hold control state to maintain the stability of the output bus. After the preceding stage bus voltage reaches the set threshold and meets the stability conditions, smoothly switch the system to the normal operation mode.

[0007] Furthermore, it also includes: periodically sampling the output current and output voltage of each parallel module after the steady-state stage, constructing a current sharing optimization objective function, and using a resource-aware distributed differential evolution algorithm to optimize the parameters for current sharing.

[0008] Furthermore, the aforementioned pre-stage active pressure building includes: All switches in the front stage are turned off, and the DC bus of each unit in the front stage is slowly charged through the pre-charge resistor, so that the voltage of the front stage bus is gradually established. Determine whether the front-end bus voltage has reached the set pre-charge threshold; if it has, bypass the pre-charge resistor, keep the lower bridge arm of the front-end always off, and only allow the upper bridge arm to be engaged with a narrow pulse width, and gradually increase the pulse width so that the front-end actively builds up voltage.

[0009] Furthermore, the holding state of the preceding stage is as follows: after the preceding stage bus voltage reaches the predetermined value, the pulse width no longer continues to increase, but instead the hysteresis voltage control is used to maintain the bus at the target value.

[0010] Furthermore, in stage 1, the resonant angular frequency is first determined: ;in, The resonant angular frequency, It is a resonant inductor. It is a resonant capacitor; Normalized positive current limiting band: ;in, For normalized positive current limiting band, This is the upper limit of the actual current. This is the input voltage for the subsequent stage, which is also the bus voltage for the preceding stage. Normalized negative current limiting band: ;in, This represents the actual value of the negative current-limiting band in the first stage. Based on the resonant cavity state plane trajectory, the duration of each switching interval in the first stage is calculated sequentially. The controller stores this information in a lookup table sequence; during online startup, the controller executes commutation sequentially according to this sequence until the resonant capacitor voltage... Upon entering the target area, the first phase ends. In stage 2, the geometric angles are calculated first: ;in: These are the two key angles between the two points on the second-stage state trajectory; Switching cycle: Switching frequency: ;in: For switching cycles; The switching frequency; For each discrete output voltage point Find a corresponding frequency ,form: ;in: For stage 2, a frequency-voltage lookup table is provided. For the first k One discrete output voltage sampling point; This is the limiting frequency corresponding to this output point; By output voltage Send the information to the pulse width modulation (PWM) module to update the switching frequency; The process of sampling, looking up, and updating the frequency of the output voltage is repeated. When the output voltage rises to the upper boundary of the second stage lookup interval, that is, when it reaches the end of the second stage effective interval determined when the frequency-voltage lookup table is established offline, the second stage ends. In stage 3, the target output is approximated by discrete frequency reduction until the output reaches the target value; the discrete frequency reduction law is: ;in: For the first k The switching frequency at each sampling time; This represents the frequency decrease step size.

[0011] Furthermore, during the steady-state phase, the output current and output voltage of each parallel module in the subsequent stage are periodically sampled to construct a current sharing optimization objective function. A resource-aware distributed differential evolution algorithm is then used to optimize the parameters for current sharing, including: Assume the subsequent level has a total n The first parallel module, the first k The output current of each module is The total output current is Then we have: ; Each module is allocated a different workload ratio based on its resource status, including: defining the first... k The allocation coefficient for each module is Then the following conditions are met: And set the reference output current for each module as follows: ;in, The total output current is used as a reference value; resource status variables are introduced. : ;in, Let the module temperature be the reference allocation coefficient; normalize it to obtain the resource-aware reference allocation coefficient: ; Assign output tasks according to the resource-aware reference allocation coefficients; The objective function for flow equalization optimization is as follows: ; in: This is the reference value for the output voltage; This is the actual output voltage; These are the weighting coefficients; Define the decision variables for each subsequent module: ;in, n This represents the number of subsequent parallel modules; In the t Each optimization cycle samples the output voltage, the current of each module's downstream stage, and the time; and calculates the total output current. The generation scale is N p The initial population: ;in: and Define the upper and lower bounds of the variable; A random number between 0 and 1; where each individual is a set of candidate assignment coefficients; Mutations: ;in: Three random variables are assigned to the population; It is a difference vector; This is the scaling factor for the variation. cross: ;in: These are the new parameters that have been mutated; The old parameters that performed well in the previous generation; Crossover rate; Each individual is a set of candidate assignment coefficients; Normalize the experimental individuals: And guarantee: ; Substitute the normalized individuals into the objective function; if an individual performs better, retain it. ; If the maximum number of iterations is reached G maxIf the change in the optimal objective function is less than a given threshold, then the optimal allocation coefficient is output: ; After obtaining the optimal allocation coefficients, calculate the reference output current for each module: ; The local controller of each module determines the topology based on the topology. Transformed into specific control quantities: ; in This is the local control input for the k-th module. This is the local control law for the corresponding topology; The upper-level differential evolution optimizer operates at low frequency and periodically updates the allocation coefficients, while the lower-level local current controller operates at high frequency and quickly tracks the reference current of each module to maintain continuous current sharing during the steady-state phase.

[0012] The above technical solution, through the phased collaborative start-up control of the front and rear stages, achieves controlled establishment of bus voltage, effective suppression of resonant cavity stress, and smooth transition from start-up mode to normal operation mode without increasing the complexity of hardware structure. It can reduce start-up impact, improve start-up reliability, and enhance the safety and feasibility of the system in practical engineering applications. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a circuit diagram of the solid-state transformer in an embodiment of the present invention; Figure 2 This is a flowchart of a coordinated control method for multi-module cascaded solid-state transformers in an embodiment of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] The topology of a solid-state transformer consists of multiple modules composed of a front-end circuit and a rear-end circuit. The following section uses the structure of a cascaded H-bridge in the front-end and an LLC resonant converter in the rear-end as an example to illustrate the system topology and its working process.

[0018] like Figure 1 As shown, the solid-state sensor in this embodiment adopts a combined topology structure of cascaded H-bridge and LLC resonant converter. The overall structure consists of four core units: a power grid input module, a cascaded H-bridge converter module, an LLC resonant converter module, and a control module. The power grid input module directly connects the medium-voltage AC power to the AC side of the cascaded H-bridge converter module. The cascaded H-bridge converter module is composed of multiple H-bridge units connected in series. Through control, multi-level rectification is achieved, converting the high-voltage AC power into multiple stable DC voltages. This DC voltage is connected to the primary side of the LLC resonant converter, which consists of H-bridges and resonant inductors. L r Magnetizing inductor L m Resonant capacitor C r The system is constructed using the principle of high-frequency resonant conversion to achieve DC voltage reduction and efficient energy transfer. The control module employs a phased coordinated control method based on optimal trajectory control to coordinate the active voltage build-up process in the preceding stage with the three-stage soft-start process in the subsequent stage, achieving a smooth transition and control during the system's soft-start process. Simultaneously, combined with current sharing regulation in the subsequent stage during steady-state operation, the overall system efficiency and stability are improved.

[0019] like Figure 2 As shown, a coordinated control method for multi-module cascaded solid-state transformers includes the following specific steps: Step S1: The system starts up and samples the grid-side input current. H-bridge bus voltage sampling The output bus voltage is sampled. The resonant current was sampled. The voltage of the resonant capacitor is sampled. The output current of each parallel module of the LLC is sampled. .

[0020] Step S2: The front-end DC bus is charged through the pre-charging stage.

[0021] Specifically, with all H-bridge switches off, the system is equivalent to diode rectification. The DC buses of each H-bridge unit are slowly charged through pre-charge resistors, allowing the H-bridge bus voltage to gradually build up. In other words, the initial inrush current is mainly suppressed by the pre-charge resistors connected in series in the circuit.

[0022] Step S3, Judgment Has the set pre-charge threshold been reached? If it has been reached, proceed to step S4; otherwise, return to step S2. The pre-charge threshold of the H-bridge bus voltage is specifically considered in conjunction with the operating conditions. In this embodiment, the pre-charge threshold is 0.49 times the line voltage divided by the number of H-bridge units per phase. .

[0023] Step S4: Bypass the pre-charge resistor. The lower arm of the H-bridge is always turned off, and only the upper arm is connected with a narrow pulse width. The pulse width is gradually increased so that the H-bridge actively builds up voltage. Step S5, Judgment Has it been achieved? If the condition is met, proceed to step S6; otherwise, return to step S4. in It is not the minimum voltage for LLC startup, but the minimum allowable input that can pull the output to the target value during the optimal trajectory control phase of OTC.

[0024] Step S6: The front stage switches to holding state, and the front stage bus voltage is maintained by hysteresis. The rear stage achieves soft start based on optimal trajectory control. Specifically, the H-bridge switches to a hold state, which means that after the H-bridge bus voltage reaches a predetermined value, the PWM pulse width no longer increases, but instead uses hysteresis voltage control to maintain the bus at the target value. The LLC achieves soft start based on optimal trajectory control. The optimal trajectory control method is used for the solid-state transformer LLC. The specific steps of the optimal trajectory control are as follows: Phase 1 employs asymmetric current-limiting trajectory establishment to first position the resonant cavity onto a suitable trajectory. In the mixed-signal implementation, when the resonant current encounters the positive current-limiting band, the PWM switches; when it encounters the negative current-limiting band, it switches in the opposite direction. Furthermore, this phase does not solve equations online, but rather executes according to a pre-established offline timetable.

[0025] First, determine the resonant angular frequency: ;in, The resonant angular frequency, It is a resonant inductor. It is a resonant capacitor.

[0026] Normalized current limiting band: ;in, For normalized positive current limiting band, This is the upper limit of the actual current. This is the LLC input voltage, also known as the H-bridge bus voltage.

[0027] Similarly, normalized negative current limiting band: ;in, This represents the actual value of the negative current-limiting band in the first stage.

[0028] The effect of input voltage variation on current stress: ;in, The input voltage is The actual current stress at that time.

[0029] Current stress is proportional to the input voltage and does not change much within the typical input fluctuation range. Therefore, the same set of meters is robust to a certain input range, but in essence, it should still be calculated for a specific power level.

[0030] At the initial startup, since the output capacitor is very large and there are only a few switching pulses in the first stage, the output voltage can be approximated as zero. At the same time, the resonant capacitor voltage and resonant current are taken as zero in the initial state.

[0031] ; Seeking the first beat : ; in: The duration of the first switch; The angle corresponding to the first segment of the trajectory; This is the radius parameter of the first trajectory circle.

[0032] Then we get:

[0033] Seeking a second beat : ; ; Then, continue the process step by step in the same way to form a complete timetable.

[0034] ; Then calculate sequentially until... Upon entering the target area, the first phase is complete.

[0035] Phase 2 employs symmetrical current-limited energy delivery. The goal of this phase is to effectively deliver energy to the output end under current-limited constraints, and then sample the energy. ,according to Offline meter outputs switching frequency.

[0036] First, calculate the geometric angle: ; in: These are the two key angles between the two states of the second stage trajectory.

[0037] Switching cycle: ; Switching frequency: ; in: For switching cycles; This refers to the switching frequency.

[0038] Thus, for each discrete output voltage point A corresponding frequency can be obtained from all of them. .

[0039] Final form: ; in: For stage 2, a frequency-voltage lookup table is provided. For the first k One discrete output voltage sampling point; This is the limiting frequency corresponding to this output point.

[0040] By output voltage The signal is sent to the PWM module to update the switching frequency. Then, sampling is repeated. The loop of —looking up the table and updating the frequency continues until the end condition of the second phase is met.

[0041] Phase 3 involves frequency reduction to approach the target output. The goal of this phase is to gradually reduce the switching frequency until the output reaches the target value.

[0042] This can be written as a discrete frequency reduction law: ; in: For the first k The switching frequency at each sampling time; This represents the frequency decrease step size.

[0043] Step S7: Determine the output bus voltage Has the LLC startup threshold been reached? If it has, proceed to step S8; otherwise, return to step S6. The start-up threshold is determined based on the applicable range of the input voltage for LLC optimal trajectory control and current limiting constraints, and is typically taken as 0.9 times the nominal input voltage. 0.95 times, the exact amount depends on the actual working conditions.

[0044] Step S8: First, switch the downstream stage from the start-up control state to the hold-up control state. After the upstream bus voltage reaches the threshold and meets the stability conditions, switch to normal operation mode. Specifically, the LLC is first switched from start-up control to hold control to maintain the stability of the output bus; after the H-bridge bus voltage reaches the set threshold and meets the stability conditions, the system is then smoothly switched to normal operation mode.

[0045] Step S9: During the steady-state operation phase, the output current and output voltage of each parallel module in the subsequent stage are sampled, an objective function with current sharing performance optimization as the core is constructed, and a resource-aware distributed differential evolution algorithm is used for optimization and solution. Specifically, during the steady-state phase, the output current of each parallel module of the LLC is periodically sampled. With output voltage A flow sharing optimization objective function is constructed, and a resource-aware distributed differential evolution algorithm is used to optimize the flow sharing control parameters for flow sharing.

[0046] The current sharing and collaborative optimization of LLC in solid-state transformers based on the resource-aware distributed differential evolution algorithm mainly focuses on current sharing in the steady-state stage. The current sharing in the steady-state stage is achieved by optimizing the variables of each LLC module to realize the balanced distribution of the output current of multiple modules.

[0047] For current sharing in solid-state transformer LLC, a resource-aware distributed differential evolution algorithm is incorporated for collaborative optimization. The specific method is as follows: Let LLC have a total n The first parallel module, the first k The output current of each module is The total output current is Then we have: ; Each module is allocated a different workload based on its resource status. Define the... k The allocation coefficient for each module is Then the following conditions are met: ; And set the reference output current for each module as follows: ;in, This is the reference value for the total output current.

[0048] To reflect the differences in module capabilities, resource state variables are introduced. Considering only the temperature most significant for engineering purposes, it can be simplified to: ;in, This refers to the module temperature.

[0049] Normalizing it yields the resource-aware reference allocation coefficient: ; Modules with better resource status and lower temperature should undertake more output tasks.

[0050] Define the decision variables for each LLC module: ; in, n This represents the number of LLC parallel modules.

[0051] The steady-state flow equalization objective function controlled by the resource-aware distributed differential evolution algorithm in step S9 is as follows: ; in: This is the reference value for the output voltage; This is the actual output voltage; These are the weighting coefficients.

[0052] In the t In each optimization cycle, the output voltage, LLC current of each module, and time are sampled, and the total output current is calculated.

[0053] The generation scale is N p The initial population: ; in: and Define the upper and lower bounds of the variable; A random number between 0 and 1.

[0054] Each individual is a set of candidate allocation coefficients.

[0055] Mutations: ; in: Three random variables are assigned to the population; It is a difference vector; This is the scaling factor for the variation.

[0056] cross: ; in, These are the new parameters that have been mutated; The old parameters that performed well in the previous generation; This represents the crossover rate.

[0057] Each individual is a set of candidate allocation coefficients.

[0058] Since the allocation coefficients must sum to 1, the experimental individuals are normalized. ; And guarantee: ; Substitute the normalized individuals into the objective function; if an individual performs better, retain it. ; If the maximum number of iterations is reached G max If the change in the optimal objective function is less than a given threshold, then the optimal allocation coefficient is output.

[0059] ; After obtaining the optimal allocation coefficients, calculate the reference output current for each module: ; Next, the local controllers of each module will determine the topology based on the data. Transformed into specific control quantities.

[0060] ; in For the subsequent LLC k Frequency compensation amount of each module This is the local control law for the corresponding topology.

[0061] The upper-level differential evolution optimizer operates at a low frequency, periodically updating the allocation coefficients, while the lower-level local current controller operates at a high frequency, rapidly tracking the reference current of each module to maintain continuous current sharing during the steady-state phase.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A coordinated control method for a multi-module cascaded solid-state transformer, wherein the topology of the solid-state transformer comprises multiple modules consisting of a front-end circuit and a rear-end circuit; characterized in that, The method includes: The preceding stage actively builds pressure; When the voltage of the current stage bus reaches the first start-up threshold of the subsequent stage, the current stage switches to a holding state, and the subsequent stage uses a phased collaborative control method based on optimal trajectory control to achieve soft start. The phased collaborative control method based on optimal trajectory control includes: Stage 1 uses asymmetric current limiting to establish the track, with the goal of first positioning the resonant cavity on a suitable trajectory; Stage 2 uses symmetric current limiting to deliver energy, with the goal of effectively delivering energy to the output terminal under current limiting constraints, and then outputting the switching frequency; Stage 3 reduces the frequency to approach the target output, with the goal of gradually reducing the switching frequency until the output reaches the target value. Determine whether the output bus voltage has reached the second start-up threshold. If it has, switch the subsequent stage from the start-up control state to the hold control state to maintain the stability of the output bus. After the preceding stage bus voltage reaches the set threshold and meets the stability conditions, smoothly switch the system to the normal operation mode.

2. The method for coordinated control of multi-module cascaded solid-state transformers according to claim 1, characterized in that, Also includes: During the steady-state phase, the output current and output voltage of each parallel module in the subsequent stage are periodically sampled to construct the current sharing optimization objective function, and the parameters are optimized for current sharing using a resource-aware distributed differential evolution algorithm.

3. The coordinated control method for multi-module cascaded solid-state transformers according to claim 1, characterized in that, The aforementioned pre-stage active pressure build-up includes: All switches in the front stage are turned off, and the DC bus of each unit in the front stage is slowly charged through the pre-charge resistor, so that the voltage of the front stage bus is gradually established. Determine whether the front-end bus voltage has reached the set pre-charge threshold; if it has, bypass the pre-charge resistor, keep the lower bridge arm of the front-end always off, and only allow the upper bridge arm to be engaged with a narrow pulse width, and gradually increase the pulse width so that the front-end actively builds up voltage.

4. The coordinated control method for multi-module cascaded solid-state transformers according to claim 1, characterized in that, The holding state of the front stage is as follows: after the front stage bus voltage reaches the predetermined value, the pulse width will no longer continue to increase, but will instead be controlled by hysteresis voltage to maintain the bus at the target value.

5. The method for coordinated control of a solid-state transformer downstream based on optimal trajectory control according to claim 1, characterized in that, In stage 1, the resonant angular frequency is first determined: ;in, The resonant angular frequency, It is a resonant inductor. It is a resonant capacitor; Normalized positive current limiting band: ;in, For normalized positive current limiting band, This is the upper limit of the actual current. This is the input voltage for the subsequent stage, which is also the bus voltage for the preceding stage. Normalized negative current limiting band: ;in, This represents the actual value of the negative current-limiting band in the first stage; Based on the resonant cavity state plane trajectory, the duration of each switching interval in the first stage is calculated sequentially. The controller stores this information in a lookup table sequence; during online startup, the controller executes commutation sequentially according to this sequence until the resonant capacitor voltage... Upon entering the target area, the first phase ends. In stage 2, the geometric angles are calculated first: ;in: These are the two key angles between the two points on the second-stage state trajectory; Switching cycle: Switching frequency: ;in: For switching cycles; The switching frequency; For each discrete output voltage point Find a corresponding frequency ,form: ;in: For stage 2, a frequency-voltage lookup table is provided. For the first k One discrete output voltage sampling point; This is the limiting frequency corresponding to this output point; By output voltage Send the information to the pulse width modulation (PWM) module to update the switching frequency; The process of sampling, looking up, and updating the frequency of the output voltage is repeated. When the output voltage rises to the upper boundary of the second stage lookup interval, that is, when it reaches the end of the second stage effective interval determined when the frequency-voltage lookup table is established offline, the second stage ends. In stage 3, the target output is approximated by discrete frequency reduction until the output reaches the target value; the discrete frequency reduction law is: ;in: For the first k The switching frequency at each sampling time; This represents the frequency decrease step size.

6. The method for coordinated control of a solid-state transformer downstream based on optimal trajectory control according to claim 2, characterized in that, During the steady-state phase, the output current and output voltage of each parallel module in the subsequent stage are periodically sampled to construct a current sharing optimization objective function. A resource-aware distributed differential evolution algorithm is then used to optimize the parameters for current sharing, including: Assume the subsequent level has a total n The first parallel module, the first k The output current of each module is The total output current is Then we have: ; Each module is allocated a different workload ratio based on its resource status, including: defining the first... k The allocation coefficient for each module is Then the following conditions are met: And set the reference output current for each module as follows: ;in, The total output current is used as a reference value; resource status variables are introduced. : ;in, Let the module temperature be the reference allocation coefficient; normalize it to obtain the resource-aware reference allocation coefficient: ; Assign output tasks according to the resource-aware reference allocation coefficients; The objective function for flow equalization optimization is as follows: ； in: This is the reference value for the output voltage. This is the actual output voltage; These are the weighting coefficients; Define the decision variables for each subsequent module: ;in, n This represents the number of subsequent parallel modules; In the t Each optimization cycle samples the output voltage, the current of each module's downstream stage, and the time; and calculates the total output current. The generation scale is N p The initial population: ;in: and Define the upper and lower bounds of the variable; A random number between 0 and 1; where each individual is a set of candidate assignment coefficients; Mutations: ;in: Three random variables are assigned to the population; It is a difference vector; This is the scaling factor for the variation; cross: ;in: These are the new parameters that have been mutated; The old parameters that performed well in the previous generation; Crossover rate; Each individual is a set of candidate assignment coefficients; Normalize the experimental individuals: And guarantee: ; Substitute the normalized individuals into the objective function; if an individual performs better, retain it. ； If the maximum number of iterations is reached G max If the change in the optimal objective function is less than a given threshold, then the optimal allocation coefficient is output: ; After obtaining the optimal allocation coefficients, calculate the reference output current for each module: ; The local controller of each module determines the topology based on the topology. Transformed into specific control quantities: ; in This is the local control input for the k-th module. This is the local control law for the corresponding topology; The upper-level differential evolution optimizer operates at low frequency and periodically updates the allocation coefficients, while the lower-level local current controller operates at high frequency and quickly tracks the reference current of each module to maintain continuous current sharing during the steady-state phase.

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