A dual-machine SPI communication method using time-division multiplexing handshake lines to implement CRC response retransmission

Abstract

This invention discloses a dual-machine SPI communication method that uses time-division multiplexing handshake lines to implement CRC response retransmission. It adds two unidirectional handshake lines to the traditional four-wire SPI bus: handshake line 1 from slave to master and handshake line 2 from master to slave. Before SPI frame communication begins, the handshake lines transmit communication request and response signals. After SPI frame communication begins, the handshake function of the two lines is completed, and their function switches to transmitting verification response signals. The system then uses these signals to determine whether to initiate retransmission within a specified time limit. Compared to the traditional method of transmitting verification responses from the SPI data channel, this method is more convenient and reliable. The multiplexing of handshake lines reduces the system's I / O resource consumption. This invention establishes a comprehensive universal frame format with mechanisms such as flow control, CRC check retransmission selection, fast one's complement verification, loop counting, and error frame counting, which can adapt to a wider range of SPI communication needs, such as high-reliability or high-speed communication modes.

Description

Technical Field

[0001] This invention relates to the field of Serial Peripheral Interface (SPI) communication technology, specifically to an SPI communication system and method between two microcontroller units (MCUs). Background Technology

[0002] SPI communication technology, proposed by Motorola, is a full-duplex, 4-wire synchronous serial peripheral interface that uses a master-slave mode. It first appeared in the MC68 series of microcontrollers. Due to its simple internal circuitry, ease of integration, standardized wiring, and high transmission speed, it is widely used in various MCUs, primarily for high-speed read / write operations with peripheral devices such as external FLASH memory and displays.

[0003] A traditional four-wire SPI communication bus includes: a clock line (SCLK), a chip select line (CS), a master transmit / slave receive line (MOSI), and a master receive / slave transmit line (MISO). In implementation, the master selects the desired slave device by pulling the chip select line low. Driven by the master clock, both devices communicate synchronously bidirectionally via shift registers. SPI was initially primarily used for reading and writing to slave peripherals by the MCU master. Because SPI communication speeds are much higher than TTL serial ports and I2C, it has gradually been expanded to communication between peer MCU processors.

[0004] However, the traditional four-wire SPI is not designed for peer-to-peer communication between MCU processors, as the two lack a channel to communicate their communication needs. This manifests in the slave device's inability to promptly inform the master of its communication requirements, relying solely on the master's continuous polling, which wastes significant MCU time, results in low communication efficiency, and poor real-time performance. Furthermore, the master cannot promptly inform the slave of its communication needs to wake it up or switch it to communication mode to prepare for data exchange. Forcibly initiating SPI communication by the master may lead to data loss.

[0005] For high-reliability applications, traditional SPI communication involves transmitting the CRC check results of both parties again in the original channel (MOSI and MISO lines) after completing the transmission of one data frame. When the original channel is untrusted, the transmission of the CRC check results is equally unreliable and the process is cumbersome.

[0006] Furthermore, SPI only specifies the physical layer protocol and lacks standardized upper-layer protocols such as the data link layer and application layer. Especially in dual-MCU processor communication scenarios, its transmission lacks a unified frame format, data flow control, CRC checksum acknowledgment, and retransmission mechanism. Summary of the Invention

[0007] This invention provides a dual-machine SPI communication system and method for implementing CRC response retransmission using time-division multiplexing handshake lines, and establishes a comprehensive general frame format specification.

[0008] To address the issues of high-frequency polling of slave communication status by the master in traditional SPI communication between dual MCU processors, which wastes MCU resources and reduces communication efficiency, as well as the cumbersome and unreliable process of transmitting CRC check response results in the original SPI channel, this invention adds two unidirectional handshake lines to the traditional four-wire SPI bus: handshake line 1 from slave to master and handshake line 2 from master to slave.

[0009] Before SPI frame communication begins, the handshake line functions to transmit communication request signals and communication response signals, which solves the inefficiency problem of traditional SPI communication relying on host polling.

[0010] Once SPI frame communication begins, the handshake function of the two handshake lines is complete, and their function switches to transmitting verification and acknowledgment signals. The system then uses these signals to determine whether to initiate retransmission within a specified time limit.

[0011] Compared to traditional methods that transmit verification response results from the SPI data channel, this method is more convenient and reliable, and the multiplexing of the handshake line function reduces the consumption of IO resources for the system.

[0012] To address the lack of a standardized frame format in traditional SPI communication, this invention establishes a comprehensive universal frame format with mechanisms such as flow control, CRC check retransmission selection, inverse code fast verification, loop counting, and error frame counting. It can adapt to a wider range of SPI communication needs and can be adapted to high reliability or high speed communication modes.

[0013] Specifically, before communication, the chip select line (CS) is at a high level. At this time, handshake line 1 and handshake line 2 represent handshake signals, and their initial state is low.

[0014] When the slave device needs to send information and is ready to receive information from the master device, the slave device pulls the handshake line 1 high to send a communication request signal to notify the master device. When the master device receives the rising edge of the handshake line 1, it generates an interrupt. After confirming that the high level is valid, it prepares to send and receive frame information. If the master device has no valid information to send, it prepares an empty frame with a standard frame structure. The frame format is detailed below. Then the master device pulls the chip select line (CS) low and sends the clock, and the master and slave devices start bidirectional communication.

[0015] When the master needs to send information and is ready to receive information from the slave, the master pulls the handshake line 2 high to send a communication request signal to notify the slave. When the slave receives the rising edge of the handshake line 2, it generates an interrupt. After confirming that the high level is valid, it prepares to send and receive frame information. If the slave has no valid information to send, it prepares an empty frame with a standard frame structure. Then the slave pulls the handshake line 1 high to send a communication response signal to the master. When the master receives the rising edge of the handshake line 1, it generates an interrupt. After confirming that the high level is valid, the master pulls the chip select line (CS) low and sends the clock. The master and slave then begin bidirectional communication.

[0016] In high-reliability communication applications, it is necessary to perform CRC checks and retransmission of transmitted and received data in case of errors.

[0017] Traditional SPI communication involves transmitting the CRC checksum response results of both parties again in the original channel (MOSI line and MISO line) after completing the transmission of a data frame.

[0018] The error rate of a channel being interfered with in a short period of time is similar. When the original channel is not trusted, the transmission of its CRC check response result is equally unreliable, and the transmission process is cumbersome.

[0019] Therefore, this invention uses a time-division multiplexing handshake line method to represent the handshake signal and the verification response signal in a time-division manner. This method overcomes the defects of traditional methods and has the advantages of high reliability, simple process and good real-time performance.

[0020] This invention specifies that: before SPI frame communication, the chip select line (CS) is at a high level, and the handshake line is initially at a low level. The effective high level of the two handshake lines represents the handshake signal between the master and slave. After the handshake is successful, the master pulls the chip select line (CS) low to start communication, at which point the handshake function is completed.

[0021] At this point, the system switches the function of the two handshake lines from transmitting handshake signals to transmitting verification response signals, and initializes the two handshake lines to a high level. Subsequently, a valid low level is used to indicate that the verification is correct.

[0022] After communication ends, the host pulls the chip select line (CS) high, and the system begins retransmission determination timing. The timing period should be greater than the sum of the CRC check calculation time (which takes the longest time for both the master and slave) and the time of any high-priority interrupts that may occur in the MCU.

[0023] The host and slave first perform a quick inverse code verification on the key bytes in the frame structure. After confirming that there are no errors, they then start CRC-32 check calculation for each valid data content. This invention recommends using hardware-accelerated CRC check calculation to improve CRC calculation efficiency.

[0024] If both handshake lines are pulled low to send a verification response signal, it means that the verification is successful, the verification function ends, the timing is canceled, and the function of the two handshake lines switches from transmitting the verification response signal back to transmitting the handshake signal. The system returns to the initial non-communication state.

[0025] If the inverse code fast verification fails, or if the handshake line remains high after the timeout period, it indicates that no verification response signal has been sent, the corresponding information verification is incorrect, and the system enters retransmission mode.

[0026] The retransmission decision occurs in the interrupt when the timer ends. As long as either or both of handshake line 1 and handshake line 2 are high, both the master and slave MCU processors need to retransmit the current frame.

[0027] During retransmission, the host pulls the chip select line (CS) low, transmits the clock, and keeps handshake line 1 and handshake line 2 at their current levels.

[0028] When the retransmission frame communication ends, the host pulls the chip select line (CS) high and starts the retransmission judgment timing again. At this time, the handshake line that was originally low level continues to remain low level, and the handshake line that was originally high level outputs a new high or low level according to the new verification result of the retransmission. This process is repeated until all are correct. The verification function ends, and the function of the two handshake lines is switched from transmitting the verification response signal to transmitting the handshake signal. The system returns to the non-communication state.

[0029] If the error persists after being retransmitted a specified number of times, the frame is discarded, and the system pulls both handshake lines low and switches its function from transmitting verification response signals back to transmitting handshake signals.

[0030] The frame format is configured with a loop counter to filter duplicate frames and an error frame count to determine the quality of system communication.

[0031] To address the lack of a standardized frame format in traditional SPI communication between dual MCU processors, this invention establishes a comprehensive and universal frame format. The specific frame format is as follows: Byte 1: Frame header, 1 byte in length. The general frame header is 0xAA, and the frame header is 0xCC when flow control is required. The second byte: Frame purpose, 1 byte in length, is used to define and distinguish the purpose of a frame; Bytes 3-4: Data segment length, 2 bytes in length, used to indicate the length of the valid data content; Bytes 5-8: These are the inverses of bytes 1-4 above, used for quick inverse verification; Bytes 9 to 8+n: Valid data content, length n bytes; if n=0, this item is not present. Bytes 9+n to 12+n: CRC-32 checksum, 4 bytes in length, used only for valid data content; Bytes 13+n~16+n: The one's complement of bytes 9+n~12+n, 4 bytes in length, used for fast verification of the one's complement of the CRC-32 check value; Byte 17+n: Cycle counter, 1 byte in length, which can be used to detect dropped frames and filter duplicate frames; Byte 18+n: Repeat byte 17+n or its inverse, 1 byte in length. When it is the repeat of byte 17+n, it indicates that the frame is used for high reliability communication mode, the valid data content needs to be checked by CRC-32, and it will be retransmitted after an error. When it is the inverse of byte 17+n, it indicates that the frame is used for high speed communication mode, and the valid data content does not need to be checked by CRC-32. Bytes 19+n to 20+n: Error frame count, 2 bytes in length, accumulates the count of received error frames and provides it to the sender to determine the quality of system communication.

[0032] The frame format includes corresponding inverse codes or simple repetitions for the frame header, frame purpose, data segment length, CRC-32 check value, and cycle count. The receiver can use this information to quickly verify the key content and improve reliability.

[0033] Using a combination of DMA and SPI for communication can significantly save MCU time. The system determines the appropriate DMA data transfer length m based on the average communication volume and the MCU's on-chip resources.

[0034] In a single SPI communication driven by DMA, the master and slave transmit m bytes. Each communication must contain the complete frame structure described above and the total length should not exceed m. Therefore, the length n of the effective data content in each frame should be less than or equal to m minus the 20 bytes occupied by the frame structure information.

[0035] If the amount of valid data to be transmitted is greater than m minus 20, it should be divided into multiple frames for transmission. When the frame length is less than m, the remaining space will be used to transmit invalid bytes. In particular, if n is zero, this frame is an empty frame with only 20 bytes of frame structure information.

[0036] When DMA is not used, the length of each SPI transmission is the longer frame length of the information sent by the master and slave.

[0037] To address the data flow control issue, this invention specifies that the general frame header is 0xAA. When one of the MCUs is time-constrained and unable to receive and process more data, it can modify its subsequent frame headers to 0xCC.

[0038] When the receiving MCU detects that the received frame header is 0xCC, it will pause sending new valid data frames and instead send empty frames with frame structure but no valid data content. Normal transmission will resume after receiving the 0xAA frame header again.

[0039] To meet the needs of high-reliability and high-speed communication, this invention offers different adaptation schemes for frame formats.

[0040] In high-reliability communication mode, the 18+n byte is set to be equal to the cyclic counter (17+n bytes) for identification. The CRC-32 check value in the frame format is valid, and the error retransmission process is as described above.

[0041] In high-speed communication mode, the 18+n byte is set as the inverse of the cyclic counter bit (byte 17+n) for identification. At this time, communication data is available by default, CRC-32 check is not performed, the retransmission mechanism is canceled, and arbitrary fixed content is written into the original check bits (bytes 9+n to 12+n) in the frame format. In this mode, after the host pulls up the chip select line (CS) at the end of communication, both the host and slave directly pull down their corresponding handshake lines to complete communication and restore the initial non-communication state. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the SPI circuit connection of the present invention.

[0043] Figure 2 This is a schematic diagram of the standard frame format specified in this invention.

[0044] Figure 3 This is a schematic diagram of the slave SPI communication process of the present invention.

[0045] Figure 4 This is a schematic diagram of the host SPI communication process of the present invention.

[0046] Figure 5 This is a schematic diagram showing the signal line level changes when the slave device initiates a communication request and successfully communicates.

[0047] Figure 6 This is a schematic diagram illustrating the signal line level changes when the host initiates a communication request and generates an error retransmission. Specific implementation methods

[0048] This invention has been successfully tested and verified on various commonly used MCU microcontrollers. The specific implementation is as follows.

[0049] like Figure 1 As shown, the hardware connections related to SPI communication in this invention consist of 6 lines. These are the traditional SPI clock line (SCLK), chip select line (CS), master transmit / slave receive line (MOSI), master receive / slave transmit line (MISO), and the newly added handshake line 1 (slave to master) and handshake line 2 (master to slave).

[0050] This invention uses time-division multiplexing for the handshake lines. Before the start of SPI frame communication, the handshake lines function to transmit communication request signals and communication response signals. After the start of SPI frame communication, the handshake function of the two handshake lines is completed, and their function switches to transmitting verification response signals. The system then determines whether to initiate retransmission based on these signals within a specified time limit.

[0051] Compared to traditional methods that transmit verification responses from the SPI data channel, this method is more convenient and reliable, and the multiplexing of the handshake line reduces the consumption of I / O resources for the system.

[0052] like Figure 2 As shown, this invention establishes a comprehensive universal frame format with mechanisms such as flow control, CRC check retransmission selection, inverse code fast verification, loop counting, and error frame counting, which can adapt to a wider range of SPI communication needs, such as high reliability or high speed communication modes.

[0053] To address the data flow control issue, this invention specifies that the general frame header is 0xAA. When one of the MCUs is time-constrained and unable to receive and process more data, it can modify its subsequent frame headers to 0xCC.

[0054] When the receiving MCU detects that the received frame header is 0xCC, it will pause sending new valid data frames and instead send empty frames with frame structure but no valid data content. Normal transmission will resume after receiving the 0xAA frame header again.

[0055] During transmission, using a combination of DMA and SPI for communication can significantly save MCU time. The system determines the appropriate DMA transmission data length m based on the average communication volume and the MCU's on-chip resources.

[0056] In a single SPI communication driven by DMA, the master and slave devices transfer m bytes. Each communication must include... Figure 2 The complete frame structure shown is not more than m bytes in total. Therefore, the length n of the effective data content in each frame should be less than or equal to m minus the 20 bytes occupied by the frame structure information.

[0057] If the amount of valid data to be transmitted is greater than m minus 20, it should be divided into multiple frames for transmission. When the frame length is less than m, the remaining space will be used to transmit invalid bytes. In particular, if n is zero, this frame is an empty frame with only 20 bytes of frame structure information.

[0058] When DMA is not used, the length of each SPI transmission is the longer frame length of the information sent by the master and slave.

[0059] To meet the needs of high-reliability and high-speed communication, this invention offers different adaptation schemes for frame formats.

[0060] In high-reliability communication mode, the 18+n byte is set to be equal to the cyclic counter (17+n bytes) for identification. The CRC-32 check value in the frame format is valid, and retransmission is initiated after an error.

[0061] In high-speed communication mode, the 18+n byte is set as the inverse of the cyclic counter bit (17+n bytes) for identification. At this time, communication data is available by default, CRC-32 check is not performed, the retransmission mechanism is canceled, and arbitrary fixed content is written into the original check bits (bytes 9+n to 12+n) in the frame format. In this mode, after the host pulls up the chip select line (CS) at the end of communication, both the host and slave directly pull down their corresponding handshake lines to complete communication and restore the initial non-communication state.

[0062] The following example illustrates this method, but it is not only applicable to the following instance; it can also be extended to other applications.

[0063] In engineering practice, the MCU that performs the main data processing is usually selected as the SPI communication master, and the MCU responsible for data acquisition or data transmission is selected as the SPI communication slave.

[0064] To achieve the main functions of this patent, the MCU needs to be configured as follows.

[0065] The chip select line (CS) slave input is configured as an externally triggered rising and falling edge interrupt input with an internal pull-up resistor (for slave MCUs that do not support chip select line interrupts, the chip select line can be connected in parallel to an interrupt-enabled IO input interface to replace it). The falling edge interrupt of the chip select line (CS) converts handshake line 1 from handshake function to verification and acknowledgment function, and the rising edge interrupt of the chip select line (CS) is used to start the retransmission determination timing.

[0066] The input terminals of handshake line 1 and handshake line 2 are configured as externally triggered rising and falling edge interrupt input ports with internal pull-down resistors. The rising edge interrupt and reliable high level together transmit the handshake signal, and the falling edge interrupt and reliable low level together transmit the verification response signal. If necessary, an LC filter can be connected to the handshake line to improve its anti-interference capability.

[0067] The chip select line (CS), handshake line 1, and handshake line 2 are configured as push-pull outputs to improve anti-interference capability. The initial level of the chip select line is high, and the initial level of handshake line 1 and handshake line 2 is low.

[0068] The SPI communication between the master and slave devices is configured as a DMA driver. The DMA data transfer length is reasonably configured based on the average system traffic and the on-chip resources of the master and slave devices. For the sake of convenience in the following description, the value is taken as 128 bytes.

[0069] Each of the master and slave devices is configured with a 128-byte transmit buffer and a 128-byte receive buffer. The transmit buffer is used to store the information frames that the master and slave devices will send to each other via SPI. The receive buffer is used to store the information frames that the master and slave devices receive from each other via SPI communication. Each DMA-driven SPI communication will transfer the 128-byte pairs of the master and slave devices' transmit buffers to the other device's 128-byte receive buffer.

[0070] The retransmission timing is set based on the CRC-32 checksum of the valid data content. Each SPI communication transmits 128 bytes. After deducting the 20 bytes occupied by the frame structure information, the maximum length of the valid data content is 108 bytes.

[0071] The retransmission determination timing is as follows: the master and slave calculate the time taken for 108 bytes of CRC-32 check respectively, add the time taken for their respective possible high-priority interrupts, take the longer time, and finally add 10% redundancy.

[0072] Based on the system's reliability requirements for transmitted data, the maximum number of retransmissions is determined, typically ranging from 3 to 5.

[0073] Where possible, it is recommended that the host and slave devices use the hardware CRC-32 accelerator in the MCU.

[0074] The following is combined Figure 3 , Figure 4 , Figure 5 The following is a detailed description of the implementation process. This describes the process by which the slave device initiates a communication request and successfully communicates.

[0075] After the master and slave are initialized, the chip select line (CS) is high when there is no communication. At this time, handshake line 1 and handshake line 2 represent handshake signals, and the initial level is low.

[0076] When the slave device needs to communicate with the master device, it frames the content to be sent and puts it into the transmit buffer. It then confirms that the information in its receive buffer has been processed and that it can receive new information. After that, it pulls high handshake 1 to send a communication request signal to the master device.

[0077] When the host receives the rising edge of handshake line 1 and generates an interrupt, it confirms that the high level is valid, that is, it confirms that it has received the communication request signal from the slave. The host also prepares for communication. If there is information to be sent, it frames it and puts it into its own transmit buffer. If not, it prepares an empty frame with only frame structure and confirms that the information in its receive buffer has been processed and it can receive new information.

[0078] After the master is ready, it pulls the chip select line (CS) low. At this time, the master pulls the handshake line 2 high. The slave confirms that the handshake line 1 is high in the interrupt generated by the falling edge of the chip select line (CS). The function of the handshake line is switched from transmitting the handshake signal to transmitting the verification response signal. At the same time, driven by the master clock and DMA, the SPI information transmission between the two parties is started.

[0079] After communication ends, the host pulls the chip select line (CS) high and starts the retransmission decision timing. The slave starts the retransmission decision timing in the interrupt generated by the rising edge of the chip select line (CS).

[0080] The master and slave first perform a quick inverse code verification on the key bytes in the frame structure. After confirming that there are no errors, they start CRC-32 check calculations for the valid data content. During this period, the status of the two handshake lines represents the respective check results of the master and slave.

[0081] If both handshake lines are pulled low to send a verification response signal, the master and slave devices will receive the falling edge of the other's handshake line, generate an interrupt, confirm that the low level is valid, which means that both parties have verified correctly, the verification function ends, each cancels the retransmission judgment timer, the function of the two handshake lines switches back from verification response to handshake signal, and the system returns to the initial non-communication state.

[0082] If the inverse code fast verification fails, or if the handshake line remains high after the timeout period, it indicates that no verification response signal has been sent, the corresponding information verification is incorrect, and the system enters retransmission mode.

[0083] like Figure 5 As shown in this example, both the master and slave devices detected that the transmission was correct, so they pulled handshake line 1 and handshake line 2 low respectively. At this time, the states of the handshake line and chip select line returned to the initial non-communication state, and the next handshake communication transmission process can proceed.

[0084] The following is combined Figure 3 , Figure 4 , Figure 6 The following describes the specific implementation process. This is the process of the host initiating a communication request and generating an error retransmission.

[0085] After the master and slave are initialized, the chip select line (CS) is high when there is no communication. At this time, handshake line 1 and handshake line 2 represent handshake signals, with an initial low level. When the master needs to communicate with the slave, the master frames the content to be sent and puts it into the transmit buffer. It also confirms that the information in its receive buffer has been processed and that it can receive new information. The master then pulls handshake line 2 high to send a communication request signal to the slave.

[0086] When the slave device receives the rising edge of handshake line 2 and generates an interrupt, it confirms that the high level is valid, that is, it confirms that it has received the communication request signal from the master. After that, the slave device also prepares for communication. If there is information to be sent, it will frame it and put it into its own transmit buffer. If not, it will prepare an empty frame with only frame structure and confirm that the information in its receive buffer has been processed and it can receive new information.

[0087] After the slave device is ready, it pulls the handshake line 1 high to send a communication response signal to the master device. The master device receives the rising edge of the handshake line 1 and generates an interrupt to confirm that the high level is valid, that is, to confirm that it has received the communication response signal from the slave device. Then, it pulls the chip select line (CS) low and confirms that the handshake line 2 is high.

[0088] When the slave device receives an interrupt generated by the falling edge of the chip select line (CS), it confirms that handshake line 1 is high. The function of the two handshake lines is switched from transmitting handshake signals to transmitting verification and acknowledgment signals. At the same time, driven by the master clock, SPI enables information exchange between the two parties.

[0089] After communication ends, the host pulls the chip select line (CS) high and starts the retransmission decision timing. The slave starts the retransmission decision timing in the interrupt generated by the rising edge of the chip select line (CS).

[0090] The master and slave first perform a quick inverse code verification on the key bytes in the frame structure. After confirming that there are no errors, they start CRC-32 check calculations for the valid data content. During this period, the status of the two handshake lines represents the respective check results of the master and slave.

[0091] If both handshake lines are pulled low to send a verification response signal, the master and slave devices will receive the falling edge of the other's handshake line, generate an interrupt, confirm that the low level is valid, which means that both parties have verified correctly, the verification function ends, each cancels the retransmission judgment timer, the function of the two handshake lines switches back from verification response to handshake signal, and the system returns to the initial non-communication state.

[0092] If the inverse code fast verification fails, or if the handshake line remains high after the timeout period, it indicates that no verification response signal has been sent, the corresponding information verification is incorrect, and the system enters retransmission mode.

[0093] like Figure 6 As shown, in this example, after the host verifies that the received content is correct, it pulls the handshake line 2 low; after the slave verifies that the received content is incorrect, it keeps the handshake line 1 high.

[0094] Once the timeout period is reached, the master and slave devices detect the need for retransmission, maintain their respective handshake line levels, and the master pulls the chip select line (CS) low to enable retransmission. During retransmission, in order to align the data, both devices must retransmit their complete current frame.

[0095] After the retransmission ends, the master and slave devices re-enter the retransmission judgment timing and verification process until the retransmission is successful. If the retransmission still fails after the specified number of times, the system discards the frame content, handshake line 1 and handshake line 2 are reset to the initial low level, the function is switched back to transmitting handshake signals, and the system returns to the initial non-communication state. During the retransmission process, the loop counter is used to filter duplicate frames.

[0096] like Figure 6 As shown, this example demonstrates the case where the second retransmission is successful.

[0097] After the retransmission is completed, the host pulls the chip select line (CS) high and restarts the retransmission judgment timer. At this time, handshake line 2 remains at a low level, while handshake line 1 is set to a low level by the slave, indicating that the verification was successful and a verification response signal is sent.

[0098] At this time, both handshake line 1 and handshake line 2 are at low level, and chip select line (CS) is at high level. Handshake line 1 and handshake line 2 resume their function of transmitting handshake signals, and the system returns to the initial non-communication state.

[0099] Using DMA to drive SPI is the preferred option of this invention. However, in some application scenarios, MCU resources are scarce and there is no available DMA channel. Therefore, this invention also supports non-DMA driven SPI communication.

[0100] At this point, the MCU directly reads and writes the corresponding transceiver registers byte by byte to complete the SPI data transmission.

[0101] The specific process is as follows: the host MCU first drives the clock and transmits the first 8 bytes of the frame. After the host obtains the first 8 bytes from the slave, it performs a quick inverse code verification of the frame header, frame purpose, and data segment length. If the verification is correct, the host selects the longer data segment from the master and slave, and adds the fixed 20 bytes of the frame structure as the transmission length. After the transmission is completed, the chip select line (CS) is pulled high. Other processes are the same as in the DMA method.

[0102] If the above inverse code verification fails, simply pull the chip select line (CS) high to end the communication; the rest of the process is the same as the DMA method.

[0103] This invention can also have many other implementation examples. The multiplexing of handshake lines and frame formats can also be applied to serial ports. All equivalent substitutions and modifications made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A dual-machine SPI communication method using time-division multiplexing handshake lines to implement CRC response retransmission, characterized in that, The SPI bus adds two unidirectional handshake lines to the traditional four-wire SPI bus: handshake line 1 from slave to master and handshake line 2 from master to slave. Its time-division characteristic is as follows: Before SPI frame communication begins, the handshake line functions to transmit communication request and response signals. After SPI frame communication begins, the handshake line switches to transmitting verification response signals, and the system uses these signals to determine whether to initiate retransmission within a specified time limit. This method establishes a comprehensive and universal frame format with mechanisms such as flow control, CRC check retransmission selection, inverse code fast verification, loop counting, and error frame counting, which can adapt to a wider range of SPI communication needs, such as high reliability or high-speed communication modes.

2. The dual-machine SPI communication method for implementing CRC response retransmission using time-division multiplexing handshake lines according to claim 1, characterized in that, Includes the following steps: S1. Before SPI frame communication, the chip select line (CS) is high. At this time, handshake line 1 and handshake line 2 represent handshake signals, and the initial state is low. If the slave device needs to send information and is ready to receive information from the master device, jump to step S2. If the master device needs to send information and is ready to receive information from the slave device, jump to step S3. S2. When the slave device needs to send information and is ready to receive information from the master device, the slave device pulls the handshake line 1 high to indicate that it is sending a communication request signal to notify the master device; after receiving the communication request signal, the master device prepares to send and receive frame information and jumps to step S4. S3. When the host has a need to send information and is ready to receive information from the slave, the host pulls the handshake line 2 high to indicate that it is sending a communication request signal to notify the slave; after receiving the communication request signal, the slave prepares to send and receive frame information, and pulls the handshake line 1 high to indicate that it is sending a communication response signal to respond to the host; after the host receives the communication response signal, it jumps to step S4. S4. The master pulls the chip select line (CS) low. At this time, the handshake function of the two handshake lines is completed. Its function is switched to verification and response and initialized to high level. The master sends the clock and the master and slave perform bidirectional SPI frame communication. S5. After the SPI frame communication ends, the master pulls the chip select line (CS) high, the system starts the retransmission judgment timer, the master and slave first perform a quick inverse code verification on the key bytes in the frame structure, and after confirming that there are no errors, they start CRC-32 check calculation for the valid data content respectively; if the CRC check results of both parties are correct within the specified time, they pull the corresponding handshake line low to indicate that they are sending a check response signal. The check ends, the timer is canceled, and the function of the two handshake lines is switched from transmitting the check response signal to transmitting the handshake signal. The system returns to the initial non-communication state and jumps to step S1. If the reverse code fast verification fails or the CRC check fails after the timeout period, and the corresponding handshake line is not pulled low to send a verification response signal, and the number of retransmissions for this frame has not reached the specified limit, the system enters retransmission mode and jumps to step S6; if the error still occurs after the specified number of retransmissions, the frame is abandoned, the system pulls both handshake lines low and switches its function from transmitting the verification response signal back to transmitting the handshake signal, the system returns to the initial non-communication state, and jumps to step S1; S6. During retransmission, the host pulls the chip select line (CS) low, transmits the clock, and keeps handshake line 1 and handshake line 2 at their current levels. When the retransmission frame communication ends, proceed to step S5 for another verification and determination.

3. A dual-machine SPI communication method for implementing CRC response retransmission using time-division multiplexing handshake lines according to claims 1 and 2, characterized in that, The signal contents of the handshake line at different time periods are as follows: Communication request signal: When SPI frame communication has not started, the chip select line (CS) is high and the two handshake lines are initially low. The signal is the first valid high level that appears in the two handshake lines, which means that the signal sender has a need to send information and is ready to receive information from the other party. Communication response signal: When SPI frame communication has not started, the chip select line (CS) is high. The signal is a valid high level sent by handshake line 1 when handshake line 2 is high. It is the handshake response of the slave to the master, indicating that the slave has received the communication request signal from the master and is ready to send and receive information. Verification acknowledgment signal: At the start of SPI frame communication, the chip select line (CS) is pulled low, and the handshake function of the two handshake lines is completed. Its function switches to transmitting the verification acknowledgment signal and is initialized to a high level. At the end of SPI frame communication, the chip select line (CS) is pulled high. This signal is the effective low level sent by each of the two handshake lines thereafter, which respectively represents that their received information has been verified correctly. If the verification fails, the corresponding handshake line of the sender remains at a high level and this signal is not sent.

4. A dual-machine SPI communication method for implementing CRC response retransmission using time-division multiplexing handshake lines according to claims 1 and 2, characterized in that: After the SPI frame communication ends and the chip select line (CS) is pulled high, the timing of the retransmission determination in step S5 should be greater than the maximum value of the time required for the master and slave to perform CRC-32 verification respectively and the total time of possible high-priority interrupts of the MCU.

5. A dual-machine SPI communication method for implementing CRC response retransmission using time-division multiplexing handshake lines according to claims 1 and 2, characterized in that, The comprehensive, universal frame format provided by this method is as follows: Byte 1: Frame header, 1 byte in length. The general frame header is 0xAA, and the frame header is 0xCC when flow control is required. The second byte: Frame purpose, 1 byte in length, is used to define and distinguish the purpose of a frame; Bytes 3-4: Data segment length, 2 bytes in length, used to indicate the length of the valid data content; Bytes 5-8: These are the inverses of bytes 1-4 above, used for quick inverse verification; Bytes 9 to 8+n: Valid data content, length n bytes; if n=0, this item is not present. Bytes 9+n to 12+n: CRC-32 checksum, 4 bytes in length, used only for valid data content; Bytes 13+n~16+n: The one's complement of bytes 9+n~12+n, 4 bytes in length, used for fast verification of the one's complement of the CRC-32 check value; Byte 17+n: Cycle counter, 1 byte in length, which can be used to detect dropped frames and filter duplicate frames; Byte 18+n: Repeat byte 17+n or its inverse, 1 byte in length. When it is the repeat of byte 17+n, it indicates that the frame is used for high reliability communication mode, the valid data content needs to be checked by CRC-32, and it will be retransmitted after an error. When it is the inverse of byte 17+n, it indicates that the frame is used for high speed communication mode, and the valid data content does not need to be checked by CRC-32. Bytes 19+n to 20+n: Error frame count, 2 bytes in length, accumulates the count of received error frames and provides it to the sender to determine the quality of system communication.

6. The frame format in the dual-machine SPI communication method for implementing CRC response retransmission using a time-division multiplexed handshake line according to claim 5, characterized in that, The content of a single SPI frame communication, that is, all the content transmitted between the master and slave when the chip select line (CS) is low, must have the complete frame format described in claim 5. If the length of the effective data content n=0, this frame is an empty frame with only 20 bytes of frame structure information.

7. The frame format in the dual-machine SPI communication method for implementing CRC response retransmission using a time-division multiplexed handshake line according to claim 5, characterized in that, This method defines two different communication modes: a high-reliability communication mode and a high-speed communication mode. The high-reliability communication mode is identified by the 18+n byte being equal to the cycle counter (17+n bytes). The CRC-32 checksum in the frame format is valid, and the retransmission process after an error is as described in claim 2. The high-speed communication mode is identified by the 18+n byte being the inverse of the cycle counter (17+n bytes). In this mode, communication data is available by default, and the CRC-32 checksum is not performed, thus canceling the retransmission mechanism to improve transmission efficiency. The original checksum (bytes 9+n to 12+n) in the frame format is written with arbitrary fixed content. In this mode, after the host pulls up the chip select line (CS line) at the end of communication, both the host and slave directly pull down their corresponding handshake lines to complete communication and restore the initial non-communication state.

8. The frame format in the dual-machine SPI communication method for implementing CRC response retransmission using a time-division multiplexed handshake line according to claim 5, characterized in that: The data flow control function uses frame headers as identifiers. The standard frame header is 0xAA. When one of the MCUs is time-constrained and unable to receive and process more data, it can modify its subsequent frame headers to 0xCC. Upon receiving a frame header of 0xCC, the receiving MCU will pause sending new valid data frames and instead send empty frames with a frame format but no valid data content. Normal transmission will resume once a 0xAA frame header is received again.

9. The frame format in the dual-machine SPI communication method for implementing CRC response retransmission using a time-division multiplexed handshake line according to claim 5, characterized in that: When the sender has no valid data content, it will send an empty frame, which contains all frame structure information except for the valid data content. This frame is 20 bytes long.

10. The frame format in the dual-machine SPI communication method for implementing CRC response retransmission using a time-division multiplexed handshake line according to claim 5, characterized in that: The frame format includes corresponding inverse codes or simple repetitions for the frame header, frame purpose, data segment length, CRC-32 check value, and cycle count. The receiver can use this information to quickly verify the key content and improve reliability.

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