A method and apparatus for updating a multi-branch instruction predictor

Abstract

The present disclosure provides a multi-branch instruction predictor updating method and device, which can enable a processor to complete branch predictor training through a single updating path in the case of concurrent execution of multiple branch instructions, and ensure that a prediction error branch can finally submit training information by performing updating permission arbitration on branch instructions and retransmission processing on branch instructions that have not obtained updating permission but have prediction errors, thereby improving the integrity of branch predictor training information while reducing hardware complexity and timing pressure, and taking into account processor performance, area and power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of processor technology, and more specifically, to a method and apparatus for updating a multi-branch instruction predictor. Background Technology

[0002] In modern high-performance processors, pipelines typically need to fetch subsequent instructions before the execution result is fully determined to improve instruction throughput. For control transfer instructions such as conditional branches and indirect branches, waiting for the branch instruction to actually complete before determining the subsequent instruction fetch path will cause pipeline stalls, reducing the overall processor execution efficiency. Therefore, branch predictors are widely used to predict the branch direction or branch target address before the branch instruction is executed, thereby assisting the instruction fetch unit in fetching subsequent instructions in advance.

[0003] As processor parallelism continues to increase, superscalar out-of-order execution processors are typically configured with multiple branch execution units, allowing multiple branch instructions to be executed simultaneously within a single processing cycle. Correspondingly, the execution results of multiple branch instructions may return simultaneously within the same cycle, all requiring use for training or correcting the branch predictor. If the branch predictor needs to receive and process multiple update requests within the same cycle, its internal memory structure and update path must support multiple write ports or multi-way parallel updates.

[0004] In existing technologies, to handle concurrent update requests for multiple branch instructions, one approach is to set up a multi-port update structure in the branch predictor, enabling the predictor to respond to multiple update operations within the same cycle. However, multi-port storage structures significantly increase hardware area and power consumption, and may lengthen the critical path, affecting processor clock speed. Another approach is to set up a buffer queue to temporarily store multiple update requests in a buffer and replay the updates sequentially in subsequent cycles. However, this approach introduces additional update latency, causing the branch predictor's training information to lag, affecting the predictor's convergence speed, and may also increase queue management complexity in high-concurrency scenarios. Summary of the Invention

[0005] This disclosure provides at least one method and apparatus for updating a multi-branch instruction predictor. This method enables the processor to complete branch predictor training through a single update path even when multiple branch instructions are executed concurrently. By arbitrating update permissions for branch instructions and re-issuing branch instructions that have not obtained update permissions but have made prediction errors, it ensures that branches with prediction errors can eventually submit training information. This reduces hardware complexity and timing pressure while improving the integrity of branch predictor training information, taking into account processor performance, area, and power consumption.

[0006] This disclosure provides a multi-branch instruction predictor update method applied to a processor with multiple branch execution units. The processor updates the branch predictor through a single update path. The method includes:

[0007] Within a single processing cycle, multiple branch instructions to be executed are acquired;

[0008] An update permission arbitration is performed on the plurality of branch instructions to be launched and executed, a target branch instruction is determined from the plurality of branch instructions to be launched and executed, and an update flag is configured for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path.

[0009] The system executes the multiple branch instructions to be executed and obtains the actual execution result and prediction result corresponding to each branch instruction.

[0010] After the branch instruction with the update flag is executed, the branch predictor is updated through the single update path according to the actual execution result and the prediction result of the branch instruction.

[0011] If a prediction error occurs in a branch instruction without the update flag, the branch instruction is marked as a resend branch instruction, and the branch instruction is re-emitted.

[0012] When the retransmission branch instruction is re-issued, the retransmission branch instruction is given the update flag, and after the retransmission branch instruction completes retransmission execution, the branch predictor is updated through the single update path.

[0013] In one optional implementation, updating the permission arbitration of the plurality of branch instructions to be executed specifically includes:

[0014] Identify whether there is a retransmitted branch instruction among the multiple branch instructions to be executed;

[0015] If the resend branch instruction exists, the resend branch instruction is preferentially identified as the target branch instruction, and the update flag is configured for the resend branch instruction.

[0016] In one optional implementation, updating the permission arbitration of the plurality of branch instructions to be executed specifically includes:

[0017] Obtain at least one arbitration reference information from each branch instruction: branch type, prediction confidence, and historical prediction behavior;

[0018] The update priority of each branch instruction is determined based on the arbitration reference information;

[0019] Based on the update priority, the target branch instruction is determined from the plurality of branch instructions to be executed.

[0020] In one optional implementation, determining the update priority of each branch instruction based on the arbitration reference information specifically includes:

[0021] If the branch instruction is a conditional branch instruction and the corresponding prediction confidence is lower than the preset confidence threshold, increase the update priority of the branch instruction.

[0022] And / or, if the arbitration reference information of multiple branch instructions meets the preset similarity conditions, the target branch instruction is determined from the multiple branch instructions in a polling or random manner.

[0023] In an optional implementation, after issuing and executing the plurality of branch instructions to be issued and executing, and obtaining the actual execution result and prediction result corresponding to each branch instruction, the method further includes:

[0024] If no prediction error occurs in a branch instruction without the update flag, the branch instruction is prohibited from updating the branch predictor through the single update path, and the branch instruction is allowed to exit the instruction queue.

[0025] In one optional implementation, if a prediction error occurs in a branch instruction without the update flag, the branch instruction is marked as a resend branch instruction, and the branch instruction is re-emitted, specifically including:

[0026] When the actual execution result of a branch instruction without the update flag is inconsistent with the predicted result, a prediction error event is generated;

[0027] In response to the predicted error event, the control field of the branch instruction is set to resend status, or the branch instruction is recorded as a resend type in the reserved station entry;

[0028] Based on the retransmission status or the retransmission type, the branch instruction is resent into the transmission queue.

[0029] In one optional implementation, when the retransmission branch instruction is re-emitted, the retransmission branch instruction receives the update flag, specifically including:

[0030] When the resend branch instruction enters the update permission arbitration process, the update flag is forcibly assigned to the resend branch instruction based on its resend attribute, so that the resend branch instruction has the permission to update the branch predictor after resend execution.

[0031] In one optional implementation, the re-execution of the re-sent branch instruction is used to submit branch predictor training information;

[0032] During the re-execution of the re-branch instruction, write-back operations on the destination register are prohibited, or execution actions related to writing back the data calculation results are skipped.

[0033] In one optional implementation, updating the branch predictor via the single update path specifically includes:

[0034] Training information is generated based on at least one of the actual execution result of the branch instruction, the prediction result, the branch address, and the branch target address.

[0035] The training information is submitted to the branch predictor through the single update path;

[0036] Based on the training information, update at least one of the following in the branch predictor: branch target buffer, mode history table, TAGE prediction structure, perceptron prediction structure, or dual-mode prediction structure.

[0037] This disclosure also provides a multi-branch instruction predictor update apparatus, applied to a processor having multiple branch execution units, wherein the processor updates the branch predictor through a single update path, and the method includes:

[0038] The branch instruction scheduling module is used to acquire multiple branch instructions to be issued and executed within a processing cycle;

[0039] An update permission arbitration module is used to perform update permission arbitration on the plurality of branch instructions to be launched and executed, determine the target branch instruction from the plurality of branch instructions to be launched and executed, and configure an update flag for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path.

[0040] The branch execution module is used to issue and execute the multiple branch instructions to be issued and executed, and to obtain the actual execution result and prediction result corresponding to each branch instruction;

[0041] The prediction result comparison module is used to update the branch predictor through the single update path after the branch instruction with the update flag has been executed, based on the actual execution result and the prediction result of the branch instruction.

[0042] The retransmission control module is used to mark a branch instruction as a retransmission branch instruction and trigger the retransmission of the branch instruction when a prediction error occurs in a branch instruction without the update flag.

[0043] The branch predictor update module is used to enable the retransmitted branch instruction to obtain the update flag when the retransmitted branch instruction is re-issued, and to update the branch predictor through the single update path after the retransmitted branch instruction has completed retransmission execution.

[0044] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the above-described multi-branch instruction predictor update method, or any possible implementation of the above-described multi-branch instruction predictor update method, are performed.

[0045] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the multi-branch instruction predictor update method described above, or any possible implementation of the multi-branch instruction predictor update method described above.

[0046] This disclosure also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-described multi-branch instruction predictor update method, or the steps in any possible implementation of the above-described multi-branch instruction predictor update method.

[0047] The multi-branch instruction predictor update method and apparatus provided in this disclosure enable the processor to complete branch predictor training through a single update path even when multiple branch instructions are executed concurrently. By arbitrating update permissions for branch instructions and re-issuing branch instructions that have not obtained update permissions but have made prediction errors, it is ensured that branches with prediction errors can eventually submit training information. This reduces hardware complexity and timing pressure while improving the integrity of branch predictor training information, taking into account processor performance, area and power consumption.

[0048] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0050] Figure 1 A flowchart of a multi-branch instruction predictor update method provided in an embodiment of this disclosure is shown;

[0051] Figure 2 A flowchart illustrating the workflow of a multi-branch instruction predictor update method provided in an embodiment of this disclosure is shown.

[0052] Figure 3 A schematic diagram of a multi-branch instruction predictor update apparatus provided in an embodiment of this disclosure is shown;

[0053] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0055] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0056] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0057] Research has revealed that in existing technologies, to handle concurrent update requests for multiple branch instructions, one approach is to set up a multi-port update structure in the branch predictor, enabling it to respond to multiple update operations within the same cycle. However, multi-port storage structures significantly increase hardware area and power consumption, and may lengthen the critical path, affecting processor clock speed. Another approach is to set up a buffer queue to temporarily store multiple update requests in a buffer and replay them sequentially in subsequent cycles. However, this method introduces additional update latency, causing the branch predictor's training information to lag, affecting the predictor's convergence speed, and may also increase queue management complexity in high-concurrency scenarios.

[0058] Based on the above research, this disclosure provides a multi-branch instruction predictor update method and apparatus, which enables the processor to complete branch predictor training through a single update path even when multiple branch instructions are executed concurrently. By arbitrating the update rights of branch instructions and re-issuing branch instructions that have not obtained update rights but have made prediction errors, it is ensured that the branches with prediction errors can eventually submit training information. This reduces hardware complexity and timing pressure while improving the integrity of branch predictor training information, taking into account processor performance, area and power consumption.

[0059] To facilitate understanding of this embodiment, a detailed description of the multi-branch instruction predictor update method disclosed in this disclosure is provided first. The execution entity of the multi-branch instruction predictor update method provided in this disclosure is generally a computer device with certain computing capabilities. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, this multi-branch instruction predictor update method can be implemented by the processor calling computer-readable instructions stored in memory.

[0060] See Figure 1The diagram shows a flowchart of a multi-branch instruction predictor update method provided in this embodiment of the present disclosure. The method is applied to a processor with multiple branch execution units. The processor updates the branch predictor through a single update path. The method includes steps S101 to S106, wherein:

[0061] S101: Obtain multiple branch instructions to be executed within a processing cycle.

[0062] The multi-branch instruction predictor update method provided in this application can be applied to processors with multiple branch execution units. This processor can be a superscalar out-of-order execution processor or other processor cores with multi-issue and multi-branch execution capabilities. The processor may include an instruction fetch module, a decoding module, a renaming module, a dispatch module, an issue module, an execution module, a memory access module, a reordering module, and a branch prediction module. The branch prediction module provides branch direction prediction results and / or branch target address prediction results before the actual execution of the branch instruction is completed. The issue module sends instructions that meet the issue conditions to the corresponding execution unit. The execution module can be configured with multiple branch execution units to support the concurrent issuance or parallel execution of multiple branch instructions within the same processing cycle.

[0063] In practical implementation, within a single processing cycle, the processor can retrieve multiple branch instructions to be issued and executed from the issue queue, reserve station, scheduling queue, or other instruction scheduling structures used to temporarily store instructions to be executed. This processing cycle can be a single clock cycle or a control cycle within the processor used for instruction scheduling, issue control, or update arbitration. The multiple branch instructions to be issued and executed can include at least one of conditional branch instructions, unconditional branch instructions, indirect branch instructions, call instructions, and return instructions; the specific branch instruction type can be determined based on the processor's instruction set architecture.

[0064] In practical implementation, the issue module or branch instruction scheduling module can identify branch instructions that meet the issue conditions within the current processing cycle based on the opcode, decoding result, control flow attributes, execution port type, or branch prediction information of each branch instruction, and treat the identified multiple branch instructions as multiple branch instructions to be issued and executed. Meeting the issue conditions may include: the source operands on which the branch instruction depends are ready, the corresponding branch execution unit has available execution resources, the branch instruction has not been pipelined cleaned up, the queue entry containing the branch instruction is valid, or the branch instruction meets the issue conditions of out-of-order scheduling logic.

[0065] In one example, the processor has two branch execution units. When two branch instructions that meet the launch conditions exist simultaneously in the launch queue, the launch module can launch the two branch instructions to their respective branch execution units within the same processing cycle. Since both branch instructions may produce actual execution results for training the branch predictor after execution, these two branch instructions need to be included in the same update permission arbitration process during or before and after launch to determine which branch instruction can update the branch predictor through a single update path in the current cycle or after this execution.

[0066] In another example, the processor may also have three or more branch execution units. When there are three or more branch instructions that meet the issue conditions within a processing cycle, the branch instruction scheduling module can simultaneously acquire these three or more branch instructions and execute them as branch instructions to be issued in the same batch for subsequent processing. Therefore, the method of this application does not limit the specific number of branch execution units and can be applied to processor architectures with two, three, or more branch execution units.

[0067] Furthermore, the branch instructions to be launched and executed may also include branch instructions for initial launch and retransmission branch instructions. A branch instruction for initial launch refers to a branch instruction that has not yet re-entered the launch process due to a prediction error and lack of update permission; a retransmission branch instruction refers to a branch instruction that was marked as retransmitted and re-entered into the launch queue because a prediction error occurred during previous execution but no update flag was obtained. When the branch instruction scheduling module obtains multiple branch instructions to be launched and executed, it can simultaneously read the instruction control field corresponding to each branch instruction to determine whether each branch instruction carries a retransmission flag, an update request flag, or other flag information indicating the instruction status.

[0068] The retransmission flag indicates whether the corresponding branch instruction is a retransmission branch instruction, while the update request flag indicates whether the corresponding branch instruction needs permission to update the branch predictor. By simultaneously acquiring the above flag information when acquiring multiple branch instructions to be executed, the subsequent update permission arbitration process can identify retransmission branch instructions and prioritize their processing when they exist. This ensures that branch instructions that were predicted incorrectly but failed to update the branch predictor previously can get an update opportunity during the retransmission process.

[0069] In some implementations, the branch instruction scheduling module can generate a candidate branch instruction set within each processing cycle. This candidate branch instruction set includes branch instructions that can be issued to each branch execution unit within the current processing cycle. Subsequently, the processor can perform update permission arbitration based on this candidate branch instruction set. By first acquiring multiple branch instructions to be issued and then uniformly arbitrating these multiple branch instructions, it is possible to avoid multiple branch execution units independently submitting update requests to the branch predictor, thereby providing a basis for subsequently updating the branch predictor using a single update path.

[0070] S102. Perform update permission arbitration on the plurality of branch instructions to be launched and executed, determine the target branch instruction from the plurality of branch instructions to be launched and executed, and configure an update flag for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path.

[0071] In practical implementation, after acquiring multiple branch instructions to be executed, the processor arbitrates update permissions among these instructions, determines the target branch instruction, and configures an update flag for it. The update flag indicates that the corresponding branch instruction has the permission to update the branch predictor through a single update path. Therefore, even if multiple branch instructions are executed simultaneously or have update requirements within a processing cycle, only the target branch instruction with the update flag is allowed to submit an update request to the branch predictor after this execution, thus preventing multiple branch instructions from simultaneously occupying the branch predictor's update path.

[0072] In its implementation, update permission arbitration can be executed by the update flag arbitration logic set in the branch instruction scheduling module, or by a separate update permission arbitration module. The update permission arbitration module receives a set of candidate branch instructions within the current processing cycle and reads information such as the instruction identifier, branch type, prediction confidence level, historical prediction behavior, whether it is a retransmission branch instruction, and whether it has an update requirement for each candidate branch instruction. Subsequently, according to preset arbitration rules, the update permission arbitration module selects a branch instruction from the candidate branch instruction set as the target branch instruction and writes the update flag into the instruction control field, reserved station entry, launch queue entry, or control information associated with the target branch instruction.

[0073] The update flag can be a single flag in the instruction control field or a status value in a multi-bit status field. For example, a `needs_update` flag can be set in the instruction control field. When the `needs_update` flag is set, it indicates that the corresponding branch instruction has the permission to update the branch predictor; when the `needs_update` flag is not set, it indicates that the corresponding branch instruction does not have the permission to update the branch predictor through a single update path after this execution. Alternatively, the update flag field can record whether the corresponding branch instruction is the target branch instruction selected by arbitration in the current processing cycle. This update flag can enter the execution phase along with the branch instruction and serve as the control basis for whether to allow an update request to be initiated to the branch predictor after the branch instruction is executed.

[0074] In some embodiments, the update permission arbitration module prioritizes identifying whether there are retransmitted branch instructions among multiple branch instructions to be launched and executed. A retransmitted branch instruction refers to a branch instruction that experienced a prediction error during previous execution but did not receive an update flag, and is therefore resent to the launch queue. When a retransmitted branch instruction exists among multiple branch instructions to be launched and executed, the update permission arbitration module prioritizes identifying the retransmitted branch instruction as the target branch instruction and configures an update flag for it.

[0075] In some implementations, the `is_replay` flag can be set in the instruction control field corresponding to the branch instruction, or the retransmission status can be recorded in the reserved station entry. When a branch instruction is resent to the launch queue due to a prediction error and without receiving an update flag, the retransmission control module sets the `is_replay` flag of the branch instruction or marks the reserved station entry of the branch instruction as a retransmission type. When the update permission arbitration module obtains the candidate branch instruction set again, it reads the `is_replay` flag or retransmission type information and forcibly assigns an update flag to the branch instruction based on the retransmission attribute. Thus, retransmitted branch instructions can preferentially pass arbitration when retransmitted, ensuring that the branch predictor can be updated through a single update path after the retransmission is completed.

[0076] In other embodiments, when there are no retransmission branch instructions among multiple branch instructions to be executed, the update permission arbitration module can determine the update priority of each branch instruction based on at least one of branch type, prediction confidence, and historical prediction behavior, and determine the target branch instruction based on the update priority. The branch type may include conditional branches, unconditional branches, indirect branches, call branches, or return branches, etc. The prediction confidence can be output by the branch predictor or determined based on information such as static weak branch criteria, dynamic confidence count, historical prediction stability, and the number of historical prediction errors. The historical prediction behavior may include the number of correct predictions, the number of incorrect predictions, changes in jump direction, and changes in target address of the corresponding branch instruction or corresponding branch address during historical execution.

[0077] For example, when a branch instruction is a conditional branch instruction and the prediction confidence corresponding to that conditional branch instruction is lower than a preset confidence threshold, the update permission arbitration module can increase the update priority of that conditional branch instruction and prioritize its identification as the target branch instruction. Since low-confidence conditional branches are more likely to affect the accuracy of subsequent predictions, prioritizing the configuration of update flags for such branch instructions allows the branch predictor to obtain more valuable training information in a timely manner, thereby improving the convergence speed and prediction accuracy of the predictor.

[0078] For example, when multiple branch instructions have the same branch type, similar prediction confidence, or similar historical prediction behavior, the update permission arbitration module can select a target branch instruction from among the multiple branch instructions using a round-robin method. This round-robin method can select instructions sequentially based on branch execution unit number, launch queue position, reserved station entry number, or the order in which branch instructions entered the queue, to avoid long-term bias towards branch instructions from a particular branch execution unit or queue position. Alternatively, the update permission arbitration module can also select a target branch instruction from among the multiple branch instructions using a random or pseudo-random method to reduce selection bias caused by fixed priorities.

[0079] In a specific example, there are two branch instructions to be issued and executed simultaneously within the current processing cycle: the first branch instruction and the second branch instruction. The update permission arbitration module first determines whether the first branch instruction and the second branch instruction are reissued branch instructions. If the first branch instruction is a reissued branch instruction and the second branch instruction is a branch instruction issued for the first time, the update permission arbitration module identifies the first branch instruction as the target branch instruction and configures an update flag for it. If neither is a reissued branch instruction, the update permission arbitration module can further compare their branch types and prediction confidence; when the first branch instruction is a low-confidence conditional branch and the second branch instruction is a branch instruction with high prediction confidence, the first branch instruction can be identified as the target branch instruction.

[0080] In another specific example, there are three branch instructions to be executed simultaneously within the current processing cycle, and none of these three branch instructions are re-issued branch instructions. Furthermore, there is no significant difference in their branch types and prediction confidence. In this case, the update permission arbitration module can select one of the branch instructions as the target branch instruction according to a round-robin rule. For example, if the branch instruction corresponding to the first branch execution unit received an update flag in the previous processing cycle, the current processing cycle can preferentially select the branch instruction corresponding to the second or third branch execution unit as the target branch instruction. Through round-robin selection, the branch instructions generated by multiple branch execution units can have a relatively balanced update opportunity across multiple processing cycles.

[0081] After the update permission arbitration is completed, branch instructions other than the target branch instruction can remain in an unmarked state or be configured as non-updated. Branch instructions without update markers can still be issued and executed normally, but whether they can exit the pipeline directly after execution depends on their prediction results. If a branch instruction without update markers predicts correctly, no update to the branch predictor is needed, and it can exit the instruction queue normally. If a branch instruction without update markers predicts incorrectly, it needs to be marked as a reissued branch instruction and re-issued in subsequent processes because it does not have the permission to update the branch predictor through a single update path. This ensures that the training information corresponding to its prediction error can eventually be submitted to the branch predictor.

[0082] In this way, this application can uniformly manage the update permissions of multiple branch instructions to be issued and executed without increasing the number of write ports of the branch predictor. This ensures that only one branch instruction receives an update flag within the same processing cycle. Furthermore, by setting a higher priority for retransmitted branch instructions, it guarantees that branch instructions that have made prediction errors but have not yet received update permissions will have an update opportunity during the retransmission process. Therefore, it maintains the hardware structure of a single update path for the branch predictor while preventing the loss of critical training information due to arbitration misses.

[0083] S103. Execute the multiple branch instructions to be executed, and obtain the actual execution result and prediction result corresponding to each branch instruction.

[0084] In practice, after completing the update permission arbitration and configuring the update flag for the target branch instruction, the processor issues and executes the plurality of branch instructions to be issued and executes them, and obtains the actual execution result and the predicted result corresponding to each branch instruction. The plurality of branch instructions to be issued and executed can be issued to the corresponding branch execution unit respectively, or they can be issued to different execution channels in the same group of branch execution resources according to the availability status of the branch execution unit, the execution port allocation result and the issuance queue scheduling result.

[0085] Specifically, the launch module can send multiple branch instructions to multiple branch execution units according to the launch conditions of each branch instruction. For a target branch instruction with an update flag, the launch module can transmit the update flag along with the control information of the target branch instruction to the corresponding branch execution unit when launching the target branch instruction; for other branch instructions without an update flag, the launch module can transmit the non-updated or unset update flag along with the control information of the branch instruction to the corresponding branch execution unit. Thus, after execution, each branch execution unit can determine whether the corresponding branch instruction has the authority to submit a branch predictor update request based on whether the corresponding branch instruction has an update flag.

[0086] During the execution of a branch instruction, the branch execution unit can calculate the actual execution result of the branch instruction based on its operands, branch conditions, immediate values, register values, program counter values, and instruction encoding information. The actual execution result may include at least one of the following: actual branch direction, actual branch target address, actual next instruction fetch address, whether the branch jumps, return address, or call target address. For conditional branch instructions, the actual execution result may include the actual jump direction after the condition is evaluated; for indirect branch instructions, the actual execution result may include the actual target address calculated based on register values ​​or memory data; for call or return instructions, the actual execution result may include the call target address or return target address.

[0087] Simultaneously, the processor acquires the prediction results corresponding to each branch instruction. These prediction results may originate from prediction information generated by the branch prediction module for the branch instruction during the fetch, decode, or rename phases and transmitted along with the instruction stream. The prediction results may include at least one of the following: predicted branch direction, predicted branch target address, predicted next fetch address, prediction confidence, predictor hit information, or predictor index information. In some implementations, the prediction results may be stored as a control field of the branch instruction in the issue queue, reserve station, reordering cache, branch execution unit input register, or other pipeline registers, and transmitted to the branch execution unit or prediction result comparison module during the issuance and execution of the branch instruction.

[0088] In some embodiments, when the branch execution unit outputs the actual execution result, it can simultaneously output the actual execution result and the corresponding prediction result to the prediction result comparison module. The prediction result comparison module is used to compare whether the actual execution result and the prediction result are consistent to determine whether a prediction error has occurred for the corresponding branch instruction. If the actual branch direction is inconsistent with the predicted branch direction, or the actual branch target address is inconsistent with the predicted branch target address, it can be determined that the branch instruction has a prediction error; if both the actual branch direction and the actual branch target address are consistent with the prediction result, it can be determined that the branch instruction is correctly predicted. For a predictor structure that only predicts the branch direction, it is also possible to determine whether a prediction error has occurred based solely on whether the actual branch direction and the predicted branch direction are consistent; for a predictor structure that predicts both the direction and the target address, it is possible to determine whether a prediction error has occurred based on the comparison results of both the direction and the target address.

[0089] In one example, the current processing cycle contains a first branch instruction and a second branch instruction. The first branch instruction is configured with an update flag, while the second branch instruction is not. The dispatch module sends the first branch instruction to the first branch execution unit and the second branch instruction to the second branch execution unit. After executing the first branch instruction, the first branch execution unit obtains a first actual execution result and acquires the first predicted result corresponding to the first branch instruction. After executing the second branch instruction, the second branch execution unit obtains a second actual execution result and acquires the second predicted result corresponding to the second branch instruction. Subsequently, the prediction result comparison module compares the first actual execution result with the first predicted result and the second actual execution result with the second predicted result to determine whether the first branch instruction and the second branch instruction were predicted correctly.

[0090] In another example, if there are three or more branch instructions to be issued and executed within the current processing cycle, the processor can issue each branch instruction to its corresponding branch execution unit and generate an actual execution result for each branch instruction independently. Each branch execution unit can output the actual execution result of the corresponding branch instruction and simultaneously pass the corresponding prediction result or prediction result identifier to the prediction result comparison module. The prediction result comparison module can perform prediction result comparisons for multiple branch instructions in parallel or time-sharing, and generate corresponding prediction status information for each branch instruction. The prediction status information is used to characterize whether the prediction of the branch instruction is correct or incorrect.

[0091] In some implementations, the actual execution result and prediction result are used not only to determine whether a branch instruction has a prediction error, but also to generate subsequent branch predictor training information. After a branch instruction with an update flag completes execution, the processor can generate training information based on the actual execution result, prediction result, branch address, branch target address, prediction confidence, or historical information of that branch instruction, and submit it to the branch predictor through a single update path. For branch instructions without update flags, the processor can also obtain their actual execution result and prediction result, but only if a prediction error occurs in that branch instruction will the subsequent re-execution process be triggered, so that the branch instruction can obtain an update flag and submit training information after re-execution.

[0092] In some embodiments, to ensure that control information is not lost in the pipeline, the processor can use update flags, prediction results, retransmission flags, branch addresses, and branch instruction identifiers as additional control information for branch instructions, and pass them along with the branch instructions between the issue, execution, and completion phases. In this way, the branch execution unit or prediction result comparison module can accurately determine whether a branch instruction has update privileges, its prediction result, and its actual execution result upon completion of the branch instruction execution, thereby providing a basis for subsequent branch predictor updates, normal exits, or retransmission processing.

[0093] S104. After the branch instruction with the update flag is executed, the branch predictor is updated through the single update path according to the actual execution result and prediction result of the branch instruction.

[0094] In practical implementation, after a branch instruction with the update flag is executed, the processor updates the branch predictor through a single update path based on the actual execution result and the predicted result of the branch instruction. That is, only branch instructions that obtain the update flag during the aforementioned update permission arbitration process have the authority to submit an update request to the branch predictor after their execution, thus ensuring that the branch predictor only needs to respond to one update request per processing cycle.

[0095] Specifically, after a branch instruction with the update flag is issued to the corresponding branch execution unit and completed, the branch execution unit outputs the actual execution result of the branch instruction. The actual execution result may include at least one of the following: actual branch direction, actual branch target address, actual next fetch address, call target address, and return target address. The processor also obtains the prediction result corresponding to the branch instruction, which may include at least one of the following: predicted branch direction, predicted branch target address, predicted next fetch address, prediction confidence, predictor hit information, and predictor index information.

[0096] After obtaining the actual execution result and the predicted result, the prediction result comparison module can compare the actual execution result and the predicted result of the branch instruction to determine whether a prediction error has occurred. For example, when the actual branch direction is inconsistent with the predicted branch direction, it can be determined that the branch instruction has a direction prediction error; when the actual branch target address is inconsistent with the predicted branch target address, it can be determined that the branch instruction has a target address prediction error; when the actual next fetch address is inconsistent with the predicted next fetch address, it can also be determined that the branch instruction has a prediction error. If all the above comparison results are consistent, it can be determined that the branch instruction prediction is correct.

[0097] It should be noted that for branch instructions marked with the update flag, regardless of whether the branch instruction is predicted correctly or incorrectly, the processor can allow the branch instruction to initiate an update request to the branch predictor through a single update path. For incorrectly predicted branch instructions, the update request can be used to correct the branch predictor, enabling it to adjust the corresponding prediction state based on the actual execution result. For correctly predicted branch instructions, the update request can be used to strengthen or maintain the existing prediction state in the branch predictor, allowing it to continue to maintain its ability to predict this type of branch behavior.

[0098] In some embodiments, the processor can generate training information based on at least one of the actual execution result of the branch instruction with the update tag, the prediction result, the branch address, and the branch target address, and submit the training information to the branch predictor through a single update path. The training information may include at least one of the following: branch instruction address, actual jump direction, actual target address, predicted jump direction, predicted target address, prediction hit / miss, prediction error, branch type, historical information index, and confidence update information. Upon receiving the training information, the branch predictor can update its internal prediction state based on the training information.

[0099] In some implementations, the single update path may include an update data path connected to the branch predictor update port by the branch execution unit or prediction result comparison module. This single update path can be used to transmit training information, update enable signals, update addresses, update data, and update type information. Since only branch instructions that have obtained update flags can occupy this single update path within a processing cycle, the branch predictor does not need to set up multiple parallel write ports, nor does it need to receive update requests from multiple branch instructions simultaneously within the same cycle.

[0100] In a specific implementation, the branch predictor may include at least one of the following: a branch target buffer, a pattern history table, a global history prediction structure, a local history prediction structure, a TAGE prediction structure, a perceptron prediction structure, and a dual-mode prediction structure. For the branch target buffer, the processor can update the corresponding entries based on the branch address and the actual branch target address to correct or establish the branch target address mapping relationship. For the pattern history table, the processor can update the saturation counter or status bit based on the actual branch direction. For the TAGE prediction structure, the processor can update the corresponding history length entries based on the actual branch direction, historical information, and prediction hit status. For the perceptron prediction structure, the processor can adjust the corresponding weights based on the actual branch direction and the prediction result. For the dual-mode prediction structure, the processor can update the direction prediction table or selector table according to the actual direction and the prediction selection result.

[0101] In a specific example, if both the first branch instruction and the second branch instruction meet the launch conditions within the current processing cycle, the update permission arbitration module identifies the first branch instruction as the target branch instruction and configures an update flag for it. After the first branch instruction completes execution, the processor generates first training information based on the actual execution result and the predicted result of the first branch instruction, and submits the first training information to the branch predictor through a single update path. At this time, although the second branch instruction can also complete execution and generate the corresponding actual execution result, it cannot directly occupy the single update path to update the branch predictor after this execution because it does not have an update flag.

[0102] In another specific example, the branch instruction with the update marker is a low-confidence conditional branch instruction. After the branch instruction completes execution, the processor compares its actual jump direction with the predicted jump direction. If the actual jump direction matches the predicted jump direction, the processor can submit training information to enhance the predicted state through a single update path; if the actual jump direction does not match the predicted jump direction, the processor can submit training information to correct the predicted state through a single update path. Thus, the branch predictor can both consolidate its predicted state using correctly predicted execution results and perform corrective training using incorrectly predicted execution results.

[0103] In some embodiments, a branch instruction with the update flag can exit the instruction queue normally after completing the branch predictor update. Exiting the instruction queue may include releasing the corresponding entry from the launch queue, reservation station, reordering buffer, or other pipeline control structures, or it may include marking the branch instruction as completed, committable, or retireable. Since the branch instruction has already committed training information through a single update path, there is no need to perform subsequent re-launch processing on this branch instruction.

[0104] In some implementations, to avoid redundant updates, the processor can clear the update flag corresponding to a branch instruction after the branch predictor update is completed, or record the update status of the branch instruction as updated. For branch instructions that have entered the retirement stage, the processor can determine that it does not need to initiate a branch predictor update request again based on the updated status, thereby avoiding repeated training of the same branch execution result.

[0105] S105. If a prediction error occurs in a branch instruction without the update flag, the branch instruction is marked as a resend branch instruction, and the branch instruction is re-emitted.

[0106] In practice, after a branch instruction without the update flag is executed, the processor determines whether a prediction error has occurred based on the actual execution result and the prediction result of the branch instruction. If the branch instruction does not have the update flag and a prediction error has occurred, the processor marks the branch instruction as a reissued branch instruction and triggers the reissue of the branch instruction.

[0107] Specifically, although branch instructions without the update flag can be issued and executed normally, and the corresponding branch execution unit can generate actual execution results, they do not have the authority to update the branch predictor through a single update path after execution because they did not obtain the update flag during the update permission arbitration process. If the actual execution result of the branch instruction matches the prediction result, the prediction result of the branch instruction is correct, and there is no need to submit corrective training information to the branch predictor; it can exit the instruction queue normally. If the actual execution result of the branch instruction does not match the prediction result, it indicates that the branch instruction has a prediction error, and the training information corresponding to the prediction error needs to be submitted to the branch predictor to prevent the branch predictor from continuing to maintain an incorrect prediction state.

[0108] In its implementation, the prediction result comparison module compares the actual execution result with the predicted result of branch instructions that do not carry the update flag. When the actual branch direction differs from the predicted branch direction, the actual branch target address differs from the predicted branch target address, or the actual next fetch address differs from the predicted next fetch address, the prediction result comparison module generates a prediction error event. This prediction error event indicates that although the corresponding branch instruction has a prediction error, because it does not carry an update flag, it cannot directly occupy a single update path to update the branch predictor after the current execution is completed.

[0109] In response to the predicted error event, the replay control module can mark the branch instruction as a replay branch instruction. In one implementation, a replay flag can be set in the instruction control field of the branch instruction, for example, setting the `is_replay` flag to indicate that the branch instruction is a replay branch instruction that needs to be re-emitted. In another implementation, the replay status of the branch instruction can be recorded in a reserved station entry, a transmit queue entry, a reordering buffer entry, or other pipeline control structure.

[0110] In some embodiments, the retransmission control module may also record at least one of the following information: the branch address corresponding to the retransmitted branch instruction, the actual execution result, the prediction result, the branch type, the historical information index, and the instruction identifier. This information can be used to re-enter the transmission process with the retransmitted branch instruction, or it can be used to generate branch predictor training information after the retransmitted branch instruction has been executed again. By retaining this information, it can be ensured that the branch predictor can be effectively updated based on its actual execution behavior after the incorrectly predicted branch instruction receives an update flag.

[0111] In some implementations, triggering a re-emission of a branch instruction may include: sending the branch instruction to a retransmission queue, or re-sending the branch instruction to the re-emission queue via an exception handling path, a selective retransmission path, or a hold station reactivation path. The retransmission queue may be a queue dedicated to storing branch instructions that need to be re-emissioned, or it may be a control structure reused with existing exception recovery, pipeline redirection, or hold station rescheduling logic. Through the retransmission queue or exception handling path, the processor can perform selective retransmission only for branch instructions that have experienced prediction errors and have not received an update flag, without repeatedly executing all branch instructions in the same cycle or the entire pipeline.

[0112] In a specific example, the first branch instruction and the second branch instruction are issued and executed simultaneously within the current processing cycle. The first branch instruction carries an update flag, while the second branch instruction does not. After the first branch instruction completes execution, the branch predictor is updated through a single update path based on its actual execution result and the predicted result. After the second branch instruction completes execution, the prediction result comparison module compares the actual execution result of the second branch instruction with the predicted result. If they match, the second branch instruction was predicted correctly and can be directly removed from the instruction queue; if they do not match, the second branch instruction has been predicted incorrectly. However, since the second branch instruction has not received an update flag, the branch predictor cannot be updated immediately. Therefore, the retransmission control module sets the retransmission flag of the second branch instruction and resends the second branch instruction into the transmission queue.

[0113] In another specific example, there are three or more branch instructions awaiting execution within the current processing cycle, of which only one branch instruction obtains an update flag through update permission arbitration. After the remaining branch instructions that did not obtain update flags complete their execution, the processor compares the prediction results of each branch instruction that did not obtain update flags. For correctly predicted branch instructions, the processor allows them to exit normally; for incorrectly predicted branch instructions, the processor marks them as retransmission branch instructions and triggers retransmission in subsequent processing cycles according to the availability of launch resources, the retransmission queue order, or preset scheduling rules. Thus, even if there are multiple branch instructions that have not obtained update flags and are incorrectly predicted within a single processing cycle, their update opportunities can be gradually guaranteed through subsequent retransmission processes.

[0114] In some embodiments, the re-issuance of the re-issued branch instruction is not intended to regenerate the ordinary data calculation result, but primarily to enable the branch instruction to re-enter the update permission arbitration in subsequent issuance processes and obtain the update flag with priority based on its re-issue attribute. Therefore, when triggering a re-issue, the re-issue control module can maintain the execution context and branch-related information of the branch instruction and provide it to the update permission arbitration module as a candidate branch instruction with higher update priority in subsequent processing cycles.

[0115] In some implementations, to reduce the performance penalty caused by retransmission, the processor can employ selective retransmission. That is, only branch instructions that have not been updated and have resulted in a prediction error are retransmitted, while branch instructions that have been correctly predicted but have not been updated are not retransmitted, nor are branch instructions that have already been updated and have been updated required to be re-executed. This approach limits the retransmission overhead to a small number of branch instructions that genuinely require corrective training information, thereby ensuring the integrity of the branch predictor's training information while reducing the impact on processor performance.

[0116] S106. When the retransmission branch instruction is re-emitted, the retransmission branch instruction obtains the update flag, and after the retransmission branch instruction completes the retransmission execution, the branch predictor is updated through the single update path.

[0117] In practice, a retransmitted branch instruction has already been identified as having a prediction error in the previous execution. Since this retransmitted branch instruction did not carry an update flag in the previous execution, it cannot directly occupy a single update path to update the branch predictor. Therefore, the processor marks this branch instruction as a retransmitted branch instruction and re-enters it into the launch queue, retransmission queue, or reserved station for path rescheduling. When the retransmitted branch instruction meets the launch conditions again in a subsequent processing cycle, the launch module or branch instruction scheduling module provides it as a candidate branch instruction to be launched and executed to the update permission arbitration module.

[0118] When a retransmission branch instruction re-enters the update permission arbitration process, the update permission arbitration module can read the retransmission flag, retransmission status, or retransmission type information corresponding to the retransmission branch instruction. If the branch instruction is detected as a retransmission branch instruction, the update permission arbitration module prioritizes identifying the retransmission branch instruction as the target branch instruction based on this retransmission attribute and configures an update flag for the retransmission branch instruction. Therefore, the retransmission branch instruction can obtain the permission to update the branch predictor through a single update path upon retransmission.

[0119] In some implementations, the retransmission branch instruction can be set to have a higher update priority than the normal first-launch branch instruction. That is, when both retransmission branch instructions and normal branch instructions exist within the same processing cycle, the update permission arbitration module preferentially selects the retransmission branch instruction as the target branch instruction and configures an update flag for it. When multiple retransmission branch instructions exist within the same processing cycle, the update permission arbitration module can select one retransmission branch instruction as the target branch instruction according to the retransmission queue order, the order in which they entered the retransmission state, the branch execution unit number, a polling rule, or a random rule. Other unselected retransmission branch instructions can remain in the retransmission queue or launch queue and participate in arbitration again in subsequent processing cycles.

[0120] In some embodiments, to ensure that retransmitted branch instructions can be identified and given priority for update flags, an `is_replay` flag can be set in the control field corresponding to the branch instruction. When a prediction error occurs in a branch instruction without an update flag, the retransmission control module sets the `is_replay` flag. When the branch instruction re-enters the transmit queue, the update permission arbitration module reads the `is_replay` flag and forcibly assigns an update flag to the branch instruction accordingly. Alternatively, the retransmission status can be recorded in the reserved station entry, reordering buffer entry, or retransmission queue entry, and the update permission arbitration module can determine the branch instruction as a retransmitted branch instruction that needs priority for update based on the retransmission status.

[0121] After the retransmitted branch instruction receives an update flag, the issuing module retransmits the retransmitted branch instruction to the corresponding branch execution unit. The retransmission execution may still go through the pipeline stages of issuing, executing, and completing, but its main purpose is to ensure that the retransmitted branch instruction completes execution with the update flag, thereby legally submitting training information to the branch predictor. In other words, retransmission execution is not necessarily used to regenerate ordinary data calculation results, but primarily to complete the control flow required for updating the branch predictor.

[0122] In some embodiments, since the re-execution branch instruction has already completed the branch condition judgment, target address calculation, or related data calculation during its first execution, the re-execution process can prevent the re-execution branch instruction from performing a write-back operation on the destination register, or skip the execution actions related to the destination register write-back. For example, the processor can set a write-back prevention flag in the control field of the re-execution branch instruction, so that the execution unit does not write data to the general-purpose register file, renamed physical register, or other destination registers after the re-execution is completed. In this way, the duplicate writing of data results caused by re-execution can be avoided, and the impact of re-execution on the normal data path can be reduced.

[0123] For branch instructions that do not involve writing back to the destination register, the processor can retain only the control actions required for branch result generation, prediction result comparison, and training information submission during re-execution, without performing operations unrelated to the final data write-back. Therefore, re-execution can be limited to a selective re-execution process for branch predictor training, rather than a complete repetition of ordinary instruction semantics.

[0124] After the re-execution of the re-issued branch instruction is completed, the branch execution unit outputs the actual execution result corresponding to the re-issued branch instruction and obtains the prediction result corresponding to the re-issued branch instruction. The processor generates training information based on the actual execution result and the prediction result, and submits the training information to the branch predictor through the single update path. The training information may include at least one of the following: branch address, actual branch direction, actual branch target address, predicted branch direction, predicted branch target address, prediction error type, prediction confidence, and historical information index.

[0125] In some implementations, after receiving the training information corresponding to the retransmission branch instruction, the branch predictor can update its internal prediction state based on this training information. For example, for a branch target buffer, the corresponding target address entry can be updated based on the actual branch target address; for a mode history table, the corresponding counter state can be updated based on the actual branch direction; for a TAGE prediction structure, the corresponding history entry can be updated based on the actual branch direction and historical information; for a perceptron prediction structure, the weights can be adjusted based on the actual result and the prediction result; and for a dual-mode prediction structure, the direction prediction table or selector table can be updated. Thus, the prediction error training information that was not submitted during the previous execution of the retransmission branch instruction can be supplemented and submitted to the branch predictor through a single update path after the retransmission is completed.

[0126] In a specific example, a first branch instruction and a second branch instruction are simultaneously issued during the first processing cycle. The first branch instruction receives an update flag, while the second branch instruction does not. After execution, the second branch instruction is determined to be a prediction error. Since it lacks an update flag, the retransmission control module marks it as a retransmission branch instruction and re-enters it into the issuance queue. In the subsequent second processing cycle, the second branch instruction, as a retransmission branch instruction, participates again in the update permission arbitration. The update permission arbitration module configures an update flag for it based on its retransmission attribute. Subsequently, the second branch instruction is re-issued and completes retransmission execution. The processor generates training information based on the actual execution result and prediction result of the second branch instruction and updates the branch predictor through a single update path.

[0127] In another specific example, within the current processing cycle, there is one retransmission branch instruction and multiple initial emission branch instructions. Although the multiple initial emission branch instructions may also have update requirements, since the retransmission branch instruction already corresponds to an uncommitted prediction error training information, the update permission arbitration module prioritizes identifying the retransmission branch instruction as the target branch instruction and configures an update flag for it. Multiple initial emission branch instructions can execute normally within this processing cycle but do not occupy a single update path. Therefore, priority can be given to ensuring that branch instructions that have experienced prediction errors but have not yet updated their branch predictors complete the submission of training information.

[0128] In some embodiments, after the retransmission branch instruction completes the branch predictor update through a single update path, the processor can clear the retransmission flag and update flag of the retransmission branch instruction and mark it as updated. Subsequently, the retransmission branch instruction can normally exit the transmit queue, retransmission queue, reservation station, or reordering buffer. By clearing the retransmission flag and update flag, the same retransmission branch instruction can be prevented from being repeatedly identified as an instruction that needs to be retransmitted or updated in subsequent pipeline stages.

[0129] In some implementations, if a retransmission branch instruction fails to obtain an update flag in a processing cycle due to launch resource conflicts, single update path occupancy, or arbitration policy limitations, the retransmission branch instruction can remain in the retransmission state and re-participate in update permission arbitration in subsequent processing cycles. By continuously maintaining the retransmission state, it can be ensured that branch instructions with prediction errors and whose branch predictors have not yet been updated will not lose their training opportunities due to a single arbitration failure.

[0130] See Figure 2 The diagram shown is a flowchart of a multi-branch instruction predictor update method provided in an embodiment of this disclosure.

[0131] like Figure 2 As shown, in one embodiment, the multi-branch instruction predictor update method includes processes such as branch instruction issuance, update permission arbitration, branch instruction execution, predictor update, and retransmission control.

[0132] Specifically, after acquiring multiple branch instructions to be executed within a processing cycle, the processor arbitrates update permissions among these instructions to determine a target branch instruction and configures an update flag for that target branch instruction. The update flag indicates that the corresponding branch instruction has the permission to update the branch predictor through a single update path. Branch instructions not selected by arbitration are not configured with an update flag or are configured to a non-update state.

[0133] Here, branch instructions marked with the "update" flag are issued to the corresponding branch execution unit for execution. After the branch instruction completes execution, the processor generates training information based on the actual execution result and the prediction result of the branch instruction, and submits this training information to the branch predictor through a single update path to complete the branch predictor update. After the update is complete, the branch instruction can exit the corresponding instruction queue or pipeline control structure.

[0134] Branch instructions without the update flag are also issued to the corresponding branch execution unit for execution. After the branch instruction completes execution, the processor compares the actual execution result of the branch instruction with the predicted result to determine whether the branch instruction has failed to predict the output. If the result is that no prediction failure has occurred, the branch instruction does not need to update the branch predictor and can exit the corresponding instruction queue or pipeline control structure.

[0135] If a branch instruction without the update flag fails to predict the branch predictor, the processor marks it as a replay instruction because it lacks the permission to update the branch predictor via a single update path. This replay instruction then re-enters the launch process. Upon re-entering the launch process, the replay instruction participates again in update permission arbitration. Based on its replay attribute, the processor prioritizes configuring the update flag for this replay instruction, ensuring that it can update the branch predictor via a single update path after re-execution.

[0136] thus, Figure 2 The embodiment shown controls which branch instructions can occupy a single update path within the same processing cycle through the update flag, and enables branch instructions that have failed to predict but have not received the update flag to re-participate in the transmission and arbitration through the replay flag. Thus, without increasing the number of update ports of the branch predictor, it ensures that the training information corresponding to the branch instructions that failed to predict can eventually be submitted to the branch predictor.

[0137] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0138] Based on the same inventive concept, this disclosure also provides a multi-branch instruction predictor update apparatus corresponding to the multi-branch instruction predictor update method. Since the principle of the apparatus in this disclosure for solving the problem is similar to the multi-branch instruction predictor update method described above in this disclosure, the implementation of the apparatus can refer to the implementation of the method, and the repeated parts will not be described again.

[0139] Please see Figure 3 , Figure 3 This is a schematic diagram of a multi-branch instruction predictor update apparatus provided in an embodiment of this disclosure. Figure 3 As shown in the illustration, the multi-branch instruction predictor update apparatus 300 provided in this embodiment is applied to a processor having multiple branch execution units. The processor updates the branch predictor through a single update path, including:

[0140] The branch instruction scheduling module 310 is used to acquire multiple branch instructions to be issued and executed within a processing cycle.

[0141] The update permission arbitration module 320 is used to perform update permission arbitration on the plurality of branch instructions to be launched and executed, determine the target branch instruction from the plurality of branch instructions to be launched and executed, and configure an update flag for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path.

[0142] The branch execution module 330 is used to issue and execute the plurality of branch instructions to be issued and executed, and to obtain the actual execution result and prediction result corresponding to each branch instruction.

[0143] The prediction result comparison module 340 is used to update the branch predictor through the single update path after the branch instruction with the update mark has been executed, based on the actual execution result of the branch instruction and the prediction result.

[0144] The retransmission control module 350 is used to mark a branch instruction as a retransmission branch instruction and trigger the retransmission of the branch instruction if a prediction error occurs in a branch instruction without the update flag.

[0145] The branch predictor update module 360 ​​is used to enable the retransmitted branch instruction to obtain the update flag when the retransmitted branch instruction is retransmitted, and to update the branch predictor through the single update path after the retransmitted branch instruction has completed retransmission execution.

[0146] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0147] The multi-branch instruction predictor update method and apparatus provided in this disclosure enable the processor to complete branch predictor training through a single update path even when multiple branch instructions are executed concurrently. By arbitrating update permissions for branch instructions and re-issuing branch instructions that have not obtained update permissions but have made prediction errors, it is ensured that branches with prediction errors can eventually submit training information. This reduces hardware complexity and timing pressure while improving the integrity of branch predictor training information, taking into account processor performance, area and power consumption.

[0148] Corresponding to Figure 1 In addition to the multi-branch instruction predictor update method, this disclosure also provides an electronic device 400, such as... Figure 4 The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including:

[0149] Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 1 The steps of the multi-branch instruction predictor update method in [the document / system].

[0150] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the multi-branch instruction predictor update method described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0151] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the multi-branch instruction predictor update method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0152] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0153] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method of updating a multi-branch instruction predictor, the method comprising: A method applicable to processors with multiple branch execution units, wherein the processor updates a branch predictor via a single update path, the method comprising: Within a single processing cycle, multiple branch instructions to be executed are acquired; An update permission arbitration is performed on the plurality of branch instructions to be launched and executed, a target branch instruction is determined from the plurality of branch instructions to be launched and executed, and an update flag is configured for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path. The system executes the multiple branch instructions to be executed and obtains the actual execution result and prediction result corresponding to each branch instruction. After the branch instruction with the update flag is executed, the branch predictor is updated through the single update path according to the actual execution result and the prediction result of the branch instruction. If a prediction error occurs in a branch instruction without the update flag, the branch instruction is marked as a resend branch instruction, and the branch instruction is re-emitted. When the retransmission branch instruction is re-issued, the retransmission branch instruction is given the update flag, and after the retransmission branch instruction completes retransmission execution, the branch predictor is updated through the single update path.

2. The method of claim 1, wherein, The process of updating permission arbitration for the multiple branch instructions to be executed includes: Identify whether there is a retransmitted branch instruction among the multiple branch instructions to be executed; If the resend branch instruction exists, the resend branch instruction is preferentially identified as the target branch instruction, and the update flag is configured for the resend branch instruction.

3. The method according to claim 1, characterized in that, The process of updating permission arbitration for the multiple branch instructions to be executed includes: Obtain at least one arbitration reference information from each branch instruction: branch type, prediction confidence, and historical prediction behavior; The update priority of each branch instruction is determined based on the arbitration reference information; Based on the update priority, the target branch instruction is determined from the plurality of branch instructions to be executed.

4. The method according to claim 3, characterized in that, The update priority of each branch instruction is determined based on the arbitration reference information, specifically including: If the branch instruction is a conditional branch instruction and the corresponding prediction confidence is lower than the preset confidence threshold, increase the update priority of the branch instruction. And / or, if the arbitration reference information of multiple branch instructions meets the preset similarity conditions, the target branch instruction is determined from the multiple branch instructions in a polling or random manner.

5. The method according to claim 1, characterized in that, After issuing and executing the plurality of branch instructions to be issued and executing, and obtaining the actual execution result and prediction result corresponding to each branch instruction, the method further includes: If no prediction error occurs in a branch instruction without the update flag, the branch instruction is prohibited from updating the branch predictor through the single update path, and the branch instruction is allowed to exit the instruction queue.

6. The method according to claim 1, characterized in that, If a prediction error occurs in a branch instruction without the aforementioned update flag, the branch instruction is marked as a resend instruction, and the branch instruction is re-emitted, specifically including: When the actual execution result of a branch instruction without the update flag is inconsistent with the predicted result, a prediction error event is generated; In response to the predicted error event, the control field of the branch instruction is set to resend status, or the branch instruction is recorded as a resend type in the reserved station entry; Based on the retransmission status or the retransmission type, the branch instruction is resent into the transmission queue.

7. The method according to claim 1, characterized in that, When the retransmission branch instruction is re-issued, enabling the retransmission branch instruction to obtain the update flag specifically includes: When the resend branch instruction enters the update permission arbitration process, the update flag is forcibly assigned to the resend branch instruction based on its resend attribute, so that the resend branch instruction has the permission to update the branch predictor after resend execution.

8. The method according to claim 1, characterized in that: The re-execution of the re-issued branch instruction is used to submit the branch predictor training information; During the re-execution of the re-branch instruction, write-back operations on the destination register are prohibited, or execution actions related to writing back the data calculation results are skipped.

9. The method according to claim 1, characterized in that, Updating the branch predictor through the single update path specifically includes: Training information is generated based on at least one of the actual execution result of the branch instruction, the prediction result, the branch address, and the branch target address. The training information is submitted to the branch predictor through the single update path; Based on the training information, update at least one of the following in the branch predictor: branch target buffer, mode history table, TAGE prediction structure, perceptron prediction structure, or dual-mode prediction structure.

10. A multi-branch instruction predictor update apparatus, characterized in that, An apparatus for use with a processor having multiple branch execution units, the processor updating a branch predictor via a single update path, the apparatus comprising: The branch instruction scheduling module is used to acquire multiple branch instructions to be issued and executed within a processing cycle; An update permission arbitration module is used to perform update permission arbitration on the plurality of branch instructions to be launched and executed, determine the target branch instruction from the plurality of branch instructions to be launched and executed, and configure an update flag for the target branch instruction. The update flag is used to indicate that the corresponding branch instruction has the permission to update the branch predictor through the single update path. The branch execution module is used to issue and execute the multiple branch instructions to be issued and executed, and to obtain the actual execution result and prediction result corresponding to each branch instruction; The prediction result comparison module is used to update the branch predictor through the single update path after the branch instruction with the update flag has been executed, based on the actual execution result and the prediction result of the branch instruction. The retransmission control module is used to mark a branch instruction as a retransmission branch instruction and trigger the retransmission of the branch instruction when a prediction error occurs in a branch instruction without the update flag. The branch predictor update module is used to enable the retransmitted branch instruction to obtain the update flag when the retransmitted branch instruction is re-issued, and to update the branch predictor through the single update path after the retransmitted branch instruction has completed retransmission execution.

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