A pre-sampling based N-bit successive approximation analog-to-digital converter

Abstract

This invention belongs to the field of mixed-signal integrated circuit technology, and specifically relates to an N-bit successive approximation analog-to-digital converter based on pre-sampling. After the SAR ADC completes the quantization of the (J-1)th cycle, this invention first connects the lower plate of the CDAC capacitor array to a reference low level V via a reset switch. REFN Perform a reset operation. After the reset is complete, disconnect the reset switch and then connect the upper plate to the common-mode voltage V. CM According to the law of charge conservation, after reset, the voltage level of the lower plate will return to the input signal voltage V sampled in the previous cycle (J-1). IN (J-1); then sampling of the input signal for the Jth cycle begins, and the lower plate is connected to the input signal V of the current cycle (J) via a sampling switch. IN (J), at this point, it is only necessary to establish ΔV=V IN (J)- V IN Sampling can be completed with (J-1). This invention improves the sampling accuracy of SAR ADC at the same sampling time by changing the switching timing without requiring additional front-end driving circuits, reduces charge back-kickback to the ADC input buffer, and lowers its bandwidth design requirements.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, and specifically relates to an N-bit successive approximation analog-to-digital converter based on presampling. Background Technology

[0002] With the continuous advancement of integrated circuit technology, the industry has placed higher demands on the performance of analog-to-digital converters (ADCs), requiring them to achieve high accuracy while increasing conversion rates. In successive approximation analog-to-digital converters (SARADCs), the sample-and-hold module largely limits the sampling rate. Therefore, improvements to the sampling module are crucial for enhancing the performance of SAR ADCs.

[0003] In SAR ADCs, there are two sampling methods: upper plate sampling and lower plate sampling. In upper plate sampling, the sampling switch is directly connected to the upper plate of the sampling capacitor. When the switch is open, charge injection and clock feedthrough directly affect the linearity of the sampling module. Lower plate sampling connects the sampling switch to the lower plate of the sampling capacitor. By controlling the timing of the upper and lower plates, the impact of charge injection and clock feedthrough on the upper plate can be avoided. Therefore, lower plate sampling is usually used in high-precision applications. The main operations of traditional lower plate sampling are as follows: Before sampling, the charge stored in the CDAC capacitor array is cleared; after sampling begins, the upper and lower plates of the CDAC are connected to a common-mode level V. CM and input signal V IN The sampling switch stores the sampled charge on the CDAC capacitor array; after the follow-up phase is completed, to eliminate the effects of charge injection and clock feedthrough, the upper plate switch is first disconnected, and then the lower plate switch is switched from V... IN Switch to reference low level V REFN This applies the input voltage to the upper plate of the CDAC, ending the hold state, and then the SAR ADC begins quantization.

[0004] Lower-plate sampling cleverly eliminates the effects of charge injection and clock feedthrough by changing the position of the sampling switch and setting the timing, reducing the degradation of sampling accuracy by switching nonlinearity and improving the linearity of the sampling module. However, traditional lower-plate sampling clears the charge stored in the CDAC before each sampling, so large signal establishment needs to be repeated for each sampling, reducing the small signal establishment time and affecting the final establishment accuracy. In addition, the establishment of large signals requires a larger bandwidth ADC input buffer to provide a larger transient current to avoid large charge kickback introducing harmonics, thus limiting the application of lower-plate sampling in the field of high-speed, high-precision SAR ADCs.

[0005] In existing high-speed / high-precision SAR ADCs, presampling is usually used to reduce the settling time of large signals, thereby improving tracking accuracy. Traditional presampling circuits often precharge the sampling capacitor through a front-end driver module (usually an operational amplifier) ​​before allowing the sampling switch to sample the input signal. The use of the front-end driver module introduces additional power consumption and area overhead, which is not conducive to low-power design. Summary of the Invention

[0006] To address the aforementioned issues and improve the sampling speed and accuracy of SAR ADCs, this invention proposes an N-bit successive approximation analog-to-digital converter based on pre-sampling. After the SAR ADC completes quantization in the (J-1)th cycle, the lower plate of the CDAC capacitor array is first connected to the reference low level V via a reset switch. REFN Perform a reset operation. After the reset is complete, disconnect the reset switch and then connect the upper plate to the common-mode voltage V. CM According to the law of charge conservation, after reset, the voltage level of the lower plate will return to the input signal voltage V sampled in the previous cycle (J-1). IN (J-1). Then, sampling of the input signal for the Jth cycle begins, with the lower electrode connected to the input signal V of the current cycle (J) via a sampling switch. IN (J), at this point, it is only necessary to establish ΔV = V IN (J)-V IN Sampling can be completed with (J-1). The pre-sampling technique proposed in this invention improves the sampling accuracy of SAR ADC at the same sampling time by changing the switching timing without the need for additional front-end driving circuits, reduces charge back-kickback to the ADC input buffer, and lowers its bandwidth design requirements.

[0007] The technical solution of the present invention is as follows:

[0008] An N-bit successive approximation analog-to-digital converter based on presampling includes a CDAC module, a comparator module, a successive approximation module, and a switch control module.

[0009] The CDAC module is a fully differential structure, such as Figure 1 As shown. The CDAC module consists of a capacitor array and switching switches, where CP1, CP2, CP3...CP... N-1 CP N CP N+1 This is a P-terminal capacitor array, with corresponding capacitance values ​​of 2. N-1 Cu, 2 N-2 Cu, 2 N- 3 Cu……2 1 Cu, 2 0 Cu, 2 0 Cu; CN1, CN2, CN3...CNN-1 CN N CN N+1 This is an N-terminal capacitor array, with corresponding capacitance values ​​of 2. N-1 Cu, 2 N-2 Cu, 2 N-3 Cu……2 1 Cu, 2 0 Cu, 2 0 Cu, where Cu is the unit capacitance, and i takes a value in N+1.

[0010] Switches KSP1, KSP2, KSP3...KSP N-1 KSP N KSP N+1 This is a sampling switch for the P-terminal capacitor array. When the switch control signal SWP... i When it is 0, the sampling switch KSP i When the capacitor is turned on, the lower plate of the P-terminal capacitor array is connected to V. INP When the switch control signal SWPi is not 0, the sampling switch KSP is activated. i Disconnect; switches KSN1, KSN2, KSN3...KSN N-1 KSN N KSN N+1 This is a sampling switch for an N-terminal capacitor array. When the switch control signal SWN... i When it is 0, the sampling switch KSN i When the circuit is turned on, the lower plate of the N-terminal capacitor array is connected to V. INN Connection, when the switch control signal SWN i When it is not 0, the sampling switch KSN i Disconnect; switches KP1, KP2, KP3...KP N-1 KP N KP N+1 This is a switching switch for the lower plate of the P-terminal capacitor array. When the switch control signal SWP... i When it is 1, switch KP i Switch to V REFP The lower plate of the P-terminal capacitor array is connected to V. REFP When the switch control signal SWP i When it is -1, switch KP i Switch to V REFN The lower plate of the P-terminal capacitor array is connected to V. REFN Switches KN1, KN2, KN3...KN N-1 KN N KN N+1 This is a switching switch for the lower plate of an N-terminal capacitor array. When the switch control signal SWN... i When the value is 1, switch KN i Switch to VREFP The lower plate of the N-terminal capacitor array is connected to V. REFP When the switch control signal SWN i When it is -1, switch KN i Switch to V REFN The lower plate of the N-terminal capacitor array is connected to V. REFN .

[0011] KCM switch P With KCM N This is the upper plate reset switch; when the upper plate reset signal CLK is received... u When it is high, switch KCM P With switch KCM N When the circuit is turned on, the upper plate is reset to the common-mode level V. CM When the upper plate reset signal CLK u When it is low, switch KCM P With switch KCM N disconnect.

[0012] The comparator module converts the voltage V on the upper plate of the P-terminal CDAC capacitor array. P The voltage V on the upper plate of the N-terminal CDAC capacitor array N Compare the results, and use the comparison result V. COM The output is latched and output to the successive approximation module. If V P >V N Then V COM =1; if V P <V N Then V COM =0.

[0013] The successive approximation module uses the comparison result V output by the comparator module. COM V under clock drive COM Latch and execute the successive approximation algorithm to successively generate an N-bit digital output code D. <1:N> .

[0014] The specific operation is as follows: During each comparison clock cycle, the comparison result V is latched. COM The logic level, and based on the latched logic level, the current bit codeword D i Update; if V COM If it is high, then D i =1; if V COM If it is low, then D i =0. After N clock cycles, the N-bit binary code D stored in the successive approximation module is finally output in parallel. <1:N> .

[0015] The switch control module uses the digital codeword D output by the successive approximation module.<1:N> With clock signal CLK r Output control signal SWP i and SWN i And control the switching of the lower plate of the P-terminal capacitor array and the N-terminal capacitor array of the CDAC module respectively. Among them, SWP i -1, 0, and 1 correspond to the lower plate of the P-terminal capacitor array connected to V, respectively. REFN V INP and V REFP ;SWN i -1, 0, and 1 correspond to the lower plate of the N-terminal capacitor array connected to V. REFN V INN and V REFP The current plate reset signal CLK r When the voltage is high, the lower plate of the CDAC module is connected to V. REFN .

[0016] Furthermore, the specific timing of the switch control module is as follows: Figure 2 As shown:

[0017] Step 1: Sampling begins in the (J-1)th cycle, where J is an integer greater than 1 and less than N+2. Upper plate reset signal CLK u Switch KCM switches from low to high level. P With KCM N When the circuit is turned on, the upper plate of the CDAC module capacitor array is connected to a common-mode voltage V. CM Then sample signal CLK S When the signal switches from low to high, the lower plate of the capacitor array at the P terminal of the CDAC module is connected to the P terminal input signal V sampled in the (J-1)th cycle. INP (J-1), the lower plate of the N-terminal capacitor array is connected to the N-terminal input signal V sampled in the (J-1)th cycle. INN (J-1). At this time, the total charge stored on the capacitor array is Q(J-1) = C. totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM ). Among them, C totP C is the total capacitance of the P-terminal capacitor array. totN This represents the total capacitance of the N-terminal capacitor array.

[0018] Step 2: After quantization is completed in cycle J-1, the lower plate reset signal CLK in cycle J is generated. r The switch control signal SWP changes from low to high level. i and SWN i Set to SWPi =SWN i =-1, at this time CD A The lower electrode plate of module C is connected to V. REFN During SAR ADC quantization, the charge on the upper plate of the CDAC module is conserved, and the total charge remains Q(J-1)=C. totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM ).

[0019] Step 3: After the lower electrode plate reset is completed, the lower electrode plate reset signal CLK is generated. r The signal switches from high to low, at which point all switches on the lower plate are open, resulting in a high-impedance state. Subsequently, the upper plate reset signal CLK is sent. u The upper plate reset switch KCM switches from low to high level. P With KCM N Closed, upper plate connected to common-mode voltage V CM Due to charge conservation and V P =V N =V CM From Q(J-1)=C totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM From this, we can obtain the voltage V of the lower plate of the capacitor array at the P terminal of the CDAC module. BP =V INP (J-1), the voltage V at the lower plate of the N-terminal capacitor array BN =V INN (J-1).

[0020] Step 4, SWP sampling phase of period J i =SWN i =0, sampled signal CLK S When switching from low to high level, the lower plates of the P and N terminals of the CDAC module are connected to the input signal V respectively. INP and V INN For the input signal V in the Jth cycle IN (J) Sampling is performed. Previously, the lower plate voltage was the input signal V during the (J-1)th cycle. IN (J-1), therefore, at this time the ADC input buffer and sampling switch only need to perform an amplitude of ΔV=V IN (J)-V IN(J-1) establishes a small signal, avoiding the establishment process of a large signal, and improves the tracking accuracy of sampling when the sampling time is the same.

[0021] Step 5: After sampling is complete, to avoid the influence of non-ideal factors such as charge injection and clock feedthrough, first disconnect the upper plate switch of the CDAC module's capacitor array, and then disconnect the lower plate switch. That is, first reset the upper plate signal CLK. u After switching from high to low level, the lower plate sampling signal CLK is then... S The signal switches from high to low. Quantization then begins in the Jth cycle.

[0022] Furthermore, the comparator module employs a dynamic comparator, and its specific operation is as follows:

[0023] During the non-quantization phase, the comparison clock signal of the dynamic comparator remains low, and the dynamic comparator is in the reset phase. At this time, the input transistors of the dynamic comparator are in the off state. During the comparison phase, the comparison clock signal flips to high, and the dynamic comparator begins the comparison. If V... P >V N Then output the comparison result V COM =1, if V P <V N Then output the comparison result V COM =0. Compared to static comparators with normally open preamplifiers, dynamic comparators avoid dynamic interference introduced by the continuous conduction of the preamplifier during the non-quantization phase by turning off the input pair transistors during the non-quantization phase.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] This invention improves the traditional lower plate sampling timing by resetting the lower plate of the CDAC module before sampling, so that the lower plate potential is restored to the input signal V of the previous cycle. IN (J-1) This eliminates the need for a large signal setup process, requiring only the establishment of a small signal voltage ΔV, which is particularly advantageous for cases with large sampling capacitance. This invention significantly improves the sampling accuracy of SAR ADCs. Attached Figure Description

[0026] Figure 1 This is a block diagram of the N-bit successive approximation analog-to-digital converter based on presampling according to the present invention;

[0027] Figure 2 This is a timing diagram of the switch switching of the present invention;

[0028] Figure 3 A comparison chart was established between the sampling voltage of this invention and that of traditional lower plate sampling.

[0029] Figure 4 This is a comparison chart of the dynamic performance simulation results of the embodiments of the present invention and the traditional lower plate sampling. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0031] This embodiment uses a pre-sampling-based N (N=16) bit successive approximation analog-to-digital converter as an example for illustration, with a sampling frequency of 20 MHz.

[0032] Step 1: After quantization is completed in the previous cycle, the lower plate reset signal CLK is sent. r Switching to high level switches the lower plate of the CDAC module from codeword to V. REFN The lower plate is reset, at which point the voltage of the lower plate of all capacitors is connected to V. REFN .

[0033] Step 2, 500ps later, the lower electrode reset signal CLK r When the signal switches to low level, all switches on the lower plate are off, and the lower plate exhibits a high impedance state. Subsequently, the upper plate reset signal CLK is sent. u Switching to high level resets the upper plate to V. CM During this period, the charge on the upper plate of the CDAC module is conserved, therefore the voltage on the lower plate recovers to the sampling voltage of the previous cycle, such as... Figure 3 As shown.

[0034] Step 3, 1ns later, sample signal CLK S When switched to high level, the lower plate of the P terminal of the CDAC module is connected to the input signal V. INP Connection, the lower plate of the N terminal is connected to the input signal V INN Connection. At this time, the voltage of the upper plate is V. CM The lower electrode is connected to the input signal. Since the voltage of the lower electrode in step 2 is the input voltage of the previous cycle, only a small signal with an amplitude of ΔV needs to be established, which significantly improves the tracking accuracy.

[0035] Step 4, 4.6ns later, the upper plate reset signal CLK u First, the signal switches from high to low. After the upper plate is disconnected, the input signal CLK... S Then switch from high level to low level to end sampling.

[0036] Figure 3 A comparison chart is established between the sampling voltage of this invention and that of traditional lower plate sampling, where V IN For the input signal, V B1 V is the voltage of the lower electrode in this invention. B2The lower plate voltage is sampled using the conventional lower plate method. t1 marks the completion of sampling in the (J-1)th cycle, with the sampled input signal voltage being V1; t2 marks the completion of lower plate reset in the Jth cycle. At this point, the lower plate voltage of this invention is the input signal V1 of the (J-1)th cycle, while the lower plate voltage of the conventional method is the common-mode voltage V. CM t3 marks the completion of sampling in the Jth cycle, at which point the sampled input voltage is V2. From Figure 3 It can be seen that, in the traditional method, a large signal voltage ΔV = V² - V needs to be established at the lower plate during sampling. CM In this invention, during sampling, the lower electrode only needs to establish a small signal with an amplitude of ΔV=V2-V1.

[0037] Figure 4 This figure compares the dynamic performance simulation results of this embodiment with those of traditional lower plate sampling. When the sampling time is 4.6 ns, the sampling frequency is 20 MHz, and the input signal frequency is 1 MHz, the effective bit depth of traditional lower plate sampling is only 13.72 bits, while the effective bit depth reaches 16.07 bits after adopting the presampling technology proposed in this invention, proving the effectiveness of this invention.

[0038] As can be seen from the above embodiments: After the SAR ADC completes the quantization of the (J-1)th cycle, the lower plate of the CDAC capacitor array is first connected to the reference low level V via a reset switch. REFN Perform a reset operation. After the reset is complete, disconnect the reset switch and then connect the upper plate to the common-mode voltage V. CM According to the law of charge conservation, after reset, the voltage level of the lower plate will return to the input signal voltage V sampled in the previous cycle (J-1). IN (J-1); then sampling of the input signal for the Jth cycle begins, and the lower plate is connected to the input signal V of the current cycle (J) via a sampling switch. IN (J), at this point, it is only necessary to establish ΔV = V IN (J)-V IN Sampling can be completed with (J-1). This invention eliminates the large signal setup process by changing the switching timing without requiring additional front-end driver circuitry, thereby improving the sampling accuracy of the SAR ADC under the same sampling time, reducing charge back-off to the ADC input buffer, and lowering its bandwidth design requirements.

Claims

1. An N-bit successive approximation analog-to-digital converter based on presampling, characterized in that: It includes a CDAC module, a comparator module, a successive approximation module, and a switch control module; The CDAC module is a fully differential structure, consisting of a capacitor array and switching switches, where CP1, CP2, CP3...CP... N-1 CP N CP N+1 This is a P-terminal capacitor array, with corresponding capacitance values ​​of 2 respectively. N-1 Cu, 2 N-2 Cu, 2 N-3 Cu……2 1 Cu, 2 0 Cu, 2 0 Cu; CN1, CN2, CN3...CN N-1 CN N CN N+1 This is an N-terminal capacitor array, with corresponding capacitance values ​​of 2... N-1 Cu, 2 N-2 Cu, 2 N- 3 Cu……2 1 Cu, 2 0 Cu, 2 0 Cu, where Cu is the unit capacitance; i takes values ​​in N+1; Switches KSP1, KSP2, KSP3...KSP N-1 KSP N KSP N+1 This is a sampling switch for the P-terminal capacitor array. When the switch control signal SWP... i When it is 0, the sampling switch KSP i When the capacitor is turned on, the lower plate of the P-terminal capacitor array is connected to V. INP Connection, when the switch control signal SWP is applied. i When it is not 0, the sampling switch KSP i Disconnect; switches KSN1, KSN2, KSN3...KSN N-1 KSN N KSN N+1 This is a sampling switch for an N-terminal capacitor array. When the switch control signal SWN... i When it is 0, the sampling switch KSN i When the circuit is turned on, the lower plate of the N-terminal capacitor array is connected to V. INN Connection, when the switch control signal SWN i When it is not 0, the sampling switch KSN i Disconnect; switches KP1, KP2, KP3...KP N-1 KP N KP N+1 This is a switching switch for the lower plate of the P-terminal capacitor array. When the switch control signal SWP... i When it is 1, switch KP i Switch to V REFP The lower plate of the P-terminal capacitor array is connected to V. REFP When the switch control signal SWP i When it is -1, switch KP i Switch to V REFN The lower plate of the P-terminal capacitor array is connected to V. REFN Switches KN1, KN2, KN3...KN N-1 KN N KN N+1 This is a switching switch for the lower plate of an N-terminal capacitor array. When the switch control signal SWN... i When the value is 1, switch KN i Switch to V REFP The lower plate of the N-terminal capacitor array is connected to V. REFP When the switch control signal SWN i When it is -1, switch KN i Switch to V REFN The lower plate of the N-terminal capacitor array is connected to V. REFN ; KCM switch P With KCM N This is the upper plate reset switch; when the upper plate reset signal CLK is received... u When it is high, switch KCM P With switch KCM N When the circuit is turned on, the upper plate is reset to the common-mode level V. CM When the upper plate reset signal CLK u When it is low, switch KCM P With switch KCM N disconnect; The comparator module converts the voltage V on the upper plate of the P-terminal CDAC capacitor array. P The voltage V on the upper plate of the N-terminal CDAC capacitor array N Compare and assign the comparison result V COM The output is latched and output to the successive approximation module; if V P >V N Then V COM =1; if V P <V N Then V COM =0; The successive approximation module uses the comparison result V output by the comparator module. COM V under clock drive COM Latch and execute the successive approximation algorithm to successively generate an N-bit digital output code D. <1:N> ; The switch control module uses the digital codeword D output by the successive approximation module. <1:N> With clock signal CLK r Output control signal SWP i and SWN i And respectively control the switching of the lower plate of the P-terminal capacitor array and the N-terminal capacitor array of the CDAC module; wherein SWP i -1, 0, and 1 correspond to the lower plate of the P-terminal capacitor array connected to V, respectively. REFN V INP and V REFP ;SWN i -1, 0, and 1 correspond to the lower plate of the N-terminal capacitor array connected to V, respectively. REFN V INN and V REFP The current plate reset signal CLK r When the voltage is high, the lower plate of the CDAC module is connected to V. REFN .

2. The N-bit successive approximation analog-to-digital converter based on presampling as described in claim 1, characterized in that, The specific operation of the successive approximation module is as follows: During each comparison clock cycle, the comparison result V is latched. COM The logic level, and based on the latched logic level, the current bit codeword D i Update; if V COM If it is high, then D i =1; if V COM If it is low, then D i =0; After N clock cycles, the N-bit binary code D stored in the successive approximation module is finally output in parallel. <1:N> .

3. The N-bit successive approximation analog-to-digital converter based on presampling as described in claim 1, characterized in that, The specific timing sequence of the switch control module is as follows: Step 1: Sampling begins in the (J-1)th cycle, where J is an integer greater than 1 and less than N+2; Upper plate reset signal CLK u Switch KCM switches from low to high level. P With KCM N When the circuit is turned on, the upper plate of the CDAC module capacitor array is connected to a common-mode voltage V. CM Subsequently, the sampling signal CLK was obtained. S When the signal switches from low to high, the lower plate of the capacitor array at the P terminal of the CDAC module is connected to the P terminal input signal V sampled in the (J-1)th cycle. INP (J-1), the lower plate of the N-terminal capacitor array is connected to the N-terminal input signal V sampled in the (J-1)th cycle. INN (J-1); At this time, the total charge stored in the capacitor array is Q(J-1)=C totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM ), where C totP C is the total capacitance of the P-terminal capacitor array. totN This represents the total capacitance of the N-terminal capacitor array. Step 2: After quantization is completed in cycle J-1, the lower plate reset signal CLK in cycle J is generated. r The switch control signal SWP changes from low to high level. i and SWN i Set to SWP i =SWN i =-1, at this time CD A The lower electrode plate of module C is connected to V. REFN During SARADC quantization, the charge on the upper plate of the CDAC module is conserved, and the total charge remains Q(J-1)=C. totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM ); Step 3: After the lower electrode plate reset is completed, the lower electrode plate reset signal CLK is generated. r When the signal switches from high to low, all switches on the lower plate are open, resulting in a high-impedance state; subsequently, the upper plate reset signal CLK is received. u The upper plate reset switch KCM switches from low to high level. P With KCM N Closed, upper plate connected to common-mode voltage V CM Due to charge conservation and V P =V N =V CM From Q(J-1) = C totP ×(V INP (J-1)-V CM )+ C totN ×(V INN (J-1)-V CM From this, we can obtain the voltage V of the lower plate of the capacitor array at the P terminal of the CDAC module. BP =V INP (J-1), the voltage V at the lower plate of the N-terminal capacitor array BN =V INN (J-1); Step 4, SWP sampling phase of period J i =SWN i =0, sampled signal CLK S When switching from low to high level, the lower plates of the P and N terminals of the CDAC module are connected to the input signal V respectively. INP and V INN For the input signal V in the Jth cycle IN (J) Sampling is performed; since the lower plate voltage was previously the input signal V of the (J-1)th cycle. IN (J-1), therefore, at this time the ADC input buffer and sampling switch only need to perform an amplitude of ΔV=V IN (J)-V IN (J-1) small signal establishment; Step 5: After sampling is complete, first reset the upper plate signal CLK. u After switching from high to low level, the lower plate sampling signal CLK is then... S The signal switches from high to low; then the quantization of the Jth cycle begins.

4. The N-bit successive approximation analog-to-digital converter based on presampling as described in claim 1, characterized in that, The comparator module employs a dynamic comparator, and its specific operation is as follows: During the non-quantization phase, the comparison clock signal of the dynamic comparator remains low, and the dynamic comparator is in the reset phase, at which time the input transistors of the dynamic comparator are in the off state; during the comparison phase, the comparison clock signal flips to high, and the dynamic comparator begins comparison. If V P >V N Then output the comparison result V COM =1, if V P <V N Then output the comparison result V COM =0.

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