Master-slave device remote communication method, device, equipment and medium

Abstract

The application relates to a long-distance communication method and device between a master device and a slave device, equipment and a medium, wherein at least one high-speed serial transceiver is included in a field programmable gate array (FPGA) of the master device, and at least one optical module is further arranged in the master device; the method comprises the following steps: in response to a test instruction, determining a target high-speed serial transceiver and a target optical module corresponding to a target slave device indicated by the test instruction; sending a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receiving a response packet returned by the target slave device; if the transmission delay of a communication link between the master device and the target slave device is within a preset range according to the response packet, generating a second data packet in response to a bus signal, the bus signal being used for indicating the transmission of data to the target slave device; and sending the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module. The application improves the success rate of long-distance communication between the master device and the slave device.

Description

Technical Field

[0001] This invention relates to the field of industrial control, and specifically to a method, apparatus, device, and medium for long-distance communication between master and slave devices. Background Technology

[0002] The master device can communicate with multiple slave devices to enable the master device to control multiple slave devices.

[0003] In related technologies, the processor of the master device is connected to a local bus and a field-programmable gate array (FPGA), and the master device and the slave device are connected via a bus, such as a serial peripheral interface (SPI) bus, thereby realizing communication between the master device and the slave device.

[0004] However, in the above method, the local bus has a chip select signal, and this chip select signal has a time limit. The master device needs to complete the communication with the slave device within the effective time of the chip select signal. However, in the field of industrial control, such as in automated production lines, when the master device controls the slave device, the distance between the master device and the slave device may be set to be far. Using bus connection forms such as SPI bus cannot guarantee that the communication with the slave device can be completed within the effective time of the chip select signal. That is, the success rate of long-distance communication between master and slave devices is low, which leads to the inability to achieve precise control of the slave device by the master device. Summary of the Invention

[0005] One objective of this invention is to provide a long-distance communication method between master and slave devices to solve the problem of low success rate in long-distance communication between master and slave devices in the prior art; a second objective is to provide a long-distance communication device between master and slave devices; a third objective is to provide an electronic device; a fourth objective is to provide a computer-readable storage medium; and a fifth objective is to provide a computer program product.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A long-distance communication method between master and slave devices, the method being applied to a field-programmable gate array (FPGA) of the master device, the FPGA including at least one high-speed serial transceiver, and the master device further comprising at least one optical module, the high-speed serial transceiver being connected to the optical module; comprising:

[0008] In response to a test command, the system determines the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command; it sends a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receives a response packet returned by the target slave device; wherein, the first data packet is used for link testing;

[0009] If, based on the response packet, it is determined that the transmission delay of the communication link between the master device and the target slave device is within a preset range, then in response to the bus signal, a second data packet is generated, the bus signal being used to indicate the transmission of data to the target slave device; and the second data packet is sent to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0010] Based on the aforementioned technical methods, a high-speed transmission link is formed using a high-speed serializer and an optical module, improving the transmission rate between the master and slave devices. Furthermore, the latency of the transmission link is tested before data communication, ensuring that data communication only occurs when the latency is within a preset range. This guarantees that data communication can be completed within the effective time of the chip select signal, thus improving the success rate of data communication. This approach ensures long-distance communication between the master and slave devices, enabling precise long-distance control of the slave devices by the master. It is suitable for scenarios in industrial control where high precision control is required, such as real-time monitoring and control of automated production lines.

[0011] Furthermore, the FPGA also includes at least one processing module connected to the high-speed serial transceiver; the high-speed serial transceiver is connected one-to-one with the optical module, and the optical module is connected one-to-one with the slave device; each processing module is configured with a clock domain, and the generation of a second data packet in response to a bus signal includes:

[0012] In response to a bus signal issued by the processor in the master device, a target processing module corresponding to the target slave device is determined;

[0013] Based on the clock domain of the target processing module, the bus signal is converted to obtain a converted bus signal; wherein, the clock domain of the converted bus signal is consistent with the clock domain of the target high-speed serial transceiver;

[0014] The second data packet is generated based on the converted bus signal.

[0015] Based on the aforementioned technical means, a target processing module that matches the target high-speed serial transceiver corresponding to the target slave device can be selected to process bus signals according to the identifier of the target slave device, thereby improving the data processing rate.

[0016] Further, generating the second data packet based on the converted bus signal includes:

[0017] Based on the converted bus signal and the preset frame format, an initial second data packet is generated; wherein the preset frame format includes a frame header, a control field, an address field, a check field, and a data field.

[0018] The initial second data packet is scrambled to obtain the second data packet.

[0019] Based on the above technical means, removing fields such as source Internet Protocol Address (IP address) and destination IP address can improve the transmission rate of data packets. Furthermore, scrambling can increase the randomness of data in the second data packet, making data jumps more frequent. This enhances the data's anti-interference capability and makes it easier for the device to recover the accurate data clock using Clock Data Recovery (CDR) technology.

[0020] Furthermore, the processing module is connected to the high-speed serial transceiver via a multiplexer; before sending the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, it further includes:

[0021] The multiplexer is controlled to open the path between the target processing module and the target high-speed serial transceiver.

[0022] Based on the above technical means, the opening and closing of the path between the target processing module and the target high-speed serial transceiver can be flexibly controlled.

[0023] Furthermore, the method also includes:

[0024] In response to a configuration command, a new high-speed serial transceiver is configured in the FPGA; wherein the new high-speed serial transceiver is configured with a clock domain.

[0025] If it is determined that the clock domain of a processing module is consistent with the clock domain of the new high-speed serial transceiver, then a correspondence between the processing module and the new high-speed serial transceiver is established.

[0026] The above-mentioned technical methods can reduce the number of processing modules and save FPGA computing resources.

[0027] Furthermore, the FPGA includes a training module, which is connected to a high-speed serial transceiver via a multiplexer; the high-speed serial transceiver is connected one-to-one with the optical module, and the optical module is connected one-to-one with the slave device; sending a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module includes:

[0028] Determine the test cases corresponding to the target slave device; wherein the test cases are used to indicate the number M of first data packets sent corresponding to the target slave device; wherein M is an integer greater than or equal to 1;

[0029] Control the multiplexer to open the path between the training module and the target high-speed serial transceiver;

[0030] Based on the target high-speed serial transceiver and the target optical module, M first data packets are sent to the target slave device.

[0031] Based on the above technical means, corresponding test cases can be used to test different slave devices to ensure the accuracy of the transmission latency obtained in subsequent tests.

[0032] Furthermore, the test case is used to indicate the minimum number P of response packets received by the target slave device; P is an integer greater than or equal to 1, and P is less than or equal to M; determining that the transmission delay of the communication link between the master device and the target slave device is within a preset range based on the response packets includes:

[0033] According to the test case, if it is determined that the number of response packets received within a preset time period is greater than or equal to P, then it is determined that the transmission delay of the communication link between the master device and the target slave device is within a preset range.

[0034] Based on the above technical means, the FPGA can accurately determine the minimum number of response packets to be received from the target device according to the test cases, that is, determine the latency range of the transmission link corresponding to the target device.

[0035] A long-distance communication device between master and slave devices, the device being applied to a field-programmable gate array (FPGA) of the master device, the FPGA including at least one high-speed serial transceiver, and the master device further comprising at least one optical module, the high-speed serial transceiver being connected to the optical module; comprising:

[0036] The training module is used to respond to a test command, determine the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command; send a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receive a response packet returned by the target slave device; wherein, the first data packet is used for link testing;

[0037] The processing module is configured to, when determining, based on the response packet, that the transmission delay of the communication link between the master device and the target slave device is within a preset range, generate a second data packet in response to a bus signal, wherein the bus signal is used to indicate the transmission of data to the target slave device; and send the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0038] An electronic device includes: a processor, a memory, and a field-programmable gate array (FPGA);

[0039] The memory stores computer-executed instructions;

[0040] The FPGA executes the computer execution instructions stored in the memory, causing the FPGA to perform the aforementioned long-distance communication method between master and slave devices.

[0041] A computer-readable storage medium storing computer-executable instructions, which, when executed by a field-programmable gate array (FPGA), are used to implement a long-distance communication method between master and slave devices.

[0042] A computer program product includes a computer program that, when executed by a field-programmable gate array (FPGA), enables a long-distance communication method between master and slave devices.

[0043] The beneficial effects of this invention are:

[0044] (1) In terms of hardware, the present invention utilizes a high-speed serializer and an optical module to form a high-speed transmission link between the master device and the slave device, thereby improving the transmission rate between the master device and the slave device.

[0045] (2) Before data communication, the FPGA of the master device can select test cases corresponding to the target slave device to test the transmission link delay, which improves the accuracy of transmission delay test and ensures that data communication is carried out only when the transmission link delay is within the preset range, thus ensuring that data communication can be completed within the effective time of the chip select signal.

[0046] (3) In the data communication process, the FPGA of the master device can select the target processing module that matches the clock domain of the target high-speed serial transceiver to perform data processing, thereby improving the data processing rate.

[0047] By combining the above measures, data communication can be completed within the effective time of the chip select signal, improving the success rate of long-distance data communication between master and slave devices, and thus enabling the master device to accurately control the slave device remotely. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of an application scenario in existing technology;

[0049] Figure 2 This is a schematic diagram of the timing signals of the local bus during a read operation in the prior art;

[0050] Figure 3 This is a schematic diagram illustrating an application scenario provided by an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of a main device provided in an embodiment of the present invention;

[0052] Figure 5 A flowchart illustrating a long-distance communication method between master and slave devices according to an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of a frame format provided in an embodiment of the present invention;

[0054] Figure 7 A schematic diagram of another frame format provided in an embodiment of the present invention;

[0055] Figure 8 A flowchart illustrating a long-distance communication method between master and slave devices according to an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of the structure of a long-distance communication device between master and slave devices according to an embodiment of the present invention;

[0057] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0058] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0059] First, the terms involved in this invention will be explained:

[0060] Local Bus: Used to connect different components inside a computer, such as the connection between the processor and memory.

[0061] Field-Programmable Gate Array (FPGA): It is a programmable logic chip that can perform general-purpose functions, that is, it can be programmed to implement certain logic processing functions.

[0062] Figure 1 This is a schematic diagram illustrating an application scenario in existing technology. For example... Figure 1 As shown, the master device and the slave device are connected via an SPI bus. The master device includes a processor and an FPGA. The processor and the FPGA are connected via a local bus. In this way, communication between the processor of the master device and the slave device can be realized based on the FPGA connected via the local bus.

[0063] Figure 2 This is a schematic diagram of the timing signals of the local bus during a read operation in the prior art. For example... Figure 2 As shown, the timing signals of the local bus typically include the chip select signal (CS_n), control signals (READ, WRITE), address signal (ADDR), and data signal (DATA). Due to the characteristics of the local bus, read and write operations between the master and slave devices must be completed within the valid time of the chip select signal, which is typically only a few hundred nanoseconds. For example, during a read operation, the master device sends the address (ADDR VALID) to the slave device, and then the slave device sends back the data (DATA VALID) to the master device. (See reference...) Figure 2 As shown, the master device must also complete the process of receiving the data signal returned by the slave device within the valid time of the chip select signal.

[0064] In the above methods, in the field of industrial control, when the distance between the master device and the slave device is far, the form of bus connection such as SPI bus cannot guarantee that the communication with the slave device will be completed within the effective time of the chip select signal. That is, the communication success rate between the master and slave devices is low, and it is impossible to achieve precise remote control of the slave device by the master device.

[0065] In view of this, embodiments of the present invention provide a long-distance communication method between master and slave devices. This method uses a high-speed serial transceiver combined with optical communication to replace the original bus connection method, improving data transmission rate. Furthermore, before communication between the master and slave devices, the communication latency of the transmission link is tested, and data communication only proceeds when the communication latency is within a reasonable range. This approach controls the communication latency of the transmission link between master and slave devices during long-distance transmission and improves the data transmission rate. This ensures that data communication is completed within the time frame of the chip select signal, increasing the success rate of long-distance communication between master and slave devices, and ultimately enabling precise remote control of the slave device by the master device.

[0066] Figure 3 This is a schematic diagram illustrating an application scenario provided by an embodiment of the present invention. For example... Figure 3 As shown, the master device includes a processor, an FPGA, and at least one optical module. The FPGA includes at least one high-speed serial transceiver (Gigabit Transceiver, GT). The processor and FPGA are connected via a local bus. Each high-speed serial transceiver is connected to one optical module, and each optical module is connected to one slave device. It should be noted that... Figure 3 This is just an example illustrating three slave devices; the present invention does not limit the number of slave devices.

[0067] The aforementioned master device is used to send control commands to the slave device and process the data returned by the slave device.

[0068] The aforementioned processor is the core control unit, responsible for executing instructions, processing data, and coordinating the operation of various parts of the system. This processor can be a Central Processing Unit (CPU), possessing powerful computing and multitasking capabilities, capable of executing complex algorithms and logical operations. Alternatively, it can be a Graphics Processing Unit (GPU), used for handling graphics-intensive tasks such as games, 3D rendering, and video editing.

[0069] The aforementioned FPGA is a programmable logic device that allows users to configure logic circuits according to their needs. It can be used to implement functions such as data packetization and depacketization, and scrambling and descrambling. This FPGA has multiple high-speed serial transceivers that support high-speed serial data transmission. The execution entity of this embodiment of the invention can be the FPGA of the main device.

[0070] It should be noted that FPGAs can integrate various types of high-speed transceivers depending on the device type. For example, they can integrate one or more high-speed serial transceivers, such as Gigabit Transceivers with Low Power (GTP), Gigabit Transceivers from Xilinx 7 series FPGAs (GTX), Gigabit Transceivers High Speed ​​(GTH), and Gigabit Transceivers Zero Latency (GTZ). Their main difference lies in the supported line rates, with the order being GTZ > GTH > GTX > GTP. All four types of transceivers feature high-speed transmission and multi-protocol support, making them suitable for different application scenarios and transmission rate requirements. This embodiment of the invention does not limit the type of high-speed serial transceiver; the specific type can be configured according to actual needs.

[0071] The aforementioned optical modules are used to convert electrical signals into optical signals for transmission, or to convert optical signals into electrical signals for reception. In this master device, the optical modules can be connected one-to-one with the high-speed serial transceivers of the FPGA, forming a high-speed serial communication link. They are then connected to slave devices via optical fibers, realizing a long-distance, high-speed, low-latency data transmission link between the master and slave devices.

[0072] The aforementioned device is used to perform data read and write operations.

[0073] In some embodiments, Figure 4 This is a schematic diagram of a main device provided according to an embodiment of the present invention. Figure 4 As shown, the aforementioned main device includes a processor, an FPGA, and at least one optical module. The FPGA of the main device includes a control module, a training module, at least one processing module, and at least one high-speed serial transceiver. The control module is connected to the processor, training module, processing module, and multiplexer, respectively. The training module and processing module are connected to the multiplexer, which is connected to the high-speed serial transceiver. It should be noted that... Figure 4 This example only illustrates the use of three processing modules and three high-speed serial transceivers. The number of processing modules and high-speed serial transceivers in this embodiment of the invention is not limited.

[0074] The aforementioned control module receives various instructions and bus signals from the processor, enabling bidirectional communication between the FPGA and the processor, and providing unified management and control for the training and processing modules within the FPGA. For example, it instructs the training module to perform link testing or notifies the processing module to perform data processing, ensuring that all modules work collaboratively according to system requirements.

[0075] The training module described above is used to test the latency of the transmission link between the master device and the slave device before data communication.

[0076] The aforementioned processing modules are used to process the bus signals issued by the processor to obtain data packets that can be adapted to the high-speed serial transceiver. Each processing module is configured with a clock domain, which can correspond to the clock domain of the high-speed serial transceiver.

[0077] In some possible implementations, the above-mentioned processing module can be connected one-to-one with a high-speed serial transceiver. In this way, due to the one-to-one correspondence, there is no need to determine the processing module, thereby improving the data processing rate. Alternatively, the processing module can correspond to multiple high-speed serial transceivers. For example, when the transmission rates of multiple high-speed serial transceivers are consistent, this method can reduce the number of processing modules required and save FPGA overhead.

[0078] In this scenario, the multiplexer can either select the path between the training module and the high-speed serial transceiver, allowing the training module to test the transmission link; or, select the path between the processing unit and the high-speed serial transceiver, enabling normal data communication between the master and slave devices.

[0079] It should be noted that FPGA allows users to configure programmable logic units and programmable connection resources based on programming, thereby realizing the logic functions set by the user. The aforementioned control module, training module and processing module can be divided based on logic functions.

[0080] It should be noted that the embodiments of the present invention do not limit the structure of the slave device, and the structure of the master device can be referred to for corresponding settings.

[0081] In some embodiments, the slave device can be an independent controller or industrial computer, and the slave device can be a sensor, actuator, frequency converter, motor, etc. Through the long-distance communication method between master and slave devices provided in this embodiment of the invention, the master device can be responsible for sending control commands and receiving status information, while the slave device can be responsible for executing actions and feeding back status information, thereby realizing precise control and monitoring of industrial processes in the field of industrial control.

[0082] Figure 5 A flowchart illustrating a long-distance communication method between master and slave devices according to an embodiment of the present invention. (See reference...) Figure 3 and Figure 5 As shown, the method includes:

[0083] S101. In response to the test command, determine the target high-speed serial transceiver and target optical module corresponding to the target device indicated by the test command.

[0084] For example, the target slave device refers to the slave device to which data communication is to be performed, and the target high-speed serial transceiver and target optical module refer to the serial transceiver and optical module connected to the target slave device. The test instruction is used to instruct the testing of the latency of the transmission link between the target slave device and the master device. The test instruction may include the identifier of the target slave device, which may be, for example, a device ID, or a code assigned to the slave device by the master device's processor. This application does not limit this, as long as it can uniquely identify the slave device.

[0085] In some possible implementations, the test command can be sent by the master device's processor. For example, the master device's processor can generate the test command and send it to the FPGA before data communication with the target slave device. The test command can also be user-triggered. For example, the master device can have a button, and the master device's FPGA can receive the test command generated by the user triggering the button.

[0086] In one example, the FPGA of the master device can store a mapping table that indicates the correspondence between the identifier of the slave device and the high-speed serial transceiver and the optical module. Therefore, the FPGA of the master device can respond to the test command and determine the target high-speed serial transceiver and the target optical module connected to the target slave device according to the identifier and configuration information of the target slave device indicated in the test command.

[0087] S102. Based on the target high-speed serial transceiver and the target optical module, send the first data packet to the target slave device and receive the response packet returned by the target slave device.

[0088] For example, the first data packet is used for transmission link latency testing, and the response packet is a data packet returned by the device after receiving the first data packet. It should be noted that this embodiment of the invention does not limit the content and format of the first data packet and the response packet. (See reference...) Figure 6 As shown, Figure 6 This is a schematic diagram of a frame format provided in an embodiment of the present invention. The data frame includes a frame header and an identifier bit. The frame formats of the first data packet and the response packet can both adopt... Figure 6 The structure shown.

[0089] In one example, the FPGA of the master device can send M first data packets to the target slave device based on the target high-speed serial transceiver and the target optical module, and receive response packets returned by the target slave device. For example, after receiving N first data packets, the target slave device can return N response packets to the master device, where M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and N is less than or equal to M.

[0090] S103. Based on the response packet, determine whether the transmission delay of the communication link between the master device and the target slave device is within the preset range.

[0091] In some possible implementations, the FPGA of the master device can pre-set the correspondence between the number of response packets and the transmission delay. Then, the FPGA of the master device can determine whether the transmission delay of the communication link between the master device and the target slave device is within the preset range based on the number of received response packets.

[0092] For example, the minimum number of response packets corresponding to a transmission delay within a preset range can be set to P. If the FPGA of the master device receives at least P response packets continuously within a preset time, it can be determined that the transmission delay of the communication link between the master device and the target slave device is within the preset range, and step S104 is executed. If the FPGA of the master device receives less than P response packets continuously within a preset time, the FPGA of the master device can return a prompt message indicating high transmission link delay to the processor. Alternatively, after waiting for a preset interval, the first data packet is retransmitted, that is, steps S102 and S103 are executed again to determine whether the transmission delay is within the preset range. If it is determined again that the transmission delay is not within the preset range, a prompt message indicating that the transmission link needs to be checked is returned to the processor.

[0093] In some possible implementations, the first data packet and the response packet may include a timestamp. The FPGA of the master device can calculate the transmission link delay between the master device and the target slave device based on the timestamp of the first data packet and the response packet, and then determine whether the calculated transmission delay is within the preset transmission delay range.

[0094] Optionally, after determining that the transmission delay of the communication link between the master device and the target slave device is within a preset range, a test success message can be returned to the processor. After receiving the test success message, the processor can send a bus signal to the FPGA.

[0095] This method ensures that when the transmission link delay is within a preset range, data communication can be completed within the effective time of the chip select signal, thus guaranteeing the completion of data communication.

[0096] S104. In response to the bus signal, generate a second data packet.

[0097] For example, the aforementioned bus signal is used to indicate the transmission of data to the target slave device. This bus signal may include control signals, service data, read / write addresses, and chip select signals, etc. The aforementioned second data packet may include control signals, service data, and read / write addresses, etc. It should be noted that this embodiment of the invention does not limit the content and format of the second data packet. (See reference...) Figure 7 As shown, Figure 7This is a schematic diagram of another frame format provided in an embodiment of the present invention. The data frame includes a frame header, a control field, an address field, a check field, and a data field. The frame format of the aforementioned second data packet can adopt... Figure 7 The structure shown. (Through) Figure 3 As shown in the structure, the optical module can be connected to a slave device in a one-to-one correspondence. Figure 7 The frame structure shown removes fields such as source IP address and destination IP address, which can improve the data packet transmission rate.

[0098] In one example, the FPGA of the master device can generate a second data packet based on the received bus signals and the preset frame format. For example, based on the control signals in the bus signals, it can determine whether it is reading or writing data, and write the corresponding code into the field corresponding to the control signal in the preset frame format. Other fields are similar and will not be exemplified one by one here. Finally, the second data packet is obtained.

[0099] S105. Send a second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0100] For example, the generated second data packet is transmitted to the target slave device via the target high-speed serial transceiver, converted into an optical signal by the target optical module, and then transmitted through an optical fiber.

[0101] The long-distance communication method between master and slave devices provided in this embodiment of the invention includes at least one optical module and an FPGA master device, wherein the FPGA includes at least one high-speed serial transceiver connected to at least one optical module; before the master device and the target slave device conduct long-distance communication, a first data packet is sent to the target slave device based on the target high-speed serial transceiver and the target optical module corresponding to the target slave device, and the transmission link delay between the target slave device and the master device is determined according to the response packet returned by the target slave device. When the transmission link delay is determined to be within a preset range, the FPGA of the master device generates a second data packet according to the received bus signal, and sends it to the target slave device based on the target high-speed serial transceiver and the target optical module corresponding to the target slave device, thereby realizing long-distance communication between the master device and the target slave device.

[0102] This method utilizes a high-speed serializer and optical modules to form a high-speed transmission link, improving the transmission rate between the master and slave devices. Furthermore, the transmission link latency is tested before data communication, ensuring that data communication only occurs when the latency is within a preset range. This guarantees that data communication can be completed within the effective time of the chip select signal, thus improving the success rate of data communication. This approach ensures long-distance communication between the master and slave devices, enabling precise remote control of the slave devices by the master. It is suitable for scenarios in industrial control where high precision control is required, such as real-time monitoring and control of automated production lines.

[0103] Figure 8 A flowchart illustrating a long-distance communication method between master and slave devices according to an embodiment of the present invention. (See reference...) Figure 3 and Figure 8 As shown, in this embodiment... Figure 4 Based on the illustrated embodiments, the long-distance communication method between master and slave devices provided by the present invention will be further described. The method includes:

[0104] S201. In response to the test command, determine the target high-speed serial transceiver and target optical module corresponding to the target device indicated by the test command.

[0105] For example, the test command can be sent by the processor of the master device. Before communicating with the target slave device, the processor of the master device can generate a test command and send it to the FPGA of the master device via the local bus. When the control module recognizes the command as a test command, the FPGA can pass the test command to the training module of the FPGA. Based on the training module, the FPGA can determine the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command. For details on how to determine the target high-speed serial transceiver and target optical module, please refer to the description of step S101 above, which will not be repeated here.

[0106] S202. Determine the test cases corresponding to the target device.

[0107] For example, the above test case is used to indicate the number M of the first data packets sent by the target device; where M is an integer greater than or equal to 1.

[0108] In one example, considering the varying distances and latency of subsequent transmission links between slave and master devices, different test cases can be set for different slave devices. Each test case can indicate the number of first data packets the corresponding slave device needs to send during link testing, and the minimum number of response packets to be received within a preset time. For example, a mapping relationship between slave device identifiers and test cases can be preset in the FPGA. Therefore, after receiving the test command, the FPGA training module can determine the test case corresponding to the target slave device based on the identifier of the target slave device indicated in the test command and the mapping relationship.

[0109] This method allows for the use of appropriate test cases to test different slave devices, ensuring the accuracy of transmission latency obtained in subsequent tests.

[0110] S203, Control the multiplexer to turn on the path between the training module and the target high-speed serial transceiver.

[0111] For example, after receiving a test command, the FPGA control module can generate a first control signal to control the multiplexer to connect the training module and the target high-speed serial transceiver. This first control signal can indicate the connection between the training module and the target high-speed serial transceiver. It should be noted that this embodiment of the invention does not limit the execution order of this step.

[0112] S204. Based on the target high-speed serial transceiver and the target optical module, send M first data packets to the target slave device.

[0113] For example, the FPGA training module can determine the number of first data packets to be sent based on the test cases corresponding to the target slave device, and then continuously send M first data packets to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0114] S205. Receive the response packet returned by the target from the device.

[0115] For example, after receiving N first data packets sent by the master device, the target slave device can return K response packets to the master device, where N and K are both integers greater than or equal to 1, and both are less than M.

[0116] S206. Based on the test cases, determine whether the number of response packets received within the preset time period is greater than or equal to P.

[0117] For example, the test case is used to indicate the minimum number P of response packets to be received corresponding to the target slave device; P is a positive integer greater than or equal to 1, and P is less than or equal to M. In this way, the FPGA can accurately determine the minimum number of response packets to be received corresponding to the target slave device based on the test case, that is, determine the latency range of the transmission link corresponding to the target slave device.

[0118] If the number of received response packets K is greater than or equal to P, the transmission delay of the communication link between the master device and the target slave device is determined to be within the preset range. The FPGA-based control module returns a test success message to the processor and executes step S207. If the number of received response packets K is less than P, the transmission delay of the communication link between the master device and the target slave device is determined to be outside the preset range. The FPGA-based control module returns a test failure message to the processor.

[0119] S207. In response to the bus signal issued by the processor in the master device, determine the target processing module corresponding to the target slave device.

[0120] For example, after receiving a successful test notification from the FPGA, the processor sends a bus signal to the FPGA via the local bus. This bus signal can be either service data to be read from the target slave device or service data to be written to the target slave device. Upon receiving the bus signal, the FPGA's control module determines the target processing module corresponding to the target slave device based on the identifier indicated by the bus signal, and then transmits the bus signal to that target processing module for processing.

[0121] As mentioned above, an FPGA can be configured with multiple processing modules, each with its own clock domain. Since there is a one-to-one correspondence between the target high-speed serial transceiver and the target slave device, and the speed of the target high-speed serial transceiver needs to be set to correspond with the clock domain of the processing module, the target processing module that matches the target high-speed serial transceiver corresponding to the target slave device can be selected to process the bus signals based on the identifier of the target slave device, thereby improving the data processing rate.

[0122] S208. Based on the clock domain of the target processing module, the bus signal is converted to obtain the converted bus signal.

[0123] For example, the clock domain of the converted bus signal is consistent with the clock domain of the target high-speed serial transceiver. It should be noted that the difference between the different clock domains can be a multiple of the clock frequency, a phase shift, etc. The target processing module can configure the clock domain conversion logic in advance according to the clock domain of the processor and the clock domain of the target high-speed serial transceiver.

[0124] For example, the target processing module of an FPGA, under the control of the original clock domain (the processor's clock domain), can follow the rising or falling edge triggering rules of the original clock domain to store bus signals into the dual-port random access memory (DRAM) cycle by cycle through the write port. Simultaneously, under the clock domain of the target processing module, data is read from the DRAM's read port according to its clock triggering rules. During reading, data is retrieved in an orderly manner according to the pre-set storage capacity and data width, achieving synchronous data transfer from the original clock domain of the bus signals to the clock domain of the target processing module.

[0125] S209. Generate a second data packet based on the converted bus signal.

[0126] For example, the target processing module of an FPGA can generate a second data packet based on a preset frame format and the converted bus signal.

[0127] Optionally, the FPGA's target processing module can generate an initial second data packet based on the converted bus signal and a preset frame format; wherein the preset frame format includes a frame header, control field, address field, check field, and data field; and scramble the initial second data packet to obtain the second data packet.

[0128] For example, the target processing module of the FPGA can be based on, for example, Figure 7 The frame format shown generates an initial second data packet. Then, a preset polynomial is used to XOR the data in the initial data packet, excluding the frame header, to obtain scrambling data. This scrambling data and the frame header are then combined to form the second data packet. This method increases the randomness of the data in the second data packet, making data transitions more frequent and improving data anti-interference capabilities. It also facilitates the recovery of an accurate data clock from the slave device using Clock Data Recovery (CDR) technology.

[0129] It should be understood that high-speed serial transceivers do not transmit the on-line clock. However, due to the frequency offset between the master and slave devices' clocks, the receiver cannot directly use its local clock for data sampling. It needs to utilize CDR (Continuous Data Retrieval) technology to recover the accurate data clock from the transmitting side to ensure data accuracy. CDR technology infers the clock signal based on the rising and falling edges of the data, thus requiring more frequent data transitions to ensure stable clock recovery. Therefore, scrambling ensures more random data transitions and more frequent transitions.

[0130] It should be noted that the initial state of the preset polynomial is the same in the master device and the slave device, ensuring that the second data packet can be correctly descrambled in the slave device.

[0131] S210, controls the multiplexer to connect the target processing module and the target high-speed serial transceiver.

[0132] For example, after receiving the bus signal, the FPGA control module can generate a second control signal to control the multiplexer to connect the target processing module and the target high-speed serial transceiver. It should be noted that this second control signal can indicate the target processing module and the target high-speed serial transceiver. This embodiment of the invention does not limit the execution order of this step.

[0133] S211. Send a second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0134] For example, the target processing module of the FPGA will generate a second data packet, which will be converted into an optical signal by the target high-speed serial transceiver and then sent to the target slave device through an optical fiber.

[0135] In some embodiments, in response to configuration instructions, the FPGA control module can configure a new high-speed serial transceiver in the FPGA; wherein the new high-speed serial transceiver is configured with a clock domain; if it is determined that the clock domain of a processing module is consistent with the clock domain of the new high-speed serial transceiver, then a correspondence between the processing module and the new high-speed serial transceiver is established. This method can reduce the number of processing modules and save FPGA computing resources.

[0136] In some embodiments, if the processor does not send a bus signal after a successful test, the target processing module of the FPGA can send an idle packet to the target slave device based on the target high-speed serial transceiver and the target optical module. The frame format of the idle packet can refer to the frame format of the aforementioned first data packet, and the present invention does not limit it.

[0137] In some embodiments, taking a read operation as an example, the target slave device recovers the clock signal from the received second data packet, converts the parallel data into serial data, finds the frame header 16'hF628 through cyclic shifting, descrambles the data according to the shifted format, parses the descrambled data to obtain the read instruction and read address, assembles and scrambles the register data at the corresponding address to generate a third data packet, and returns it to the master device. The third data packet received by the target optical module of the master device is input to the target high-speed serial transceiver of the master device FPGA. The target high-speed serial transceiver recovers the clock and converts the parallel data into serial data, which is then input to the target processing module of the FPGA. The target processing module finds the frame header 16'hF628 through cyclic shifting, descrambles the data according to the shifted format, parses the descrambled data to obtain the read data, and inputs it to the control module of the FPGA. If the chip select signal is still valid at this time, the read data is sent to the processor based on the local bus; otherwise, the read operation fails.

[0138] The long-distance communication method between master and slave devices provided in this invention includes at least one optical module and an FPGA master device, wherein the FPGA includes at least one high-speed serial transceiver connected to at least one optical module. Before the master device and the target slave device conduct long-distance communication, the FPGA training module can first send M first data packets to the target slave device based on the test cases corresponding to the target slave device, as well as the target high-speed serial transceiver and the target optical module corresponding to the target slave device. According to the test cases, it is determined whether the number of received response packets meets the latency requirements of the target slave device. When it is determined that the latency of the transmission link is within a preset range, the FPGA control module of the master device can determine the target processing module corresponding to the target slave device based on the received bus signal, so as to select a matching target processing module to perform clock domain conversion processing on the bus signal to obtain the converted bus signal and generate a second data packet. The second data packet is sent to the target slave device based on the target high-speed serial transceiver and the target optical module corresponding to the target slave device, thereby realizing long-distance communication between the master device and the target slave device.

[0139] This approach achieves several advantages. First, it utilizes a high-speed serializer and optical module to establish a high-speed transmission link between the master and slave devices, increasing their transmission rate. Second, before data communication, the master device's FPGA can select test cases corresponding to the target slave device to test the transmission link's latency, improving the accuracy of latency testing. This ensures that data communication only occurs when the latency is within a preset range, guaranteeing that data communication can be completed within the effective time of the chip select signal. Third, during data communication, the master device's FPGA can select a target processing module whose clock domain matches that of the target high-speed serial transceiver for data processing, increasing the data processing speed. This combination of measures ensures that data communication can be completed within the effective time of the chip select signal, improving the success rate of long-distance data communication between the master and slave devices, and ultimately enabling precise long-distance control of the slave device by the master device.

[0140] Figure 9 This is a schematic diagram of the structure of a long-distance communication device between master and slave devices according to an embodiment of the present invention, as shown below. Figure 9 As shown, the long-distance communication device 300 between master and slave devices in this embodiment of the invention includes:

[0141] Training module 301 is configured to respond to a test command, determine the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command; send a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receive a response packet returned by the target slave device; wherein, the first data packet is used for link testing;

[0142] The processing module 302 is configured to, when determining, based on the response packet, that the transmission delay of the communication link between the master device and the target slave device is within a preset range, generate a second data packet in response to a bus signal, wherein the bus signal is used to indicate the transmission of data to the target slave device; and send the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0143] In some possible implementations, the FPGA further includes at least one processing module connected to the high-speed serial transceiver; the high-speed serial transceiver is connected one-to-one with the optical module, and the optical module is connected one-to-one with the slave device; a control module is used to determine the target processing module corresponding to the target slave device in response to a bus signal issued by the processor in the master device.

[0144] Processing module 302 is used to perform conversion processing on the bus signal based on the clock domain of the target processing module to obtain a converted bus signal; wherein the clock domain of the converted bus signal is consistent with the clock domain of the target high-speed serial transceiver; and to generate the second data packet according to the converted bus signal.

[0145] In some possible implementations, processing module 302 is specifically used for:

[0146] Based on the converted bus signal and the preset frame format, an initial second data packet is generated; wherein the preset frame format includes a frame header, a control field, an address field, a check field, and a data field.

[0147] The initial second data packet is scrambled to obtain the second data packet.

[0148] In some possible implementations, the processing module is connected to the high-speed serial transceiver via a multiplexer; before the processing module 302 sends the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, the control module controls the multiplexer to open the path between the target processing module and the target high-speed serial transceiver.

[0149] In some possible implementations, a control module is configured in the FPGA to configure a new high-speed serial transceiver in response to a configuration command; wherein the new high-speed serial transceiver is configured with a clock domain; if it is determined that the clock domain of a processing module is consistent with the clock domain of the new high-speed serial transceiver, then a correspondence between the processing module and the new high-speed serial transceiver is established.

[0150] In some possible implementations, the FPGA includes a training module connected to a high-speed serial transceiver via a multiplexer; the high-speed serial transceiver is connected one-to-one with the optical module, and the optical module is connected one-to-one with the slave device; a control module is used to determine test cases corresponding to the target slave device; wherein the test cases are used to indicate the number M of first data packets sent corresponding to the target slave device; wherein M is an integer greater than or equal to 1; and to control the multiplexer to open the path between the training module and the target high-speed serial transceiver.

[0151] The training module 301 is specifically used to send M first data packets to the target slave device based on the target high-speed serial transceiver and the target optical module.

[0152] In some possible implementations, the test case is used to indicate the minimum number P of response packets received by the target slave device; P is an integer greater than or equal to 1, and P is less than or equal to M; determining that the transmission delay of the communication link between the master device and the target slave device is within a preset range based on the response packets includes:

[0153] The training module 301 is specifically used to determine, based on the test cases, that if the number of response packets received within a preset time period is greater than or equal to P, the transmission delay of the communication link between the master device and the target slave device is within a preset range.

[0154] The apparatus of this invention can be used to execute the technical solutions of any of the method embodiments shown above. Its implementation principle and technical effect are similar, and will not be repeated here.

[0155] Figure 10 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention. Figure 10 As shown, the electronic device 400 may include a processor 401, a memory 402, and a field-programmable gate array (FPGA) 403. This electronic device may be the aforementioned main device.

[0156] The memory 402 is used to store programs. Specifically, the program may include program code, which includes computer-executable instructions.

[0157] The memory 402 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0158] FPGA403 is used to execute computer execution instructions stored in memory402 to implement the long-distance communication method between master and slave devices described in the foregoing method embodiments.

[0159] Optionally, the electronic device 400 may also include a communication interface 404. In specific implementations, if the communication interface 404, FPGA 403, memory 402, and processor 401 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0160] Optionally, in a specific implementation, if the communication interface 404, FPGA 403, memory 402 and processor 401 are integrated on a single chip, then the communication interface 404, FPGA 403, memory 402 and processor 401 can communicate through an internal interface.

[0161] The present invention also provides a computer-readable storage medium storing computer program instructions, which, when executed by the FPGA, implements the above-described long-distance communication method between master and slave devices.

[0162] The present invention also provides a computer program product, including a computer program that, when executed by an FPGA, implements the above-described long-distance communication method between master and slave devices.

[0163] The aforementioned computer-readable storage media can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0164] An exemplary readable storage medium is coupled to a processor, enabling an FPGA to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the FPGA. The FPGA and the readable storage medium can reside within an application-specific integrated circuit (ASIC). Alternatively, the FPGA and the readable storage medium can exist as discrete components in a long-distance communication device between master and slave devices.

[0165] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0166] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A long-distance communication method between master and slave devices, characterized in that, The method is applied to a field-programmable gate array (FPGA) of a main device, wherein the FPGA includes at least one high-speed serial transceiver, and the main device also includes at least one optical module, wherein the high-speed serial transceiver is connected to the optical module; the method includes: In response to a test command, the system determines the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command; it sends a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receives a response packet returned by the target slave device; wherein, the first data packet is used for link testing; If, based on the response packet, it is determined that the transmission delay of the communication link between the master device and the target slave device is within a preset range, then in response to the bus signal, a second data packet is generated, the bus signal being used to indicate the transmission of data to the target slave device; and the second data packet is sent to the target slave device based on the target high-speed serial transceiver and the target optical module.

2. The method according to claim 1, characterized in that, The FPGA also includes at least one processing module, which is connected to the high-speed serial transceiver; the high-speed serial transceiver is connected to the optical module in a one-to-one correspondence, and the optical module is connected to the slave device in a one-to-one correspondence. Each processing module is configured with a clock domain, which, in response to a bus signal, generates a second data packet, including: In response to a bus signal issued by the processor in the master device, a target processing module corresponding to the target slave device is determined; Based on the clock domain of the target processing module, the bus signal is converted to obtain a converted bus signal; wherein, the clock domain of the converted bus signal is consistent with the clock domain of the target high-speed serial transceiver; The second data packet is generated based on the converted bus signal.

3. The method according to claim 2, characterized in that, The step of generating the second data packet based on the converted bus signal includes: Based on the converted bus signal and the preset frame format, an initial second data packet is generated; wherein the preset frame format includes a frame header, a control field, an address field, a check field, and a data field. The initial second data packet is scrambled to obtain the second data packet.

4. The method according to claim 2, characterized in that, The processing module is connected to the high-speed serial transceiver via a multiplexer; before sending the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, it further includes: The multiplexer is controlled to open the path between the target processing module and the target high-speed serial transceiver.

5. The method according to claim 2, characterized in that, The method further includes: In response to a configuration command, a new high-speed serial transceiver is configured in the FPGA; wherein the new high-speed serial transceiver is configured with a clock domain. If it is determined that the clock domain of a processing module is consistent with the clock domain of the new high-speed serial transceiver, then a correspondence between the processing module and the new high-speed serial transceiver is established.

6. The method according to any one of claims 1-5, characterized in that, The FPGA includes a training module, which is connected to a high-speed serial transceiver via a multiplexer; the high-speed serial transceiver is connected to the optical module in a one-to-one correspondence, and the optical module is connected to the slave device in a one-to-one correspondence. Based on the target high-speed serial transceiver and the target optical module, a first data packet is sent to the target slave device, including: Determine the test cases corresponding to the target slave device; wherein the test cases are used to indicate the number M of first data packets sent corresponding to the target slave device; wherein M is an integer greater than or equal to 1; Control the multiplexer to open the path between the training module and the target high-speed serial transceiver; Based on the target high-speed serial transceiver and the target optical module, M first data packets are sent to the target slave device.

7. The method according to claim 6, characterized in that, The test case is used to indicate the minimum number P of response packets that the target can receive from the device; P is an integer greater than or equal to 1, and P is less than or equal to M; The step of determining that the transmission delay of the communication link between the master device and the target slave device is within a preset range based on the response packet includes: According to the test case, if it is determined that the number of response packets received within a preset time period is greater than or equal to P, then it is determined that the transmission delay of the communication link between the master device and the target slave device is within a preset range.

8. A long-distance communication device between master and slave devices, characterized in that, The device is applied to a field-programmable gate array (FPGA) of a main device, the FPGA including at least one high-speed serial transceiver, and the main device also includes at least one optical module, the high-speed serial transceiver being connected to the optical module; the device includes: The training module is used to respond to a test command, determine the target high-speed serial transceiver and target optical module corresponding to the target slave device indicated by the test command; send a first data packet to the target slave device based on the target high-speed serial transceiver and the target optical module, and receive a response packet returned by the target slave device; wherein, the first data packet is used for link testing; The processing module is configured to, when determining, based on the response packet, that the transmission delay of the communication link between the master device and the target slave device is within a preset range, generate a second data packet in response to a bus signal, wherein the bus signal is used to indicate the transmission of data to the target slave device; and send the second data packet to the target slave device based on the target high-speed serial transceiver and the target optical module.

9. An electronic device, characterized in that, include: Processors, memory, and field-programmable gate arrays (FPGAs); The memory stores computer-executed instructions; The FPGA executes computer execution instructions stored in the memory, causing the FPGA to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a field-programmable gate array, are used to implement the method as described in any one of claims 1-7.

11. A computer program product, characterized in that, Includes a computer program that, when executed by a field-programmable gate array, implements the method of any one of claims 1-7.

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