Data transmission method and display device

Abstract

The application discloses a data transmission method and a display device. The method comprises the following steps: outputting a differential dimming signal and a differential clock signal through a display controller, wherein the differential dimming signal is used for carrying dimming data corresponding to a frame of image; receiving the differential dimming signal and the differential clock signal through a dimming controller, and generating target dimming data for backlight control based on the differential dimming signal and the differential clock signal. The dimming data and the clock signal are transmitted in the form of differential signals, so that the data transmission rate can be effectively improved, the layout wiring in the panel can be simplified, the product cost can be optimized, and in addition, the transmission mode of the differential signal can effectively reduce the electromagnetic interference problem and improve the display performance of the equipment.

Description

A data transmission method and a display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a data transmission method and a display device. Background Technology

[0002] With the rapid development of display technology, high frame rates and high resolutions have become the core directions for upgrading the performance of display devices. While high-performance display devices improve the smoothness, detail, and contrast of images, they also bring about a significant increase in the complexity of processing and transmitting display-related data, which places higher demands on the data transmission efficiency within the display device.

[0003] Currently, display devices mostly employ local dimming technology to achieve precise backlight control, and the communication between the dimming controller and its front-end chip (such as a timing controller) is a crucial aspect of this technology's implementation. In existing design architectures, the dimming controller and its front-end chip communicate via a Serial Peripheral Interface (SPI) bus to transmit local dimming data using the SPI protocol. Furthermore, to meet the massive dimming data transmission requirements of high-performance display devices, a single dimming controller typically needs to be connected to 2-4 SPI buses in parallel.

[0004] However, the SPI bus typically includes multiple basic signal lines, which are used to transmit chip select, clock, and data signals respectively. Data interaction is achieved through the coordinated operation of these basic signal lines. Therefore, when a single dimming controller is connected to multiple SPI buses, the number of signal lines between the dimming controller and its upstream chips increases proportionally. This directly leads to increased internal wiring complexity, occupies more space, and the excessive number of signal lines exacerbates electromagnetic interference (EMI) problems, reduces signal integrity, and ultimately affects the overall performance of the display device. Summary of the Invention

[0005] This application provides a data transmission method and a display device to solve the problems of complex internal wiring, low transmission efficiency, and strong electromagnetic interference in the process of transmitting dimming data between the dimming controller and its front-end chip in the prior art.

[0006] In a first aspect, this application provides a data transmission method applied to a display device, the display device including a display controller and a dimming controller, the display controller and the dimming controller being electrically connected, the method comprising:

[0007] The display controller outputs a differential dimming signal and a differential clock signal, wherein the differential dimming signal is used to carry the dimming data corresponding to one frame of image;

[0008] The dimming controller receives differential dimming signals and differential clock signals, and generates target dimming data for backlight control based on the differential dimming signals and differential clock signals.

[0009] Secondly, this application provides a display device, including a display controller and at least one dimming controller, wherein the display controller is electrically connected to the dimming controller, and:

[0010] The display controller is used to output differential dimming signals and differential clock signals, wherein the differential dimming signals are used to carry dimming data corresponding to a frame of image;

[0011] The dimming controller is used to: receive differential dimming signals and differential clock signals, and generate target dimming data for backlight control based on the differential dimming signals and differential clock signals.

[0012] The beneficial effects of the embodiments of this application are as follows:

[0013] The data transmission method and display device provided in this application transmit dimming data and clock signals between the display controller and the dimming controller by transmitting differential dimming signals and differential clock signals. Compared with the prior art's use of the SPI protocol to transmit dimming data, the method of transmitting dimming data using differential signals in this application can effectively improve the data transmission rate and better meet the transmission needs of massive dimming data. Furthermore, using differential signals for the transmission of dimming data and clock signals only requires connecting four differential signal lines between each dimming controller and the display controller. This reduces the number of traces, simplifies the board layout, reduces the size of the connectors used to connect the dimming controller and the display controller, decreases the number of pins, and optimizes product costs. Moreover, since differential signals transmit effective information (i.e., dimming data) based on the difference between two signals, the voltage variation amplitude of the differential dimming signals used to transmit dimming data in this application is smaller. This reduction in voltage variation amplitude effectively reduces the degree of electromagnetic wave emission, effectively reducing electromagnetic interference problems and thus improving the display performance of the device. Attached Figure Description

[0014] Figure 1A is a schematic diagram of the structure of a display device provided by related technologies;

[0015] Figure 1B is a schematic diagram of the structure of another display device provided by related technologies;

[0016] Figure 2 is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0017] Figure 3 is a schematic diagram of the workflow of a data transmission method provided in an embodiment of this application;

[0018] Figure 4 is a structural schematic diagram of another display device provided in an embodiment of this application;

[0019] Figure 5A is a schematic diagram of the structure of a display controller provided in an embodiment of this application;

[0020] Figure 5B is a schematic diagram of another display controller provided in an embodiment of this application;

[0021] Figure 6 is a schematic diagram of the structure of a first dimming signal provided in an embodiment of this application;

[0022] Figure 7A is a schematic diagram of a dimming controller provided in an embodiment of this application;

[0023] Figure 7B is a schematic diagram of another dimming controller provided in an embodiment of this application;

[0024] Figure 8A is a schematic diagram of the structure of another display device provided in an embodiment of this application;

[0025] Figure 8B is a schematic diagram of the structure of another display device provided in an embodiment of this application;

[0026] Figure 9A is a schematic diagram of another dimming controller provided in an embodiment of this application;

[0027] Figure 9B is a schematic diagram of another dimming controller provided in an embodiment of this application;

[0028] Figure 10 is a schematic diagram of the workflow of a dimming controller generating target dimming data according to an embodiment of this application;

[0029] Figure 11 is a schematic diagram of the structure of a second target signal segment provided in an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0031] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0032] Referring to Figures 1A and 1B, in a conventional display device 1, the dimming data generation module 11 (which may be a timing controller, system-on-a-chip, etc.) communicates with the dimming controller 12 via an SPI bus L1 to transmit dimming data based on the SPI protocol. However, this method of transmitting dimming data based on the SPI bus typically has a data transmission rate of only 5MHz-10MHz, which is relatively slow. Therefore, to meet the transmission requirements of large amounts of dimming data in high-performance display devices, the number of SPI buses is increased.

[0033] Specifically, referring to Figures 1A and 1B, multiple SPI buses are configured in parallel between the dimming data generation module 11 and a dimming controller 12. An SPI bus L1 typically includes multiple basic signal lines L11, such as lines for transmitting chip select (CS), clock (Clk), and data single (DS) signals, and may even include lines for transmitting vertical synchronization (VSync) signals. Dimming data transmission is achieved through the coordinated operation of these multiple basic signal lines.

[0034] However, this leads to a significant increase in the number of signal lines between the dimming controller 12 and the dimming data generation module 11. As shown in Figure 1B, n SPI buses connect the dimming data generation module 11 and a dimming controller 12, resulting in at least 3n signal lines between them. This connection architecture directly increases the complexity of internal wiring and occupies more space; it also leads to larger connectors, increased product costs, and is not conducive to miniaturization design; furthermore, excessive signal lines exacerbate electromagnetic interference problems, reduce signal integrity, and ultimately affect overall display performance.

[0035] In view of this, embodiments of this application provide a data transmission method and a display device. By utilizing a high-speed differential driving method to transmit dimming data, the data transmission efficiency is increased, while the number of traces between the dimming controller and its front-end chip is reduced, thereby simplifying the internal wiring of the device, reducing electromagnetic interference problems, and effectively improving the overall performance of the display device.

[0036] The objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features described herein can be combined with each other without conflict.

[0037] The data transmission method and display device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0038] Referring to Figure 2, the display device 2 includes a display controller 21, at least one dimming controller 22, and a backlight panel 23. The display controller 21 is electrically connected to each dimming controller 22 via differential signal lines 24. The backlight panel 23 is provided with a plurality of dimmers 231 and a plurality of light-emitting units 232, which are arranged in an array. One dimmer 231 is electrically connected to at least one light-emitting unit 232 (Figure 2 shows an example of one dimmer 231 being electrically connected to four light-emitting units 232).

[0039] Referring to Figure 2, among the multiple dimmers 231 arranged in the backlight panel 23, the dimmers 231 located in the same row are connected in series. A dimming controller 22 is electrically connected to the dimmer closest to it in each of the multiple rows of dimmers 231, and the dimmers closest to the dimmer controller 22 in different rows are electrically connected to the dimmer controller 22 in parallel. For example, a dimmer controller 22 can be electrically connected to the dimmer closest to it in each of the eight rows of dimmers 231, and these eight dimmers closest to the dimmer controller 22 are connected in parallel.

[0040] It should be understood that Figure 2 is merely an example of a display device and should not constitute any limitation on the display device provided in the embodiments of this application. Specifically, the embodiments of this application do not limit the specific connection method between the dimming controller and the dimmer, which can be flexibly set according to the architectural design of the display device. For example, multiple dimmers located in the same column can be connected in series, and the dimming controller can be electrically connected to the dimmer closest to the dimming controller in each of the multiple columns of dimmers. In addition, in the display device provided in the embodiments of this application, the number of dimming controllers, the number of dimmers, the number of light-emitting units, the number of dimmers connected to a dimming controller, and the number of light-emitting units connected to a dimmer are not limited. These numbers can be flexibly set according to actual business needs (such as performance requirements) and / or actual architectural design (such as the size of the display device).

[0041] Referring to Figure 2, the display controller 21 can be any of a system-on-chip (SoC), a timing controller (TCON), or a timing controller with embedded local dimming (TELD), depending on the specific architecture of the display device. The light-emitting unit 232 can be a mini light-emitting diode (Mini LED), etc.

[0042] In a specific implementation, referring to Figure 2, the display controller 21 can generate dimming data (i.e., local dimming data) based on the display data. This display data is obtained after a series of processing steps on the video stream data or image data. Then, the display controller 21 can send the display data to the display panel (not shown in Figure 2) to control the display panel to display images. Simultaneously, using the data transmission method provided in this application embodiment, the dimming data generated by the display controller 21 is sent to the dimming controller 22 via the differential signal line 24 (see subsequent embodiments for details). After receiving the dimming data, the dimming controller 22 sends the dimming data to the dimmer 231 connected to itself. The dimmer 231 controls the light-emitting unit 232 connected to itself to emit backlight of corresponding brightness according to the dimming data. When different light-emitting units 232 emit backlight of different brightness, the light-emitting units 232 on the backlight panel 23 project the light onto the display panel, thus displaying the corresponding image on the display panel.

[0043] The data transmission method provided in this application embodiment can be applied to the display device shown in FIG2, and is used to realize dimming data transmission between the display controller 21 and the dimming controller 22 through the differential signal line 24. Referring to FIG3, the data transmission method may include:

[0044] In step S301, the display controller 21 outputs a differential dimming signal and a differential clock signal, wherein the differential dimming signal is used to carry the dimming data corresponding to a frame of image.

[0045] In this embodiment, the differential dimming signal may include a first dimming signal and a second dimming signal, which have equal amplitudes but opposite phases; the first dimming signal is the positive phase (P-terminal) signal in the differential dimming signal, and the second dimming signal is the inverted phase (N-terminal) signal in the differential dimming signal. The differential clock signal may also include a first clock signal and a second clock signal, which have equal amplitudes but opposite phases; the first clock signal is the positive phase (P-terminal) signal in the differential clock signal, and the second clock signal is the inverted phase (N-terminal) signal in the differential clock signal.

[0046] In this embodiment of the application, the differential signal line 24 used to connect the display controller 21 and a dimming controller 22 includes at least one signal line, that is, the differential signal line 24 can be a single signal line or a group of signal lines.

[0047] For ease of understanding, the following explanation will use the example of differential signal line 24 comprising 4 signal lines:

[0048] Referring to Figure 4, the differential signal line 24 may include a first differential signal line 241 and a second differential signal line 242. That is, the display controller 21 is electrically connected to each dimming controller 22 via the first differential signal line 241 and the second differential signal line 242, respectively. The first differential signal line 241 is used to transmit differential dimming signals, and the second differential signal line 242 is used to transmit differential clock signals. Specifically, the first differential signal line 241 may include a first signal line L11 and a second signal line L12; the first signal line L11 is used to transmit a first dimming signal D_P, and the second signal line L12 is used to transmit a second dimming signal D_N. The second differential signal line 242 may include a third signal line L21 and a fourth signal line L22; the third signal line L21 is used to transmit a first clock signal Clk_P, and the fourth signal line L22 is used to transmit a second clock signal Clk_N.

[0049] In this embodiment, since the differential dimming signal carries dimming data corresponding to one frame of image, a dimming controller and a display controller only need to be connected through one or a few signal lines to achieve the transmission of a large amount of dimming data. This design architecture proposed in this embodiment effectively simplifies internal wiring while achieving dimming data transmission, and reduces the size of the connector used to connect the display controller and the dimming controller, thereby lowering product costs and facilitating miniaturization.

[0050] In some embodiments, before outputting the differential dimming signal and the differential clock signal, the display controller 21 may also generate a differential dimming signal based on the initial dimming signal and a differential clock signal based on the initial clock signal; both the initial dimming signal and the initial clock signal are single-ended signals, the initial dimming signal is used to carry dimming data corresponding to a frame of image, and both the initial dimming signal and the initial clock signal are generated by the display controller 21 based on the SPI protocol.

[0051] Specifically, the display controller 21 can perform single-ended to differential conversion on the initial dimming signal to obtain a differential dimming signal, and perform single-ended to differential conversion on the initial clock signal to obtain a differential clock signal. In this embodiment, the display controller 21 has at least two feasible implementation methods in generating the differential dimming signal and the differential clock signal:

[0052] Method 1:

[0053] In some embodiments, the display controller 21 can directly perform single-ended to differential conversion on the initial dimming signal to obtain a differential dimming signal, and directly perform single-ended to differential conversion on the initial clock signal to obtain a differential clock signal; the frequency of the clock signal (first clock signal and / or second clock signal) in the differential clock signal is equal to the frequency of the initial clock signal.

[0054] The following section, based on the internal architecture design of the display controller 21, elaborates on the methods by which it generates differential dimming signals and differential clock signals:

[0055] Referring to Figure 5A, the display controller 21 includes a first signal conversion module 211 and a second signal conversion module 212. The output terminal of the first signal conversion module 211 is electrically connected to a first differential signal line 241, and the output terminal of the second signal conversion module 212 is electrically connected to a second differential signal line 242. The first signal conversion module 211 receives an initial dimming signal D_1 and processes it to generate differential dimming signals (D_P, D_N). The differential dimming signals (D_P, D_N) are transmitted through the first differential signal line 241. The second signal conversion module 212 receives an initial clock signal Clk_1 and converts it to generate differential clock signals (Clk_P, Clk_N). The differential clock signals (Clk_P, Clk_N) are transmitted through the second differential signal line 242.

[0056] In a specific implementation, after other processing modules within the display controller 21 (not shown in Figure 5A) generate the initial dimming signal D_1 and the initial clock signal Clk_1 based on the SPI protocol, they input the initial dimming signal D_1 into the first signal conversion module 211 for single-ended to differential conversion, so that the first signal conversion module 211 outputs differential dimming signals (D_P, D_N); at the same time, they input the initial clock signal Clk_1 into the second signal conversion module 212 for single-ended to differential conversion, so that the second signal conversion module 212 outputs differential clock signals (Clk_P, Clk_N).

[0057] In this embodiment of the application, both the first signal conversion module 211 and the second signal conversion module 212 can be differential operational amplifiers, low-voltage differential signaling (LVDS) converters, etc.

[0058] Since the initial clock signal and initial dimming signal generated based on the SPI protocol are both digital domain signals, converting them into differential signals in the analog domain and transmitting them using differential signal lines can effectively improve the signal transmission efficiency. Specifically, the transmission rate of the initial clock signal and initial dimming signal in the digital domain can only reach 1Mbps-10Mbps, while in this application, the transmission rate of dimming data is achieved by transmitting differential signals in the analog domain, which can reach 100Mbps-600Mbps.

[0059] Method 2:

[0060] In some embodiments, the display controller 21 can directly perform single-ended to differential conversion processing on the initial dimming signal to obtain a differential dimming signal; the display controller 21 can perform frequency division processing on the initial clock signal to generate a second intermediate clock signal, and perform single-ended to differential conversion processing on the second intermediate clock signal to obtain a differential clock signal; the frequency of the initial clock signal is K times the frequency of the second intermediate clock signal (K is a positive integer and K≥2), and the frequency of the clock signal in the differential clock signal is equal to the frequency of the second intermediate clock signal.

[0061] The following section, based on the internal architecture design of the display controller 21, elaborates on the methods by which it generates differential dimming signals and differential clock signals:

[0062] Referring to Figure 5B, the display controller 21 may further include a first clock processing module 213; the output terminal of the first clock processing module 213 is electrically connected to the input terminal of the second signal conversion module 212, and the input terminal of the first clock processing module 213 is used to receive the initial clock signal Clk_1. The first clock processing module 213 can perform frequency division processing on the initial clock signal Clk_1 to obtain a second intermediate clock signal Clk_2, the frequency of the second intermediate clock signal Clk_2 being less than the frequency of the initial clock signal Clk_1; the second signal conversion module 212 can convert the second intermediate clock signal Clk_2 to generate differential clock signals (Clk_P, Clk_N).

[0063] In a specific implementation, after other processing modules within the display controller 21 (not shown in Figure 5B) generate the initial dimming signal D_1 and the initial clock signal Clk_1 based on the SPI protocol, they input the initial dimming signal D_1 into the first signal conversion module 211 for single-ended to differential conversion processing, so that the first signal conversion module 211 outputs differential dimming signals (D_P, D_N). At the same time, the initial clock signal Clk_1 is input into the first clock processing module 213 for frequency division processing. The first clock processing module 213 outputs the second intermediate clock signal Clk_2 into the second signal conversion module 212 for single-ended to differential conversion processing, so that the second signal conversion module 212 outputs differential clock signals (Clk_P, Clk_N).

[0064] In this embodiment, the first clock processing module 213 can be implemented using a K:1 (K is a positive integer and K≥2) phase-locked loop (PLL). The K:1 PLL can perform a K-fold frequency division on the initial clock signal Clk_1, reducing the frequency of the second intermediate clock signal Clk_2, and thus reducing the frequency of the differential clock signal.

[0065] Therefore, while transmitting dimming data in the form of differential signals, the clock signal is frequency divided to reduce the frequency of the clock signal transmitted through the differential signal line. The reduction in frequency will increase the period of the differential clock signal, thereby reducing the number of level transitions during clock signal transmission, thus reducing the electromagnetic interference generated by the differential clock signal and improving equipment performance.

[0066] Furthermore, regardless of the method used in the embodiments of this application, the display controller 21, in the process of mapping the initial dimming signal to generate the differential dimming signal, will also combine the data enable signal (DE), the vertical synchronization signal VSync, and the chip select signal CS, as follows:

[0067] In some embodiments, referring to FIG6, the first dimming signal D_P includes a plurality of first signal segments S1 and a plurality of second signal segments S2, wherein the plurality of second signal segments S2 are disposed between the plurality of first signal segments S1, and the data amount of the first signal segment S1 and the data amount of the second signal segment S2 are both M bits; M is a positive integer and M≥3 (FIG6 is an example of M=7).

[0068] The first signal segment S1 is used to carry the first data, the second data, and the third data; the first data represents the level state of the data enable signal DE, the second data represents the level state of the vertical synchronization signal VSync, and the third data represents the level state of the chip select signal CS. The chip select signal CS is generated by the display controller 21 based on the SPI protocol, and the vertical synchronization signal VSync is used to distinguish the display cycle of different frame images.

[0069] The second signal segment S2 is used to carry dimming data and the first data; the level state of the data enable signal DE represented by the first data in the first signal segment S1 is different from the level state of the data enable signal DE represented by the first data in the second signal segment S2, and the position of the first data in the first signal segment S1 is the same as the position of the first data in the second signal segment S2.

[0070] Referring to Figure 6, taking the example that both the first signal segment S1 and the second signal segment S2 include 7 bits of data (i.e., B6-B0), in each first signal segment S1, the data at position B6 is used as the first data, and the first data is "0", that is, the data enable signal DE is low. At this time, the transmission of synchronization signals (vertical synchronization signal VSync and chip select signal CS) is performed, rather than the transmission of dimming data.

[0071] In each first signal segment S1, the data at position B5 is used as the second data. The value of the second data can be "0" or "1". When it is "1", the vertical synchronization signal VSync is high, and the display cycle of the previous frame image ends and the display cycle of the current frame image begins. When it is "0", the vertical synchronization signal VSync is low, and the display of the current frame image officially begins.

[0072] In each first signal segment S1, the data at position B4 is used as the third data. The value of the third data can be "0" or "1". When it is "1", the chip select signal CS is high, and preparation for dimming data transmission is carried out. When it is "0", the chip select signal CS is low, and dimming data transmission can begin. Therefore, the dimming data of different frames can be distinguished based on the chip select signal CS.

[0073] Referring to Figure 6, corresponding to the position of the first data in the first signal segment S1, in each second signal segment S2, the data at position B6 is also used as the first data, and the first data is "1", that is, the data enable signal DE is high. At this time, the other positions (B5-B0) on the second signal segment S2 are used to carry dimming data (b5~b0 in the second signal segment S2 shown in Figure 6 represent different dimming data) for the transmission of dimming data. For example, in the second signal segment S2, position B5 carries dimming data b5, position B4 carries dimming data b4, and so on.

[0074] It should be understood that Figure 6 is only an example, and the embodiments of this application do not limit the data volume of the first signal segment and the second signal segment, as long as it meets the data carrying requirements. For example, the data volume of the first signal segment and the second signal segment can be 3 bits, 4 bits, 8 bits, etc.

[0075] Furthermore, the embodiments of this application do not limit the positions of the first data, the second data, and the third data within the first signal segment. Taking the first dimming signal shown in FIG6 as an example, the data at position B0 of the first signal segment can also be used as the first data, the data at position B1 as the third data, and the data at position B2 as the second data.

[0076] Furthermore, the embodiments of this application do not limit the position of the first data in the second signal segment, as long as the position of the first data in the first signal segment and the second signal segment is consistent. Taking the first dimming signal shown in Figure 6 as an example, the data at position B3 of the second signal segment can also be used as the first data. In this case, positions B6-B4 and B2-B0 of the second signal segment are used to carry the dimming data.

[0077] It should be noted that since the first and second dimming signals in the differential dimming signal have equal amplitudes but opposite phases, meaning the composition of the second dimming signal is similar to that of the first dimming signal, it will not be elaborated further.

[0078] In practical implementation, when the dimming controller 22 receives the differential dimming signal, it can identify the first dimming signal and the second dimming signal. When the first data in the first signal segment is identified as "0", the vertical sync signal VSync and the chip select signal CS are extracted from the second and third data in the first signal segment for subsequent image display. When the first data in the second signal segment is identified as "1", the dimming data is extracted from the data at other positions in the second signal segment, and the subsequent dimming data is recovered.

[0079] In step S302, the differential dimming signal and differential clock signal are received by the dimming controller 22, and target dimming data for backlight control is generated based on the differential dimming signal and differential clock signal.

[0080] In the above data transmission method, the display controller and the dimming controller transmit dimming data and clock signals by transmitting differential dimming signals and differential clock signals. Compared with the existing technology that uses the SPI protocol to transmit dimming data, the method of transmitting dimming data using differential signals in this application can effectively improve the data transmission rate and better meet the transmission needs of massive dimming data. In addition, using differential signals to transmit dimming data and clock signals only requires connecting four differential signal lines between each dimming controller and the display controller. The number of traces is reduced, which not only simplifies the board layout, but also reduces the size of the connector used to connect the dimming controller and the display controller, reduces the number of pins, and optimizes product costs. Furthermore, since differential signals transmit effective information (i.e., dimming data) based on the difference between two signals, the voltage variation range of the differential dimming signal used to transmit dimming data in this application is approximately 100mV-300mV, which is relatively small. The reduction in voltage variation range can effectively reduce the degree of electromagnetic wave emission. In addition, in the two signal lines used to transmit differential signals, the current directions are opposite and the amplitudes are approximately equal, so the generated electromagnetic fields will cancel each other out. All of these factors will effectively reduce electromagnetic interference problems and thus improve the display performance of the device.

[0081] In some embodiments, referring to Figures 4, 5A, and 5B, the dimming controller 22 can receive a differential dimming signal via the first differential signal line 241. Specifically, the dimming controller 22 receives a first dimming signal via the first signal line L11 and a second dimming signal via the second signal line L12, thereby achieving the reception of the differential dimming signal. The dimming controller 22 can receive a differential clock signal via the second differential signal line 242. Specifically, the dimming controller 22 receives a first clock signal via the third signal line L21 and a second clock signal via the fourth signal line L22, thereby achieving the reception of the differential clock signal.

[0082] In some embodiments, the dimming controller 22 may include the following during the execution of step S302:

[0083] In step S302-1, the dimming controller 22 generates a target dimming signal based on the differential dimming signal, and generates a target clock signal based on the differential clock signal; both the target clock signal and the target dimming signal are single-ended signals, and the target dimming signal is used to carry dimming data.

[0084] In this embodiment of the application, corresponding to the way the display controller 21 generates the differential dimming signal and the differential clock signal, the dimming controller 22 also has at least the following two feasible implementation methods in the process of generating the target dimming signal and the target clock signal:

[0085] Method 1:

[0086] In some embodiments, when the dimming controller 22 performs step S302-1 to generate a target dimming signal, it may do so in the following manner: the dimming controller 22 performs differential-to-single-ended conversion on the first dimming signal and the second dimming signal to obtain the target dimming signal.

[0087] In some embodiments, when the dimming controller 22 performs step S302-1 to generate a target clock signal, it may do so in the following manner: the dimming controller 22 directly performs differential-to-single-ended conversion on the first clock signal and the second clock signal to obtain the target clock signal; the frequencies of the first clock signal and the second clock signal are both equal to the frequency of the target clock signal, and the frequency of the target clock signal is equal to the frequency of the initial clock signal.

[0088] The following section, based on the internal architecture design of the dimming controller 22, elaborates on the methods by which it generates the target dimming signal and the target clock signal:

[0089] Referring to Figure 7A, the dimming controller 22 includes a third signal conversion module 221 and a fourth signal conversion module 222; the input terminal of the third signal conversion module 221 is electrically connected to the first differential signal line 241, and the input terminal of the fourth signal conversion module 222 is electrically connected to the second differential signal line 242; wherein:

[0090] The third signal conversion module 221 is used to receive the differential dimming signals (D_P, D_N) transmitted by the first differential signal line 241, and generate a target dimming signal LVDS_D based on the differential dimming signals (D_P, D_N); the target dimming signal LVDS_D is a single-ended signal used to carry dimming data. The fourth signal conversion module 222 is used to receive the differential clock signals (Clk_P, Clk_N) transmitted by the second differential signal line 242, and generate a target clock signal LVDS_Clk based on the differential clock signals (Clk_P, Clk_N); the target clock signal LVDS_Clk is also a single-ended signal.

[0091] In a specific implementation, referring to Figure 7A, the third signal conversion module 221 receives the first dimming signal D_P through the first signal line L11 and the second dimming signal D_N through the second signal line L12. It then converts the first dimming signal D_P and the second dimming signal D_N to output the target dimming signal LVDS_D. Simultaneously, the fourth signal conversion module 222 receives the first clock signal Clk_P through the third signal line L21 and the second clock signal Clk_N through the fourth signal line L22. It then converts the first clock signal Clk_P and the second clock signal Clk_N to output the target clock signal LVDS_Clk.

[0092] In this embodiment, both the third signal conversion module 221 and the fourth signal conversion module 222 can be differential operational amplifiers, low-voltage differential signal converters, etc.

[0093] Method 2:

[0094] In some embodiments, when the dimming controller 22 performs step S302-1 to generate a target dimming signal, it may do so in the following manner: the dimming controller 22 performs differential-to-single-ended conversion on the first dimming signal and the second dimming signal to obtain the target dimming signal.

[0095] In some embodiments, when the dimming controller 22 performs step S302-1 to generate the target clock signal, it may do so in the following manner: the dimming controller 22 first performs conversion processing on the first clock signal and the second clock signal to obtain a first intermediate clock signal; then, it performs frequency multiplication processing on the first intermediate clock signal to obtain the target clock signal.

[0096] The first intermediate clock signal is a single-ended signal, and its frequency is equal to that of the first clock signal and the second clock signal. The target clock signal has a frequency greater than that of the first clock signal and the second clock signal, and its frequency is equal to that of the initial clock signal.

[0097] In one feasible embodiment, the dimming controller 22 can perform integer frequency multiplication on the first intermediate clock signal to obtain a target clock signal; the frequency of the target clock signal is K times the frequency of the first clock signal, and the frequency of the target clock signal is K times the frequency of the second clock signal; K is a positive integer, and K≥2.

[0098] In another feasible embodiment, the dimming controller 22 may also perform non-integer frequency multiplication on the first intermediate clock signal to obtain the target clock signal. For example, the dimming controller 22 may perform frequency multiplication of the first intermediate clock signal by 2.5 to obtain the target clock signal.

[0099] It should be noted that this application does not limit the multiplier of the first clock signal; it can be an integer multiplier or a non-integer multiplier. Similarly, this application does not limit the division factor of the initial clock signal; it can be an integer multiplier or a non-integer multiplier, as long as the division factor is consistent with the multiplication factor.

[0100] Therefore, transmitting a lower frequency first clock signal via differential signal lines can effectively reduce the number of level transitions during clock signal transmission compared to transmitting a high frequency clock signal, thereby reducing electromagnetic interference generated by the differential clock signal and improving equipment performance.

[0101] The following section, based on the internal architecture design of the dimming controller 22, elaborates on the methods by which it generates the target dimming signal and the target clock signal:

[0102] Referring to Figure 7B, the dimming controller 22 further includes a second clock processing module 223; the input terminal of the second clock processing module 223 is electrically connected to the output terminal of the fourth signal conversion module 222; wherein:

[0103] The fourth signal conversion module 222 is also used to generate a first intermediate clock signal Clk_3 based on the differential clock signals (Clk_P, Clk_N). The second clock processing module 223 performs frequency multiplication on the first intermediate clock signal Clk_3 to obtain the target clock signal LVDS_Clk.

[0104] In a specific implementation, referring to Figure 7B, the third signal conversion module 221 receives the first dimming signal D_P through the first signal line L11 and the second dimming signal D_N through the second signal line L12. It then converts the first dimming signal D_P and the second dimming signal D_N to output the target dimming signal LVDS_D. Simultaneously, the fourth signal conversion module 222 receives the first clock signal Clk_P through the third signal line L21 and the second clock signal Clk_N through the fourth signal line L22. It then converts the first clock signal Clk_P and the second clock signal Clk_N to output the first intermediate clock signal Clk_3 to the second clock processing module 223. The second clock processing module 223 performs frequency multiplication on the first intermediate clock signal Clk_3 and outputs the target clock signal LVDS_Clk.

[0105] In this embodiment, the second clock processing module 223 can be implemented using a 1:K (K is a positive integer and K≥2) phase-locked loop. The 1:K phase-locked loop can multiply the first intermediate clock signal Clk_3 by a factor of K to obtain the target clock signal LVDS_Clk. This ensures that the frequency of the target clock signal LVDS_Clk is consistent with the frequency of the initial clock signal Clk_1, guaranteeing the accuracy of dimming data parsing.

[0106] In step S302-2, the dimming controller 22 generates target dimming data based on the target dimming signal and the target clock signal.

[0107] In some embodiments, after generating a target dimming signal based on a differential dimming signal and a target clock signal based on a differential clock signal, the dimming controller 22 uses the target clock signal to sample the target dimming signal to obtain target dimming data.

[0108] Referring to Figures 7A and 7B, the dimming controller 22 further includes a signal processing module 224. In the hardware architecture shown in Figure 7A, the signal processing module 224 is electrically connected to the output terminals of the third signal conversion module 221 and the fourth signal conversion module 222, respectively. In the hardware architecture shown in Figure 7B, the signal processing module 224 is electrically connected to the output terminals of the third signal conversion module 221 and the second clock processing module 223, respectively.

[0109] The signal processing module 224 is used to receive the target dimming signal LVDS_D and the target clock signal LVDS_Clk, and generate target dimming data based on the target dimming signal LVDS_D and the target clock signal LVDS_Clk.

[0110] Further, referring to Figures 7A and 7B, the signal processing module 224 may include a data sampling unit 2241 and a data generation unit 2242; the data sampling unit 2241 and the data generation unit 2242 are electrically connected. The data sampling unit 2241 is used to sample the target dimming signal LVDS_D using the target clock signal LVDS_Clk to obtain multiple dimming sampling data, and sends the dimming sampling data to the data generation unit 2242. The data generation unit 2242 is used to determine the target dimming data based on the multiple dimming sampling data and a preset dimming precision.

[0111] In this embodiment, when the preset dimming precision is Q bits (Q is a positive integer), the data generation unit 2242 generates a target dimming data for every Q consecutive dimming sample data received from the multiple dimming sample data. For example, assuming Q=8, the 8 dimming sample data received by the data generation unit 2242 are: 10010101, then the data generation unit 2242 can determine a target dimming data based on "10010101".

[0112] Furthermore, in high-performance display devices, multiple dimming controllers are typically configured, meaning that one display controller needs to be connected to multiple dimming controllers. Based on this, embodiments of this application provide at least two connection architectures, as follows:

[0113] Architecture 1:

[0114] Referring to Figure 8A, the display device 2 is provided with multiple dimming controllers 22, each of which is electrically connected to multiple dimmers 231. The display controller 21 is electrically connected to each dimming controller 22 via a first differential signal line 241 and a second differential signal line 242. For any dimming controller 22, the differential dimming signal received by the dimming controller 22 is the differential signal transmitted by the display controller 21 via the first differential signal line 241, and the differential clock signal received by the dimming controller 22 is the differential signal transmitted by the display controller 21 via the second differential signal line 242.

[0115] In a specific implementation, referring to Figure 8A, multiple dimming controllers 22 are connected in parallel. The differential dimming signal output by the display controller 21 is transmitted sequentially to each dimming controller 22 via the first differential signal line 241. Simultaneously, the differential clock signal output by the display controller 21 is transmitted sequentially to each dimming controller 22 via the second differential signal line 242. After receiving the differential dimming signal and the differential clock signal, the dimming controller 22 can receive and process them in the manner described in the corresponding embodiment of Figure 7A or Figure 7B to obtain the target dimming data. The target dimming data is then sent to the dimmer 231 connected to itself, so that the dimmer 231 controls the backlight brightness of the light-emitting unit (not shown in Figure 8A) connected to itself according to the target dimming data.

[0116] Referring to Figure 8A, under this design architecture, the dimming controller 22 only needs to be equipped with a differential signal receiving component. This differential signal receiving component can be composed of the third signal conversion module 221 and the fourth signal conversion module 222 in Figure 7A, or it can be composed of the third signal conversion module 221, the fourth signal conversion module 222 and the second clock processing module 223 in Figure 7B. It can be set in accordance with the internal structure on one side of the display controller 21. This application embodiment does not limit this.

[0117] Therefore, only one differential signal receiving component needs to be set in each dimming controller, which is simple to implement and has a low product cost. However, this architecture, which connects multiple dimming controllers on a set of differential signal lines, will result in a larger load on the differential signal line group and a relatively lower signal transmission efficiency.

[0118] Architecture 2:

[0119] Referring to Figure 8B, the display device 2 is provided with a plurality of dimming controllers 22, each of which is electrically connected to a plurality of dimmers 231. The plurality of dimming controllers 22 are connected in series in sequence through a first differential signal line 241 and a second differential signal line 242, respectively. The first dimming controller among the plurality of dimming controllers 22 (i.e. the dimming controller closest to the display controller 21) is electrically connected to the display controller 21 through the first differential signal line 241 and the second differential signal line 242, respectively.

[0120] Specifically, for the first dimming controller, the differential dimming signal received by the dimming controller 22 is the differential signal transmitted by the display controller 21 through the first differential signal line 241, and the differential clock signal received by the dimming controller 22 is the differential signal transmitted by the display controller 21 through the second differential signal line 242.

[0121] For any non-first dimming controller among multiple dimming controllers 22, the differential dimming signal received by the dimming controller 22 is the differential signal transmitted by the previous dimming controller through the first differential signal line 241, and the differential clock signal received by the dimming controller 22 is the differential signal transmitted by the previous dimming controller through the second differential signal line 242.

[0122] Referring to Figure 8B, taking the dimming controller 22-B in Figure 8B as an example, the differential dimming signal received by the dimming controller 22-B is the differential signal output by the dimming controller 22-A and transmitted through the first differential signal line 241; the differential clock signal received by the dimming controller 22-B is the differential signal output by the dimming controller 22-A and transmitted through the second differential signal line 242.

[0123] Based on this, in the design architecture shown in Figure 8B, for any non-last dimming controller among the multiple dimming controllers 22, the dimming controller 22 is also used to generate a differential dimming signal and transmit the differential dimming signal to the next dimming controller through the first differential signal line 241, and generate a differential clock signal and transmit the differential clock signal to the next dimming controller through the second differential signal line 242.

[0124] Therefore, for the dimming controller 22 in the design architecture shown in Figure 8B, it needs to include not only a differential signal receiving component but also a differential signal transmitting component. The differential signal receiving component receives the differential dimming signal and the differential clock signal, and converts them into the target dimming signal and the target clock signal. The differential signal transmitting component converts the target dimming signal and the target clock signal back into the differential dimming signal and the differential clock signal, and transmits them to the subsequent stage through the first differential signal line 241 and the second differential signal line 242 connected to it. Therefore, the internal structure of the dimming controller 22 shown in Figure 8B can be as follows:

[0125] Referring to Figure 9A, the dimming controller 22 includes a differential signal receiving component A1 and a differential signal transmitting component A2. The differential signal receiving component A1 can be composed of the third signal conversion module 221 and the fourth signal conversion module 222 shown in Figure 7A. Correspondingly, the differential signal transmitting component A2 includes a fifth signal conversion module 225 and a sixth signal conversion module 226. The fifth signal conversion module 225 is used to receive the target dimming signal output by the third signal conversion module 221, convert the target dimming signal into a differential dimming signal, and output it through the first differential signal line 241. The sixth signal conversion module 226 is used to receive the target clock signal output by the fourth signal conversion module 222, convert the target clock signal into a differential clock signal, and output it through the second differential signal line 242.

[0126] Referring to Figure 9B, the differential signal receiving component A1 can be composed of the third signal conversion module 221, the fourth signal conversion module 222, and the second clock processing module 223 shown in Figure 7B. Correspondingly, the differential signal transmitting component A2 also includes a third clock processing module 227; the third clock processing module 227 is connected between the fourth signal conversion module 222 and the sixth signal conversion module 226, and is used to receive the target clock signal output by the fourth signal conversion module 222, and perform frequency division processing on the target clock signal to obtain a third intermediate clock signal Clk_4, the frequency of which is the same as the frequency of the first intermediate clock signal Clk_3. The sixth signal conversion module 226 is used to receive the third intermediate clock signal Clk_4, convert the third intermediate clock signal Clk_4 into a differential clock signal, and output it through the second differential signal line 242. The fifth signal conversion module 225 is used to receive the target dimming signal output by the third signal conversion module 221, convert the target dimming signal into a differential dimming signal, and output it through the first differential signal line 241.

[0127] It should be understood that regardless of whether the dimming controller adopts the architecture design shown in Figure 9A or Figure 9B, the differential dimming signal it receives is the same as the differential dimming signal it outputs to the next stage, and the differential clock signal it receives is also the same as the differential clock signal it outputs to the next stage.

[0128] Therefore, multiple dimming controllers are connected in series via differential signal line groups. The differential dimming signal and differential clock signal generated by the display controller are transmitted step by step through each dimming controller. In this way, only one dimming controller is connected to each differential signal line, which reduces the load and effectively improves the signal transmission speed, thus achieving high-speed transmission of dimming data.

[0129] Furthermore, regardless of whether architecture one or architecture two is adopted, in some embodiments, referring to Figures 8A and 8B, the dimming controller 22 can also receive feedback data sent by the dimmer 231 connected to it. This feedback data is the status data of each light-emitting unit connected to it obtained by the dimmer 231. Then, the dimming controller 22 can feed back this feedback data to the display controller 21 so that the display controller 21 can monitor the status of each light-emitting unit on the backlight panel 23 in real time and perform adjustments or compensation operations to optimize the backlight brightness.

[0130] Furthermore, referring to Figures 8A and 8B, since the display device 2 has multiple dimming controllers 22 internally, each dimming controller 22 only needs to parse the portion of dimming data corresponding to the light-emitting unit it controls, without needing to parse all the dimming data corresponding to a frame of image. This effectively saves computing resources. Based on this, this application also creatively designs the data parsing method of the dimming controller, as follows:

[0131] Referring to Figure 10, for any dimming controller 22, the dimming controller 22 may perform the following steps in the process of generating target dimming data:

[0132] Step S1001: Determine the target signal segment in the target dimming signal.

[0133] In some embodiments, the dimming controller 22 may perform step S1001 in the following manner: the dimming controller 22 determines at least one second target signal segment among a plurality of second signal segments; the position of the second target signal segment in the first dimming signal corresponds to the receiving position information pre-configured in the dimming controller 22; and the signal interval in the target dimming signal converted from at least one second target signal segment is taken as the target signal segment.

[0134] Referring to Figures 11 and 6, the first dimming signal and the second dimming signal include multiple second signal segments S2 carrying dimming data. In this embodiment, each dimming controller 22 is pre-configured with receiving location information. After receiving the differential dimming signal, the dimming controller 22 can select a second target signal segment S2-A from the multiple second signal segments S2 of the first dimming signal and the second dimming signal according to the receiving location information. The signal interval in the target dimming signal obtained by converting the second target signal segment S2-A in the first dimming signal and the second target signal segment S2-A in the second dimming signal is used as the target signal segment.

[0135] For example, referring to FIG11, the first four second signal segments S2 in the first dimming signal Clk_P can be used as the second target signal segment S2-A of the first dimming controller (i.e. 22-A) in the architecture shown in FIG8A or FIG8B, and the target signal segment can be determined in the target dimming signal accordingly.

[0136] Step S1002: Using the target clock signal, sample the dimming data carried in the target signal segment to obtain multiple dimming sampling data.

[0137] In a specific implementation, referring to Figures 7A, 7B and 11, the data sampling unit 2241 in the dimming controller 22 can use the target clock signal to sample the dimming data carried in the target signal segment of the target dimming signal to obtain multiple dimming sampling data.

[0138] Step S1003: Determine the target dimming data based on multiple dimming sampling data.

[0139] In a specific implementation, referring to Figures 7A, 7B and 11, the data generation unit 2242 in the dimming controller 22 can determine the target dimming data based on multiple dimming sampling data.

[0140] Table 1 below compares the performance of the differential signal-based data transmission method provided in this application with that of the traditional SPI protocol-based data transmission method:

[0141]

[0142] Table 1

[0143] As shown in Table 1, compared to the traditional SPI-based data transmission method, the differential signal-based data transmission method provided in this application can increase the dimming data transmission rate by 30-60 times, significantly improving data transmission efficiency. Therefore, it can better meet the data transmission requirements of high-performance display devices. Furthermore, this method in the embodiments of this application, while increasing the data transmission rate, can also reduce the number and complexity of on-board traces, which helps to reduce product costs and improve market competitiveness. It can also reduce electromagnetic interference and improve system performance.

[0144] Furthermore, in specific implementations, the display device in the embodiments of this application can be a smart terminal, tablet computer, laptop computer, smart handheld device, personal computer, computer, smart screen, in-vehicle device, various wearable devices, etc. In addition, other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limitations on this application.

[0145] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0146] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data transmission method, characterized in that, An application in a display device, the display device including a display controller and a dimming controller, the display controller being electrically connected to the dimming controller, the method comprising: outputting a differential dimming signal and a differential clock signal through the display controller, wherein the differential dimming signal is generated based on an initial dimming signal, a data enable signal, a vertical sync signal, and a chip select signal, the initial dimming signal being used to carry dimming data corresponding to a frame of image, the differential dimming signal including at least a first signal segment for carrying the data enable signal, the vertical sync signal, and the chip select signal, and a second signal segment for carrying the dimming data; receiving the differential dimming signal and the differential clock signal through the dimming controller, and generating target dimming data for backlight control based on the differential dimming signal and the differential clock signal.

2. The method as described in claim 1, characterized in that, The step of generating target dimming data for backlight control based on the differential dimming signal and the differential clock signal includes: generating a target dimming signal through the dimming controller based on the differential dimming signal, and generating a target clock signal through the dimming controller based on the differential clock signal; generating the target dimming data through the dimming controller according to the target dimming signal and the target clock signal; wherein the target clock signal and the target dimming signal are both single-ended signals, and the target dimming signal is used to carry the dimming data.

3. The method as described in claim 2, characterized in that, The differential dimming signal includes a first dimming signal and a second dimming signal; the first dimming signal includes multiple first signal segments and multiple second signal segments, with the multiple second signal segments positioned between the multiple first signal segments. The data size of both the first signal segment and the second signal segment is M bits, where M is a positive integer and M≥3; the first signal segment carries first data, second data, and third data, wherein the first data represents the level state of the data enable signal, the second data represents the level state of the vertical synchronization signal, and the third data represents the level state of the chip select signal. The chip select signal is generated by the display controller based on the serial peripheral interface protocol, and the vertical synchronization signal is used to distinguish the display cycles of different frame images; the second signal segment carries the dimming data and the first data; wherein the first data carried in the first signal segment is set to a first value to represent that the data enable signal is in a first level state; the first data carried in the second signal segment is set to a second value different from the first value to represent that the data enable signal is in a second level state.

4. The method as described in claim 3, characterized in that, The step of generating a target dimming signal based on the differential dimming signal through the dimming controller includes: converting the first dimming signal and the second dimming signal through the dimming controller to obtain the target dimming signal.

5. The method as described in claim 3, characterized in that, The step of generating the target dimming data by the dimming controller based on the target dimming signal and the target clock signal includes: determining a target signal segment in the target dimming signal by the dimming controller; sampling the dimming data carried in the target signal segment using the target clock signal by the dimming controller to obtain multiple dimming sample data; and determining the target dimming data based on the multiple dimming sample data by the dimming controller.

6. The method as described in claim 5, characterized in that, The step of determining a target signal segment in the target dimming signal through the dimming controller includes: determining at least one second target signal segment among the plurality of second signal segments through the dimming controller, wherein the position of the second target signal segment in the first dimming signal corresponds to the receiving position information pre-configured in the dimming controller; and using the dimming controller to take the signal interval in the target dimming signal converted by the at least one second target signal segment as the target signal segment.

7. The method as described in claim 2, characterized in that, The differential clock signal includes a first clock signal and a second clock signal; the frequencies of the first clock signal and the second clock signal are both equal to the frequency of the target clock signal; the step of generating the target clock signal based on the differential clock signal through the dimming controller includes: converting the first clock signal and the second clock signal through the dimming controller to obtain the target clock signal, wherein the frequency of the target clock signal is equal to the frequency of the initial clock signal.

8. The method as described in claim 2, characterized in that, The differential clock signal includes a first clock signal and a second clock signal; the frequency of the target clock signal is greater than the frequency of the first clock signal, and the frequency of the target clock signal is greater than the frequency of the second clock signal. The step of generating a target clock signal based on the differential clock signal via the dimming controller includes: converting the first clock signal and the second clock signal using the dimming controller to obtain a first intermediate clock signal, wherein the first intermediate clock signal is a single-ended signal and its frequency is equal to the frequencies of the first clock signal and the second clock signal; and performing frequency multiplication processing on the first intermediate clock signal using the dimming controller to obtain the target clock signal, wherein the frequency of the target clock signal is equal to the frequency of the initial clock signal.

9. The method as described in claim 8, characterized in that, The frequency of the target clock signal is K times the frequency of the first clock signal, and the frequency of the target clock signal is K times the frequency of the second clock signal, where K is a positive integer and K≥2.

10. The method according to any one of claims 1-9, characterized in that, Before outputting the differential dimming signal and differential clock signal through the display controller, the method further includes: processing the initial dimming signal through the display controller to generate the differential dimming signal, and converting the initial clock signal through the display controller to generate the differential clock signal; wherein the initial dimming signal is used to carry the dimming data, and the initial clock signal is generated by the display controller based on a serial peripheral interface protocol.

11. The method according to any one of claims 1-9, characterized in that, The dimming controller includes multiple components, and the display controller is electrically connected to each of the dimming controllers via a first differential signal line group and a second differential signal line group, respectively. The second differential signal line group is used to transmit the differential clock signal. For any dimming controller, the differential dimming signal received by the dimming controller is transmitted by the display controller via the first differential signal line group, and the differential clock signal received by the dimming controller is transmitted by the display controller via the second differential signal line group.

12. The method according to any one of claims 1-9, characterized in that, The dimming controller includes multiple dimming controllers, which are connected in series sequentially via a first differential signal line group and a second differential signal line group. The first dimming controller among the multiple dimming controllers is electrically connected to the display controller via both the first and second differential signal line groups. For the first dimming controller, the differential dimming signal received by the dimming controller is transmitted by the display controller via the first differential signal line group, and the differential clock signal received by the dimming controller is transmitted by the display controller via the second differential signal line group. For any non-first dimming controller among the multiple dimming controllers, the differential dimming signal received by the dimming controller is transmitted by the previous dimming controller via the first differential signal line group, and the differential clock signal received by the dimming controller is transmitted by the previous dimming controller via the second differential signal line group.

13. The method as described in claim 12, characterized in that, The method further includes: for any non-last dimming controller among the plurality of dimming controllers, generating the differential dimming signal through the dimming controller and transmitting the differential dimming signal to the next dimming controller through the first differential signal line group; and generating the differential clock signal through the dimming controller and transmitting the differential clock signal to the next dimming controller through the second differential signal line group.

14. A display device, characterized in that, The system includes a display controller and at least one dimming controller, the display controller being electrically connected to the dimming controller, wherein: the display controller is configured to: output a differential dimming signal and a differential clock signal, wherein the differential dimming signal is generated based on an initial dimming signal, a data enable signal, a vertical sync signal, and a chip select signal, the initial dimming signal being used to carry dimming data corresponding to a frame of image, and the differential dimming signal including at least a first signal segment for carrying the data enable signal, the vertical sync signal, and the chip select signal, and a second signal segment for carrying the dimming data; the dimming controller is configured to: receive the differential dimming signal and the differential clock signal, and generate target dimming data for backlight control based on the differential dimming signal and the differential clock signal.

15. The device as claimed in claim 14, characterized in that, The display controller is electrically connected to the dimming controller via a first differential signal line group and a second differential signal line group, respectively; the first differential signal line group is used to transmit the differential dimming signal, and the second differential signal line group is used to transmit the differential clock signal.

16. The device as claimed in claim 15, characterized in that, The display controller includes a first signal conversion module and a second signal conversion module, wherein: the output terminal of the first signal conversion module is electrically connected to the first differential signal line group, and the output terminal of the second signal conversion module is electrically connected to the second differential signal line group; the first signal conversion module is used to: process the initial dimming signal to generate the differential dimming signal, and transmit the differential dimming signal through the first differential signal line group, wherein the initial dimming signal is a single-ended signal used to carry the dimming data; the second signal conversion module is used to: convert the initial clock signal to generate the differential clock signal, and transmit the differential clock signal through the second differential signal line group, wherein the initial clock signal is generated by the display controller based on a serial peripheral interface protocol.

17. The device as claimed in claim 16, characterized in that, The display controller further includes a first clock processing module, wherein: the output terminal of the first clock processing module is electrically connected to the input terminal of the second signal conversion module; the first clock processing module is used to: perform frequency division processing on the initial clock signal to obtain a second intermediate clock signal, wherein the frequency of the second intermediate clock signal is less than the frequency of the initial clock signal; the second signal conversion module is further used to: convert the second intermediate clock signal to generate the differential clock signal.

18. The device as claimed in claim 15, characterized in that, The dimming controller includes a third signal conversion module, a fourth signal conversion module, and a signal processing module, wherein: the input terminal of the third signal conversion module is electrically connected to the first differential signal line group, the input terminal of the fourth signal conversion module is electrically connected to the second differential signal line group, and the output terminals of both the third and fourth signal conversion modules are electrically connected to the signal processing module; the third signal conversion module is used to: receive the differential dimming signal transmitted by the first differential signal line group, and generate a target dimming signal based on the differential dimming signal, wherein the target dimming signal is a single-ended signal and is used to carry the dimming data; the fourth signal conversion module is used to: receive the differential clock signal transmitted by the second differential signal line group, and generate a target clock signal based on the differential clock signal, wherein the target clock signal is a single-ended signal; the signal processing module is used to: generate the target dimming data according to the target dimming signal and the target clock signal.

19. The device as claimed in claim 18, characterized in that, The dimming controller further includes a second clock processing module, wherein: the input terminal of the second clock processing module is electrically connected to the output terminal of the fourth signal conversion module, and the output terminal of the second clock processing module is electrically connected to the signal processing module; the fourth signal conversion module is further configured to: generate a first intermediate clock signal based on the differential clock signal, wherein the first intermediate clock signal is a single-ended signal; the second clock processing module is configured to: perform frequency multiplication processing on the first intermediate clock signal to obtain the target clock signal.

20. The device as claimed in claim 18 or 19, characterized in that, The signal processing module includes a data sampling unit and a data generation unit, wherein: the data sampling unit is electrically connected to the data generation unit; the data sampling unit is used to: sample the dimming data carried in the target signal segment of the target dimming signal using the target clock signal to obtain multiple dimming sample data, wherein the target signal segment is determined by the dimming controller in the target dimming signal based on pre-configured receiving position information; the data generation unit is used to: determine the target dimming data based on the multiple dimming sample data.

Images