A network link characteristic high-fidelity simulation method, device and system

Abstract

The application discloses a network link characteristic high-fidelity simulation method, device and system, the method comprises the following steps: building a network simulation environment through general network simulation software, simulating the network topology and the motion state of nodes for the target network, collecting and reporting the parameter data of the target network; completing the theoretical calculation of the core characteristic parameters of the network link through the Python calculation module according to the collected parameter data; performing software and hardware collaborative simulation through the software layer and the hardware layer; completing the dynamic routing calculation of the adaptive link real-time state through the theoretical calculation result of the core characteristic parameters of the network link and the measured data returned by the hardware layer, and synchronously issuing the routing scheme to the software and hardware layers to update the traffic forwarding rules, so that the dynamic closed-loop linkage of the whole simulation process is realized. The application aims to greatly improve the simulation accuracy, solve the problem that the pure software simulation is disconnected with the actual scene, realize the whole-process automatic linkage, eliminate the manual operation error, and improve the simulation efficiency.

Description

Technical Field

[0001] This invention relates to the field of network communication simulation technology, specifically to a method, apparatus, and system for highly realistic simulation of network link characteristics. Background Technology

[0002] In the research and engineering implementation of various communication network systems, the simulation accuracy and coordination of link characteristics such as latency, packet loss rate, latency jitter, and dynamic connectivity directly determine the rationality and reliability of network routing design, heterogeneous network communication protocol optimization, and end-to-end transmission system performance verification. This is a core foundational aspect of communication network system development. Especially for communication networks with highly dynamic topologies and significant time-varying link characteristics, the accuracy and real-time performance of link characteristic simulation are crucial prerequisites for network system design and optimization. Existing pure software simulation methods often employ single simulation tools. For example, they may use network topology simulation software to dynamically simulate network node movement trajectories and link topology, then use the software's built-in simple calculation functions to estimate link characteristic parameters; or they may use software such as Python, NS3, or OPNET to write calculation and routing simulation modules to simulate link latency, packet loss, jitter, and perform routing calculations. The advantages of this type of pure software simulation method are low implementation cost, convenient operation, and no need for complex hardware adaptation. However, it has obvious limitations: On the one hand, the core functions of general network topology simulation software focus on node movement and network topology simulation. Its built-in link characteristic calculation module has low accuracy and cannot accurately simulate the nanosecond-level latency fluctuations, real packet loss patterns, and time-varying link characteristics of the network layer in real-world scenarios. On the other hand, the simulation module written in pure software lacks real-time bidirectional linkage with the network topology / node movement simulation module. The dynamic changes in network topology and node status cannot be fed back to the link characteristic calculation and routing simulation process in real time, resulting in a disconnect between the simulation results and the actual network link operation scenario. The simulation accuracy is difficult to meet the needs of high-precision research and development and testing. Another type of simple hardware and software simulation method usually involves separating network topology simulation software and simple hardware simulation modules. For example, after completing the simulation of node movement and network topology dynamics using network topology simulation software such as STK and NS3, the simulation results are manually exported and then manually input into a separate computing device to complete the link characteristic calculation. The calculation results are then manually imported back into the routing simulation module. In some scenarios, network simulation tools are used to simulate network latency or packet loss, but the parameter settings of these tools lack real-time linkage with the link characteristic calculation results and need to be manually adjusted.While this approach initially combines software simulation with hardware-level characteristic simulation, it suffers from problems such as cumbersome operation, untimely data interaction, and poor coordination. Manually importing and exporting data is not only inefficient but also prone to introducing human error. The Traffic Control (TC) tool is completely disconnected from the network topology simulation and link calculation modules, resulting in the simulation of network latency and packet loss failing to accurately match the dynamic changes in network topology and node states, thus affecting the overall accuracy of link characteristic simulation. At the same time, in the existing simple software and hardware combination method, the routing calculation algorithm and the link characteristic simulation process lack coordination, and the routing calculation does not fully incorporate the link parameters simulated in real time, further reducing the practicality and accuracy of the simulation results. To date, the closest existing technology in this field only achieves unidirectional data transmission between network topology simulation software and computing modules, failing to achieve bidirectional linkage with TC tools and hardware simulation units, and lacking a full-process software-hardware co-simulation mechanism adapted to various dynamic communication networks. Existing link simulation solutions based on programmable hardware can only achieve static link simulation with fixed parameters, unable to dynamically adjust simulation parameters according to node movement, link connectivity, and network topology changes in the communication network, and do not link link simulation results with the network routing calculation process in real time, failing to adapt to the core characteristics of highly dynamic changes in communication network topology and multi-link collaboration. Furthermore, existing link characteristic simulation technologies, whether purely software-based or using a simple software-hardware combination, have not formed a complete software-hardware co-simulation mechanism, failing to achieve fully automated linkage of network topology and node state simulation, link characteristic calculation, network underlying characteristic simulation, and routing calculation. This results in low simulation efficiency, insufficient accuracy, and poor fit with actual operating scenarios, making it difficult to meet the actual needs of high-precision R&D and testing of various communication networks. In summary, existing network link characteristic simulation technologies suffer from several problems. Pure software simulation lacks precision, cannot accurately simulate dynamic link characteristics, and is disconnected from network topology and node movement changes. Simple hardware and software simulation is cumbersome, prone to human error, and data interaction between different stages is not timely. It also lacks a fully automated collaborative mechanism and suffers from core technical issues such as asynchronous routing calculations and link simulation status, and a lack of closed-loop verification capabilities for simulation parameters. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a method, device and system for high-fidelity simulation of network link characteristics, which addresses the above-mentioned problems of the prior art. This invention aims to significantly improve simulation accuracy, solve the problem of the disconnect between pure software simulation and actual scenarios, realize full-process automated linkage, eliminate human operation errors and improve simulation efficiency.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A high-fidelity simulation method for network link characteristics includes the following steps: S1, building a network simulation environment using general network simulation software to simulate the network topology and node motion states of the target network, and collecting and reporting the node motion states and basic link parameters of the target network; S2, using a Python calculation module to perform theoretical calculations of the core characteristic parameters of the network link based on the collected node motion states and basic link parameters of the target network; S3, performing software and hardware co-simulation through software and hardware layers: the software layer calls the qdisc component of the Linux kernel TC tool, and the hardware layer relies on programmable hardware units, combined with the qdisc queue scheduling principle of the qdisc component, to achieve accurate simulation of network link latency, packet loss, and jitter. Through closed-loop verification between theoretical calculation values ​​and actual simulation values, the simulation parameters are dynamically adjusted to ensure that the simulation accuracy closely matches the actual network link characteristics; S4, using the theoretical calculation results of the core characteristic parameters of the network link and the measured data returned by the hardware layer to complete dynamic routing calculations adapted to the real-time link status, and synchronously distributing the routing scheme to the software and hardware layers to update traffic forwarding rules to achieve dynamic closed-loop linkage throughout the simulation process.

[0005] Optionally, step S1 includes: S1.1 Simulation environment and parameter configuration, including: importing the node parameters and topology data of the target network into the general network simulation software, configuring the link topology parameters, and setting the simulation step size, simulation duration and data acquisition frequency to build a network simulation environment consistent with the actual communication network; S1.2, Node motion and link dynamic simulation, including: starting the simulation, simulating the motion trajectory of network nodes, the change of relative positions between nodes and the dynamic connection and disconnection of links, capturing node motion status data and basic link parameters in real time, and storing all data in the local real-time data buffer of the simulation software at a preset frequency. S1.3, Automated real-time parameter transmission, includes: using a secondary development program for simulation software written in Python to call the standard interface of the simulation software to poll and read the local real-time data buffer, perform format standardization processing on the read data, and transmit the processed parameters in real time to the dedicated data receiving port of the Python computing module through a local high-speed socket.

[0006] Optionally, in step S2, when the Python calculation module performs theoretical calculations of the core characteristic parameters of the network link based on the collected node motion states and basic link parameters of the target network, the core characteristic parameters of the network link include the link propagation delay, and the calculation function expression for the link propagation delay is: ; in, For link propagation delay, This represents the real-time distance of the link. The speed at which a signal propagates in the transmission medium. This refers to the processing latency of the network devices at both ends of the link. The delay deviation caused by the dynamic characteristics of the link.

[0007] Optionally, in step S2, when the Python calculation module completes the theoretical calculation of the core characteristic parameters of the network link based on the collected node motion state and basic link parameters of the target network, the core characteristic parameters of the network link include the link packet loss rate. Calculating the link packet loss rate includes first dividing the lost network data packets by the total number of network data packets to obtain the basic link packet loss rate, and then multiplying the basic link packet loss rate by a preset dynamic correction factor for the packet loss rate to obtain the final link packet loss rate.

[0008] Optionally, step S3 includes: S3.1 The software layer receives the core network link characteristic parameters fed back by the Python computing module, calls the qdisc component of the Linux kernel TC tool to complete the queue initialization, and configures the core parameters including: queue length, scheduling algorithm, fixed delay compensation value, delay jitter range, packet loss random seed, packet loss rate threshold, and enables packet loss correlation settings at the same time. S3.2, the software layer encapsulates the link data transmitted by the Python computing module according to the data packet format of the actual satellite network. The encapsulated data packets are sent into the qdisc queue in priority order. At the same time, the hardware clock adds an enqueue timestamp to each data packet and records the enqueue timestamp. S3.3 employs a method of combining fixed delay compensation with random delay jitter. During packet scheduling, a fixed delay compensation consistent with the baseline delay value is first added to the packet. Then, according to the preset delay jitter range, a random delay jitter value is assigned to the packet through a random number generator. The total simulated delay is the sum of the two. By calculating the difference between the enqueue timestamp and the dequeue timestamp, precise control of the simulated delay of the packet is achieved. S3.4, perform packet loss simulation, including: using a random packet loss algorithm based on Bernoulli distribution, after the data packet is enqueued, generate a random number in the range of 0-1 in real time. If the random number is less than the preset packet loss rate threshold, the data packet is directly discarded; if it is greater than the packet loss rate threshold, it is processed according to the scheduling algorithm. At the same time, by setting the packet loss correlation, the packet loss probability of adjacent data packets is correlated to simulate the continuous characteristics of packet loss in the actual network link. S3.5, packet dequeueing and hardware test data feedback, including: dequeueing packets in the qdisc queue according to the scheduling algorithm, adding nanosecond-level dequeue timestamps to the hardware, and real-time statistics of high-precision data including actual latency, number of lost packets, and packet loss location, and synchronously feeding back the hardware results to the Python calculation module as the true value; S3.6, Verification and Dynamic Parameter Adjustment, including: The Python calculation module compares the actual hardware values ​​with the theoretical calculation values. When the deviation exceeds the limit, adjustment instructions are simultaneously sent to the software layer and the hardware pipeline. The parameters at both ends are corrected synchronously, and the error is quickly converged to ensure simulation accuracy.

[0009] Optionally, step S4 includes: S4.1, the hardware and software integration of link state data, including: the Python calculation module completes the fusion and verification of multi-source data: the theoretical parameters output by the link characteristic calculation link are aligned and verified with the high-precision data such as the measured latency, actual packet loss rate, link connectivity status, and traffic congestion status transmitted back in real time by the programmable hardware unit, abnormal simulation data are eliminated, and a real-time link state matrix covering the entire link is constructed to provide accurate input for routing calculation that is completely synchronized with the simulation scenario; S4.2, Scenario-based adaptation and computation of routing algorithms, including: dynamically adapting routing algorithms according to the network topology characteristics and simulation requirements simulated by the simulation software: for static topology scenarios, Dijkstra's algorithm is used to solve the single-source shortest path; for dynamic topology scenarios, AODV on-demand routing algorithm is used; and for multi-path optimal routing scenarios, Yen's algorithm is used. The algorithm takes the fused real-time link state matrix as the only input and aims to optimize the minimum latency, the lowest packet loss rate, and the highest link connectivity stability to solve for the optimal routing path and candidate path set from the source node to the destination node. S4.3, Software and hardware synchronization and closed-loop update of routing results, including: the calculated optimal routing scheme is output in a standardized format to directly support the routing design, communication protocol verification and performance testing of the target network; on the other hand, it is synchronously and bidirectionally sent to the qdisc queue and programmable hardware unit in the software layer to update the traffic forwarding rules, flow matching table and scheduling priority of the software and hardware, so that the routing strategy matches the link simulation status in real time; when the network node motion state changes significantly or the hardware measured link parameters exceed the preset threshold, the route recalculation is automatically triggered to realize the dynamic closed-loop linkage between the routing scheme and the full-process link simulation.

[0010] Optionally, the programmable hardware unit is a P4 programmable switch, a network card, or an FPGA.

[0011] Furthermore, the present invention also provides a network link characteristic high-fidelity simulation device for the aforementioned network link characteristic high-fidelity simulation method, comprising an FPGA as a programmable hardware unit, the FPGA comprising: The core control module, CMCU, is a control module that enables bidirectional collaboration between the FPGA and the software layer. The message input processing unit is used to perform message input processing. The delay allocation and scheduling unit is used to perform delay allocation and scheduling. The message output and statistics unit is used to perform message output and statistics. The storage medium URAM is used to provide data buffers for the three units: the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit. The control core module CMCU and the storage medium URAM are respectively connected to the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit.

[0012] Optionally, the message input processing unit includes: The PREPARSE module, which is the message entry point for collaborative processing between the FPGA and the software layer, is responsible for distinguishing between beacon data messages and software control messages. For control messages, it directly forwards them to the control core module CMCU. For data messages, it constructs standardized meta data to provide a unified data basis for subsequent flow identification and delay allocation. The address management module UAM consists of a first-in-first-out (FIFO) queue, which provides cache addresses for beacon message allocation and recycling using the storage medium URAM. The message writing module PKT_AE_WRITE is responsible for writing beacon messages to the URAM storage medium. The hash lookup module Hash_LookUp uses the CRC32 hash algorithm to accurately match beacon flows based on the packet quintuple and Meta data. The matching results are fed back to the control core module CMCU in real time, realizing real-time coordination between flow identification rules and satellite dynamic topology. The flow hit counting module FLOW_HIT_COUNT is used to count the number of hits of the current beacon flow based on the flow identifier FLOW_ID obtained by the hash lookup module Hash_LookUp. Each cycle consists of 128 hits. At the same time, the first packet of the flow is marked, which provides a counting basis for the accurate allocation of subsequent flow delays and ensures the orderly execution of multiple sets of delay parameters issued by the software. The delay allocation and scheduling unit includes: The stream delay allocation module FLOW_DELAY_DISTRIBUTOR works in real-time with the Python calculation module to coordinate delay parameters. The beacon stream delay parameters calculated by the Python calculation module are sent to the URAM storage medium corresponding to the stream delay allocation module FLOW_DELAY_DISTRIBUTOR by the control core module CMCU. The stream delay allocation module FLOW_DELAY_DISTRIBUTOR calculates the addressing address according to the following formula: ; in, For addressing addresses; The stream identifier obtained from the hash lookup table above; The flow hit counting module obtains the count, and the flow delay allocation module FLOW_DELAY_DISTRIBUTOR reads the corresponding delay value through the calculated address and updates it to the Meta data, realizing the hardware-level precise execution of software delay parameters, while supporting real-time dynamic updates of parameters to adapt to the dynamic changes of beacon links; The Schedule_time_calculation module calculates the precise transmission time of the current beacon message based on the latency value in the Meta data and the transmission time of the previous message, and updates it to the storage medium URAM and Meta data. This provides a time reference for the precise scheduling of the Priority Queue Scheduling Module PIFO, ensuring the accurate reproduction of the software-defined latency value at the hardware level. The Priority Queue Scheduling (PIFO) module, based on the scheduling time issued by the software layer, achieves nanosecond-level precise control of message transmission timing through the cascaded scheduling of 512 shift registers, and performs hardware-level calibration of latency errors simulated by the software. At the same time, it completes hardware-level random packet loss simulation based on the packet loss rate threshold issued by Python, and the scheduling results are sent back to the Python calculation module in real time, providing a basis for adjusting the TC queue parameters. The message output and statistics unit includes: The message reading module PKT_AE_READ is responsible for writing and reading beacon messages to the storage medium URAM, realizing hardware-level caching and ordered scheduling of messages. It supports the storage and reading of beacon messages of up to 1518 bytes, and also completes the allocation and reclamation of bufid addresses to ensure the orderly execution of the entire message scheduling process. The PKT_DT_time stream latency statistics module is used to calculate the statistical data of beacon stream packet time interval, actual latency, and packet loss in real time. Each stream stores 128 statistical samples. The Statistical Results Encapsulation Module Summary_DT_send is used to encapsulate statistical data into standardized Ethernet packets and send them back to the Python calculation module in real time, providing accurate data support for deviation verification and parameter adjustment in the software layer.

[0013] Furthermore, the present invention also provides a high-fidelity simulation system for network link characteristics, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the high-fidelity simulation method for network link characteristics.

[0014] Compared with existing technologies, the present invention can mainly achieve the following beneficial effects: The present invention can adapt to the core characteristics of high dynamics, heterogeneity, and multi-link collaboration of various communication networks, realize high-fidelity network link characteristics and full-process software and hardware co-simulation, and can be applied to various wired and wireless communication network link characteristic simulation, network routing protocol verification, end-to-end communication system performance testing and other R&D scenarios, including but not limited to integrated air-space-ground-sea networks, terrestrial mobile communication networks, industrial internet, data center networks and other scenarios. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0016] Figure 2 This is a flowchart of a method for simulating network underlying characteristics in an embodiment of the present invention.

[0017] Figure 3 This is a structural diagram of the internal functional modules of the simulation device for network link characteristics in an embodiment of the present invention.

[0018] Figure 4 This is a flowchart illustrating the overall hardware and software integration for high-fidelity simulation of network link characteristics in this embodiment of the invention.

[0019] Figure 5 This is a timing diagram of message processing and delay control in an embodiment of the present invention. Detailed Implementation

[0020] This embodiment addresses the core requirement of high-fidelity simulation of network link characteristics by achieving full-process hardware and software collaboration across multiple stages, including network topology and node state simulation, link characteristic calculation, underlying network characteristic simulation, and network routing calculation. Utilizing general-purpose network simulation software, Python computing modules, the Linux kernel TC tool qdisc component, programmable hardware units, and standard routing algorithms, it achieves high-precision simulations of various communication network link characteristics such as latency, packet loss rate, latency jitter, and dynamic connectivity. The simulation results can be directly adapted to various engineering scenarios such as network routing design, communication protocol optimization, and end-to-end system performance testing for various communication networks. To enable those skilled in the art to better understand the technical solution of this invention, the following will provide a more detailed description of the technical solution of this invention in conjunction with the accompanying drawings in the embodiments of this invention.

[0021] like Figure 1As shown, the high-fidelity simulation method for network link characteristics in this embodiment includes the following steps: S1, building a network simulation environment using general network simulation software to simulate the network topology and node motion state of the target network, and collecting and reporting the node motion state and basic link parameters of the target network; S2, using a Python calculation module to perform theoretical calculations of the core characteristic parameters of the network link based on the collected node motion state and basic link parameters of the target network; S3, performing software and hardware co-simulation through the software and hardware layers: the software layer calls the qdisc component of the Linux kernel TC tool, and the hardware layer relies on programmable hardware units, combined with the qdisc queue scheduling principle of the qdisc component, to achieve accurate simulation of network link latency, packet loss, and jitter. Through closed-loop verification between theoretical calculation values ​​and actual simulation values, the simulation parameters are dynamically adjusted to ensure that the simulation accuracy closely matches the actual network link characteristics; S4, using the theoretical calculation results of the core characteristic parameters of the network link and the measured data returned by the hardware layer to complete dynamic routing calculations adapted to the real-time state of the link, and synchronously distributing the routing scheme to the software and hardware layers to update traffic forwarding rules to achieve dynamic closed-loop linkage of the entire simulation process. This embodiment of the high-fidelity simulation method for network link characteristics first uses general network simulation software to dynamically simulate network topology and node states, achieving real-time automated acquisition and transmission of basic link parameters without manual import / export operations. Second, based on link propagation delay and packet loss rate calculation models adapted to different transmission scenarios, it calculates flow-specific link characteristic parameters and synchronously sends the results bidirectionally to the software and hardware execution ends. Third, it employs a layered simulation architecture using TC / qdisc, coordinating network traffic control tools and programmable hardware units. The software layer, composed of network traffic control tools, performs coarse-grained simulation of link characteristics, while the hardware layer, composed of programmable hardware units, achieves nanosecond-level precise delay control, hardware-level packet loss simulation, and software simulation error calibration. Simultaneously, it receives measured data from the hardware layer to verify the deviation between theoretical and actual values ​​and dynamically correct parameters. Finally, it integrates the theoretical calculation results of link characteristics with the measured hardware data to perform dynamic routing calculations adapted to the real-time state of the link, and synchronously sends the routing scheme to the software and hardware layers to update traffic forwarding rules, achieving dynamic closed-loop linkage throughout the simulation process. This embodiment addresses the core requirement of high-fidelity simulation of network link characteristics. It achieves full-process hardware and software collaboration across multiple stages, including network topology and node state simulation, link characteristic calculation, network underlying characteristic simulation, and network routing calculation. Relying on general-purpose network simulation software, Python computing modules, the Linux kernel TC tool qdisc component, programmable hardware units, and standard routing algorithms, it completes high-precision simulations of various communication network link characteristics such as latency, packet loss rate, latency jitter, and dynamic connectivity. The simulation results can be directly adapted to various engineering scenarios such as network routing design, communication protocol optimization, and end-to-end system performance testing for various communication networks.The core implementation logic of this embodiment is as follows: Based on real-time automated data interaction, the manual import and export process is eliminated, realizing real-time feedback of network node status and topology changes to link characteristic calculation, real-time configuration of calculation results to network underlying simulation, and real-time support of simulation results to routing calculation. At the same time, through closed-loop verification between theoretical calculation values ​​and actual simulation values, simulation parameters are dynamically adjusted to ensure simulation accuracy. The software and hardware work together in each stage, with the software layer completing model calculation, state simulation and algorithm scheduling, and the hardware layer completing accurate simulation of network characteristics and nanosecond-level data processing, ultimately achieving a high degree of fit simulation of network link characteristics.

[0022] In this embodiment, step S1 builds a full-dimensional network simulation environment based on general network simulation software, completes the parameter configuration and dynamic simulation of network node attributes and link topology, realizes real-time acquisition of node motion status and basic link parameters, and transmits the parameters to the Python calculation module without delay through an automated program, providing accurate and real-time basic data for link characteristic calculation. Step S1 specifically includes: S1.1 Simulation environment and parameter configuration, including: importing the node parameters and topology data of the target network into general network simulation software, configuring the link topology parameters, and setting the simulation step size, simulation duration and data acquisition frequency to build a network simulation environment consistent with the actual communication network; general network simulation software includes but is not limited to STK, NS3, OPNET, GNS3, etc., which can be flexibly selected according to the type of target network; S1.2, Node motion and link dynamic simulation, including: starting the simulation, simulating the motion trajectory of network nodes, the change of relative positions between nodes and the dynamic connection and disconnection of links, capturing node motion status data and basic link parameters in real time, and storing all data in the local real-time data buffer of the simulation software at a preset frequency. S1.3, Automated Real-Time Parameter Transmission, includes: using a secondary development program written in Python to call the simulation software's standard interface to poll and read the local real-time data buffer; after reading, the data is standardized in format; and the processed parameters are transmitted in real-time to the dedicated data receiving port of the Python computing module via a local high-speed socket. Transmission latency is controlled to the millisecond level, with no manual intervention throughout the process, avoiding errors and delays from manual data processing.

[0023] In step S2, a computing module is built using Python as the development platform. It receives real-time node motion and link basic parameters transmitted by the network simulation software. Based on the preset high-precision link characteristic calculation model, the core characteristic parameters of the network link are calculated, and the calculation results are fed back to the network underlying characteristic simulation module in real time, providing a precise theoretical parameter benchmark for network characteristic simulation. (1) Loading the calculation model and initializing the parameters: The preset link characteristic calculation model is loaded in the Python computing module, including the free space propagation delay model and the link packet loss rate calculation model. At the same time, the key parameters of the model are initialized. The parameters can be flexibly adjusted according to the actual simulation scenario. (2) Real-time parameter reception and preprocessing: The Python computing module receives the standardized parameters transmitted by STK in real time through a dedicated data receiving port, verifies the validity of the parameters, removes outliers, and fills in missing values. (3) Calculation of core link characteristic parameters. In step S2 of this embodiment, when the Python computing module completes the theoretical calculation of the core characteristic parameters of the network link based on the collected node motion state and link basic parameters of the target network, the core characteristic parameters of the network link include the link propagation delay. The calculation function expression of the link propagation delay is: ; in, For link propagation delay, This represents the real-time distance of the link. The speed at which a signal propagates in the transmission medium. This refers to the processing latency of the network devices at both ends of the link. The delay deviation caused by the dynamic characteristics of the link.

[0024] In step S2 of this embodiment, when the Python calculation module completes the theoretical calculation of the core characteristic parameters of the network link based on the collected node motion state and basic link parameters of the target network, the core characteristic parameters of the network link include the link packet loss rate. Calculating the link packet loss rate includes first dividing the lost network data packets by the total number of network data packets to obtain the basic link packet loss rate, and then multiplying the basic link packet loss rate by a preset dynamic correction factor for the packet loss rate to obtain the final link packet loss rate.

[0025] Step S2 also includes real-time feedback of calculation results: the calculated baseline latency value, reasonable range of latency jitter, packet loss rate threshold and other core parameters are transmitted in real time to the parameter configuration interface of the network underlying characteristic simulation module through network sockets, and all calculation data are stored in high-speed solid-state drives for subsequent simulation result traceability and deviation verification.

[0026] Software and hardware co-simulation is performed through both software and hardware layers: the software layer calls the qdisc component of the Linux kernel TC tool, while the hardware layer relies on programmable hardware units composed of P4 programmable switches / network cards / FPGAs, combined with the qdisc queue scheduling principle, to achieve accurate simulation of network link latency, packet loss, and jitter. Simultaneously, through closed-loop verification between theoretical calculations and actual simulation values, simulation parameters are dynamically adjusted to ensure that the simulation accuracy closely matches the actual network link characteristics; for example... Figure 2 As shown, step S3 in this embodiment includes: S3.1 The software layer receives the core network link characteristic parameters fed back by the Python computing module, calls the qdisc component of the Linux kernel TC tool to complete the queue initialization, and configures the core parameters including: queue length, scheduling algorithm, fixed delay compensation value, delay jitter range, packet loss random seed, packet loss rate threshold, and enables packet loss correlation settings at the same time. S3.2, the software layer encapsulates the link data transmitted by the Python computing module according to the data packet format of the actual satellite network. The encapsulated data packets are sent into the qdisc queue in priority order. At the same time, the hardware clock adds an enqueue timestamp to each data packet and records the enqueue timestamp. S3.3 employs a method of combining fixed delay compensation with random delay jitter. During packet scheduling, a fixed delay compensation consistent with the baseline delay value is first added to the packet. Then, according to the preset delay jitter range, a random delay jitter value is assigned to the packet through a random number generator. The total simulated delay is the sum of the two. By calculating the difference between the enqueue timestamp and the dequeue timestamp, precise control of the simulated delay of the packet is achieved. S3.4, perform packet loss simulation, including: using a random packet loss algorithm based on Bernoulli distribution, after the data packet is enqueued, generate a random number in the range of 0-1 in real time. If the random number is less than the preset packet loss rate threshold, the data packet is directly discarded; if it is greater than the packet loss rate threshold, it is processed according to the scheduling algorithm. At the same time, by setting the packet loss correlation, the packet loss probability of adjacent data packets is correlated to simulate the continuous characteristics of packet loss in the actual network link. S3.5, packet dequeueing and hardware test data feedback, including: dequeueing packets in the qdisc queue according to the scheduling algorithm, adding nanosecond-level dequeue timestamps to the hardware, and real-time statistics of high-precision data including actual latency, number of lost packets, and packet loss location, and synchronously feeding back the hardware results to the Python calculation module as the true value; S3.6, Verification and Dynamic Parameter Adjustment, including: The Python calculation module compares the actual hardware values ​​with the theoretical calculation values. When the deviation exceeds the limit, adjustment instructions are simultaneously sent to the software layer and the hardware pipeline. The parameters at both ends are corrected synchronously, and the error is quickly converged to ensure simulation accuracy.

[0027] Step S4 is the closed-loop implementation stage of the hardware-software co-simulation. Its core is to integrate the theoretical calculation results of link characteristics with the actual link operation data measured by the hardware, thereby achieving real-time routing calculations that match the dynamic link characteristics of the network. In this embodiment, step S4 includes: S4.1, the hardware and software integration of link state data, including: the Python calculation module completes the fusion verification of multi-source data: the theoretical parameters output by the link characteristic calculation link are aligned and verified with the high-precision data such as the measured latency, actual packet loss rate, link connectivity status, and traffic congestion status transmitted back in real time by the programmable hardware unit, abnormal simulation data are eliminated, and a real-time link state matrix covering the entire link is constructed to provide accurate input for routing calculation that is completely synchronized with the simulation scenario; S4.2, Scenario-based adaptation and computation of routing algorithms, including: dynamically adapting routing algorithms according to the network topology characteristics and simulation requirements simulated by the simulation software: for static topology scenarios, Dijkstra's algorithm is used to solve the single-source shortest path; for dynamic topology scenarios, AODV on-demand routing algorithm is used; and for multi-path optimal routing scenarios, Yen's algorithm is used. The algorithm takes the fused real-time link state matrix as the only input and aims to optimize the minimum latency, the lowest packet loss rate, and the highest link connectivity stability to solve for the optimal routing path and candidate path set from the source node to the destination node. S4.3, Software and hardware synchronization and closed-loop update of routing results, including: the calculated optimal routing scheme is output in a standardized format to directly support the routing design, communication protocol verification and performance testing of the target network; on the other hand, it is synchronously and bidirectionally sent to the qdisc queue and programmable hardware unit in the software layer to update the traffic forwarding rules, flow matching table and scheduling priority of the software and hardware, so that the routing strategy matches the link simulation status in real time; when the network node motion state changes significantly or the hardware measured link parameters exceed the preset threshold, the route recalculation is automatically triggered to realize the dynamic closed-loop linkage between the routing scheme and the full-process link simulation.

[0028] The programmable hardware unit is a P4 programmable switch, a network card, or an FPGA.

[0029] This embodiment of the method effectively solves the problems of low accuracy in traditional pure software simulation, cumbersome operation of simple software and hardware combination simulation, and untimely data interaction through the coordinated linkage of the above four steps S1 to S4. It achieves high-precision, high-real-time, and high-fit simulation of network link characteristics. The accuracy of the simulation results and the matching degree between the simulation results and the actual network link operation scenario are significantly improved. It can be directly applied to practical R&D work such as routing design, communication protocol optimization, and network architecture planning of various communication networks.

[0030] This embodiment also provides a high-fidelity network link characteristic simulation device for the aforementioned high-fidelity network link characteristic simulation method, including an FPGA as a programmable hardware unit. Based on the overall architecture of the aforementioned high-fidelity network link characteristic simulation method, this embodiment uses an FPGA chip to complete the engineering implementation design for the hardware implementation layer of the programmable hardware unit and network simulation module in the device. Through modular hardware logic development, this device realizes core functions in network link characteristic simulation such as high-speed caching of data packets, accurate flow identification, accurate latency allocation and control, packet scheduling, hardware-software data interaction, and link status statistics. It provides underlying support for hardware-level simulation of network link latency, packet loss, and jitter, while simultaneously achieving high-speed real-time data interaction with the Python computing module and TC tool in the simulation device, ensuring high accuracy and real-time performance of the hardware-software co-simulation. This device is a complete simulation system including the aforementioned simulation device, supporting operating environment, and full-process co-simulation program, enabling one-click configuration of simulation tasks, fully automated operation, real-time visualization output of simulation results, and data retention. The core design concept of this FPGA hardware implementation scheme is as follows: Through modular hardware logic partitioning, it completes the entire process of message processing from the ingress to the egress, while simultaneously receiving and parsing link simulation parameters and statistically analyzing and transmitting link status data. Data interaction between functional modules is achieved through standardized interfaces. URAM is used as the core storage medium to ensure high-speed reading and writing of message data, flow status data, and latency parameters. Precise message scheduling is achieved through a PIFO queue, ultimately fulfilling the core requirements of the programmable hardware unit in the patent, including packet latency addition, packet loss control, jitter simulation, and nanosecond-level processing. Figure 3 As shown, the FPGA includes: The core control module, CMCU, is a control module that enables bidirectional collaboration between the FPGA and the software layer. The message input processing unit is used to perform message input processing. The delay allocation and scheduling unit is used to perform delay allocation and scheduling. The message output and statistics unit is used to perform message output and statistics. The storage medium URAM is used to provide data buffers for the three units: the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit. The control core module CMCU and the storage medium URAM are respectively connected to the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit.

[0031] In this embodiment, the message input processing unit includes: The PREPARSE module, which is the message entry point for collaborative processing between the FPGA and the software layer, is responsible for distinguishing between beacon data messages and software control messages. For control messages, it directly forwards them to the control core module CMCU. For data messages, it constructs standardized meta data to provide a unified data basis for subsequent flow identification and delay allocation. The address management module UAM consists of a first-in-first-out (FIFO) queue, which provides cache addresses for beacon message allocation and recycling using the storage medium URAM. The message writing module PKT_AE_WRITE is responsible for writing beacon messages to the URAM storage medium. The hash lookup module Hash_LookUp uses the CRC32 hash algorithm to accurately match beacon flows based on the packet quintuple and Meta data. The matching results are fed back to the control core module CMCU in real time, realizing real-time coordination between flow identification rules and satellite dynamic topology. The flow hit counting module FLOW_HIT_COUNT is used to count the number of hits of the current beacon flow based on the flow identifier FLOW_ID obtained by the hash lookup module Hash_LookUp. Each cycle consists of 128 hits. At the same time, the first packet of the flow is marked, which provides a counting basis for the accurate allocation of subsequent flow delays and ensures the orderly execution of multiple sets of delay parameters issued by the software.

[0032] In this embodiment, the delay allocation and scheduling unit includes: The stream delay allocation module FLOW_DELAY_DISTRIBUTOR works in real-time with the Python calculation module to coordinate delay parameters. The beacon stream delay parameters calculated by the Python calculation module are sent to the URAM storage medium corresponding to the stream delay allocation module FLOW_DELAY_DISTRIBUTOR by the control core module CMCU. The stream delay allocation module FLOW_DELAY_DISTRIBUTOR calculates the addressing address according to the following formula: ; in, For addressing addresses; The stream identifier obtained from the hash lookup table above; The flow hit counting module obtains the count, and the flow delay allocation module FLOW_DELAY_DISTRIBUTOR reads the corresponding delay value through the calculated address and updates it to the Meta data, realizing the hardware-level precise execution of software delay parameters, while supporting real-time dynamic updates of parameters to adapt to the dynamic changes of beacon links; The Schedule_time_calculation module calculates the precise transmission time of the current beacon message based on the latency value in the Meta data and the transmission time of the previous message, and updates it to the storage medium URAM and Meta data. This provides a time reference for the precise scheduling of the Priority Queue Scheduling Module PIFO, ensuring the accurate reproduction of the software-defined latency value at the hardware level. The Priority Queue Scheduling (PIFO) module, based on the scheduling time issued by the software layer, achieves nanosecond-level precise control of message transmission timing through the cascading scheduling of 512 shift registers, and performs hardware-level calibration of latency errors simulated by the software. At the same time, it completes hardware-level random packet loss simulation based on the packet loss rate threshold issued by Python, and the scheduling results are sent back to the Python calculation module in real time, providing a basis for adjusting TC queue parameters.

[0033] In this embodiment, the message output and statistics unit includes: The message reading module PKT_AE_READ is responsible for writing and reading beacon messages to the storage medium URAM, realizing hardware-level caching and ordered scheduling of messages. It supports the storage and reading of beacon messages of up to 1518 bytes, and also completes the allocation and reclamation of bufid addresses to ensure the orderly execution of the entire message scheduling process. The PKT_DT_time stream latency statistics module is used to calculate the statistical data of beacon stream packet time interval, actual latency, and packet loss in real time. Each stream stores 128 statistical samples. The Statistical Results Encapsulation Module Summary_DT_send is used to encapsulate statistical data into standardized Ethernet packets and send them back to the Python calculation module in real time, providing accurate data support for deviation verification and parameter adjustment in the software layer.

[0034] The hardware logic of this FPGA solution is divided into 11 core functional modules, including the URAM address management module UAM, the hash lookup module Hash_LookUp, the flow hit counting module FLOW_HIT_COUNT, the flow delay allocation module FLOW_DELAY_DISTRIBUTOR, the scheduling time calculation module Schedule_time_calculation, the priority queue scheduling module PIFO, the packet writing module PKT_AE_WRITE, the packet reading module PKT_AE_READ, the flow delay statistics module PKT_DT_time, the statistics result encapsulation module Summary_DT_send, the control core module CMCU, and the packet pre-parsing module PREPARSE. These modules work collaboratively to complete the entire packet processing process. A 256-bit Meta data bus serves as the core data exchange channel between modules. The Meta data contains key information such as flow identifier, packet length, delay value, scheduling time, and cache address, providing a unified data basis for the logic processing of each module. Detailed descriptions of the 11 core functional modules are as follows: The control core module (CMCU) serves as the core command bridge for bidirectional collaboration between the FPGA and the software layer, operating on a 500MHz system clock. It receives NACP control messages from the Python computing module, parses them into 64-bit hardware control commands, and distributes them to the corresponding functional modules to perform operations such as flow table updates, latency parameter adjustments, and packet loss rate configurations. Simultaneously, it aggregates the execution results and link statistics from each module, encapsulates them into NACP response messages, and transmits them back to the Python computing module in real time.

[0035] PREPARSE module: It is the message entry point for FPGA collaborative processing. It is responsible for distinguishing between beacon data messages and software control messages, providing a foundation for the collaborative processing of subsequent modules. For control messages, it directly forwards them to the control core module CMCU. For data messages, it constructs standardized meta data to provide a unified data basis for subsequent flow identification and delay allocation.

[0036] The Address Management Module (UAM) consists of an 11-bit wide and 2048-bit deep FIFO. It allocates and reclaims URAM cache addresses for beacon messages, ensuring the orderly management of the message hardware cache. At the same time, it adapts to the simulation requirements of continuous beacon stream transmission through address recycling.

[0037] The Hash Lookup module is the core unit for accurate beacon flow identification, working in real-time with the Python computation module to configure the flow table. The Python computation module updates flow table entries in real-time based on the beacon link topology simulated by STK, and sends the updates to the RAM of this module via the CMCU module. This module uses the CRC32 hash algorithm to accurately match beacon flows based on the packet 5-tuple and Meta data, supporting simultaneous identification of 10,000 beacon flows. The matching results are fed back to the CMCU module in real-time, achieving real-time coordination between flow identification rules and dynamic satellite topology.

[0038] The flow hit counting module FLOW_HIT_COUNT: Based on the FLOW_ID obtained by hash lookup, it cyclically counts the number of hits of the current beacon flow, with 128 hits per cycle. At the same time, it marks the first packet of the flow, providing a counting basis for the accurate allocation of subsequent flow delays and ensuring the orderly execution of multiple sets of delay parameters issued by the software.

[0039] The FLOW_DELAY_DISTRIBUTOR module is the core execution unit for implementing software-calculated parameters in hardware. It works in real-time with the Python calculation module to achieve delay parameter coordination. The beacon stream delay parameters calculated by the Python calculation module are distributed by the CMCU module and stored in the URAM storage medium of this module. This module reads the corresponding delay value through the calculated address and updates it to the Meta data, achieving precise hardware-level execution of software delay parameters. It also supports real-time dynamic updates of parameters to adapt to dynamic changes in the beacon link.

[0040] The Schedule_time_calculation module calculates the precise transmission time of the current beacon message based on the latency value in the Meta data and the transmission time of the previous message. This time value is then updated in the URAM and Meta data, providing a time reference for the accurate scheduling of the PIFO module and ensuring the accurate reproduction of the software-defined latency value at the hardware level.

[0041] Priority Queue Scheduling Module (PIFO): This module is the core unit for precise nanosecond-level latency control and software simulation with hardware calibration. It works in conjunction with the TC / qdisc module to achieve queue scheduling. The specific process is as follows: Figure 5As shown. The objects include: message, enqueue interface, qdisc scheduler, PIFO queue (priority queue scheduling module PIFO) and calculation module. The execution steps include: (1) message arrives, the message arrives through the enqueue interface; (2) timestamp t1; (3) message enqueue, enters the priority queue scheduling module PIFO; (4) qdisc scheduler stores message; (5) calculation module reads link parameters; (6) qdisc scheduler inserts message into queue; (7) calculation module sorts message according to scheduling time T_schedule; (8) calculation module sends system clock T_current to qdisc scheduler; (9) qdisc scheduler waits until T_current=T_schedule and executes message dequeue; (10) priority queue scheduling module PIFO timestamps message t2; (11) enqueue interface executes message sending.

[0042] The Priority Queue Scheduling (PIFO) module, based on the scheduling time issued by the software, achieves nanosecond-level precise control of message transmission timing through the cascading scheduling of 512 shift registers, and performs hardware-level calibration of the latency error simulated by the software. At the same time, it completes hardware-level random packet loss simulation based on the packet loss rate threshold issued by Python, and the scheduling results are sent back to the Python calculation module in real time, providing a basis for adjusting the TC queue parameters.

[0043] The message writing module PKT_AE_WRITE and the message reading module PKT_AE_READ are responsible for writing and reading beacon messages into and from URAM, respectively, realizing hardware-level caching and ordered scheduling of messages. They support the storage and reading of beacon messages up to 1518 bytes, and also complete the allocation and reclamation of BUFID addresses to ensure the orderly execution of the entire message scheduling process.

[0044] The PKT_DT_time module for flow latency statistics and the Summary_DT_send module for statistical result encapsulation are the core data acquisition units for hardware and software closed-loop verification. The PKT_DT_time module calculates real-time statistical data such as packet time intervals, actual latency, and packet loss counts for beacon flows, storing 128 statistical samples for each flow. The Summary_DT_send module encapsulates the statistical data into standardized Ethernet packets and transmits them back to the Python calculation module in real-time, providing accurate data support for software-layer deviation verification and parameter adjustment. It is the core data source for the closed-loop collaboration mechanism.

[0045] Figure 4This is the overall flowchart of the hardware and software integration for high-fidelity simulation of network link characteristics in this embodiment. The overall flowchart of the hardware and software integration for high-fidelity simulation of network link characteristics includes four steps: network topology and node state simulation, link characteristic calculation, network underlying characteristic calculation, and routing calculation, as shown in steps S1 to S4 above.

[0046] This embodiment of the method, through the aforementioned end-to-end hardware and software collaborative design, verifies that the high-fidelity simulation method, device, and system for network link characteristics described in this invention can achieve the following technical effects: Full-process automated collaboration: Enables fully automated linkage of network topology simulation, Python computation, TC / qdisc simulation, FPGA hardware execution, and routing computation, without manual import / export operations; Significantly enhanced dynamic adaptability: Simulation parameters can be dynamically adjusted in real time according to the movement state of network nodes and topology changes, fully adapting to the characteristics of highly dynamic network scenarios; Strong compatibility and scalability: Supports parallel simulation of large data streams, flexibly adapting to simulation scenarios of different communication networks such as wired and wireless, static and dynamic, single-link and multi-link, and flexibly adjusting the computational model, routing algorithm, and hardware configuration parameters according to the needs of the target system.

[0047] In addition, this embodiment also provides a high-fidelity simulation system for network link characteristics, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the high-fidelity simulation method for network link characteristics.

[0048] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A high-fidelity simulation method for network link characteristics, characterized in that, The process includes the following steps: S1, building a network simulation environment using general network simulation software to simulate the network topology and node motion states of the target network, collecting and reporting the node motion states and basic link parameters of the target network; S2, using a Python calculation module to perform theoretical calculations of the core characteristic parameters of the network links based on the collected node motion states and basic link parameters of the target network; S3, performing software and hardware co-simulation through the software and hardware layers: the software layer calls the qdisc component of the Linux kernel TC tool, and the hardware layer relies on programmable hardware units, combined with the qdisc queue scheduling principle of the qdisc component, to achieve accurate simulation of network link latency, packet loss, and jitter. Through closed-loop verification between theoretical calculation values ​​and actual simulation values, simulation parameters are dynamically adjusted to ensure that the simulation accuracy closely matches the actual network link characteristics; S4, using the theoretical calculation results of the core characteristic parameters of the network links and the measured data returned by the hardware layer to perform dynamic routing calculations adapted to the real-time link status, and synchronously distributing the routing scheme to the software and hardware layers to update traffic forwarding rules to achieve dynamic closed-loop linkage throughout the simulation process.

2. The high-fidelity simulation method for network link characteristics according to claim 1, characterized in that, Step S1 includes: S1.1 Simulation environment and parameter configuration, including: importing the node parameters and topology data of the target network into the general network simulation software, configuring the link topology parameters, and setting the simulation step size, simulation duration and data acquisition frequency to build a network simulation environment consistent with the actual communication network; S1.2, Node motion and link dynamic simulation, including: starting the simulation, simulating the motion trajectory of network nodes, the change of relative positions between nodes and the dynamic connection and disconnection of links, capturing node motion status data and basic link parameters in real time, and storing all data in the local real-time data buffer of the simulation software at a preset frequency. S1.3, Automated real-time parameter transmission, includes: using a secondary development program for simulation software written in Python to call the standard interface of the simulation software to poll and read the local real-time data buffer, perform format standardization processing on the read data, and transmit the processed parameters in real time to the dedicated data receiving port of the Python computing module through a local high-speed socket.

3. The high-fidelity simulation method for network link characteristics according to claim 2, characterized in that, In step S2, when the Python calculation module performs theoretical calculations of the core characteristic parameters of the network link based on the collected node motion states and basic link parameters of the target network, the core characteristic parameters of the network link include the link propagation delay, and the calculation function expression for the link propagation delay is: ； in, For link propagation delay, This represents the real-time distance of the link. The speed at which a signal propagates in the transmission medium. This refers to the processing latency of the network devices at both ends of the link. The delay deviation caused by the dynamic characteristics of the link.

4. The high-fidelity simulation method for network link characteristics according to claim 2, characterized in that, In step S2, when the Python calculation module completes the theoretical calculation of the core characteristic parameters of the network link based on the collected node motion state and basic link parameters of the target network, the core characteristic parameters of the network link include the link packet loss rate. The calculation of the link packet loss rate includes first dividing the lost network data packets by the total number of network data packets to obtain the basic link packet loss rate, and then multiplying the basic link packet loss rate by a preset dynamic correction factor for the packet loss rate to obtain the final link packet loss rate.

5. The high-fidelity simulation method for network link characteristics according to claim 3, characterized in that, Step S3 includes: S3.1 The software layer receives the core network link characteristic parameters fed back by the Python computing module, calls the qdisc component of the Linux kernel TC tool to complete the queue initialization, and configures the core parameters including: queue length, scheduling algorithm, fixed delay compensation value, delay jitter range, packet loss random seed, packet loss rate threshold, and enables packet loss correlation settings at the same time. S3.2, the software layer encapsulates the link data transmitted by the Python computing module according to the data packet format of the actual satellite network. The encapsulated data packets are sent into the qdisc queue in priority order. At the same time, the hardware clock adds an enqueue timestamp to each data packet and records the enqueue timestamp. S3.3 employs a method of combining fixed delay compensation with random delay jitter. During packet scheduling, a fixed delay compensation consistent with the baseline delay value is first added to the packet. Then, according to the preset delay jitter range, a random delay jitter value is assigned to the packet through a random number generator. The total simulated delay is the sum of the two. By calculating the difference between the enqueue timestamp and the dequeue timestamp, precise control of the simulated delay of the packet is achieved. S3.4, perform packet loss simulation, including: using a random packet loss algorithm based on Bernoulli distribution, after the data packet is enqueued, generate a random number in the range of 0-1 in real time. If the random number is less than the preset packet loss rate threshold, the data packet is directly discarded; if it is greater than the packet loss rate threshold, it is processed according to the scheduling algorithm. At the same time, by setting the packet loss correlation, the packet loss probability of adjacent data packets is correlated to simulate the continuous characteristics of packet loss in the actual network link. S3.5, packet dequeueing and hardware test data feedback, including: dequeueing packets in the qdisc queue according to the scheduling algorithm, adding nanosecond-level dequeue timestamps to the hardware, and real-time statistics of high-precision data including actual latency, number of lost packets, and packet loss location, and synchronously feeding back the hardware results to the Python calculation module as the true value; S3.6, Verification and Dynamic Parameter Adjustment, including: The Python calculation module compares the actual hardware values ​​with the theoretical calculation values. When the deviation exceeds the limit, adjustment instructions are simultaneously sent to the software layer and the hardware pipeline. The parameters at both ends are corrected synchronously, and the error is quickly converged to ensure simulation accuracy.

6. The high-fidelity simulation method for network link characteristics according to claim 5, characterized in that, Step S4 includes: S4.1, the hardware and software integration of link state data, including: the Python calculation module completes the fusion verification of multi-source data: the theoretical parameters output by the link characteristic calculation link are aligned and verified with the high-precision data such as the measured latency, actual packet loss rate, link connectivity status, and traffic congestion status transmitted back in real time by the programmable hardware unit, abnormal simulation data are eliminated, and a real-time link state matrix covering the entire link is constructed to provide accurate input for routing calculation that is completely synchronized with the simulation scenario; S4.2, Scenario-based adaptation and computation of routing algorithms, including: dynamically adapting routing algorithms according to the network topology characteristics and simulation requirements simulated by the simulation software: for static topology scenarios, Dijkstra's algorithm is used to solve the single-source shortest path; for dynamic topology scenarios, AODV on-demand routing algorithm is used; and for multi-path optimal routing scenarios, Yen's algorithm is used. The algorithm takes the fused real-time link state matrix as the only input and aims to optimize the minimum latency, the lowest packet loss rate, and the highest link connectivity stability to solve for the optimal routing path and candidate path set from the source node to the destination node. S4.3, Software and hardware synchronization and closed-loop update of routing results, including: the calculated optimal routing scheme is output in a standardized format to directly support the routing design, communication protocol verification and performance testing of the target network; on the other hand, it is synchronously and bidirectionally sent to the qdisc queue and programmable hardware unit in the software layer to update the traffic forwarding rules, flow matching table and scheduling priority of the software and hardware, so that the routing strategy matches the link simulation status in real time; when the network node motion state changes significantly or the hardware measured link parameters exceed the preset threshold, the route recalculation is automatically triggered to realize the dynamic closed-loop linkage between the routing scheme and the full-process link simulation.

7. The high-fidelity simulation method for network link characteristics according to claim 6, characterized in that, The programmable hardware unit is a P4 programmable switch, a network card, or an FPGA.

8. A network link characteristic high-fidelity simulation apparatus for the network link characteristic high-fidelity simulation method according to any one of claims 1 to 7, comprising an FPGA as a programmable hardware unit, the FPGA comprising: The core control module, CMCU, is a control module that enables bidirectional collaboration between the FPGA and the software layer. The message input processing unit is used to perform message input processing. The delay allocation and scheduling unit is used to perform delay allocation and scheduling. The message output and statistics unit is used to perform message output and statistics. The storage medium URAM is used to provide data buffers for the three units: the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit. The control core module CMCU and the storage medium URAM are respectively connected to the message input processing unit, the delay allocation and scheduling unit, and the message output and statistics unit.

9. The high-fidelity simulation device for network link characteristics according to claim 8, characterized in that, The message input processing unit includes: The PREPARSE module, which is the message entry point for collaborative processing between the FPGA and the software layer, is responsible for distinguishing between beacon data messages and software control messages. For control messages, it directly forwards them to the control core module CMCU. For data messages, it constructs standardized meta data to provide a unified data basis for subsequent flow identification and delay allocation. The address management module UAM consists of a first-in-first-out (FIFO) queue, which provides cache addresses for beacon message allocation and recycling using the storage medium URAM. The message writing module PKT_AE_WRITE is responsible for writing beacon messages to the URAM storage medium. The hash lookup module Hash_LookUp uses the CRC32 hash algorithm to accurately match beacon flows based on the packet quintuple and Meta data. The matching results are fed back to the control core module CMCU in real time, realizing real-time coordination between flow identification rules and satellite dynamic topology. The flow hit counting module FLOW_HIT_COUNT is used to count the number of hits of the current beacon flow based on the flow identifier FLOW_ID obtained by the hash lookup module Hash_LookUp. Each cycle consists of 128 hits. At the same time, the first packet of the flow is marked, which provides a counting basis for the accurate allocation of subsequent flow delays and ensures the orderly execution of multiple sets of delay parameters issued by the software. The delay allocation and scheduling unit includes: The stream delay allocation module FLOW_DELAY_DISTRIBUTOR works in real-time with the Python calculation module to coordinate delay parameters. The beacon stream delay parameters calculated by the Python calculation module are sent to the URAM storage medium corresponding to the stream delay allocation module FLOW_DELAY_DISTRIBUTOR by the control core module CMCU. The stream delay allocation module FLOW_DELAY_DISTRIBUTOR calculates the addressing address according to the following formula: ； in, For addressing addresses; The stream identifier obtained from the hash lookup table above; The flow hit counting module obtains the count, and the flow delay allocation module FLOW_DELAY_DISTRIBUTOR reads the corresponding delay value through the calculated address and updates it to the Meta data, realizing the hardware-level precise execution of software delay parameters, while supporting real-time dynamic updates of parameters to adapt to the dynamic changes of beacon links; The Schedule_time_calculation module calculates the precise transmission time of the current beacon message based on the latency value in the Meta data and the transmission time of the previous message, and updates it to the storage medium URAM and Meta data. This provides a time reference for the precise scheduling of the Priority Queue Scheduling Module PIFO, ensuring the accurate reproduction of the software-defined latency value at the hardware level. The Priority Queue Scheduling (PIFO) module, based on the scheduling time issued by the software layer, achieves nanosecond-level precise control of message transmission timing through the cascaded scheduling of 512 shift registers, and performs hardware-level calibration of latency errors simulated by the software. At the same time, it completes hardware-level random packet loss simulation based on the packet loss rate threshold issued by Python, and the scheduling results are sent back to the Python calculation module in real time, providing a basis for adjusting the TC queue parameters. The message output and statistics unit includes: The message reading module PKT_AE_READ is responsible for writing and reading beacon messages to the storage medium URAM, realizing hardware-level caching and ordered scheduling of messages. It supports the storage and reading of beacon messages of up to 1518 bytes, and also completes the allocation and reclamation of bufid addresses to ensure the orderly execution of the entire message scheduling process. The PKT_DT_time stream latency statistics module is used to calculate the statistical data of beacon stream packet time interval, actual latency, and packet loss in real time. Each stream stores 128 statistical samples. The Statistical Results Encapsulation Module Summary_DT_send is used to encapsulate statistical data into standardized Ethernet packets and send them back to the Python calculation module in real time, providing accurate data support for deviation verification and parameter adjustment in the software layer.

10. A high-fidelity simulation system for network link characteristics, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the high-fidelity simulation method for network link characteristics as described in any one of claims 1 to 7.

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