3D FPGA interconnect architecture based on configurable repeaters

Abstract

The application discloses a 3D FPGA interconnection architecture based on a configurable repeater, which comprises a plurality of layers of dies; the vertical direction of the die comprises a post-wiring, a configurable repeater unit and a through silicon via in a silicon substrate region in sequence; the configurable repeater unit comprises an input selector, a mode selection and signal path, an output driver and a configuration memory, wherein the mode selection and signal path comprises three modes, which are a pass-through mode, a latching mode and a terminal mode. The application constructs a special low-delay data channel through a plurality of chips through the CRU pass-through mode, supports dynamic reconfiguration to adapt to traffic changes while significantly reducing transmission delay and area overhead, and can effectively absorb the reflection energy of unused branches to guarantee signal integrity, thereby providing a high-energy-efficiency and high-reliability interconnection solution for large-scale streaming data transmission.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a 3D FPGA interconnect architecture based on configurable repeaters. Background Technology

[0002] With the introduction of 2.5D FPGAs based on Interposers by companies such as AMD and Xilinx (e.g., Virtex-7 2000T, Alveo U250), chip capacity has been significantly improved. However, this approach suffers from inherent problems such as long SLL line latency (on the order of microseconds), high driver power consumption, and large chip size. The industry anticipates achieving true 3D FPGA stacking through TSV vertical interconnect technology to overcome the performance bottleneck of 2.5D solutions.

[0003] In 3D FPGA chips, achieving efficient and low-latency inter-layer signal transmission is a core challenge in architecture design. Existing technologies mainly face the following problems: 1) The structure of the 3D hybrid granularity switch box is relatively complex: It requires a dedicated through-path circuit and a hybrid granularity access multiplexer at each interconnect point. For large-scale 3D FPGAs (tens of layers stacked), the total area and static power consumption of the switch box are still relatively high. 2) Fine granularity control: The design of the switch box is mainly aimed at local interconnects at the CLE level. For continuous streaming of large amounts of data (such as the output of DSP computing arrays, video streaming data, high-speed SerDes signal transmission, etc.), the bit-by-bit switching of the switch box is too "fine-grained" and the efficiency is not optimal. 3) Long design iteration cycle: The design of the switch box is tightly coupled with the overall routing architecture of the FPGA. Modifying the switch box will affect the routing resources of the entire die layer, resulting in a long design verification cycle.

[0004] 2) Existing TSV repeater solutions are not configurable. In traditional 3D integrated circuits, TSV channels usually contain repeater buffers with fixed functions to drive signals. However, the functions of these repeaters are fixed—either simple buffers (bypass) or registers with latches. They cannot dynamically adjust their working mode according to the actual needs of the signal (whether low-latency pass-through or timing-synchronous latching is required).

[0005] 3) Lack of lightweight vertical interconnects that support “streaming” For cross-layer transmission of large amounts of continuous data such as video streams, radar data streams, and AI feature maps, if each data bit goes through complex switching boxes and routing decisions, it will generate unnecessary overhead. The industry needs a lighter vertical interconnect solution that is more suitable for batch data streams.

[0006] 4) The problem of path end reflection is not solved. In 3D interconnects, a vertical path may only use part of the layers (for example, the signal is transmitted from the 1st layer to the 5th layer and then terminates). The path branches of the 6th layer and above are in a floating state. These floating branches will cause signal reflection, which will interfere with the path being used and cause signal integrity problems. Existing technologies lack the means to handle vertical path end matching. Summary of the Invention

[0007] The purpose of this invention is to provide a 3D FPGA interconnect architecture based on configurable repeaters as an alternative and supplement to the three-dimensional hybrid granularity wiring switch box, specifically addressing the problems of low-latency cross-layer communication, path end reflection, and dynamic reconfiguration of vertical paths in data streaming transmission.

[0008] The first aspect of this invention provides a 3D FPGA interconnect architecture based on a configurable repeater, comprising: Multilayer core; The die includes, in a vertical direction, a back-end wiring, a configurable repeater unit, and a silicon via in the silicon substrate region. The configurable repeater unit includes an input selector, a mode selector and signal path, an output driver, and a configuration memory. The mode selector and signal path includes three modes: pass-through mode, latch mode, and endpoint mode.

[0009] In this scheme, the pass-through mode is used at least for the cross-layer transmission of asynchronous signals, wherein the signal is transmitted directly from the input to the output through a pair of transmission gates or a tri-state buffer.

[0010] In this scheme, the latching mode is used at least for cross-layer transmission of synchronization signals. The signal is output after passing through an edge-triggered D flip-flop or after passing through a level-sensitive latch. The clock signal for clock alignment comes from the FPGA global clock or the dedicated clock for through-silicon vias.

[0011] In this scheme, the endpoint mode is not used for signal transmission, but for the end point of a vertical path. The input terminal is connected to ground or power supply through a programmable resistor, and the programmable resistor includes a transistor analog resistor that is controlled to be turned on / off by a configuration bit.

[0012] In this scheme, each layer of the die is provided with a configurable repeater unit array at the inlet / outlet of the vertical channel, wherein multiple configurable repeater units are vertically connected in series through silicon vias to form a repeater chain.

[0013] In this scheme, each configurable repeater unit corresponds to a vertical signal path. The configurable repeater unit is used to process signals from the lower layer and send them to the upper layer, or to access signals from the logic of this layer into the vertical channel.

[0014] In this solution, the configurable repeater unit is located between the through-silicon via pad and the FPGA internal interconnect resources, wherein the FPGA internal interconnect resources include at least a three-dimensional hybrid granularity switch box.

[0015] In this scheme, the input selector is used to select the input signal source of the configurable repeater unit, wherein the input signal source includes at least one of the following: lower layer through-silicon via input, FPGA logic signal of this layer, or output feedback of the configurable repeater unit of this layer.

[0016] In this scheme, the output driver is used to drive the processed signal to the upper silicon via or the logic of this layer, wherein the output driver has a programmable drive strength.

[0017] In this scheme, the configuration register is used to store the configuration information of the configurable repeater unit, wherein the configuration information includes input source selection configuration, operating mode selection configuration, drive strength selection configuration, and endpoint resistance value selection configuration.

[0018] The 3D FPGA interconnect architecture based on configurable repeaters disclosed in this invention has the following beneficial effects: 1. Optimal latency: The latency of the pass-through mode is only one transmission gate or a simple buffer, which is shorter than the path through the switch box.

[0019] 2. Area efficiency: The CRU has far fewer transistors than a complete six-port switch box, making it suitable for large-scale deployment.

[0020] 3. Supports streaming: Designed for bulk data streams, it can establish a low-latency "pass-through bus" that spans multiple layers.

[0021] 4. Solving signal integrity: The endpoint mode effectively absorbs reflected energy from unused branches.

[0022] 5. Dynamically reconfigurable: Supports runtime adjustments to adapt to dynamically changing traffic patterns. Attached Figure Description

[0023] Figure 1 The diagram shows the structure of the existing HBM solution. Figure 2 The diagram shows the structural schematic of the existing 2D scheme. Figure 3 This is a schematic diagram of an existing 3D router relay structure; Figure 4 A schematic diagram of a 3D FPGA interconnect architecture based on a configurable repeater according to the present invention is shown. Figure 5 The diagram shows the internal circuit structure of a configurable repeater unit based on a configurable repeater 3D FPGA interconnect architecture according to the present invention. Detailed Implementation

[0024] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0025] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0026] Before introducing this invention, some terms will be explained below.

[0027] FPGA chip: Field-Programmable Gate Array, is a semi-custom integrated circuit whose hardware functions can be defined by software configuration. Its core feature is that it is field-programmable. After leaving the factory, FPGA chips can be modified multiple times by users according to their needs to realize various customized functions, from simple logic control to complex signal processing.

[0028] Three-Dimensional FPGA: An FPGA that uses a three-dimensional stacked structure, which realizes the stacking and interconnection of multiple dies through through silicon vias or other vertical interconnect technologies.

[0029] TSV: Through-Silicon Via, a technology used to achieve wafer-level vertical interconnects.

[0030] CLE: Configurable Logic Element, the basic logic unit of an FPGA.

[0031] INT: Interconnection, interconnection module, wiring resources used in FPGA to implement signal interconnection.

[0032] Repeater: A circuit unit used in long-distance interconnects to restore signal strength and shape. It contains buffers or latches to prevent signal attenuation due to parasitic RC on the transmission line.

[0033] Configurable Repeater: The core circuit unit proposed in this invention, whose operating mode (through mode, latch mode, and end mode) can be dynamically set by the configuration bit.

[0034] Bypass / Transparent Mode: A working mode for configurable repeaters. Signals are transmitted directly from the input to the output with minimal delay (only the delay of a transmission gate or simple buffer), without any intermediate processing.

[0035] Latch / Registered Mode: A configurable repeater operating mode. The signal is sampled by an edge-triggered latch or flip-flop and then output in the next clock cycle. This mode is used for timing-critical pipelined cross-layer transmissions.

[0036] Terminated Mode: A working mode for the configurable repeater. The input is connected to ground or power supply via a programmable resistor to absorb signal energy for use at the end of the path or unused branches, preventing signal reflection.

[0037] Repeater Chain: A programmable transmission path formed by connecting configurable repeaters at the same position in each die layer in the vertical direction via TSVs.

[0038] Network-on-Chip (NoC): A chip-based communication architecture based on packet switching and routers, commonly used in large-scale multi-core processors.

[0039] Pass-through Bus: A concept proposed in this invention, referring to a virtual data transmission channel formed by a chain of repeaters that can penetrate multiple layers of dies.

[0040] Dynamic Reconfiguration: During normal FPGA operation, the functionality of certain configuration bits can be modified through a partial reconfiguration interface without affecting other logic modules.

[0041] In 3D integrated circuits, the parasitic resistance and capacitance of the TSV vertical channel can cause signal attenuation and increased delay. To address this issue, engineers typically insert repeater buffers into the TSV path. These repeaters are placed at regular intervals (e.g., through 1-2 die layers) to restore the voltage swing and drive capability of the signal.

[0042] In traditional 3D memory chips (such as HBM), these repeaters are fixed-function—typically simple inverter chains or buffers. They are designed to maximize transfer speeds but lack programmability.

[0043] In the FPGA field, the concept of "programmable repeaters" has been proposed by academia, but it has mainly been applied to long-line resources in two-dimensional FPGAs (such as the optional enable of long-line drivers in Xilinx FPGAs). However, there is currently no mature solution to extend these concepts to three dimensions and form a vertical interconnect architecture for the system.

[0044] Accordingly, the present invention lists the following implementation schemes that are most similar to the present invention: Scheme 1, Scheme 2, or Scheme 3.

[0045] Option 1: Fixed-function TSV trunk buffer (HBM solution), such as Figure 1 The diagram shows a schematic of an existing HBM solution. In HBM and other 3D memory chips, a fixed-function relay buffer is placed every one or two layers along the TSV path. These buffers are typically two inverters connected end-to-end (used to restore logic levels). The drawback is that these relay buffers have a fixed function and can only be used as buffers; they lack latching or other modes. For short paths that don't require relaying, these buffers introduce unnecessary delays. Furthermore, they cannot handle reflections from floating branches at the end of the signal path.

[0046] Option 2: Programmable long-line drivers in Xilinx FPGAs (2D solution), such as... Figure 2 As shown, this is a schematic diagram of the existing 2D solution. In Xilinx Virtex series FPGAs, long line resources are equipped with programmable enabled drivers. Users can select whether to enable the driver at a certain interconnect point through configuration bits to control the transmission distance of the signal. The disadvantage is that it is only suitable for long line transmission in a two-dimensional plane and has not been extended to three-dimensional TSV vertical channels. Moreover, this driver does not have latching mode and endpoint mode, and its function is limited.

[0047] Option 3: 3D router relay based on Network-on-Chip (NoC), such as... Figure 3The diagram shows a schematic of an existing 3D router relay structure. Some academic papers propose introducing a network-on-chip (NoC) in a 3D FPGA, with a router set up on each die layer. Data is transmitted between routers in the form of data packets, with TSVs serving as vertical links. The routers contain registers for pipelined operation. The disadvantages are that the router structure is complex (including routing tables, arbitrators, and buffers), has a large area overhead, and the routing decision of data packets increases the latency (usually several clock cycles). Moreover, the router structure is not suitable for the transmission of single-bit control signals.

[0048] In summary, as shown in Table 1, which presents a comparison of Schemes 1, 2, and 3 with the present invention, the present invention aims to provide a configurable repeater array that achieves on-demand 3D vertical interconnection through flexible switching of three operating modes (through / latch / terminal), achieving a better balance between area, latency, and flexibility.

[0049] Table 1. Comparison details of Schemes 1, 2, and 3 with the present invention

[0050] Specifically, as shown in the figure, this invention discloses a 3D FPGA interconnect architecture based on a configurable repeater, comprising: Multilayer core; The die includes, in a vertical direction, a back-end wiring, a configurable repeater unit, and a silicon via in the silicon substrate region. The configurable repeater unit includes an input selector, a mode selector and signal path, an output driver, and a configuration memory. The mode selector and signal path includes three modes: pass-through mode, latch mode, and endpoint mode.

[0051] It should be noted that, in this embodiment, as Figure 4 As shown, the 3D FPGA chip of the present invention includes multiple dies (Die0, Die1, ..., DieN-1). Each die has a CRU array at the entrance / exit of the vertical channel. Each CRU corresponds to a vertical signal path and is responsible for processing the signal from the lower layer (D port) and sending it to the upper layer (U port), or for connecting the signal from the logic of this layer to the vertical channel. The CRU is located between the TSV pad and the FPGA internal interconnect resources (such as a 3D hybrid granularity switch box or a direct connection to CLE). The FPGA internal interconnect resources include at least a 3D hybrid granularity switch box.

[0052] Furthermore, it should be noted that, in this embodiment, as Figure 5The diagram shows the internal circuit structure of a configurable repeater unit. The Input MUX selects the source of the input signal for the CRU. The available sources include: TSV input (D_IN) from the lower layer, signal (L_IN) from the FPGA logic of this layer (through interconnect modules), and output feedback from the CRU of this layer (for testing / diagnosis). It is used to implement a transmission gate-based multiplexer and is controlled by the configuration bit.

[0053] Furthermore, it should be noted that, in this embodiment, the core of the CRU is a configurable signal processing path that supports three operating modes. The pass-through mode is used at least for cross-layer transmission of asynchronous signals, where the signal is transmitted directly from the input to the output through a pair of transmission gates or a tri-state buffer. The latch mode is used at least for cross-layer transmission of synchronous signals, where the signal is output after passing through an edge-triggered D flip-flop or a level-sensitive latch. The clock signal for clock alignment comes from the FPGA global clock or the dedicated clock for through-silicon vias (TSVs). The endpoint mode is not used for signal transmission but for the end of a vertical path. The input is connected to ground or power supply through a programmable resistor, and the programmable resistor includes a transistor analog resistor that is controlled to be turned on / off by a configuration bit.

[0054] Specifically, in this embodiment, Mode 1: Bypass / Transparent Mode. Circuit implementation: The signal is directly transmitted from the input to the output through a pair of transmission gates (TG) or a simple tri-state buffer. There are no latches or flip-flops on this path; Delay characteristics: Minimum delay, approximately tens of picoseconds (depending on the on-resistance of the TG and the load capacitance); Applicable scenarios: Signals need to quickly cross multiple dies, where it is not desirable to be registered in intermediate layers, and for the cross-layer transmission of asynchronous signals, as well as for establishing high-speed data flow channels through multiple layers.

[0055] Mode 2: Latch / Registered Mode. The circuit implementation involves the signal passing through an edge-triggered D flip-flop (or a level-sensitive latch) before output. The clock signal (CLK_CRU) can come from the FPGA global clock GCLK network or the TSV dedicated clock TCLK. Delay characteristics: a one-clock-cycle delay (plus the flip-flop's setup / hold time). Applicable scenarios: synchronization signals transmitted across layers, when clock alignment is required, vertical data transmission in pipelined structures to improve throughput, and when signal paths are too long or timing is tight, inserting registers to interrupt critical paths.

[0056] Mode 3: Termination Mode. Circuit implementation: The input is connected to ground (VSS) or power supply (VDD) through a programmable resistor (a transistor analog resistor controlled by a configuration bit) to absorb signal energy and prevent reflection. Delay characteristics: Not used for signal transmission, only for the termination. Applicable scenarios: The end of a vertical path (the signal terminates at a certain layer and no longer transmits upwards), and unused vertical branches (such as a vertical channel that is no longer used after the 3rd layer; the CRUs of layers 4 to N should be set to termination mode), as well as impedance matching in test mode.

[0057] Furthermore, it should be noted that, in this embodiment, the output driver is used to drive the processed signal to the upper-layer through-silicon via (TSV) (U_OUT) or the logic of this layer (L_OUT). The output driver has a programmable drive strength to adapt to TSVs of different lengths and loads.

[0058] Furthermore, it should be noted that, in this embodiment, the configuration register is used to store the configuration information of the configurable repeater unit, wherein the configuration information includes input source selection configuration (2-bit), operating mode selection configuration (2-bit: pass-through / latch / end point / hold), drive strength selection configuration (2-bit), and end point resistance value selection configuration (2-bit, for end point mode).

[0059] Furthermore, multiple configurable repeater units are vertically connected in series via through-silicon vias to form a repeater chain. Correspondingly, for example, a repeater chain in a 4-layer stacked FPGA can be connected in the following manner.

[0060] Example 1: Establishing a direct data flow channel spanning four layers: Suppose there is a video stream that needs to be transmitted from Die0 to Die3, requiring low latency and no registering.

[0061] Die0: The input source of CRU[0] is selected as L_IN (from the logic of this layer), the working mode is selected as pass-through mode, and the output is to U_OUT.

[0062] Die1: The input source of CRU[1] is selected as D_IN (from the lower layer TSV), the working mode is selected as pass-through mode, and the output is to U_OUT.

[0063] Die2: The input source of CRU[2] is selected as D_IN (from the lower layer TSV), the working mode is selected as pass-through mode, and the output is to U_OUT.

[0064] Die3: The input source of CRU[3] is selected as D_IN (from the lower layer TSV), the working mode is selected as pass-through mode, and the output is to L_OUT (output to the logic of this layer).

[0065] Total delay = pass-through mode delay × 4 + TSV transmission delay, which is much smaller than the delay after passing through the switch box.

[0066] Example 2: Cross-layer transfer with pipelined registers: Assuming strict timing requirements, registers need to be inserted in the intermediate layer.

[0067] Die0: CRU[0] pass-through mode, sending data.

[0068] Die1: CRU[1] latch mode, data is sampled and registered on the rising edge of the clock.

[0069] Die2: CRU[2] pass-through mode, which transmits the registered data.

[0070] Die3: CRU[3] pass-through mode, output to the logic of this layer.

[0071] In this way, Die1's CRU acts as a pipeline register, interrupting the vertical path and helping to meet timing constraints.

[0072] Example 3: End point at the end of the path: Assume that a vertical channel only uses Die2, and CRUs of Die3 and above are set to endpoint mode.

[0073] The CRU settings for Die0, Die1, and Die2 can be configured as needed (through-through or latch-up).

[0074] The CRUs of Die3, Die4, ..., DieN-1 are set to end-point mode: the input is grounded through a programmable resistor to absorb reflected energy and ensure the integrity of the Die2 output signal.

[0075] Accordingly, in the organizational structure, each TSV location corresponds to one CRU. The CRU array is integrated with the FPGA's configuration circuitry, and the configuration address is determined by the TSV coordinates (X, Y, Layer). The configuration methods include: static configuration, where the configuration bitstream loads the CRU's configuration register simultaneously during the FPGA power-on configuration phase, and the user declares the CRU configuration by instantiating "programmable repeater primitives" using a hardware description language during design; and dynamic reconfiguration, where the CRU configuration is modified during system operation via the FPGA's PartialReconfiguration interface. For example, the repeater chain connection method can be dynamically adjusted based on the current data flow direction.

[0076] Furthermore, as shown in Table 2, a detailed comparison of the advantages of Schemes 1, 2, and 3 with the present invention is presented. In this invention, the delay of the pass-through mode is only one transmission gate or a simple buffer, which is shorter than the path through the switch box. At the same time, the number of transistors in the CRU is much less than that of a complete six-port switch box, making it suitable for large-scale deployment. It is designed specifically for batch data streams and can establish a low-latency "pass-through bus" that runs through multiple layers. Moreover, the endpoint mode effectively absorbs the reflected energy of unused branches and can support runtime adjustments to adapt to dynamically changing traffic patterns.

[0077] Table 2. Comparison of the advantages of Schemes 1, 2, and 3 with the present invention

[0078] In the several embodiments provided by this invention, it should be understood that the disclosed content can be implemented in other ways. For example, the architectural embodiments described above are merely illustrative, and actual implementations may have other divisions.

[0079] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0080] The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional modules.

[0081] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A 3D FPGA interconnect architecture based on configurable repeaters, characterized in that, include: Multilayer core; The die includes, in a vertical direction, a back-end wiring, a configurable repeater unit, and a silicon via in the silicon substrate region. The configurable repeater unit includes an input selector, a mode selector and signal path, an output driver, and a configuration memory. The mode selector and signal path includes three modes: pass-through mode, latch mode, and endpoint mode.

2. The 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The pass-through mode is used at least for the cross-layer transmission of asynchronous signals, wherein the signal is transmitted directly from the input to the output through a pair of transmission gates or a tri-state buffer.

3. The 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The latching mode is used at least for cross-layer transmission of synchronization signals, wherein the signal is output after passing through an edge-triggered D flip-flop or after passing through a level-sensitive latch, wherein the clock signal for clock alignment comes from the FPGA global clock or the dedicated clock for through-silicon vias.

4. The 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The endpoint mode is not used for signal transmission, but for the end point of a vertical path, wherein the input is connected to ground or power supply via a programmable resistor, and the programmable resistor includes a transistor analog resistor that is controlled to be turned on / off by a configuration bit.

5. A 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, Each layer of the die has a configurable repeater unit array at the inlet / outlet of the vertical channel, wherein multiple configurable repeater units are vertically connected in series through through-silicon vias to form a repeater chain.

6. The 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, Each configurable repeater unit corresponds to a vertical signal path, wherein the configurable repeater unit is used to process signals from the lower layer and send them to the upper layer, or to access signals from the logic of this layer into the vertical channel.

7. A 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The configurable repeater unit is located between the through-silicon via pad and the FPGA internal interconnect resources, wherein the FPGA internal interconnect resources include at least a three-dimensional hybrid granularity switch box.

8. A 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The input selector is used to select the input signal source of the configurable repeater unit, wherein the input signal source includes at least one of the following: lower layer through-silicon via input, FPGA logic signal of this layer, or output feedback of the configurable repeater unit of this layer.

9. A 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The output driver is used to drive the processed signal to the upper through-silicon via or the logic of this layer, wherein the output driver has a programmable drive strength.

10. A 3D FPGA interconnect architecture based on a configurable repeater according to claim 1, characterized in that, The configuration register is used to store the configuration information of the configurable repeater unit, wherein the configuration information includes input source selection configuration, operating mode selection configuration, drive strength selection configuration, and endpoint resistance value selection configuration.

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