Chip defect positioning method

Abstract

The application provides a chip defect positioning method, comprising: providing a chip, the chip comprising a top metal layer; using an optical detection lens to perform global positioning on the chip to obtain a first bright spot and a second bright spot corresponding to two adjacent edges of the chip respectively; using the optical detection lens to position the first bright spot and the second bright spot respectively, and obtaining coordinate values corresponding to pixel positions with the highest signal intensity in signal intensity curves of the first bright spot and the second bright spot respectively as coordinate positions of defects in the chip. The application can position the positions of defects under the top metal layer without removing the top metal layer when there is a single defect, improves the efficiency of defect positioning, and improves the accuracy of defect analysis.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for locating chip defects. Background Technology

[0002] Defect localization in a chip is the most crucial step in failure analysis. However, because a top metal layer on the chip can obscure the defect, it hinders localization. Therefore, the top metal layer is typically removed before defect localization. For power chips, which often have only one defect, even when targeting a single defect, the top metal layer must still be removed before localization.

[0003] Currently, common location methods include microscopy, beam-induced resistance change (BEDR) location, and thermal imaging location. Microscopy location captures photons released when electron-hole recombination occurs at the defect point when electricity is applied, locating the defect through photon distribution. It offers high accuracy and is suitable for leakage current analysis and latch-up analysis. However, the top metal layer blocks photons, requiring its removal before microscopy location, which may destroy original defect evidence. Beam-induced resistance change (BEDR) location uses a focused laser beam to scan the chip surface, raising the local temperature and causing resistance changes. It offers high accuracy and is suitable for short-circuit analysis and resistive leakage current analysis. However, the top metal layer also hinders laser heating. Thermal imaging location obtains thermal distribution images through thermal radiation to locate abnormal hotspots (i.e., defects). Its advantage is less susceptibility to the obstruction of the top metal layer, allowing location without removing it; however, its accuracy is lower.

[0004] Please refer to Figure 1 In the power chip, a substrate 10 has an epitaxial layer 12, a well region 14 on the epitaxial layer 12, a trench in the well region 14 extending into the epitaxial layer 12, and a polysilicon layer 16 filled in the trench, which can be a gate polysilicon layer; doped regions 18 are formed in the well region 14 on both sides of the trench, which can be source / drain regions; an insulating dielectric layer 20 is located on the well region 14, and a contact hole is formed in the insulating dielectric layer 20, which penetrates the doped region 18. A contact hole injection region is provided at the bottom of the doped region 18 for forming an ohmic contact, and the bottom of the contact hole exposes the contact hole injection region; a top metal layer 30 fills the contact hole and covers the insulating dielectric layer 20.

[0005] Please refer to Figure 2 Since there is no barrier layer under the top metal layer 30, the surface after removing the top metal layer 30 is the insulating dielectric layer 20, and the top metal layer 30 inside the contact hole is removed simultaneously, electrical testing cannot continue.

[0006] Please refer to Figure 3 A barrier layer 40 is formed on the inner wall of the contact hole, and the barrier layer 40 covers the surface of the insulating dielectric layer 20. The contact hole is filled with a metal material, which may be tungsten. The barrier layer 40 may be made of titanium or titanium nitride.

[0007] Please refer to Figure 4 Because a barrier layer 40 lies beneath the top metal layer 30, the surface after removing the top metal layer 30 is the barrier layer 40. This barrier layer 40 is conductive and very thin. While electrical testing is possible, chemical removal of the top metal layer 30 may lead to changes in the chip's electrical properties due to the chemical (strong acid / alkali) treatment. Furthermore, if the defect is located within the top metal layer 30 or between the top metal layer 30 and the underlying structure, removing the top metal layer 30 will disrupt the defect morphology and affect the defect analysis results. Summary of the Invention

[0008] The purpose of this invention is to provide a chip defect localization method that can locate the position of the defect under the cover of the top metal layer without removing the top metal layer when dealing with a single defect, thereby improving the efficiency of defect localization and the accuracy of defect analysis.

[0009] To achieve the above objectives, the present invention provides a chip defect localization method, comprising:

[0010] A chip is provided, the chip including a top metal layer;

[0011] The chip is globally located using an optical detection lens to obtain the first and second bright spots corresponding to two adjacent edges of the chip, respectively.

[0012] The optical detection lens is used to locate the first bright spot and the second bright spot respectively, and the coordinate values ​​corresponding to the pixel positions with the highest signal intensity in the signal intensity curves of the first bright spot and the second bright spot are obtained respectively, which are used as the coordinate positions of defects in the chip.

[0013] Optionally, the optical detection lens is an InGaAs lens.

[0014] Optionally, when performing global positioning of the chip, the magnification of the optical detection lens is less than the magnification of the optical detection lens when positioning the first bright spot and the second bright spot.

[0015] Optionally, when performing global positioning of the chip and positioning of the first bright spot and the second bright spot, a voltage is applied to the chip to generate photoelectric conversion at the location of the defect, and the defect emits light as a light-emitting point.

[0016] Optionally, the reference point for global positioning of the chip is the same as the reference point for positioning the first bright spot and the second bright spot.

[0017] Optionally, when performing global positioning of the chip and positioning of the first and second bright spots, the origin of the coordinate system of the optical detection lens is used as the reference point, and the reference point is not changed during positioning while the chip remains stationary.

[0018] Optionally, the step of obtaining the coordinate values ​​corresponding to the pixel positions with the highest signal intensity in the signal intensity curves of the first and second bright spots respectively includes:

[0019] Under the optical detection lens, the signal strengths at several pixel positions and at several pixel positions of the first bright spot and the second bright spot are obtained respectively.

[0020] Based on several pixel positions and corresponding signal intensities of the first and second bright spots, signal intensity curves of the first and second bright spots are obtained respectively.

[0021] The pixel position with the highest signal strength is obtained based on the peak values ​​of the signal strength curves of the first and second bright spots;

[0022] The coordinates of the defect are determined based on the pixel position with the highest signal strength among the first and second bright spots.

[0023] Optionally, after obtaining the coordinate location of the defect in the chip, a number of markers may be set around the coordinate location of the defect.

[0024] Optionally, the step of setting several markers around the coordinate location of the defect includes:

[0025] Move the coordinates of the defect to the center point of the optical detection lens;

[0026] Based on the center point of the optical detection lens, several marks are set around the coordinate position of the defect.

[0027] Optionally, the top metal layer does not have a pattern, and the mark is located on the top metal layer.

[0028] The chip defect localization method provided by this invention includes: providing a chip, the chip including a top metal layer; using an optical detection lens to perform global localization of the chip to obtain a first bright spot and a second bright spot corresponding to two adjacent edges of the chip, respectively; using the optical detection lens to locate the first bright spot and the second bright spot respectively, and obtaining the coordinate values ​​corresponding to the pixel positions with the highest signal intensity in the signal intensity curves of the first bright spot and the second bright spot respectively, as the coordinate positions of the defects in the chip. This invention utilizes the propagation characteristics of light in a medium, eliminating the need to remove the top metal layer for single defects. By analyzing the signals of bright spots at the chip edges, the location of defects hidden by the top metal layer can be located, improving the efficiency of defect localization; furthermore, it eliminates the need for chemical treatment of the chip, reducing the risk of electrical changes in the chip caused by strong acid and alkali treatments, and the morphology of the defect location is not destroyed, improving the accuracy of subsequent defect analysis. Attached Figure Description

[0029] Figure 1 This is a cross-sectional schematic diagram of a power chip in the prior art that does not have a barrier layer.

[0030] Figure 2 This is a cross-sectional schematic diagram of a power chip in the prior art that does not have a barrier layer and has had its top metal layer removed.

[0031] Figure 3 This is a cross-sectional schematic diagram of a power chip with a barrier layer in the prior art.

[0032] Figure 4 This is a cross-sectional schematic diagram of a power chip in the prior art with a barrier layer and the top metal layer removed.

[0033] Figure 5 This is a flowchart of a chip defect localization method provided in an embodiment of the present invention.

[0034] Figure 6 This is a cross-sectional schematic diagram of total internal reflection of light in a substrate in a chip defect localization method provided by an embodiment of the present invention.

[0035] Figure 7 This is a top view of total internal reflection of light in a substrate in a chip defect localization method provided by an embodiment of the present invention.

[0036] Figure 8 This is a highlight diagram illustrating the global positioning of a chip in a chip defect localization method provided in an embodiment of the present invention.

[0037] Figure 9 This is a bright spot image used to locate a first bright spot in a chip defect location method provided in an embodiment of the present invention.

[0038] Figure 10The signal intensity curve of the first bright spot in the chip defect localization method provided in an embodiment of the present invention.

[0039] Figure 11 This is a bright spot diagram for locating a second bright spot in a chip defect location method provided in an embodiment of the present invention.

[0040] Figure 12 The signal intensity curve of the second highlight in the chip defect localization method provided in an embodiment of the present invention.

[0041] Figure 13 This is a schematic diagram illustrating the setting of several marks around the location of a defect in a chip defect localization method provided in an embodiment of the present invention.

[0042] Figure 14 An electron microscope image showing a mark located on the top metal layer in a chip defect localization method provided in an embodiment of the present invention.

[0043] Figure 15 This is a slice image of a defect in a chip defect localization method provided in an embodiment of the present invention.

[0044] in, Figures 1-4 The attached figures are labeled as follows:

[0045] 10-Substrate; 12-Epipolar layer; 14-Trap region; 16-Polysilicon layer; 18-Doped region; 20-Insulating dielectric layer; 30-Top metal layer; 40-Barrier layer.

[0046] Figure 6 and Figure 7 The attached figures are labeled as follows:

[0047] 100 - Substrate; 200 - Top metal layer; 300 - Passivation layer; 400 - Defect; 500 - Bright spot. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The accompanying drawings are all in a very simplified form and are not drawn to scale, only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures; in particular, different proportions are sometimes used because different drawings need to show different focuses.

[0049] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0050] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0052] Please refer to Figure 5 This embodiment provides a chip defect localization method, including:

[0053] Step S1: Provide a chip, which includes a top metal layer;

[0054] Step S2: Use an optical detection lens to perform global positioning of the chip to obtain the first and second bright spots corresponding to two adjacent edges of the chip, respectively;

[0055] Step S3: Use an optical detection lens to locate the first bright spot and the second bright spot respectively, and obtain the coordinate values ​​of the pixel position with the highest signal intensity in the signal intensity curves of the first bright spot and the second bright spot respectively, so as to use as the coordinate position of the defect in the chip;

[0056] The following is combined Figures 6-15The chip defect location method provided in this embodiment will be described in detail.

[0057] Execution step S1: Please refer to Figure 6 and Figure 7 The chip is provided, comprising a substrate 100, a top metal layer 200, and a passivation layer 300. The chip is a power chip. The substrate 100 may include a substrate, an epitaxial layer, a well region, a doped region, a gate structure, and a source / drain region (structures not specifically shown in the figure), and may also include contacts and an insulating dielectric layer, but is not limited to the above structures. The top metal layer 200 is located on the top surface of the substrate 100 (i.e., the top surface of the chip may be the top metal layer 200), and the area of ​​the top metal layer 200 may be smaller than the area of ​​the substrate 100. The substrate 100 has a passivation layer 300 on its edge. Figure 7 (not shown in the image) The passivation layer 300 also extends to cover the edge of the top metal layer 200 to protect the top metal layer 200. The material of the passivation layer 200 may be an oxide and / or a nitride. Light can easily pass through the passivation layer 200.

[0058] Execution step S2: Please refer to Figure 8 , Figure 8 A bright spot image is created for global localization of the entire chip. Applying voltage to the chip causes photoelectric conversion at defect locations, converting electricity into light. The defect then acts as a light-emitting point, emitting infrared light, which requires an infrared lens for detection. Using an optical detection lens for global chip localization, when a significant defect exists, light propagates in all directions, and after reflection, reaches the chip edge, thus appearing as a bright spot at the chip edge. Figure 8 (The white rectangular dashed box indicates a bright spot), which is detected by the optical detection lens. In this embodiment, the optical detection lens is preferably an InGaAs lens. The detection wavelength of the InGaAs lens is between 750nm and 1650nm, which can detect infrared light. Furthermore, under low magnification conditions, the optical detection lens performs global positioning of the chip to obtain a bright spot map of the entire chip. In this embodiment, the origin of the coordinate system of the optical detection lens's moving mechanism is preferably used as the reference point. Then, the optical detection lens is used to perform global positioning of the chip, without changing the reference point and keeping the chip stationary. Alternatively, other positions can be used as the reference point, such as the lower left corner or the center of the chip, as long as the reference point is not changed and the chip is not moved during global positioning.

[0059] Please continue to refer to this. Figure 6 and Figure 7When light emitted from the light source enters the optically less dense medium (air) from the optically denser medium (substrate 100), total internal reflection occurs when the angle of incidence is greater than the critical angle. At this point, the light travels along the substrate 100 from the light-emitting point (defect 400 is the light-emitting point) to the farthest point (chip edge) via continuous total internal reflection. The chip edge is not shielded by the top metal layer 200. Figure 6 As can be seen, defect 400 acts as a light-emitting point. Light is continuously reflected by total internal reflection in substrate 100 to the edge of substrate 100 (i.e., chip edge), and then emits light through passivation layer 300 to create a bright spot at the chip edge. Figure 6 (As shown in the middle circular dashed frame). From Figure 7 As can be seen, defect 400 acts as a light-emitting point, and light propagates in all directions. Light attenuates as it travels through the medium. In a uniform medium, the degree of attenuation is positively correlated with the propagation distance; the farther the propagation distance, the greater the attenuation, and the weaker the brightness of the bright spot 500 at the chip edge. Conversely, brightness is the luminous intensity (i.e., light strength). Therefore, by capturing bright spots at the chip edge, defects hidden by the top metal layer inside the chip can be located. In many cases, power chips have only one defect. This embodiment focuses on locating defects with a single defect, and all bright spots at the chip edge are caused by this single defect.

[0060] In this embodiment, a first bright spot and a second bright spot corresponding to two adjacent edges of the chip are obtained. Specifically, under the optical detection lens, bright spots on all edges of the chip are detected. The chip is square, i.e., it has four edges. A single defect will produce a bright spot on at least two adjacent edges, and may also produce a bright spot on three or four edges. The bright spots corresponding to two adjacent edges of the chip are selected as the first bright spot and the second bright spot. If a single defect produces a bright spot on three or four edges, the light intensity of the bright spots on the three or four edges will be different because the distance of the defect from the three or four edges may be different. Preferably, the bright spots of the two adjacent edges with the highest light intensity among the three or four edges are selected as the first bright spot and the second bright spot. Figure 8 The two bright spots shown in the white rectangular dashed frame can be the first bright spot and the second bright spot. The location of a single defect can be located by the first bright spot and the second bright spot. Furthermore, the light propagates in all directions, and the closer the distance, the higher the light intensity and the smaller the attenuation. It is preferable to select the two bright spots with the highest light intensity among the three or four edges, which is more conducive to accurately locating the defect.

[0061] Step S3: Apply voltage to the chip, which also generates photoelectric conversion at the defect location in the chip, converting electricity into light. The defect acts as a light-emitting point, emitting infrared light, which needs to be detected by an infrared lens. The first and second bright spots are located (localized) using an optical detection lens, preferably an InGaAs lens. InGaAs lenses have a detection wavelength between 750nm and 1650nm and can detect infrared light. Under high magnification, the first and second bright spots are located separately to obtain bright spot maps. In this embodiment, the magnification of the optical detection lens is lower when performing global chip positioning than when locating the first and second bright spots. For example, for... Figure 8 The two bright spots (the first and second bright spots) shown within the white rectangular dashed frame are located. A magnified view of this location facilitates subsequent analysis of the signal strength of the first and second bright spots. Please refer to [the provided text]. Figure 9 This can serve as a location illustration for the primary highlight; please refer to it. Figure 11 This can be a schematic diagram for locating the second bright spot. In this embodiment, the reference point for locating the first and second bright spots using the optical detection lens is the same as the reference point for global chip positioning using the optical detection lens. The reference point is not changed during local positioning, and the chip remains stationary.

[0062] In this embodiment, the coordinates of the pixel positions with the highest signal intensity in the signal intensity curves of the first and second bright spots are obtained respectively, and used as the coordinates of defects in the chip. Specifically, under an optical detection lens, several pixel positions of the first bright spot and the corresponding signal intensities are detected. For example, the optical detection lens can obtain a digital image composed of countless tiny squares, each small square being a pixel position. One bright spot corresponds to several pixel positions, and each pixel position has a corresponding signal intensity. Based on the several pixel positions of the first bright spot and the corresponding signal intensities, since a bright spot will have several pixel positions, and the signal intensities at different pixel positions will differ, it is necessary to establish a signal intensity curve for the bright spot based on the several pixel positions and the corresponding signal intensities to obtain the signal intensity curve of the first bright spot. Please refer to... Figure 10 , Figure 10 It indicated Figure 9The signal intensity curve of the first bright spot is plotted, with the horizontal axis representing pixel position and the vertical axis representing signal intensity. The pixel position with the highest signal intensity is obtained based on the peak value of the signal intensity curve for the first bright spot. The pixel position corresponding to the highest signal intensity of the first bright spot is then determined based on the curve correspondence. Next, the Y-coordinate of the defect is calibrated using the pixel position with the highest signal intensity in the first bright spot, establishing the chip's coordinate system.

[0063] Similarly, using an optical detection lens, the pixel positions of the second bright spot and the corresponding signal intensities are detected; based on these pixel positions and corresponding signal intensities, a signal intensity curve for the second bright spot is obtained; please refer to... Figure 12 , Figure 12 It indicated Figure 11 The signal strength curve of the second bright spot is plotted, with the horizontal axis representing pixel position and the vertical axis representing signal strength. The pixel position with the highest signal strength is determined by the peak value of the signal strength curve for the second bright spot. The pixel position corresponding to this peak signal strength is then determined based on the curve correspondence. Next, the X-coordinate of the defect is calibrated using the pixel position with the highest signal strength in the second bright spot, establishing the chip's coordinate system. If the X-coordinate of the defect is calibrated based on the first bright spot, then the Y-coordinate is calibrated based on the second bright spot. The defect's coordinate position on the chip is then obtained using both the X and Y coordinates.

[0064] Furthermore, when the top metal layer does not have a pattern, the process also includes setting several marks (marking) around the coordinate position of the defect. Specifically, the coordinate position of the defect is moved to the center point of the optical detection lens. For example, if the coordinate position of the defect is (X0, Y0), this coordinate position (X0, Y0) is moved to the center point of the optical detection lens, that is, the coordinate position of the defect is aligned with the center point of the optical detection lens. Based on the center point of the optical detection lens, several marks are set around the coordinate position of the defect. Specifically, the laser marking device is connected to the optical detection lens, the center point of the optical detection lens is aligned with the coordinate position of the defect, and within the radius provided by the optical detection lens, the laser marking device is used to mark the top layer around the coordinate position of the defect. An image of the marked defect is obtained through the optical detection lens. The image contains the marks and the center point of the optical detection lens (the center point is the defect position), and a grid ruler is superimposed on the image. The grid ruler is a built-in grid ruler of the optical detection lens, which can be automatically superimposed when saving the image. Each grid cell in the grid ruler has a fixed size, and the distance from the mark to the defect is determined by counting the grid cells. Although the coordinates of the defect are known, subsequent analysis requires moving the chip to the corresponding device for processing. The defect is typically marked, but directly marking its coordinates might obscure its morphology, affecting the analysis results. Therefore, several markers are placed around the defect's coordinates. Since the defect's coordinates align with the center point of the optical detection lens, these markers are placed around the lens's center point to mark the defect's location, thus avoiding damage to its morphology.

[0065] In this embodiment, the top metal layer does not have a pattern; the mark is located on the top metal layer. When the top metal layer has a pattern, the location of the defect can be obtained by referring to the edge of the pattern, and marking is not required. Please refer to... Figure 13 , Figure 13The image shows the marked area. The grid in the image is a grid ruler. The scale of each grid in the grid ruler can be the same, and the scale of one grid can be 5μm (not limited to this). The black dots in the image (as shown by the black circular dashed frame) are markers. The white-filled dot in the center of the image is the center point of the optical detection lens (i.e., the defect location, which is not marked at the defect). Several markers are distributed around the coordinate position of the defect. That is, the distance from the marker to the defect is determined by counting the grids. For example, consider two marks adjacent to the center point of the optical detection lens horizontally (left and right) and two marks adjacent to the center point vertically (top and bottom). Each grid is 5 μm in size. The distance between the left mark and the center point of the optical detection lens is approximately 5 grids, so the distance from the left mark to the center point of the optical detection lens is 25 μm. The distance between the right mark and the center point of the optical detection lens is approximately 4.5 grids, so the distance from the right mark to the center point of the optical detection lens is 22.5 μm. The distance between the top mark and the center point of the optical detection lens is approximately 5 grids, so the distance from the top mark to the center point of the optical detection lens is 25 μm. The distance between the bottom mark and the center point of the optical detection lens is approximately 5 grids, so the distance from the bottom mark to the defect is 25 μm. In other words, the distances from the center point of the optical detection lens to the four marks are determined by counting the grids, thus determining the distances from the four marks to the defect. The figure illustrates seven marks, and the spacing between the seven marks and the coordinates of the defect can be the same (or different). Please refer to... Figure 14 The diagram shows that the marker (indicated by the white dashed box in the diagram) is located on the top metal layer.

[0066] Furthermore, after obtaining the distances from several markers to the defect, an optical measuring instrument is used for measurement. Based on these distances, the location of the defect can be determined. For example, each marker can be treated as a dot, and circles can be drawn with the distance from each marker to the defect as the radius. The position of the circles corresponding to all markers is the location of the defect. After obtaining the location of the defect, physical property analysis is performed on the defect to obtain its morphology and size. This allows us to determine which film layer and process the defect occurs in, facilitating subsequent process control. Please refer to [reference needed]. Figure 15 The defect is indicated by the white dashed box in the image. Figure 15 This is for illustrative purposes only; the structure will differ after slicing different chips.

[0067] In summary, the chip defect localization method provided by this invention includes: providing a chip, the chip comprising a top metal layer; using an optical detection lens to perform global localization of the chip to obtain a first bright spot and a second bright spot corresponding to two adjacent edges of the chip, respectively; using the optical detection lens to locate the first bright spot and the second bright spot respectively, and obtaining the coordinate values ​​corresponding to the pixel positions with the highest signal intensity in the signal intensity curves of the first bright spot and the second bright spot respectively, as the coordinate positions of the defects in the chip. This invention utilizes the propagation characteristics of light in a medium, eliminating the need to remove the top metal layer for single defects. By analyzing the signals of bright spots at the chip edges, the location of defects hidden by the top metal layer can be located, improving the efficiency of defect localization; furthermore, it eliminates the need for chemical treatment of the chip, reducing the risk of electrical changes in the chip caused by strong acid and alkali treatments, and the morphology of the defect location is not destroyed, improving the accuracy of subsequent defect analysis.

[0068] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A chip defect location method, characterized in that, include: A chip is provided, the chip including a top metal layer; The chip is globally located using an optical detection lens to obtain the first and second bright spots corresponding to two adjacent edges of the chip, respectively. The optical detection lens is used to locate the first bright spot and the second bright spot respectively, and the coordinate values ​​corresponding to the pixel positions with the highest signal intensity in the signal intensity curves of the first bright spot and the second bright spot are obtained respectively, which are used as the coordinate positions of defects in the chip.

2. The chip defect location method as described in claim 1, characterized in that, The optical detection lens is an InGaAs lens.

3. The chip defect location method as described in claim 1, characterized in that, When performing global positioning of the chip, the magnification of the optical detection lens is less than that when positioning the first bright spot and the second bright spot.

4. The chip defect location method as described in claim 1, characterized in that, When performing global positioning of the chip and positioning of the first bright spot and the second bright spot, a voltage is applied to the chip, and photoelectric conversion is generated at the location of the defect, and the defect emits light as a light-emitting point.

5. The chip defect location method as described in claim 1, characterized in that, The reference point for global positioning of the chip is the same as the reference point for positioning the first bright spot and the second bright spot.

6. The chip defect location method as described in claim 5, characterized in that, When performing global positioning of the chip and positioning of the first and second bright spots, the origin of the coordinate system of the optical detection lens is used as the reference point, and the reference point is not changed during positioning while the chip remains stationary.

7. The chip defect location method as described in claim 1, characterized in that, The steps for obtaining the coordinates of the pixel positions with the highest signal intensity in the signal intensity curves of the first and second bright spots respectively include: Under the optical detection lens, the signal strengths at several pixel positions and at several pixel positions of the first bright spot and the second bright spot are obtained respectively. Based on several pixel positions and corresponding signal intensities of the first and second bright spots, signal intensity curves of the first and second bright spots are obtained respectively. The pixel position with the highest signal strength is obtained based on the peak values ​​of the signal strength curves of the first and second bright spots; The coordinates of the defect are determined based on the pixel position with the highest signal strength among the first and second bright spots.

8. The chip defect location method as described in claim 1, characterized in that, After obtaining the coordinate location of the defect in the chip, the method further includes setting several markers around the coordinate location of the defect.

9. The chip defect location method as described in claim 8, characterized in that, The step of setting several marks around the coordinate location of the defect includes: Move the coordinate position of the defect to the center point of the optical detection lens; Based on the center point of the optical detection lens, several marks are set around the coordinate position of the defect.

10. The chip defect location method as described in claim 8, characterized in that, The top metal layer has no pattern, and the mark is located on the top metal layer.

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