A phase detection circuit, method and electronic device
By introducing an orthogonal generator and comparator calibration mechanism into the frequency multiplier, the signal phase difference is adjusted, which solves the performance degradation problem caused by the poor orthogonality of the frequency multiplier, improves signal stability and differential performance, and is suitable for millimeter-wave communication.
Patent Information
- Application Number
- CN202510205361.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-08-25
AI Technical Summary
In existing technologies, the poor orthogonality of frequency multipliers leads to signal performance degradation, especially under PVT variations, where performance such as noise and differential properties become unstable, affecting the application of millimeter-wave communication.
A quadrature generator is used to generate a precise differential signal, which is then multiplied by a frequency multiplier. A comparator is used to calibrate the signal phase, and a bidirectional shift register is used to adjust the phase difference of the quadrature generator to achieve rapid and accurate signal calibration.
It improves the differential and duty cycle stability of the signal after frequency multiplication, ensures the system remains stable under various PVT conditions, avoids signal quality fluctuations, and improves the performance of the frequency multiplier.
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Figure CN122631945A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit design, and more specifically, to a phase detection circuit, method, and electronic device. Background Technology
[0002] Millimeter-wave communication is a high-speed, high-bandwidth wireless communication method, but it suffers from problems such as high hardware costs and limited output distance, which restricts its development in practical applications. Using traditional baseband local oscillators to obtain high-frequency sources has limitations in terms of phase noise and stability. In order to solve the bottleneck problem of millimeter-wave communication, frequency multiplier technology has been widely used. The method of using low-frequency local oscillators cascaded with frequency multipliers can effectively solve this problem.
[0003] Frequency multiplier technology amplifies millimeter-wave signals by multiplying low-frequency signals, thereby improving output power and frequency response. For example, in 5G-10G frequency multiplication, in scenarios with high noise requirements, the Gilbert cell structure, compared to frequency multipliers implemented with logic gates (XOR), offers wider operating bandwidth, better noise performance, and superior circuit performance, making it suitable for high-frequency circuits. In practical applications, due to its structure, the Gilbert cell requires a quadrature signal generator before it. In many processes, the poor orthogonality of the four-phase output signals under PVT (Polymer Transformer) conditions leads to deterioration in the duty cycle, differential characteristics, and noise performance of the frequency multiplier output signal.
[0004] In related technologies, frequency doubling is often achieved using the Gilbert cell structure. The input of the frequency multiplier requires four-phase signals (with phases differing by 90° sequentially). Due to the large phase difference between the four-phase signals achieved by the delay unit under PVT (i.e., specific process, voltage, and temperature conditions), the performance of the frequency multiplier, such as noise and differential performance, is poor, making it unsuitable for some high-demand scenarios. Summary of the Invention
[0005] This application provides a phase detection circuit, method, and electronic device to at least solve the performance degradation problem caused by poor orthogonality of frequency multipliers in related technologies.
[0006] According to one embodiment of this application, a phase detection circuit is provided, including: a quadrature generator, a frequency multiplier, a comparator, and a bidirectional shift register. The frequency multiplier has its input connected to the quadrature generator and its output connected to the comparator, and is used to multiply the frequency of the differential signal generated by the quadrature generator, outputting the multiplied signal to the comparator. The comparator compares a reference signal with the signal output by the frequency multiplier, generates high and low levels, and outputs the high and low levels to the bidirectional shift register. The bidirectional shift register has its output connected to the quadrature generator and is used to change the phase difference of the differential signal generated by the quadrature generator according to the high and low levels output by the comparator.
[0007] According to another embodiment of this application, a phase detection method is provided, comprising: a frequency multiplier multiplies the differential signal generated by a quadrature generator and outputs the multiplied signal to a comparator; the comparator compares the signal output by the frequency multiplier with a reference voltage and generates high and low levels, so that a bidirectional shift register changes the phase difference of the differential signal generated by the quadrature generator according to the high and low levels.
[0008] According to yet another embodiment of this application, an electronic device is also provided, including the phase detection circuit described above.
[0009] Through the embodiments described above in this application, the differential signal with precise phase difference generated by the quadrature generator, followed by frequency multiplication by the frequency multiplier, can improve the differential performance and duty cycle stability of the multiplied signal. The comparator compares the reference signal with the signal output by the frequency multiplier, generating high and low level signals based on their phase relationship. This calibration mechanism enables the system to remain stable under various PVT conditions, avoiding signal quality fluctuations caused by environmental changes. The bidirectional shift register adjusts the phase of the quadrature generator based on the high and low level signals fed back from the comparator, achieving rapid and accurate calibration of the signal orthogonality. This solves the performance degradation problem caused by poor orthogonality of the frequency multiplier in related technologies. Attached Figure Description
[0010] Figure 1 This is a phase detection circuit diagram according to an embodiment of this application;
[0011] Figure 2 This is a phase detection circuit diagram according to another embodiment of the present application;
[0012] Figure 3 This is a phase detection circuit diagram according to yet another embodiment of this application;
[0013] Figure 4 This is a phase detection circuit diagram according to another embodiment of this application;
[0014] Figure 5 This is a flowchart of a phase detection method according to an embodiment of this application;
[0015] Figure 6 This is a phase detection circuit diagram according to another embodiment of this application;
[0016] Figure 7 This is a schematic diagram of orthogonality calibration feedback according to an embodiment of this application;
[0017] Figure 8 This is a schematic diagram of an orthogonal generator model according to an embodiment of this application. Figure 1 ;
[0018] Figure 9 This is a schematic diagram of an orthogonal generator model according to an embodiment of this application. Figure 2 . Detailed Implementation
[0019] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.
[0020] Figure 1 The phase detection circuit diagram according to an embodiment of this application includes: a quadrature generator, a frequency multiplier, a comparator, and a bidirectional shift register. The frequency multiplier, with its input connected to the quadrature generator and its output connected to the comparator, is used to multiply the frequency of the differential signal generated by the quadrature generator and output the multiplied signal to the comparator. The comparator compares a reference signal with the signal output by the frequency multiplier, generates high and low levels, and outputs the high and low levels to the bidirectional shift register. The bidirectional shift register, with its output connected to the quadrature generator, is used to change the phase difference of the differential signal generated by the quadrature generator according to the high and low levels output by the comparator.
[0021] In an exemplary embodiment of this application, the frequency multiplier is used to multiply the frequency of the differential signal generated by the quadrature generator, including: the frequency multiplier is used to multiply the frequency of two sets of differential signals with a phase difference of 90 degrees generated by the quadrature generator.
[0022] In one embodiment, the frequency multiplier is a Gilbert cell structure.
[0023] In an exemplary embodiment of this application, a bidirectional shift register is used to change the phase difference of the differential signal generated by the quadrature generator according to the high or low level of the comparator output, including: when the comparator output is low, the bidirectional shift register shifts right to increase the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator; when the comparator output is high, the bidirectional shift register shifts left to decrease the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator.
[0024] In exemplary embodiments of this application, as Figure 2 As shown, except Figure 1 The phase detection circuit shown includes a frequency divider, whose output is connected to a bidirectional shift register and a comparator, and is used to provide a clock signal for the comparator and the shift register.
[0025] In exemplary embodiments of this application, as Figure 3 As shown, except Figure 2The phase detection circuit shown includes the following components: an input buffer connected to the input of the quadrature generator and the input of the frequency divider, used to generate a clock control signal and input the clock control signal to the quadrature generator; and an output buffer connected to the frequency multiplier and the comparator, used to shape and drive the signal output by the frequency multiplier.
[0026] In exemplary embodiments of this application, as Figure 4 As shown, except Figure 3 The phase detection circuit shown includes a filter module, whose input is connected to the frequency multiplier and whose output is connected to the comparator, used to perform low-pass filtering on the signal output by the frequency multiplier.
[0027] Figure 5 This is a flowchart of a phase detection method according to an embodiment of this application, which includes the following steps:
[0028] Step S502: The frequency multiplier multiplies the differential signal generated by the quadrature generator and outputs the multiplied signal to the comparator.
[0029] In an exemplary embodiment of this application, the frequency multiplier multiplies the differential signal generated by the quadrature generator, including: the frequency multiplier multiplies the two sets of differential signals generated by the quadrature generator with a phase difference of 90 degrees.
[0030] In step S504, the comparator compares the signal output by the frequency multiplier with the reference voltage and generates high and low levels, so that the bidirectional shift register changes the phase difference of the differential signal generated by the quadrature generator according to the high and low levels.
[0031] In an exemplary embodiment of this application, the bidirectional shift register changes the phase difference of the differential signal generated by the quadrature generator according to the high and low levels, including: when the comparator outputs a low level, the bidirectional shift register shifts to the right and increases the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator; when the comparator outputs a high level, the bidirectional shift register shifts to the left and decreases the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator.
[0032] In an exemplary embodiment of this application, a frequency divider is used to provide clock signals for the comparator and shift register.
[0033] In an exemplary embodiment of this application, the signal output by the frequency multiplier is low-pass filtered by a filtering module.
[0034] To facilitate understanding of the technical solutions provided in the application embodiments, the following description is based on specific scenario embodiments.
[0035] Figure 6 This is a phase detection circuit diagram according to another embodiment of this application, such as... Figure 6 As shown, the overall frequency multiplier link includes an input buffer, a quadrature generator, a Gilbert cell, an output buffer, a low-pass filter, a comparator, a quadrature latch, and a shift register. The core circuitry includes the quadrature generator, the Gilbert cell, the comparator, and the shift register. The Gilbert cell is a type of frequency multiplier structure. First, the signal passes through the quadrature generator to produce four-phase signals with sequentially 90° phase differences. These are then input to the Gilbert cell for frequency multiplication. The multiplied output is driven and shaped by the output buffer before being output. Simultaneously, the signal is low-pass filtered after passing through the output buffer and input to the comparator. The comparator compares the duty cycle coefficient with 50%, and the comparator output is input to the shift register to control left or right shift. Whether to maintain the current position is determined before outputting or the feedback loop continues to adjust, controlling the phase difference of the four-phase output. After the overall system loops, the phase error of the four-phase signal under PVT can be significantly reduced, improving the frequency multiplier performance.
[0036] In this embodiment, the input frequency of the phase detection circuit is 5-10 GHz, and the output is 10-20 GHz. The input and output buffers are designed with sufficient driving capability (square wave transmission is used internally). A quadrature generator combined with a calibration circuit outputs a high-precision four-phase output, which is then input to the Gilbert cell for frequency multiplication. This embodiment effectively improves the accuracy of the four-phase output through the quadrature calibration circuit, effectively mitigating the performance degradation issues of the Gilbert cell under PVT conditions, such as duty cycle, differential characteristics, and noise.
[0037] like Figure 7 The diagram shown illustrates the orthogonality calibration feedback. The differential signal is input to the delay chain of the quadrature generator, which outputs a four-phase signal. The signal is then frequency-multiplied by a Gilbert unit. The frequency-multiplied signal is shaped and driven by an output buffer. The output signal is filtered and then input to a comparator for comparison with Vref (reference signal). If the difference is less than Vref, the comparator outputs a low level, indicating that the phase deviation is less than 90°. This controls the shift register to shift right, feeding back to the quadrature generator to increase the output phase difference. Conversely, if the difference is greater, the phase difference decreases. The overall calibration period is based on the number of delay units as needed. When the calibration period exceeds the number of delay units, the latch-up function is activated.
[0038] Figure 8 This is a schematic diagram of an orthogonal generator model according to an embodiment of this application. Figure 1 , Figure 8The quadrature generator shown achieves the unit step size by changing the number of delay units. Figure 8 An input signal “p(n)” is initially introduced into the delay chain, which consists of multiple delay units connected in series. The output signals of each delay unit are labeled X(0), X(1), X(2), X(3), and X(4), representing different delay states of the signal after passing through the delay unit. The output signal “dp(dn)” is obtained by combining the appropriately delayed signal with the original input signal to ensure a precise 90° phase difference between the output signals. The accuracy of the signal phase difference can be controlled by the X(n) switch, which represents the control switch for the number of delay units, used to adjust the delay in the signal path, thereby fine-tuning the phase of the output signal.
[0039] Figure 9 This is a schematic diagram of an orthogonal generator model according to an embodiment of this application. Figure 2 The unit step size is achieved by controlling the load size, and Figure 8 The delay chains in the two are different. Figure 9 The quadrature generator in the model uses a buffer to process the input signal p(n) and generate the output signal dp(dn). Figure 9 The control mechanism in this system changes the phase difference of the signal by adjusting the load size of the buffer, rather than directly changing the number of delay units. Changing the load size affects the time delay of the signal as it passes through the circuit, thus affecting the signal phase. This method also uses the X(n) switch to adjust the signal phase, ensuring that the output differential signal has a precise 90° phase difference.
[0040] Figure 8 and Figure 9 Both of the orthogonal generator model structures shown are applicable to the frequency multiplier in the embodiments of this application.
[0041] As shown in the schematic diagram of the quadrature generator model above, the quadrature generator is used to generate two sets of differential signals with a phase difference of 90°. The phase difference accuracy can be controlled by the X(n) switch. Under PVT, the phase difference accuracy is adjusted by a comparator and a shift register, feeding the control signal back to the quadrature generator to adjust the phase difference, and then outputting it to the Gilbert unit to complete the frequency multiplication. Therefore, the quadrature calibration model proposed in this application effectively solves the duty cycle and differential problems caused by poor orthogonality.
[0042] Compared with related technologies, the embodiments of this application adopt a frequency multiplier with, for example, a Gilbert cell structure. On this basis, an additional positive calibration scheme is adopted to improve the stability of the frequency multiplier under PVT and effectively improve the noise performance of the high-speed frequency multiplier. In practical applications, the smaller the step size of a single delay unit in the quadrature generator, the higher its four-phase output accuracy, and the better the differential performance and duty cycle of the frequency multiplier output.
[0043] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.
[0044] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0045] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.
[0046] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.
[0047] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.
[0048] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.
[0049] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.
Claims
1. A phase detection circuit, characterized in that, The circuit includes: a quadrature generator, a frequency multiplier, a comparator, and a bidirectional shift register, wherein, The frequency multiplier has its input terminal connected to the quadrature generator and its output terminal connected to the comparator. It is used to multiply the frequency of the differential signal generated by the quadrature generator and output the multiplied signal to the comparator. The comparator is used to compare the reference signal and the signal output by the frequency multiplier, generate a high level and a low level, and output the high and low levels to the bidirectional shift register; The bidirectional shift register has its output connected to the quadrature generator, and is used to change the phase difference of the differential signal generated by the quadrature generator according to the high and low levels output by the comparator.
2. The phase detection circuit according to claim 1, characterized in that, The frequency multiplier is used to multiply the frequency of the differential signal generated by the quadrature generator, including: The frequency multiplier is used to multiply the frequency of the two differential signals generated by the quadrature generator, which have a 90-degree phase difference.
3. The phase detection circuit according to claim 1, characterized in that, The bidirectional shift register is used to change the phase difference of the differential signal generated by the quadrature generator according to the high and low levels output by the comparator, including: When the comparator outputs a low level, the bidirectional shift register shifts to the right, which is used to increase the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator; When the comparator outputs a high level, the bidirectional shift register shifts left to reduce the phase difference of the differential signal generated by the quadrature generator by controlling the number of turned-on delay units in the quadrature generator.
4. The phase detection circuit according to claim 1, characterized in that, Also includes: The frequency divider, whose output is connected to the bidirectional shift register and the comparator, is used to provide a clock signal for the clock of the comparator and the shift register.
5. The phase detection circuit according to claim 4, characterized in that, Also includes: An input buffer, connected to the input of the quadrature generator and the input of the frequency divider, is used to generate a clock control signal and input the clock control signal into the quadrature generator; An output buffer, with its input connected to the frequency multiplier and its output connected to the comparator, is used to shape and drive the signal output by the frequency multiplier.
6. The phase detection circuit according to claim 5, characterized in that, Also includes: The filtering module has its input connected to the frequency multiplier and its output connected to the comparator, and is used to perform low-pass filtering on the signal output by the frequency multiplier.
7. A phase detection method, applied to the phase detection circuit according to any one of claims 1-6, characterized in that, include: The frequency multiplier multiplies the frequency of the differential signal generated by the quadrature generator and outputs the multiplied signal to the comparator. The comparator compares the signal output by the frequency multiplier with the reference voltage and generates high and low levels, so that the bidirectional shift register changes the phase difference of the differential signal generated by the quadrature generator according to the high and low levels.
8. The method according to claim 7, characterized in that, The frequency multiplier multiplies the frequency of the differential signal generated by the quadrature generator, including: The frequency multiplier multiplies the frequency of the two differential signals generated by the quadrature generator, which have a 90-degree phase difference.
9. The method according to claim 7, characterized in that, The bidirectional shift register changes the phase difference of the differential signal generated by the quadrature generator according to the high and low levels, including: When the comparator outputs a low level, the bidirectional shift register shifts to the right, and the phase difference of the differential signal generated by the quadrature generator is increased by controlling the number of turn-on delay units in the quadrature generator; When the comparator outputs a high level, the bidirectional shift register shifts to the left, and the phase difference of the differential signal generated by the quadrature generator is reduced by controlling the number of turn-on delay units in the quadrature generator.
10. The method according to claim 7, characterized in that, The method further includes providing a clock signal for the comparator and the shift register via a frequency divider.
11. The method according to claim 7, characterized in that, The method further includes: performing low-pass filtering on the signal output by the frequency multiplier using a filtering module.
12. An electronic device, characterized in that, Includes the phase detection circuit described in any one of claims 1 to 6.