Storage data reading method, storage device, and computer program product
By asynchronously issuing mapping table read commands to execute user data tasks in parallel, the problem of serial blocking of read requests in flash memory is solved, achieving low latency and high throughput in high-concurrency scenarios, and is suitable for various flash storage devices.
Patent Information
- Application Number
- CN202610755247.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-28
- Publication Date
- 2026-08-25
AI Technical Summary
In existing technologies, flash memory suffers from high read latency and low system throughput due to serial blocking of read requests caused by the synchronous loading of the L2P mapping table during data reading. Furthermore, the multi-plane hardware concurrency capability is not fully utilized.
By asynchronously issuing map table read commands and scheduling user data read tasks that have hit the cache to be executed in parallel on idle planes during the waiting period, the read blocking caused by map table loading is eliminated, and the hardware concurrency capabilities of multiple planes are fully utilized.
Significantly reduces read latency in high-concurrency scenarios, improves system throughput, concurrency capabilities and resource utilization, and adapts to different flash memory hardware architectures.
Smart Images
Figure CN122633110A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data storage technology, and in particular to a data storage and retrieval method, storage device, and computer program product. Background Technology
[0002] Flash memory, as a highly integrated embedded storage solution, integrates flash memory chips and a main control chip. Due to its advantages in cost, size, and ease of use, it is widely used in tablets, smart TV boxes, smartphones, and various IoT devices. Because flash memory inherently features off-site updates and garbage collection, the logical address issued by the host must be translated into an actual physical address by querying an L2P (Logical to Physical) mapping table to complete data access.
[0003] In related technologies, the following two methods are mainly used to achieve data reading: The first method is synchronous loading of the L2P mapping table. This method employs a synchronous blocking loading model: when processing I / O read requests, if the L2P mapping table cache is not hit, the system must wait for the L2P mapping table to be loaded from flash memory before continuing the data read operation. This leads to two prominent problems: first, the mapping table loading and data reading are executed serially, resulting in accumulated read latency; second, the main control chip cannot issue other read commands during the waiting period, leading to low hardware resource utilization.
[0004] The second method is the Sequential Write Log (SeqWriteLog) acceleration method. This method reduces the number of repeated loadings of the L2P mapping table by recording the logical addresses of recent writes, but it does not change the underlying synchronous blocking model. This method fails to utilize the multi-plane architecture of flash memory (a plane is a basic unit that can run independently and in parallel within a flash memory chip), and multiple read commands are still scheduled serially, limiting concurrency capabilities.
[0005] In summary, existing technologies generally suffer from the following drawbacks: Synchronous blocking leads to high read latency; Plane concurrency capabilities are not fully utilized: read commands are executed serially, multi-plane hardware parallelism is idle, and system throughput is low. Summary of the Invention
[0006] The main purpose of this application is to propose a data storage and reading method, storage device, and computer program product, which aims to solve the problems of serial blocking of read requests and high read latency caused by synchronous loading of L2P mapping tables in the prior art.
[0007] The first aspect of this application provides a method for reading stored data, including: Query the L2P mapping table corresponding to the current read task; When the L2P mapping table cache corresponding to the current read task is not hit, an asynchronous mapping table read command is sent to the flash memory, and the cache status of the L2P mapping table is marked as loading. While waiting for the L2P mapping table to finish loading, retrieve at least one other read task from the task queue, wherein the L2P mapping table cache of the other read task has been hit; Determine the busy / idle status of each plane in the flash memory, and schedule at least one other read task's user data read command and L2P mapping table read command to different idle planes for parallel execution.
[0008] As can be seen from the above, by asynchronously issuing mapping table read commands and scheduling user data read tasks that have hit the cache to be executed in parallel on idle planes during the waiting period, the read blocking caused by mapping table loading is eliminated, the hardware concurrency capability of multiple planes is fully utilized, the read latency in high-concurrency scenarios is significantly reduced and the system throughput is improved.
[0009] In at least one possible implementation, before querying the L2P mapping table corresponding to the current read task, the method further includes: monitoring the read task sequence issued by the host, counting the number of consecutive read tasks and the amount of data they request; confirming that a preset number of read tasks have been received consecutively and that the amount of data requested by each read task is less than or equal to a preset sector threshold.
[0010] As mentioned above, detecting consecutive small data block read tasks before asynchronous delivery and enabling asynchronous parallelism only in high-concurrency random read scenarios avoids introducing unnecessary overhead in non-high-concurrency scenarios (such as sequential reads or large block reads). Since there are no address conflicts between small data block read operations, the parallelism of the Plane is almost unlimited, releasing the throughput potential of the flash multi-Plane architecture.
[0011] In at least one possible implementation, after scheduling at least one other read task's user data read command and the L2P mapping table read command to different idle Planes for parallel execution, the method further includes: detecting the number of read commands being executed on each Plane. When the number of read commands reaches a preset threshold, DMA transfer is triggered, the completed mapping table is cached in the main control chip memory, and the completed user data is transferred to the host.
[0012] As described above, traditional DMA transfers are typically triggered by host read requests (i.e., DMA only starts after the host actively requests data). This application proposes using hardware parallelism (i.e., the number of concurrent read commands) as the triggering condition, thereby reducing the time data remains in the cache, releasing cache resources in advance, and freeing up space for subsequent commands. This proactive DMA transfer can significantly reduce the overall system response latency.
[0013] In at least one possible implementation, after the cached state of the L2P mapping table is marked as loading, if a subsequent read task requests the same L2P mapping table, the duplicate mapping table read command is skipped, and the process waits for the L2P mapping table to finish loading.
[0014] As can be seen from the above, by marking the status as "loading", other read tasks can directly hit the cache when they need to access the same logical address, avoiding repeated mapping table read requests and reducing redundant mapping table loading operations.
[0015] In at least one possible implementation, when a preset number of read tasks are not received consecutively, or when the amount of data requested by any read task in a series of consecutive read tasks exceeds a preset sector threshold, the following steps are also performed: If the L2P mapping table cache is hit, then the user data read command is issued directly; If the L2P mapping table cache is not hit, the system will synchronously wait for the L2P mapping table to be loaded before issuing the user data read command.
[0016] As can be seen from the above, when the condition of consecutive small data blocks is not met, the system switches to the conventional synchronous read mode to ensure that the system can still work stably in the traditional way in non-target scenarios (such as sequential read or large block read scenarios). Together with the asynchronous delivery mode, it constitutes a complete mode adaptive reading scheme.
[0017] In at least one possible implementation, when the L2P mapping table cache of the current read task is hit, the target plane where the user data is located is determined according to the L2P mapping table. When there are no pending read commands in the target plane, a user data read command is issued to the target plane.
[0018] As can be seen from the above, in the scenario of a cache hit, the target Plane is checked for idleness before the read command is issued, which avoids command serialization due to Plane conflicts and improves the scheduling efficiency of read commands when the cache is hit.
[0019] In at least one possible implementation, if there are incomplete read commands in the target plane, the current read task is skipped, the current read task is put back to the end of the task queue, and the next read task is queried.
[0020] As can be seen from the above, when the target plane is busy, a non-blocking scheduling strategy is adopted to put the current read task back to the end of the queue and continue to process other tasks, so as to prevent the entire task queue from being stalled due to the busyness of a single plane, thereby improving the fairness of task scheduling and the overall concurrency.
[0021] In at least one possible implementation, scheduling at least one other read task's user data read command and L2P mapping table read command to different idle planes for parallel execution includes: Execution can be performed in parallel on different planes within the same flash memory chip; or in parallel on planes between different flash memory chips.
[0022] As can be seen from the above, it can adapt to a wider range of flash memory hardware architectures, covering all flash storage devices from low-end eMMC to high-end SSDs (such as UFS, NVMe SSDs, etc.).
[0023] Secondly, embodiments of this application provide a storage device including a processor and a memory, the memory being coupled to the processor, the memory being used to store computer program code, the computer program code including computer instructions, and when the processor reads the computer instructions from the memory, the processor performs the steps in the storage data reading method as described in the first aspect.
[0024] Thirdly, embodiments of this application provide a computer program product, the computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform the steps in the data storage reading method described in the first aspect.
[0025] The beneficial effects of this application are: Eliminate mapping table loading blocking and reduce read latency: By asynchronously issuing mapping table read commands and returning immediately, user data read commands for other read tasks are scheduled to be executed in parallel on different planes while waiting for the mapping table to load, maximizing hardware parallel utilization. Read IOPS in high-concurrency scenarios are greatly improved, thereby increasing the throughput and resource utilization of the storage system. Attached Figure Description
[0026] Figure 1 This is a flowchart illustrating a portion of an embodiment of the data retrieval method provided in this application; Figure 2 This is a flowchart illustrating another part of an embodiment of the data storage reading method provided in this application; Figure 3 This is a schematic diagram of the structure of a storage device according to an embodiment of this application. Detailed Implementation
[0027] The solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0028] It should be noted that all directional indicators (such as up, down, left, right, front, and back) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0029] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or an intervening component can coexist. When a component is described as "connected to" another component, it can be directly connected to the other component or an intervening component can coexist.
[0030] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.
[0031] This application provides a method for reading stored data. This method is applied to a flash memory, wherein the flash memory may include a main control chip, a flash chip, and a flash translation layer (FTL) firmware. The main control chip is responsible for coordinating the operation of the entire memory, the flash chip is used to actually store data, and the FTL firmware undertakes key functions such as the conversion of logical addresses to physical addresses.
[0032] Please refer to Figure 1 The storage data reading method provided in this application includes: In step S103, the L2P mapping table corresponding to the current read task is queried; In step S105, when the L2P mapping table cache corresponding to the current read task is not hit, a mapping table read command is asynchronously sent to the flash memory, and the cache status of the L2P mapping table is marked as loading. In step S106, while waiting for the L2P mapping table to finish loading, at least one other read task in the task queue is retrieved, wherein the L2P mapping table cache of the other read task has been hit; In step S107, the busy / idle status of each plane in the flash memory is determined, and at least one other read task's user data read command and L2P mapping table read command are scheduled to be executed in parallel on different idle planes.
[0033] As can be seen from the above, by asynchronously issuing mapping table read commands and scheduling user data read tasks that have hit the cache to be executed in parallel on idle planes during the waiting period, the read blocking caused by mapping table loading is eliminated, the hardware concurrency capability of multiple planes is fully utilized, the read latency in high-concurrency scenarios is significantly reduced and the system throughput is improved.
[0034] In at least one possible implementation, before querying the L2P mapping table corresponding to the current read task, the method further includes: In step S101, the read task sequence issued by the monitoring host is counted, and the number of consecutive read tasks and the amount of data they request are counted. In step S102, it is confirmed that a preset number of read tasks are received continuously and the amount of data requested by each read task is less than or equal to a preset sector threshold.
[0035] As mentioned above, detecting consecutive small data block read tasks before asynchronous delivery and enabling asynchronous parallelism only in high-concurrency random read scenarios avoids introducing unnecessary overhead in non-high-concurrency scenarios (such as sequential reads or large block reads). Since there are no address conflicts between small data block read operations, the parallelism of the Plane is almost unlimited, releasing the throughput potential of the flash multi-Plane architecture.
[0036] In at least one possible implementation, after scheduling at least one other read task's user data read command and the L2P mapping table read command to different idle Planes for parallel execution, the method further includes: In step S108, the number of read commands being executed by each Plane is detected; In step S108, when the number of read commands reaches a preset threshold, DMA transfer is triggered, the mapping table that has been read is cached in the main control chip memory, and the user data that has been read is transferred to the host.
[0037] As described above, traditional DMA transfers are typically triggered by host read requests (i.e., DMA only starts after the host actively requests data). This application proposes using hardware parallelism (i.e., the number of concurrent read commands) as the triggering condition, thereby reducing the time data remains in the cache, releasing cache resources in advance, and freeing up space for subsequent commands. This proactive DMA transfer can significantly reduce the overall system response latency.
[0038] In at least one possible implementation, after the cached state of the L2P mapping table is marked as loading, if a subsequent read task requests the same L2P mapping table, the duplicate mapping table read command is skipped, and the process waits for the L2P mapping table to finish loading.
[0039] As can be seen from the above, by marking the status as "loading", other read tasks can directly hit the cache when they need to access the same logical address, avoiding repeated mapping table read requests and reducing redundant mapping table loading operations.
[0040] In at least one possible implementation, when a preset number of read tasks are not received consecutively, or when the amount of data requested by any read task in a series of consecutive read tasks exceeds a preset sector threshold, the following steps are also performed: In step S202, if the L2P mapping table cache is hit, a user data read command is directly issued. In step S203, if the L2P mapping table cache is not hit, the system will synchronously wait for the L2P mapping table to be loaded before issuing the user data read command.
[0041] As can be seen from the above, when the condition of consecutive small data blocks is not met, the system switches to the conventional synchronous read mode to ensure that the system can still work stably in the traditional way in non-target scenarios (such as sequential read or large block read scenarios). Together with the asynchronous delivery mode, it constitutes a complete mode adaptive reading scheme.
[0042] In at least one possible implementation, it also includes: In step S104, when the L2P mapping table cache of the current read task is hit, the following steps are performed: In step S1010, the target plane where the user data is located is determined according to the L2P mapping table; In steps S1011-1012, when the target Plane has no outstanding read commands, a user data read command is issued to the target Plane.
[0043] As can be seen from the above, in the scenario of a cache hit, the target Plane is checked for idleness before the read command is issued, which avoids command serialization due to Plane conflicts and improves the scheduling efficiency of read commands when the cache is hit.
[0044] In at least one possible implementation, it also includes: In step S1013, if there are incomplete read commands in the target plane, the current read task is skipped, the current read task is put back to the end of the task queue, and the next read task is queried.
[0045] As can be seen from the above, when the target plane is busy, a non-blocking scheduling strategy is adopted to put the current read task back to the end of the queue and continue to process other tasks, so as to prevent the entire task queue from being stalled due to the busyness of a single plane, thereby improving the fairness of task scheduling and the overall concurrency.
[0046] In at least one possible implementation, scheduling at least one other read task's user data read command and L2P mapping table read command to different idle planes for parallel execution includes: Execution in parallel on different planes within the same flash memory chip; It can be executed in parallel on a plane between different flash memory chips.
[0047] As can be seen from the above, it can adapt to a wider range of flash memory hardware architectures, covering all flash storage devices from low-end eMMC to high-end SSDs (such as UFS, NVMe SSDs, etc.). The following is combined Figure 1 and Figure 2 This document describes in detail an example of a data storage reading method provided in an embodiment of this application. Please refer to the flowchart below. Figure 1 This example includes the following steps: S101: Monitor the read task sequence issued by the host, and count the number of consecutive read tasks and the amount of data they request; The main control chip monitors the read task sequence issued by the host and counts the number of consecutive read tasks and the amount of data they request. Specifically, after receiving a read task, the main control chip parses the task parameters of multiple consecutive read tasks and extracts the data length information requested by each read task. For example, if the read task set contains 5 consecutive read tasks, each task requests to read 1KB, 2KB, 1KB, 3KB, and 2KB of data respectively.
[0048] S102: Confirm whether a preset number of read tasks have been received consecutively and whether the data volume requested by each read task is less than or equal to a preset sector threshold. If yes, proceed to S103; otherwise, proceed to S201-S203.
[0049] The preset number can be set according to the flash page size and system queue depth, with typical values of 4, 8, or 16; the preset sector threshold is usually set to the flash physical page size (e.g., 4KB, 8KB, or 16KB) to ensure that small data block read operations do not exceed the single page size. It should be noted that this application is not limited to this and can be adjusted according to the actual hardware and load.
[0050] If the amount of data requested by each of multiple consecutive read tasks is less than or equal to this threshold, it indicates that the data blocks accessed by these read tasks are small and scattered. In high-concurrency read scenarios with consecutive small data blocks, almost every read task will encounter an L2P mapping table cache miss. If a traditional synchronous method is used, each task must first wait for the mapping table to load (approximately 50-100μs) and then wait for data to be read (approximately 50-100μs), resulting in accumulated latency and prolonged Plane idleness.
[0051] S103: Query the L2P mapping table corresponding to the current read task; In flash memory storage systems, the host accesses data via logical block addresses (LBAs), while flash memory requires physical block addresses (PBAs). The L2P mapping table records the correspondence between logical and physical addresses, typically organized as entries. Because the SRAM capacity inside the controller chip is extremely limited (e.g., 32KB-256KB), it cannot accommodate a complete mapping table (e.g., for a 1TB SSD, a 4KB granular mapping table would require approximately 512MB). Therefore, the mapping table is mostly stored in flash memory and dynamically loaded into the SRAM cache only when needed.
[0052] When the host issues a read task (including the starting LBA and length), the flash translation layer (FTL) of the main control chip first calculates the mapping table index based on the LBA, and then looks up the corresponding entry in the SRAM cache. This process takes tens to hundreds of nanoseconds, which is negligible compared to the flash access time (in the microsecond range).
[0053] S104: Check if the L2P mapping table cache corresponding to the current read task is hit. If not, execute S105-S109; if yes, execute S1010-S1013.
[0054] If a cache hit occurs, it means that the physical address required by the current read task is already in the cache, and a user data read command can be sent to the flash memory. At this time, either the conventional synchronous or asynchronous mode can be used. However, if a cache miss occurs, the mapping table needs to be read from the flash memory. This is the main source of read latency in high-concurrency read scenarios with consecutive small data blocks.
[0055] S105: When the L2P mapping table cache corresponding to the current read task is not hit, an asynchronous mapping table read command is sent to the flash memory, and the cache status of the L2P mapping table is marked as loading. Traditional cache states only have two options: "valid" and "invalid." This application introduces a new cache state: "Loading." "Loading" indicates that a read command is currently executing in the background for the L2P mapping table, but the data is not yet ready. This state is stored in a single bit of the cache descriptor.
[0056] When the L2P mapping table cache of a read task misses, a mapping table read command is asynchronously sent to the flash memory, and the cached entry is simultaneously marked as "loading" to avoid subsequent requests for the same mapping table being sent repeatedly, thereby saving flash memory and cache resources. This state is only used for internal scheduling. The host quickly detects that the command has been received by completing the queue entry, using register-level response to mask flash-level latency, without waiting for actual data loading, effectively improving concurrency and throughput.
[0057] When the mapping table is loaded, its status is updated to "valid," and all read tasks waiting for the mapping table are woken up. Each mapping table cache entry maintains a linked list of waiting tasks to ensure that waiting tasks can be woken up. If the mapping table read command fails (including flash read errors, read timeouts, etc.), its status is updated to "Error," and an error is returned to the main control chip.
[0058] S106: While waiting for the L2P mapping table to finish loading, obtain at least one other read task in the task queue, wherein the L2P mapping table cache of the other read task has been hit; The "waiting for the mapping table to finish loading" period is a crucial time window: from the asynchronous issuance of the mapping table read command to the completion of the mapping table loading, typically 50-100 μs. During this period, the main control chip is not idle; it maintains a read task queue (software queue, located in the main control chip's memory) to temporarily store incomplete read tasks received from the host interface. Each read task includes a starting LBA, data length, task status (waiting for mapping table / waiting for data / completed), and a mapping table cache index. The task queue is organized in FIFO order, but the main control chip can skip the task at the head of the queue and select subsequent tasks based on the Plane's busy / idle status.
[0059] Specifically, the mapping table read command is issued to the target Plane (denoted as Plane X) specified by its physical address. When selecting other read tasks, the main control chip first checks whether the L2P mapping table corresponding to the candidate read task has been cached (i.e., its status is "valid"). If it has been cached, it then obtains the physical address of the user data and the target Plane, and determines whether the Plane is idle and different from Plane X. Only when all the above conditions are met is the task selected and the user data read command is immediately issued. If there are no other read tasks that meet the conditions in the current task queue, the main control chip continues scanning or enters a short waiting period until the mapping table is loaded or a new task arrives.
[0060] S107: Confirm the busy / idle status of each Plane in the flash memory, and schedule the user data read command of the at least one other read task and the L2P mapping table read command to different idle Planes for parallel execution.
[0061] Flash memory chips typically contain multiple planes (e.g., 2 or 4 planes per die). Each plane has its own set of page registers and an independent data path, allowing read commands to be executed in parallel. The main controller chip maintains a counter for each plane, recording the number of read commands currently being executed. This counter is usually reset to zero during initialization, incremented with each command issued, and decremented by one when a read command is completed. A zero counter indicates that the plane is idle.
[0062] For each other read task acquired in S106, the main control chip first checks whether its L2P mapping table cache has been hit (because only a hit can obtain the physical address and thus the target plane), and then checks whether the target plane's counter is zero. If it is zero, the task is selected as a candidate task that can be issued. Multiple tasks can be selected simultaneously, as long as their planes do not conflict and are all different from the plane where the mapping table read command is located.
[0063] S108: Detect the number of read commands being executed in each Plane; Specifically, the main control chip monitors in real time the number of read commands currently being executed by each plane in the flash memory chip, including mapping table read commands and user data read commands. This detection of concurrent operation count is achieved by maintaining a set of counters: each plane has its own counter; whenever a read command is issued to a plane, the counter for that plane is incremented by 1; when the read command on that plane is completed, the counter for that plane is decremented by 1. In this way, the main control chip can accurately grasp the current busy / idle status of each plane and the overall number of concurrent read operations in the system.
[0064] S109: When the number of read commands reaches a preset threshold, DMA transfer is triggered to cache the completed mapping table to the main control chip memory and transfer the completed user data to the host.
[0065] The preset threshold can be set according to the total number of Planes in the system, host interface bandwidth, etc. For example, when the system contains 4 Planes, the threshold can be set to 4, indicating that DMA is triggered when all Planes are busy. When the number of concurrent read commands reaches this threshold, the main control chip triggers DMA to perform data transfer, specifically including: The completed reading of the mapping table is transferred from the flash page register to the mapping table cache area (such as SRAM or DRAM) of the main control chip, and the status of the table entry is updated to "valid" so that subsequent read tasks can hit the cache; the completed reading of user data is transferred from the flash page register to the memory address specified by the host, and the read command counter of the corresponding Plane is decremented by 1.
[0066] After DMA is triggered, the counter does not need to be reset immediately, but will gradually decrease as each command is completed, and will be retried when the threshold is reached again.
[0067] Unlike existing technologies where DMA transfers are typically passively triggered by host read requests, this application proposes using hardware parallelism (number of concurrent read commands) as an active triggering condition, thereby reducing the time data remains in the cache, releasing cache resources in advance, and improving the overall response speed of the system.
[0068] S1010: When the L2P mapping table cache of the current read task is hit, determine the target Plane where the user data is located according to the L2P mapping table; The main control chip first reads the physical address from the mapping table. The physical address typically contains several fields: channel number, chip enable number, die number, plane number, block number, page number, etc. By parsing the plane number field, the target plane to which the user data belongs in the flash memory can be uniquely identified.
[0069] S1011: Check if there are any incomplete read commands in the target plane; if not, execute S1012; if so, execute S1013.
[0070] The main control chip maintains a status flag (such as a bit or counter) for each Plane to indicate whether there are any pending read commands for that Plane. This flag is updated collaboratively by command issuance and completion: it is set to "busy" when a command is issued and cleared to "idle" when the command is completed. The main control chip can query these flags at any time to obtain real-time busy / idle information for each Plane.
[0071] S1012: Issue a user data read command to the target Plane.
[0072] If the target plane's status is "idle," a user data read command is immediately sent to the target plane, and the plane's status is updated to "busy." This ensures that each plane executes only one read command at a time, avoiding hardware conflicts and enabling read commands on different planes to be executed concurrently.
[0073] S1013: Skip the current read task, put it back to the end of the task queue, and query the next read task.
[0074] If the target Plane is in a "busy" state, the current read task will not be blocked and wait, but will be placed back to the end of the task queue (or enter the waiting queue) and immediately move on to process the next read task. When the busy Plane is completed, its state is updated to idle. This prevents the entire task queue from stalling due to a single busy Plane, thus improving the overall concurrency of task scheduling.
[0075] In at least one possible implementation, see Figure 2 When a preset number of read tasks are not received consecutively, or when the amount of data requested by any read task in the consecutive read tasks exceeds a preset sector threshold, the following steps are executed: S201: Confirm that the L2P mapping table cache is hit. If yes, proceed to S202; otherwise, proceed to S203.
[0076] S202: Directly issue user data read command; S203: Synchronously wait for the L2P mapping table to finish loading before issuing the user data read command.
[0077] When the condition of consecutive small data blocks is not met, switch to the regular synchronous read mode to ensure that the system can still work in a simple and stable way in non-target scenarios (such as sequential read or large block read scenarios), and avoid introducing unnecessary asynchronous parallel scheduling overhead.
[0078] In at least one possible implementation, in order to effectively intercept repeated read requests for the same mapping table in asynchronous delivery mode and avoid wasting flash memory bandwidth and power consumption, after marking the cache state of the L2P mapping table as loading, the method further includes: If a subsequent read task requests the same L2P mapping table, the repeated issuance of the mapping table read command will be skipped, and the subsequent read task will be added to the waiting queue until it is awakened after the initial read task completes the mapping table loading.
[0079] When a target read task triggers asynchronous loading due to a missing mapping table, the system marks its mapping table status as "loading". If a subsequent read task requests the same mapping table, the system detects this status, skips the operation of repeatedly issuing read commands, and puts the subsequent task into a waiting state until the initial read task completes the mapping table loading, thereby achieving deduplication and resource optimization of mapping table loading in a multi-tasking environment.
[0080] In at least one possible implementation, in order to adapt to various flash memory hardware architectures (covering from low-end eMMC to high-end UFS, NVMe SSD, etc.), this application schedules at least one other read task's user data read command and L2P mapping table read command to be executed in parallel on different idle planes, specifically including the following two methods: (1) Parallel execution on different planes within the same flash memory chip A single flash memory chip typically contains multiple planes (e.g., 2 or 4), each with its own page register and data path. The controller chip can achieve plane-level parallelism within the same chip in two ways: first, by issuing a Multi-Plane Read command, which automatically operates multiple planes in parallel within the flash memory chip; second, by issuing read commands independently to different planes, which are then scheduled and executed by the flash memory controller. Regardless of the method used, read operations on multiple planes can occur simultaneously, sharing the same chip's I / O bus without interfering with each other.
[0081] (2) Parallel execution on planes between different flash memory chips When a system contains multiple flash memory chips (each with an independent chip select signal CE), or integrates multiple dies within a single package (each die with an independent CE), the planes on different chips (or dies) are physically completely independent. The master control chip can simultaneously issue read commands to any plane on different chips, enabling true concurrent execution. The degree of parallelism is limited only by the number of channels and chip select signals on the master control chip.
[0082] The two methods described above can be used individually or in combination (for example, executing multiple sets of parallel read commands simultaneously on different planes of different chips) to fully utilize the multi-level parallel resources of the flash memory storage system.
[0083] Please refer to Figure 3This application embodiment also provides a storage device, including a processor 100 and a memory 200, the memory 200 being coupled to the processor 100, the memory 200 being used to store computer program code, the computer program code including computer instructions, when the processor 100 reads the computer instructions from the memory 200, causing the processor 100 to execute the steps in the method of any possible implementation of any of the foregoing embodiments.
[0084] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.
[0085] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.
[0086] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.
Claims
1. A method for reading stored data, applied to a flash memory, characterized in that, include: Query the L2P mapping table corresponding to the current read task; When the L2P mapping table cache corresponding to the current read task is not hit, an asynchronous mapping table read command is sent to the flash memory, and the cache status of the L2P mapping table is marked as loading. While waiting for the L2P mapping table to finish loading, at least one other read task is retrieved from the task queue, wherein the L2P mapping table cache of the other read task has been hit; Determine the busy / idle status of each Plane in the flash memory, and schedule the user data read command of at least one other read task and the L2P mapping table read command to different idle Planes for parallel execution.
2. The data storage and retrieval method according to claim 1, characterized in that, Before querying the L2P mapping table corresponding to the current read task, the following is also included: Monitor the sequence of read tasks issued by the host, and count the number of consecutive read tasks and the amount of data they request; Confirm that a preset number of read tasks are received consecutively, and that the amount of data requested by each read task is less than or equal to a preset sector threshold.
3. The data storage retrieval method according to claim 1, characterized in that, After scheduling the user data read commands of the at least one other read task and the L2P mapping table read commands to different idle Planes for parallel execution, the method further includes: Detect the number of read commands being executed in each Plane; When the number of read commands reaches a preset threshold, DMA transfer is triggered to cache the completed mapping table in the main control chip memory and transfer the completed user data to the host.
4. The data storage and retrieval method according to claim 1, characterized in that, After marking the cache status of the L2P mapping table as loading, the following steps are included: If a subsequent read task requests the same L2P mapping table, the repeated issuance of L2P mapping table read commands will be skipped, and the process will wait for the L2P mapping table to be loaded.
5. The method for reading stored data according to claim 2, characterized in that, If a preset number of read tasks are not received consecutively, or if the amount of data requested by any of the consecutive read tasks exceeds a preset sector threshold, the following steps are also performed: If the L2P mapping table cache is hit, the user data read command is issued directly. If the L2P mapping table cache is not hit, the system will synchronously wait for the L2P mapping table to be loaded before issuing the user data read command.
6. The method for reading stored data according to any one of claims 1-5, characterized in that, When the L2P mapping table cache corresponding to the current read task is hit, the following steps are executed: The target plane where the user data is located is determined based on the L2P mapping table; When the target plane has no pending read commands, the user data read command is issued to the target plane.
7. The method for reading stored data according to claim 6, characterized in that, The method further includes: If the target plane has incomplete read commands, the current read task is skipped, the current read task is put back to the end of the task queue, and the next read task is queried.
8. The method for reading stored data according to claim 1, characterized in that, The step of scheduling the user data read commands of the at least one other read task and the L2P mapping table read commands to different idle Planes for parallel execution includes: Execution in parallel on different planes within the same flash memory chip; It can be executed in parallel on a plane between different flash memory chips.
9. A storage device, characterized in that, It includes a processor and a memory coupled to the processor. The memory is used to store computer program code, the computer program code including computer instructions, which, when the processor reads the computer instructions from the memory, cause the processor to perform the steps in the stored data reading method as described in any one of claims 1-8.
10. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps of the stored data reading method as described in any one of claims 1-8.