Test methods, apparatuses, electronic devices, media, and products

Abstract

The present disclosure relates to a test method, device, electronic device, medium and product. The method comprises: disconnecting the connection between the storage controller and the interface of the storage chip, controlling the test module to be connected to the interface, and sending write test data to the storage chip via the interface for testing. Wherein, the data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module configuration. And receive the read data and perform verification to determine the test result. By using the test module to replace the storage controller, the test module can directly construct the required write test data, and send it to the storage chip through the interface between the storage controller and the storage chip, so that the sequence of the write test data is not affected by the scheduling strategy, to construct a more severe power integrity test scenario.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a test method, apparatus, electronic device, medium, and product. Background Technology

[0002] As chip frequencies increase, the interactions between power supply noise, transient current requirements, and signal integrity become more complex, data throughput is also greater, and the requirements for the performance of the core power supply and input / output (IO) power supply on its power delivery network (PDN) are also higher.

[0003] Therefore, ensuring power integrity plays a crucial role in the overall performance and stability of the system. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a testing method, apparatus, electronic device, medium, and product.

[0005] According to a first aspect of the present disclosure, a testing method is provided, the method comprising: Disconnect the interface between the storage controller and the storage chip; connect the control test module to the interface and send write test data to the storage chip via the interface for testing, wherein the data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module configuration; receive readback data and verify it to determine the test result.

[0006] In this embodiment, by replacing the storage controller with a test module, the test module can directly construct the required write test data and send it to the storage chip through the interface between the storage controller and the storage chip. This makes the sequence of write test data unaffected by the scheduling policy, thereby constructing a more severe power integrity test scenario and completing the power integrity test of the interface between the storage controller and the storage chip.

[0007] In some embodiments of this disclosure, the write test data is generated via the test module configuration, including: the write test data is configured as a preset first data sequence or a second data sequence formed according to preset changes.

[0008] In this embodiment, the test module can be configured to generate multiple data sequences as write test data to construct the test data required for a more severe power integrity test scenario.

[0009] In some embodiments of this disclosure, the write test data is configured as a preset first data sequence, including: the write test data includes at least one set of data groups, each set of data groups includes multiple data, and the multiple data correspond one-to-one with the write pins of the memory chip; the at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval.

[0010] In this embodiment, the test data required for a relatively severe power integrity test scenario can be constructed by cyclically forming a first data sequence with the data group at a preset time interval.

[0011] In some embodiments of this disclosure, the written test data includes a first data group and a second data group. The first data group includes a plurality of first data, and the second data group includes a plurality of second data. The first data and the second data are different. The at least one data group cyclically constitutes the first data sequence according to a preset time interval, including: the first data group and the second data group alternately appear to constitute the first data sequence according to the preset time interval.

[0012] In this embodiment, by setting two data groups and having these two data groups alternate at a preset time interval to form a relatively regular and changing first data sequence, the test data required for a relatively severe power integrity test scenario is constructed.

[0013] In some embodiments of this disclosure, a preset number of data groups constitute a data set, and at least a portion of the data in the data set is used to represent numbers or letters; the at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval, including: the data set continuously cyclically constitutes the first data sequence according to the preset time interval.

[0014] In this embodiment, a first data sequence is formed by continuously cycling the data set according to a preset time interval. Since some of the data represents numbers and letters, the types of data in the data set used for testing are increased, and more data formats can be generated to construct the test data required for more severe power integrity test scenarios.

[0015] In some embodiments of this disclosure, the writing test data according to the second data sequence formed by preset changes includes: obtaining source data of register configuration; and performing data processing on the source data based on the preset processing method to form the second data sequence.

[0016] In this embodiment, the source data can be configured through registers, which can make the data source have a certain degree of randomness. The configured source data is processed based on a preset processing method to form a second data sequence. Thus, based on the data source with a certain degree of randomness, regular changes are made to construct the test data required for a random or more severe power integrity test scenario set according to requirements.

[0017] In some embodiments of this disclosure, the source data includes first source data and second source data, wherein the first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the write time interval of the memory chip; the step of processing the source data based on the preset processing method to form the second data sequence includes: one of the first source data and the second source data is used as row data, and the other of the two is used as column data; the two data at the intersection of the row data and the column data are subjected to first data processing to form the second data sequence.

[0018] In this embodiment, by configuring the first source data and the second source data, and using the first source data and the second source data as row data or column data in the coordinate system respectively, the two data at the intersection of the corresponding row data and column data can be processed to obtain the remaining data sequence. This simplifies the cumbersome configuration of test data and can also form the test data required for a relatively harsh power integrity test scenario.

[0019] In some embodiments of this disclosure, the first data processing method includes XOR processing.

[0020] In this embodiment, by performing an XOR operation on the two data points at the intersection of the first source data and the second source data at the row data and column data positions, the specific data in the second data sequence is obtained, which increases the diversity of test data transformation and forms the test data required for a more severe power integrity test scenario.

[0021] In some embodiments of this disclosure, the source data includes third source data, which corresponds one-to-one with the write pins of the memory chip. The step of processing the source data based on the preset processing method to form the second data sequence includes: forming a basic data group based on the third source data, and performing cyclic shifting processing on the basic data group with a unit time interval as the shift parameter to form the second data sequence.

[0022] In this embodiment, the third source data can be randomly generated, and a basic data group is generated based on the third source data. The basic data group is then subjected to a cyclic shift operation to obtain a second data sequence, which increases the randomness of the data and forms the test data required for a more severe power integrity test scenario.

[0023] In some embodiments of this disclosure, the third source data includes pseudo-random binary sequence initial data, and the step of forming a basic data group based on the third source data includes: using the third source data as the basic data group; or, performing a preset operation on the third source data to form the basic data group.

[0024] In this embodiment, the third source data can include pseudo-random binary sequence initial data and be used as the basic data group, or the third source data can be subjected to preset operations to form the basic data group, thereby increasing the randomness of the data and forming the test data required for a more severe power integrity test scenario.

[0025] According to a second aspect of the present disclosure, a testing apparatus is provided, the apparatus comprising: A switching module is configured to disconnect the interface between the storage controller and the storage chip; the switching module is also configured to control a test module to connect to the interface; the test module is further configured to send write test data to the storage chip via the interface for testing, wherein the data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module; the test module is also configured to receive readback data and perform verification to determine the test result.

[0026] In some embodiments of this disclosure, the test module is further configured to: configure the written test data as a preset first data sequence or a second data sequence formed according to a preset change.

[0027] In some embodiments of this disclosure, the test module is further configured such that: the write test data includes at least one set of data groups, each set of data groups includes multiple data, and the multiple data correspond one-to-one with the write pins of the memory chip; the at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval.

[0028] In some embodiments of this disclosure, the written test data includes a first data group and a second data group. The first data group includes a plurality of first data, and the second data group includes a plurality of second data. The first data and the second data are different. The test module is further configured such that the first data group and the second data group alternately appear at the preset time interval to form the first data sequence.

[0029] In some embodiments of this disclosure, a preset number of data groups constitute a data set, and at least a portion of the data in the data set is used to represent numbers or letters; the test module is further configured such that the data set continuously and cyclically constitutes the first data sequence according to the preset time interval.

[0030] In some embodiments of this disclosure, the test module is further configured to: acquire source data configured in the register; and perform data processing on the source data based on the preset processing method to form the second data sequence.

[0031] In some embodiments of this disclosure, the source data includes first source data and second source data, wherein the first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the write time interval of the memory chip; the test module is further configured to: use one of the first source data and the second source data as row data, and the other as column data, and perform first data processing on the two data at the intersection of the row data and the column data to form the second data sequence.

[0032] In some embodiments of this disclosure, the first data processing method includes XOR processing.

[0033] In some embodiments of this disclosure, the source data includes third source data, which corresponds one-to-one with the write pins of the memory chip. The test module is further configured to: form a basic data group based on the third source data, and perform cyclic shifting processing on the basic data group with a unit time interval as the shift parameter to form the second data sequence.

[0034] In some embodiments of this disclosure, the third source data includes pseudo-random binary sequence initial data, and the test module is further configured to: use the third source data as the basic data group; or, perform preset operations on the third source data to form the basic data group.

[0035] According to a third aspect of the present disclosure, an electronic device is provided, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the test method described above.

[0036] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of a terminal, the terminal is enabled to perform the test method as described above.

[0037] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program or instructions that, when executed by a processor, implement the testing method described above.

[0038] The technical solution provided by the embodiments of this disclosure can include the following beneficial effects: by disconnecting the interface between the storage controller and the storage chip, a control test module is connected to the interface and sends write test data to the storage chip for testing via the interface. The data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module. Readback data is received and verified to determine the test result, thereby performing power integrity testing on the interface between the storage controller and the storage chip. The technical solution of this disclosure uses a test module to replace the storage controller. The test module can directly construct the required write test data and send it to the storage chip via the interface between the storage controller and the storage chip, so that the sequence of write test data is not affected by the scheduling strategy, thus constructing a more severe power integrity test scenario.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0041] Figure 1 This is a schematic diagram illustrating an existing technical solution for testing power integrity according to an exemplary embodiment; Figure 2 This is a schematic diagram illustrating a technical solution for testing power integrity using the test method of this disclosure according to an exemplary embodiment; Figure 3 This is a flowchart illustrating a test method according to an exemplary embodiment; Figure 4 This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 5 This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 6 This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 7 This is a flowchart illustrating a test method according to an exemplary embodiment; Figure 8This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 9 This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 10 This is a schematic diagram illustrating the writing of test data in the form of a data table according to an exemplary embodiment; Figure 11 This is a schematic diagram illustrating the process of generating and writing test data according to an exemplary embodiment of the test module configuration; Figure 12 This is a block diagram of a testing apparatus according to an exemplary embodiment; Figure 13 This is a block diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims. It should also be understood that the term “and / or” as used in this disclosure refers to any or all possible combinations including one or more of the associated listed items.

[0043] As chip frequencies increase, the interplay between power supply noise, transient current demands, and signal integrity becomes increasingly complex, data throughput also increases, and the requirements for the performance of the core power supply and input / output (IO) power supply to the power delivery network (PDN) become more stringent. Therefore, ensuring power integrity (PI) plays a crucial role in the overall system performance and stability.

[0044] Existing solutions for testing power integrity, such as testing the power integrity of the interface between the memory controller (MC) and the memory chip, refer to... Figure 1The power integrity simulation and test data pattern is constructed by sending stimuli through the build-in-self-test (BIST) or central processing unit (CPU) in front of the storage controller, and then sent to the storage chip. However, after the stimuli are scheduled by the storage controller, they may no longer meet the requirements of a severe power integrity test data pattern (PI pattern). This is because the storage controller needs to schedule write or read commands based on the timing of the storage chip, and due to differences in storage or read addresses and the need for refresh, it is impossible to construct a severe power integrity test scenario.

[0045] Based on this, this disclosure provides a testing method. By disconnecting the interface between the storage controller and the storage chip, a control test module is connected to the interface and sends write test data to the storage chip via the interface for testing. The data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module. Readback data is received and verified to determine the test result. In this embodiment, the test module replaces the storage controller to perform power integrity testing on the interface between the storage controller and the storage chip. The test module can directly construct the required write test data and send it to the storage chip via the interface between the storage controller and the storage chip, ensuring that the sequence of write test data is not affected by scheduling policies, thus constructing a more severe power integrity test scenario.

[0046] This disclosure provides an exemplary embodiment of a testing method that can be applied to electronic devices, specifically smart devices such as mobile phones, tablets, laptops, smart robots, and smart wearable devices. Furthermore, the electronic device also includes various hardware resources and energy storage devices that provide power for the operation of these hardware resources.

[0047] For ease of understanding, the test method of this disclosure is described first. The test method of this disclosure includes testing the power integrity of the interface between the memory controller and the memory chip, and can also be used to test the power integrity of other interfaces. This disclosure uses testing the power integrity of the interface between the memory controller and the memory chip as an example to describe the test method of this disclosure. This test method is applied to the testing phase after the chip is returned to the die.

[0048] This disclosure provides a testing method, such as... Figure 2 and Figure 3 As shown, the method includes: S100, Disconnect the interface between the storage controller and the storage chip.

[0049] When conducting power integrity tests on the interface between the storage controller and the storage chip, if the storage controller is used to directly send test data, the storage controller will schedule these test data and send them in a configured timing sequence. However, due to the scheduling strategy of the storage controller and the influence of commands such as activation commands, precharge commands, and refresh commands, there may be no interval or the interval may be uncontrollable between test data, which makes it impossible to construct a severe power integrity test scenario.

[0050] In this step, the connection between the storage controller and the storage chip can be disconnected. In other words, the storage controller is not used to send test data, so as to avoid the storage controller's scheduling policy causing the test data to have no interval or uncontrollable interval factors.

[0051] S200, the control test module is connected to the interface, and sends write test data to the storage chip for testing via the interface. The data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module configuration.

[0052] In this step, refer to Figure 2 A test module can be designed to replace the storage controller, enabling the test module to send test data to the storage chip. The test module's functions can include configuring and generating test data, sending test data, reading back data, and verifying results. By controlling the interface between the test module and the storage controller and storage chip, the test module can send write test data to the storage chip via this interface. The data format of the write test data generated by the test module conforms to the data format of the interface between the storage controller and storage chip. Understandably, the test module can also be configured to generate and send commands to the storage chip other than read and write commands; however, the scheduling strategy within the test module is controllable, thus allowing for the construction of more severe power integrity test scenarios. Understandably, in actual testing, multiple write commands can be sent as needed; that is, the test module needs to send multiple write test data.

[0053] S300 receives and verifies the readback data to determine the test result.

[0054] The test module can receive and verify data read back from the storage chip, and determine the power integrity of the interface between the storage controller and the storage chip based on the verification results.

[0055] In this embodiment, by replacing the storage controller with a test module, the test module can directly construct the required write test data and send it to the storage chip through the interface between the storage controller and the storage chip. This makes the sequence of write test data unaffected by the scheduling policy, thereby constructing a more severe power integrity test scenario and completing the power integrity test of the interface between the storage controller and the storage chip.

[0056] In some embodiments, in step 200, writing test data is generated via a test module configuration, including: configuring the written test data as a preset first data sequence or a second data sequence formed according to a preset change.

[0057] In one embodiment, writing test data may include a first data sequence formed by preset values. This first data sequence may be pre-configured as a template for direct use, or it may be configured directly as needed.

[0058] In another embodiment, writing test data may include a second data sequence formed according to a preset change, which may be a data sequence formed based on a certain processing method.

[0059] In this embodiment, the written test data may include a first data sequence formed by preset data, or a second data sequence formed according to a preset change rule. Therefore, the test module can be configured to generate multiple data sequences as written test data to construct the test data required for a more severe power integrity test scenario.

[0060] In some embodiments, the test data is generated via a test module configuration and further includes: performing a remap operation on the first data sequence and / or the second data sequence according to the interface data format between the storage controller and the storage chip, so that the data format of the test data is consistent with the data format of the interface between the storage controller and the storage chip.

[0061] In some embodiments, the write test data is configured as a preset first data sequence, including: the write test data includes at least one set of data groups, each set of data groups includes multiple data, the multiple data correspond one-to-one with the write pins of the memory chip, and the at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval.

[0062] The write test data includes at least one set of data groups, and the data in each data group can be generated directly as needed. Each data group corresponds one-to-one with a write pin (Data Queue, DQ) of the memory chip, and data is written from the corresponding write pin. The preset time interval includes a preset number of unit intervals (UI), where each unit interval represents the time window required for the memory chip's write pin to transmit one data unit. Understandably, the size of each time window can vary. When the memory chip executes a write command, the number of unit intervals included in the written data is the number of data groups in the write test data. For ease of understanding, the write test data can be organized into a data table based on the number of write pins (DQ) and the number of time windows (UI) required to transmit one data unit. (See reference...) Figure 4 The data in the DQ direction represents the data in the data group corresponding one-to-one with the write pin, and the data in the UI direction represents the number of time windows (UI) required to transmit one data unit. Assuming there are n valid data points in the DQ direction and m valid data points in the UI direction, the generated test data is... bit. Here, all data in the DQ direction on a UI is defined as a data group.

[0063] In this embodiment, the test data required for a relatively severe power integrity test scenario can be constructed by cyclically forming a first data sequence with the data group at a preset time interval.

[0064] In some embodiments, the test data to be written includes a first data group and a second data group. The first data group includes a plurality of first data, and the second data group includes a plurality of second data. The first data and the second data are different. At least one set of data groups cyclically constitutes a first data sequence according to a preset time interval, including: the first data group and the second data group appear alternately to constitute a first data sequence according to a preset time interval.

[0065] Since the first data in the first data group differs from the second data in the second data group, the first data may include, for example, the binary value 1, and the second data may include, for example, the binary value 0. This disclosure does not specifically limit this. Therefore, it can be understood that when the first data sequence is understood as a data table, the first data sequence is presented as a form in which the value 1 in the first data group and the value 0 in the second data group alternate at unit time intervals (UI direction), as shown in the reference. Figure 5 Understandably, the first data may also include the binary value 0, and the second data may also include the binary value 1; this disclosure does not impose any specific limitations on this.

[0066] In this embodiment, by setting two data groups and having these two data groups alternate at a preset time interval to form a relatively regular and changing first data sequence, the test data required for a relatively severe power integrity test scenario is constructed.

[0067] In some embodiments, a preset number of data groups constitute a data set, and at least some data in some data groups in the data set are used to represent numbers or letters; at least one set of data groups cyclically constitutes a first data sequence according to a preset time interval, including: the data set continuously cyclically constitutes a first data sequence according to a preset time interval.

[0068] The preset quantity can be set according to needs, and this embodiment does not impose a specific limitation. A preset quantity of data groups can constitute a data set, and the data set continuously cycles according to a preset quantity of unit time intervals to form a first data sequence. This first data sequence can be pre-configured as a template for direct use, or it can be configured directly according to needs. Numbers or letters can represent any binary data, octal data, decimal data, hexadecimal data, etc., and this embodiment does not impose a specific limitation. A data group in the data set can include multiple cycles of the same numbers or letters. When the first data sequence is understood as a data table, for example, refer to... Figure 6 The first data sequence has a preset quantity of 4. The data set, consisting of 4 data groups, is continuously cycled every 4 unit time intervals to form the first data sequence. In the first data group, some data represents the hexadecimal number 'A'; in the second data group, some data represents the numerical value '0'; in the third data group, some data represents the hexadecimal number '5'; and in the fourth data group, some data represents the numerical value '0'. Specifically, the first data group contains multiple cyclical arrangements of 'A'; the second data group contains multiple cyclical arrangements of '0'; the third data group contains multiple cyclical arrangements of '5'; and the fourth data group contains multiple cyclical arrangements of '0'. Therefore, Figure 6 The first data sequence is presented as a data set A / 0 / 5 / 0 continuously repeating at 4-unit time intervals. This is only an illustrative description; the specific data in the data set can be set according to requirements, and this embodiment does not impose any specific limitations.

[0069] In this embodiment, a first data sequence is formed by continuously cycling the data set according to a preset time interval. Since some of the data represents numbers and letters, the types of data in the data set used for testing are increased, and more data formats can be generated to construct the test data required for more severe power integrity test scenarios.

[0070] In some embodiments, such as Figure 7As shown, the second data sequence formed by writing test data according to preset changes includes: S710, Obtain source data for register configuration.

[0071] S720. The source data is processed based on a preset processing method to form a second data sequence.

[0072] In this embodiment, the source data can be configured through registers, which can make the data source have a certain degree of randomness. The configured source data is processed based on a preset processing method to form a second data sequence. Thus, based on the data source with a certain degree of randomness, regular changes are made to construct the test data required for a random or more severe power integrity test scenario set according to requirements.

[0073] In some embodiments, the source data includes first source data and second source data. The first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the unit time interval for writing to the memory chip. The source data is processed according to a preset processing method to form a second data sequence, including: one of the first source data and the second source data is used as row data, and the other of the two is used as column data. The two data at the intersection of the row data and the column data are subjected to first data processing to form the second data sequence.

[0074] In this step, first source data and second source data can be generated according to specific needs, so that the first data sequence can be directly configured according to test requirements. Specifically, the first source data and second source data can be generated separately using two registers, and one of the first source data and the other can be used as row data and the other as column data. The two data points at the intersection of the row data and column data are processed using a coordinate system to form the second data sequence. The first source data and second source data can also be generated in other ways, and this embodiment does not impose specific limitations.

[0075] In one embodiment, when the first data sequence is understood as a data table, reference is made to... Figure 8 The UI direction can be used as the x-direction of the coordinate system, and the DQ direction as the y-direction. For example, the configuration registers for the DQ direction can be used to generate the first source data [1, 0, 1, 1, 1, 0, 0, 0…], and the configuration registers for the UI direction can be used to generate the second source data [1, 1, 0, 1, 0, 0, 1, 1…]. The first source data serves as column data, and the second source data serves as row data. By performing first data processing on the intersection points of the corresponding row and column data in the coordinate system, the remaining data sequence is obtained, forming the complete second data sequence. For example, refer to… Figure 8First, data processing is performed on x0=1 and y0=1 to obtain data 0 at the intersection point (0, 0); first, data processing is performed on x0=1 and y1=0 to obtain data 1 at the intersection point (0, 1). The configuration registers in the DQ direction and UI direction can generate the first and second source data respectively according to specific needs; this embodiment does not impose specific limitations. Understandably, the DQ direction can also be used as the x-direction of the coordinate system, and the UI direction as the y-direction; this embodiment does not impose specific limitations.

[0076] In this embodiment, by configuring the first source data and the second source data, and using the first source data and the second source data as column data or row data in the coordinate system respectively, the two data at the intersection of the corresponding row data and column data can be processed to obtain the remaining data sequence. This simplifies the cumbersome configuration of test data and can also form the test data required for a relatively harsh power integrity test scenario.

[0077] In some embodiments, the first data processing method includes XOR processing.

[0078] In one embodiment, reference Figure 8 We can use the UI direction as the x-direction of the coordinate system and the DQ direction as the y-direction, that is, treat the data in the UI direction as row data and the data in the DQ direction as column data. We perform an XOR operation on the two data points at the intersection of the row and column data of the first source data [1, 1,0, 1, 0, 0, 1, 1…] and the second source data [1, 0, 1, 1, 1, 0, 0, 0…] to obtain the specific data in the second data sequence.

[0079] In this embodiment, the specific data in the second data sequence is obtained by performing an XOR operation on the two data at the intersection of the first source data and the second source data at the row data and column data. This increases the randomness of the data and forms the test data required for a more severe power integrity test scenario.

[0080] In some embodiments, the source data includes third source data, which corresponds one-to-one with the write pins of the memory chip. The source data is processed according to a preset processing method to form a second data sequence, including: forming a basic data group based on the third source data, and performing cyclic shifting processing on the basic data group with a unit time interval as the shift parameter to form the second data sequence.

[0081] In this step, third source data corresponding one-to-one with the write pins of the memory chip can be generated using registers, and a basic data group is formed based on the third source data, with the data in the basic data group corresponding one-to-one with the write pins of the memory chip. Other methods can also be used to generate the third source data; this embodiment does not impose specific limitations.

[0082] In one embodiment, the basic data group is cyclically shifted, including: cyclically shifting all data in the basic data group to the left (or right). Assume the memory chip has n write pins, and the write test data includes m unit time intervals, where n>0 and m>0. Therefore, the basic data group includes n data items. Under the premise that m<=n, the data in the n basic data groups are shifted sequentially. The first shift involves 0 data items, which correspond to the write pins of the memory chip in the first unit time interval; the second shift involves 1 data item, which corresponds to the write pins of the memory chip in the second unit time interval; the third shift involves 2 data items, which corresponds to the write pins of the memory chip in the third unit time interval; the mth shift involves (m-1) data items, which corresponds to the write pins of the memory chip in the mth unit time interval, to obtain... The second data sequence of bits. Understandably, when m > n, the basic data group completes one round of shifting operation during the nth shift. To update the data within the remaining unit time interval, a second basic data group can be generated simultaneously when generating the first basic data group. The cyclic shift operation of the second basic data group follows the steps above, and data groups for the (n+1)th to mth unit time intervals are generated sequentially. Understandably, if m > 2n, then a second and third basic data group are generated simultaneously when generating the first basic data group; that is, the number of basic data groups generated is determined according to the relationship between m and n.

[0083] When interpreting the first data sequence as a data table, refer to Figure 9 For example, the basic data set includes [0, 1,0, 1, 0, 1, 0, 1…]. A cyclic shift operation is performed on the basic data set: the first shift involves 0 data points, which are used as the data in the DQ direction when UI is 0; the second shift involves 1 data point, which is used as the data in the DQ direction when UI is 1; the third shift involves 2 data points, which are used as the data in the DQ direction when UI is 2; the m-th shift involves (m-1) data points, which are used as the data in the DQ direction when UI is (m-1), to obtain… The second data sequence.

[0084] In this embodiment, the third source data can be randomly generated, and a basic data group is generated based on the third source data. The basic data group is then subjected to a cyclic shift operation to obtain a second data sequence, which increases the randomness of the data and forms the test data required for a more severe power integrity test scenario.

[0085] In some embodiments, the third source data includes initial data of a pseudo-random binary sequence. Forming a basic data group based on the third source data includes: using the third source data as the basic data group; or performing a preset operation on the third source data to form the basic data group.

[0086] The third source data may include initial data for pseudo-random binary sequences (PRBS), i.e., seed data for PRBS. Preset operations may include primitive polynomial operations.

[0087] In this step, the PRBS seed data can be used as the first basic data set. The data obtained after performing the first primitive polynomial operation on the third source data can be used as the second basic data set. The data obtained after performing the second primitive polynomial operation on the third source data can be used as the third basic data set, and so on. (Reference) Figure 9 For example, the seed data for PRBS, as the first base data group, includes [0, 1, 0, 1, 0, 1, 0, 1…]. (See reference) Figure 10 For example, the data obtained after performing the first primitive polynomial operation on the seed data based on PRBS is used as the second basic data group, including [0,0, 1, 1, 1, 0, 1, 0…].

[0088] As described above, it is understandable that if m > n, a second basic data set needs to be generated. If m <= n, then the basic data set used when generating the second write test data is the second basic data set; and the basic data set used when generating the third write test data is the third basic data set. That is to say, the multiple second test data sequences generated by the method in this embodiment are not the same.

[0089] In this embodiment, the third source data can include pseudo-random binary sequence initial data and be used as the basic data group, or the third source data can be subjected to preset operations to form the basic data group, which increases the diversity of test data transformation to form the test data required for more severe power integrity test scenarios.

[0090] For ease of understanding, the following specific embodiment describes the detailed scheme for configuring the test module to generate and write test data in the test method provided in this disclosure, as follows: Figure 11 As shown.

[0091] S1101. The test data to be written includes a first data group and a second data group. The first data group and the second data group alternately appear at a preset time interval to form a first data sequence.

[0092] The first data group includes multiple first data points, and the second data group includes multiple second data points. The first data points and the second data points are different.

[0093] S1102. A preset number of data groups constitute a data set, and the data set continuously cycles at a preset time interval to form a first data sequence.

[0094] In this dataset, at least a portion of the data in a subset of the dataset is used to represent numbers or letters.

[0095] S1103. Obtain the first source data and the second source data configured in the register. One of the first source data and the second source data is used as row data, and the other is used as column data. Perform XOR processing on the two data at the intersection of the row data and the column data to form the second data sequence.

[0096] The first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the write time interval of the memory chip.

[0097] S1104. Obtain the third source data configured in the register, form a basic data group based on the third source data, and perform cyclic shifting on the basic data group with a unit time interval as the shift parameter to form a second data sequence.

[0098] The third source data corresponds one-to-one with the write pins of the memory chip. The third source data includes the initial data of the pseudo-random binary sequence. The basic data group is formed based on the third source data, including: using the third source data as the basic data group; or, performing preset operations on the third source data to form the basic data group.

[0099] S1105. Select one type of write test data from the write test data generated in the above steps according to the register configuration and perform power integrity test. The data format of the write test data conforms to the data format of the interface between the storage controller and the storage chip.

[0100] The testing method provided in this disclosure includes the generation of multiple test data sets. Understandably, in practice, only one type of test data is used for each power integrity test. This test data can be selected via a register or other methods; this disclosure does not impose any specific limitations.

[0101] In one exemplary embodiment, a testing apparatus is provided for implementing the method described above. (Reference) Figure 12 As shown, the testing device may include a switching module 1201 and a testing module 1202. During the implementation of the above method, the switching module 1201 is configured to disconnect the preset interface between the storage controller and the storage chip. The switching module 1201 is also configured to control the testing module 1202 to connect to the preset interface. The testing module 1202 is configured to send write test data to the storage chip via the preset interface for testing. The data format of the write test data conforms to the data format of the preset interface. The write test data is generated by the testing module 1202. The testing module 1202 is also configured to receive readback data and perform verification to determine the test result.

[0102] In one exemplary embodiment, a testing apparatus is provided, wherein the testing module 1202 is further configured to: The test data to be written is configured as a preset first data sequence or a second data sequence formed according to preset changes.

[0103] In one exemplary embodiment, a testing apparatus is provided, wherein the testing module 1202 is further configured to: The write test data includes at least one set of data groups, each set of data groups includes multiple data groups, and each set of multiple data groups corresponds one-to-one with the write pin of the memory chip; At least one set of data groups is used to form the first data sequence in a cyclical manner at a preset time interval.

[0104] In one exemplary embodiment, a testing apparatus is provided, wherein writing test data includes a first data group and a second data group, the first data group including a plurality of first data, and the second data group including a plurality of second data, wherein the first data and the second data are different, and the testing module 1202 is further configured to: The first data group and the second data group appear alternately at a preset time interval to form the first data sequence.

[0105] In one exemplary embodiment, a testing apparatus is provided, wherein a preset number of data groups constitute a data set, and at least a portion of the data in a portion of the data groups in the data set is used to represent numbers or letters; the testing module 1202 is further configured to: The data set is continuously cyclically arranged at preset time intervals to form the first data sequence.

[0106] In one exemplary embodiment, a testing apparatus is provided, wherein the testing module 1202 is further configured to: Obtain the source data for register configuration; The source data is processed using a preset processing method to form a second data sequence.

[0107] In one exemplary embodiment, a testing apparatus is provided, wherein the source data includes first source data and second source data, the first source data corresponding one-to-one with the write pins of the memory chip, and the second source data corresponding one-to-one with the write time intervals of the memory chip; the testing module 1202 is further configured to: One of the first source data and the second source data is used as row data, and the other is used as column data. The two data points at the intersection of the row data and the column data are processed to form the second data sequence.

[0108] In one exemplary embodiment, a testing apparatus is provided, wherein the first data processing method includes XOR processing.

[0109] In one exemplary embodiment, a testing apparatus is provided, wherein the source data includes third source data, the third source data corresponding one-to-one with the write pins of the memory chip, and the testing module 1202 is further configured to: A basic data set is formed based on the third source data. The basic data set is then cyclically shifted using a unit time interval as the shift parameter to form a second data sequence.

[0110] In one exemplary embodiment, a testing apparatus is provided, wherein the third source data includes pseudo-random binary sequence initial data, and the testing module 1202 is further configured to: Use third-source data as the base data group; or, Pre-defined operations are performed on the third source data to form a basic data set.

[0111] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0112] This disclosure also provides an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the test method described in the above embodiments. The electronic device is, for example, a mobile phone, a laptop computer, a tablet computer, and a wearable device.

[0113] refer to Figure 13 As shown, the electronic device 1300 may include one or more of the following components: processing component 1302, memory 1304, power supply component 1306, multimedia component 1308, audio component 1310, input / output (I / O) interface 1312, sensor component 1314, and communication component 1316.

[0114] Processing component 1302 typically controls the overall operation of electronic device 1300, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1302 may include one or more processors 1320 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1302 may include one or more modules to facilitate interaction between processing component 1302 and other components. For example, processing component 1302 may include a multimedia module to facilitate interaction between multimedia component 1308 and processing component 1302.

[0115] Memory 1304 is configured to store various types of data to support the operation of electronic device 1300. Examples of such data include instructions for any application or method operating on electronic device 1300, contact data, phonebook data, messages, pictures, videos, etc. Memory 1304 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0116] Power supply component 1306 provides power to various components of electronic device 1300. Power supply component 1306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1300.

[0117] Multimedia component 1308 includes a screen that provides an output interface between electronic device 1300 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1308 includes a front-facing camera module and / or a rear-facing camera module. When electronic device 1300 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera module and / or the rear-facing camera module may receive external multimedia data. Each front-facing camera module and rear-facing camera module may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0118] Audio component 1310 is configured to output and / or input audio signals. For example, audio component 1310 includes a microphone (MIC) configured to receive external audio signals when electronic device 1300 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1304 or transmitted via communication component 1316. In some embodiments, audio component 1310 also includes a speaker for outputting audio signals.

[0119] I / O interface 1312 provides an interface between processing component 1302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0120] Sensor assembly 1314 includes one or more sensors for providing state assessments of various aspects of electronic device 1300. For example, sensor assembly 1314 may detect the on / off state of electronic device 1300, the relative positioning of components such as the display and keypad of electronic device 1300, changes in position of electronic device 1300 or a component of electronic device 1300, the presence or absence of user contact with electronic device 1300, the orientation or acceleration / deceleration of electronic device 1300, and temperature changes of electronic device 1300. Sensor assembly 1314 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1314 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0121] Communication component 1316 is configured to facilitate wired or wireless communication between electronic device 1300 and other terminals. Electronic device 1300 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 1316 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1316 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0122] In an exemplary embodiment, the electronic device 1300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods shown in the above embodiments or combinations thereof.

[0123] In one exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1304 including instructions, which can be executed by a processor 1320 of an electronic device 1300 to perform the methods shown in the above embodiments or combinations thereof. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage terminal, etc. When the instructions in the storage medium are executed by the processor of the terminal, the terminal is able to perform the methods shown in the above embodiments or combinations thereof.

[0124] In one exemplary embodiment, a computer program product is provided, including a computer program or instructions that, when executed by a processor, implement the method described above.

[0125] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0126] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0128] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0129] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0130] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, when implementing each example, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained through appropriate means, in accordance with relevant laws and regulations. The specific methods of notification and / or authorization can vary depending on the actual situation and application scenario; the scope of the solution is not limited in this regard.

[0131] In this manual and the sample solutions, any processing of personal information will be conducted only under legal grounds (such as obtaining the consent of the data subject or being necessary for the performance of a contract) and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

Claims

1. A testing method, characterized in that, include: Disconnect the interface between the storage controller and the storage chip; The control test module is connected to the interface and sends write test data to the memory chip for testing via the interface. The data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module. Receive and verify the readback data to determine the test results.

2. The test method according to claim 1, characterized in that, The write test data is generated via the test module configuration and includes: The test data to be written is configured as a preset first data sequence or a second data sequence formed according to preset changes.

3. The test method according to claim 2, characterized in that, The written test data is configured as a preset first data sequence, including: The write test data includes at least one set of data groups, each set of data groups includes multiple data groups, and the multiple data groups correspond one-to-one with the write pins of the memory chip; The at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval.

4. The test method according to claim 3, characterized in that, The written test data includes a first data group and a second data group. The first data group includes multiple first data items, and the second data group includes multiple second data items. The first data items are different from the second data items. The at least one data group cyclically forms the first data sequence according to a preset time interval, including: The first data group and the second data group alternately appear at the preset time interval to form the first data sequence.

5. The test method according to claim 3, characterized in that, A predetermined number of data groups constitute a data set, wherein at least a portion of the data in the data groups is used to represent numbers or letters; the at least one set of data groups cyclically constitutes the first data sequence according to a predetermined time interval, including: The data set is continuously cyclically constructed to form the first data sequence according to the preset time interval.

6. The test method according to claim 2, characterized in that, The second data sequence formed by writing test data according to preset changes includes: Obtain the source data for register configuration; The source data is processed according to the preset processing method to form the second data sequence.

7. The test method according to claim 6, characterized in that, The source data includes first source data and second source data. The first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the write time intervals of the memory chip. The step of processing the source data based on the preset processing method to form the second data sequence includes: One of the first source data and the second source data is used as row data, and the other is used as column data. The two data at the intersection of the row data and the column data are subjected to first data processing to form the second data sequence.

8. The test method according to claim 7, characterized in that, The first data processing method includes XOR processing.

9. The test method according to claim 6, characterized in that, The source data includes third source data, which corresponds one-to-one with the write pins of the memory chip. The step of processing the source data based on the preset processing method to form the second data sequence includes: Based on the third source data, a basic data group is formed. Using a unit time interval as the shift parameter, the basic data group is cyclically shifted to form the second data sequence.

10. The test method according to claim 9, characterized in that, The third source data includes initial data of a pseudo-random binary sequence, and the formation of a basic data set based on the third source data includes: The third source data is used as the base data group; or, The third source data is subjected to a preset operation to form the basic data group.

11. A testing apparatus, characterized in that, include: A switching module configured to disconnect the interface between the storage controller and the storage chip; The switching module is also configured to control the test module to connect to the interface; The test module is configured to send write test data to the storage chip via the interface for testing, wherein the data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module. The test module is also configured to receive readback data and perform verification to determine the test results.

12. The testing apparatus according to claim 11, characterized in that, The test module is also configured to: The written test data is configured as a preset first data sequence or a second data sequence formed according to preset changes.

13. The testing apparatus according to claim 12, characterized in that, The test module is also configured to: The write test data includes at least one set of data groups, each set of data groups includes multiple data groups, and the multiple data groups correspond one-to-one with the write pins of the memory chip; The at least one set of data groups cyclically constitutes the first data sequence according to a preset time interval.

14. The testing apparatus according to claim 12, characterized in that, The test module is also configured to: Obtain the source data for register configuration; The source data is processed according to the preset processing method to form the second data sequence.

15. The testing apparatus according to claim 14, characterized in that, The source data includes first source data and second source data. The first source data corresponds one-to-one with the write pins of the memory chip, and the second source data corresponds one-to-one with the write time intervals of the memory chip. The test module is further configured to: One of the first source data and the second source data is used as row data, and the other is used as column data. The two data at the intersection of the row data and the column data are subjected to first data processing to form the second data sequence.

16. The testing apparatus according to claim 14, characterized in that, The source data includes third source data, which corresponds one-to-one with the write pins of the memory chip. The test module is also configured to: Based on the third source data, a basic data group is formed. Using a unit time interval as the shift parameter, the basic data group is cyclically shifted to form the second data sequence.

17. The testing apparatus according to claim 16, characterized in that, The third source data includes initial data of a pseudo-random binary sequence, and the test module is further configured to: The third source data is used as the base data group; or, The third source data is subjected to a preset operation to form the basic data group.

18. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to perform the test method as described in any one of claims 1 to 10.

19. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the terminal, the terminal is able to perform the test method as described in any one of claims 1 to 10.

20. A computer program product comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, the test method as described in any one of claims 1 to 10 is implemented.

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