Storage device and method of operating the same

Abstract

The present disclosure relates to a storage device and an operating method thereof. According to an embodiment of the disclosed technology, a storage device is provided. The storage device includes a first memory device configured to store data, a second memory device including a first cache memory configured to store mapping information between a physical data address and a logical data address of the stored data, and a second cache memory configured to store segments of the mapping information, and a memory controller in communication with the first memory device and the second memory device and configured to update the mapping information in response to a write request received from an external host device, wherein the memory controller is configured to allocate a first region for the mapping information among regions of the second cache memory in response to determining that a size of a workload corresponding to the write request is less than or equal to a first threshold value.

Description

Cross-reference to related applications

[0001] This patent document claims priority and interest in Korean Patent Application No. 10-2025-0024366, filed on February 25, 2025, and Korean Patent Application No. 10-2025-0097093, filed on July 18, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The technologies and implementation methods disclosed in this patent document generally relate to storage devices and their operating methods. Background Technology

[0003] Memory devices store data in response to write requests and output the stored data in response to read requests. For example, memory devices can be volatile memory devices, such as dynamic random access memory (DRAM) and static RAM (SRAM), which are volatile memory devices that lose stored data when power is off, and non-volatile memory devices, such as flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM), which retain stored data even when power is off.

[0004] Memory devices can update the mapping information between logical addresses and physical addresses based on logical addresses and write requests received from the host device. However, the space in cache memory storing this mapping information is limited, and the mapping update operation of refreshing the mapping information stored in cache memory can incur overhead and reduce the durability of the memory device. Therefore, techniques that increase the cycle time of mapping update operations may be needed. Summary of the Invention

[0005] Various embodiments relate to storage devices that allocate a portion of cache memory for data stored in another cache memory, and methods of operating such storage devices.

[0006] According to an embodiment, the storage device may include: a first memory device configured to store data; a second memory device including a first cache memory configured to store mapping information between physical data addresses and logical data addresses of the stored data, and a second cache memory configured to store segments of the mapping information; and a memory controller communicating with the first and second memory devices and configured to update the mapping information in response to a write request received from an external host device, wherein the memory controller is configured to allocate a first region for the mapping information in a region of the second cache memory in response to determining that the size of the workload corresponding to the write request is less than or equal to a first threshold.

[0007] According to an embodiment, the storage device may include: a first memory device configured to store data; a second memory device including a first cache memory configured to store mapping information between physical data addresses and logical data addresses of the stored data, and a second cache memory configured to store segments of the mapping information; and a memory controller communicating with the first and second memory devices and configured to allocate a first region for the mapping information within a region of the second cache memory, wherein the memory controller is configured to: in response to receiving a write request from an external host device, determine whether a cache hit or cache miss occurs for the segment corresponding to the write request, modify the segment in response to a cache hit for the segment, and update the mapping information in response to a cache miss for the segment. Attached Figure Description

[0008] Figure 1 This is a block diagram of an electronic system according to an embodiment of the disclosed technology.

[0009] Figure 2 This is a block diagram of a storage device according to an embodiment of the disclosed technology.

[0010] Figure 3 This is a flowchart illustrating an operation method of a storage device according to an embodiment of the disclosed technology.

[0011] Figure 4 This is a schematic diagram of a storage device according to some embodiments of the disclosed technology.

[0012] Figure 5 This is a flowchart illustrating an operation method of a storage device according to some embodiments of the disclosed technology.

[0013] Figure 6This is a schematic diagram of a storage device according to some embodiments of the disclosed technology.

[0014] Figure 7 This is a flowchart illustrating an operation method of a storage device according to some embodiments of the disclosed technology.

[0015] Figure 8 This is a flowchart illustrating an operation method of a storage device according to some embodiments of the disclosed technology.

[0016] Figure 9 This is a flowchart illustrating an operation method of a storage device according to some embodiments of the disclosed technology.

[0017] Figure 10 This is a schematic diagram illustrating a second memory device according to some embodiments of the disclosed technology.

[0018] Figure 11 This is a block diagram illustrating a memory card system that applies some embodiments of a storage device according to the disclosed technology; and

[0019] Figure 12 This is a block diagram illustrating an electronic system according to an embodiment of the disclosed technology. Detailed Implementation

[0020] The embodiments of the disclosed technology will be described in detail and clearly below so that those skilled in the art can easily implement the present invention.

[0021] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0022] Figure 1 This is a block diagram of an electronic system 10 according to an embodiment of the disclosed technology. (See reference...) Figure 1 The electronic system 10 can be a computing system configured to process various types of information or store processed information as data. In some embodiments, the electronic system 10 can be implemented as a personal computer (PC), a laptop, a desktop computer, a server, a workstation, a tablet PC, a smartphone, a digital camera, a black box, etc.

[0023] Electronic system 10 may include host device 11 and storage device 100. Host device 11 can control various operations of electronic system 10. More specifically, host device 11 can control the operation of other components, including electronic system 10. Host device 11 may be implemented as a general-purpose processor, a special-purpose processor, or an application processor (AP).

[0024] Host device 11 can communicate with storage device 100. For example, host device 11 can request programming operations, read operations, erase operations, etc., from storage device 100. Host device 11 can transmit host request REQ, data DATA, and logical address ADD to storage device 100 for programming operations on storage device 100. For example, host device 11 can transmit host request REQ and logical address ADD to storage device 100 for write operations on storage device 100. The set of host request REQ, data DATA, and logical address ADD provided by host device 11 to storage device 100 can be referred to as workload.

[0025] In some embodiments, a host request (REQ) for a write operation can indicate a sequential write operation or a random write operation. A sequential write operation can be an operation that sequentially writes contiguous data corresponding to logical addresses to storage device 100. Conversely, a random write operation can be an operation that writes non-contiguous data corresponding to logical addresses to storage device 100.

[0026] Storage device 100 can store data. For example, the storage device can store data under the control of host device 11. In some embodiments, storage device 100 may include at least one of solid-state drive (SSD), embedded memory, and removable external memory. When storage device 100 is an SSD, storage device 100 may conform to the Non-Volatile Fast Memory (NVMe) standard. When storage device 100 is embedded memory or removable external memory, storage device 100 may conform to the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard. Host device 11 and storage device 100 may each generate data packets based on the standard protocol adopted and transmit the generated data packets to each other.

[0027] Storage device 100 may include a memory controller 110, a first memory device 120, and a second memory device 130. The memory controller 110 can control the operation of storage device 100. For example, the memory controller 110 can control the operation of storage device 100 according to internal policies or in response to a host request REQ. The memory controller 110 can store data DATA in the first memory device 120 or read data DATA stored in the first memory device 120 based on internal policies or in response to a host request REQ.

[0028] The memory controller 110 may generate a programming command in response to a host request REQ corresponding to a programming operation received from the host device 11, and provide the generated programming command to the first memory device 120. The memory controller 110 may also generate a write command in response to a host request REQ corresponding to a write operation received from the host device 11, and provide the generated write command to the first memory device 120.

[0029] The memory controller 110 stores the mapping information between logical addresses (ADD) and physical addresses in the second memory device 130, and can update the mapping information in response to a write request. For example, in response to a write request, the memory controller 110 can provide a write command, a physical address, and data (DATA) to the first memory device 120, and can update the mapping information between logical addresses (ADD) and physical addresses in the second memory device 130. In some embodiments, the mapping information stored in the second memory device 130 may include physical-to-logical (P2L) mapping information.

[0030] The memory controller 110 can perform a mapping update operation. For example, the memory controller 110 can perform a mapping update operation that refreshes the mapping information stored in the second memory device 130 to the first memory device 120 and erases the mapping information from the second memory device 130. The mapping update operation may incur significant overhead and reduce the durability of the second memory device 130.

[0031] The memory controller 110 can perform a mapping update operation in response to various factors. For example, the memory controller 110 can respond to determining that there is insufficient additional space within the second memory device 130 to perform a mapping update operation to update the mapping information. Therefore, the size of the space within the second memory device 130 used to store the mapping information can be directly related to the frequency of the mapping update operation, and thus can be related to the performance of the storage device 100 or the electronic system 10, as well as the durability of the storage device 100. Therefore, within the limited space of the second memory device 130, it is necessary to ensure additional space or areas for mapping information.

[0032] The following will refer to Figures 2 to 9 A more detailed description is given of how the memory controller 110 ensures additional space or regions for mapping information.

[0033] The first memory device 120 can store data DATA under the control of the memory controller 110. For example, the first memory device 120 can store metadata, which includes user data received from the host device 11 and mapping information or segments received from the second memory device 130 via a mapping update operation.

[0034] The first memory device 120 may be a non-volatile memory device, such as NAND flash memory, but the scope of the disclosed technology is not limited thereto. The first memory device 120 may be one of a variety of devices that can retain stored data even when power is off, such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), or ferroelectric random access memory (FRAM).

[0035] The second memory device 130 can store mapping information or segments under the control of the memory controller 110. In some embodiments, the second memory device 130 can temporarily store mapping information between logical addresses (ADD) and physical addresses, and then provide the stored mapping information to the first memory device 120 via a mapping update operation.

[0036] The second memory device 130 can be one of various devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), etc.

[0037] Because the second memory device 130 operates at a relatively faster speed (e.g., the speed of write operations or read operations) than the first memory device 120, the memory controller 110 can quickly store or update the mapping information in the second memory device 130. Therefore, the storage device 100 can use a portion of the second memory device 130 to cache the mapping information. Reference will be made below. Figure 2 and Figure 3 To describe it in more detail.

[0038] exist Figure 1 In this embodiment, the second memory device 130 is exemplarily described as being placed outside the memory controller 110, but the scope of the disclosed technology is not limited thereto. The second memory device 130 may be included within the memory controller 110.

[0039] Figure 2 This is a block diagram of a storage device 100 according to an embodiment of the disclosed technology. (See reference) Figure 2 The storage device 100 may include a memory controller 110, a first memory device 120, and a second memory device 130. Figure 2 The memory controller 110, the first memory device 120, and the second memory device 130 shown are similar to Figure 1 The memory controller 110, the first memory device 120, and the second memory device 130 are shown. Therefore, redundant descriptions of these components will be omitted below.

[0040] The second memory device 130 may include a first cache memory 131 and a second cache memory 132. The first cache memory 131 may store mapping information MP, and the second cache memory 132 may store segments (e.g., L2 segments) SG.

[0041] For ease of understanding, the first cache memory 131 and the second cache memory 132 are illustrated as separate cache memories, but the scope of the disclosed technology is not limited thereto. The first cache memory 131 and the second cache memory 132 can be implemented as a single cache memory. Furthermore, the second memory device 130 may include at least two or more cache memories, as needed. Reference will be made below. Figure 10 A more detailed description of an embodiment in which the first cache memory 131 and the second cache memory 132 are implemented as a single cache memory is provided.

[0042] In some embodiments, the first cache memory 131 can be used as a cache for storing mapping information MP for write operations of the storage device 100, and the second cache memory 132 can be used as a cache for storing segments SG for read operations of the storage device 100. For example, the first cache memory 131 can store and update the mapping information MP between the physical address and logical address ADD of the data DATA to be stored in the first memory device 120, and the second cache memory 132 can cache segments SG of the data to be read from the first memory device 120.

[0043] The memory controller 110 can use a portion of the second cache memory 132 to handle write requests WREQ (or the workload of write requests WREQ). For example, when the requests received from the host device 11 are primarily write requests WREQ, or when the workload of read requests is low, the memory controller 110 can allocate a portion (e.g., the first region R1 and the second region R2) of the second cache memory 132 for the mapping information MP, and can load and cache the segments corresponding to the write requests WREQ. Write requests and read requests can be... Figure 1 The host request REQ in the table refers to write operations and read operations, respectively.

[0044] In some embodiments, the size of regions (e.g., first region R1 and second region R2) in the second cache memory 132 can be varied as needed. In some embodiments, the second memory device 130 may include at least three cache memories, and the memory controller 110 may, exemplarily, allocate at least one of the three or more cache memories as the first region R1.

[0045] In some embodiments, the memory controller 110 may load segments corresponding to write requests WREQ into the first region R1, or modify already loaded segments, instead of updating the mapping information MP stored in the first cache memory 131 based on the write request WREQ. By allocating the first region R1 to the mapping information MP (e.g., by loading or modifying segments corresponding to write requests WREQ into the first region R1 instead of updating the mapping information MP), the memory controller 110 can handle more write requests WREQ and their workload until all available space in the first cache memory 131 is exhausted (e.g., until all space used for updating the mapping information MP is exhausted). Therefore, the update frequency of updating the mapping information MP can be reduced, and the cycle or time period of the mapping update operation can be increased.

[0046] However, when the memory controller 110 indiscriminately allocates a portion of the first cache memory 131 (e.g., the first region R1) for the mapped information MP, it can cause performance degradation of the storage device 100. For example, when the workload of write request WREQ exhibits low locality (e.g., when the number of segments corresponding to write request WREQ is large or the workload size exceeds a threshold), all segments corresponding to write request WREQ may not be loaded into the first region R1, resulting in more frequent mapping update operations. Therefore, the memory controller 110 may perform mapping update operations at shorter intervals than when a portion of the first cache memory 131 (e.g., the first region R1) is not allocated for the mapped information MP. This can further degrade the performance of the storage device 100.

[0047] Therefore, in some implementations, if certain conditions are met, the memory controller 110 selectively allocates a portion of the first cache memory 131 (e.g., the first region R1) to the mapped information. For example, such selective allocation is performed based on a locality check. For example, the memory controller 110 may perform a comparison operation between the size of the workload corresponding to the write request WREQ and a threshold. Based on the result of this comparison operation, the memory controller 110 may selectively allocate a portion of the first cache memory 131 (e.g., the first region R1) to the mapped information MP. For example, the memory controller 110 may allocate a portion of the first cache memory 131 (e.g., the first region R1) to the mapped information MP in response to determining that the size of the workload corresponding to the write request WREQ is less than or equal to a threshold (i.e., locality is high).

[0048] In some implementations, in response to determining that the workload corresponding to the write request WREQ is greater than a threshold, the memory controller 110 may deallocate a portion of the first cache memory 131 (e.g., the first region R1), and the segment corresponding to the write request WREQ may no longer be loaded into the deallocated first region R1 or may be modified. Reference will be made below. Figure 3 To describe it in more detail.

[0049] Figure 3 This is an operation flowchart of a storage device 100 according to an embodiment of the present disclosure. (See also...) Figure 2 and Figure 3 The memory controller 110 may selectively allocate a portion (e.g., a first region R1) of the first cache memory 131 to the mapping information MP based on the result of a comparison operation between the size of the workload corresponding to the write request WREQ and a threshold.

[0050] In step S110, the memory controller 110 may receive a write request WREQ from the external host device 11. In some embodiments, the write request WREQ may correspond to one or more logical addresses. In other words, the workload corresponding to the write request WREQ may include at least one logical address. At least one logical address may correspond to at least one segment.

[0051] In step S120, the memory controller 110 can determine whether the size of the workload corresponding to the write request WREQ is less than or equal to a first threshold TH1. For example, based on the write request WREQ and logical address ADD received from the external host device 11, the memory controller 110 can determine the number of segments corresponding to the write request WREQ (e.g., the size of the workload), and can determine whether the number of segments or the size of the workload is less than or equal to the first threshold TH1, thereby determining the locality of the workload corresponding to the write request WREQ. When the number of segments (or the size of the workload) is small, the locality of the workload corresponding to the write request WREQ is high; when the number of segments is large, the locality can be low.

[0052] In step S130, the memory controller 110 may allocate a first region R1 for the mapping information MP in response to determining that the workload size is less than or equal to a first threshold TH1 (e.g., high locality). For example, the memory controller 110 may allocate the first region R1 for the mapping information MP within a region of the second cache memory 132 (e.g., the first region R1 and the second region R2).

[0053] In some embodiments, the memory controller 110 may store data DATA corresponding to the write request WREQ in the first memory device 120, and may load the segment corresponding to the write request WREQ into the first region R1, or modify the loaded segment.

[0054] In some embodiments, the memory controller 110 may update the mapping information MP corresponding to the write request WREQ in the first cache memory 131 in response to determining that the workload size is greater than a first threshold TH1 (e.g., low locality).

[0055] In some embodiments, the memory controller 110 may determine whether the first region R1 is in an allocatable state as a requirement for allocating the first region R1 for the mapping information MP. When the first region R1 is in an allocatable state, the memory controller 110 may allocate the first region R1 for the mapping information MP. However, when the first region R1 is not in an allocatable state (e.g., in an unallocable state), the memory controller 110 may not allocate the first region R1 for the mapping information MP until the first region R1 becomes allocatable again. Reference will be made below. Figure 6 and Figure 7 Provides a more detailed description of the allocatable state of the first region R1.

[0056] Figure 4 This is a schematic diagram of a storage device 100 according to some embodiments of the disclosed technology. (See reference) Figure 2 and Figure 4The memory controller 110 can modify the segmentation or update the mapping information MP based on whether a cache hit occurs in the first region R1.

[0057] In response to receiving a write request WREQ from the external host device 11, the memory controller 110 may load the segment corresponding to the write request WREQ into the first region R1, or modify a segment already loaded into the first region R1. In some embodiments, loading a segment into the first region R1 may require more overhead than modifying a segment already loaded into the first region R1. Therefore, when the segment corresponding to the write request WREQ is not loaded into the first region R1, updating the mapping information MP in the first cache memory 131 requires less write time than loading the segment into the first region R1, and thus can provide better write performance.

[0058] In some embodiments, the memory controller 110 determines whether the segment corresponding to the write request WREQ is a cache hit (e.g., the segment corresponding to the write request is loaded into the first cache region R1) or a cache miss (e.g., the segment corresponding to the write request is not loaded into the first cache region R1). In some embodiments, when a cache miss occurs, the memory controller 110 may first update the mapping information MP and then load the segment into the first region R1 via a background operation.

[0059] The first cache memory 131 stores mapping information MP, and the mapping information MP may include multiple mapping entries MP1 to MPn. Each of the multiple mapping entries MP1 to MPn can indicate the mapping relationship between logical addresses and physical addresses. In addition, the second cache memory 132 may include a first region R1 and a second region R2, and the first region R1 and the second region R2 can respectively store multiple segments SGa to SGm and SG1 to SGp, where n, m and p are arbitrary natural numbers.

[0060] In some embodiments, when the memory controller 110 receives a read request from an external host device (not shown) corresponding to at least one segment loaded into the first region R1, the memory controller 110 may perform a read operation on the data DATA stored in the first memory device 120 based on the corresponding segment, and may provide the read data DATA to the external host device (not shown).

[0061] The operations described below, including first operations ① through fifth operations ⑤, are exemplary operations that facilitate understanding of the disclosed technology, and the scope of the disclosed technology is not limited thereto.

[0062] In the first operation ①, the memory controller 110 can determine whether a cache hit or a cache miss has occurred. For example, the memory controller 110 can determine that a cache hit has occurred, indicating that the segment corresponding to the write request WREQ received from the external host device 11 has been loaded into the first region R1. For example, the memory controller 110 can determine that a cache miss has occurred, indicating that the segment corresponding to the write request WREQ received from the external host device 11 has not been loaded into the first region R1.

[0063] In the second operation ②, the memory controller 110 may modify the segment in response to a cache hit (e.g., when the segment corresponding to the write request WREQ is loaded in the first region R1). For example, when the segment corresponding to the write request WREQ is the a-th segment SGa, the memory controller 110 determines that the segment SGa is loaded in the first region R1 (e.g., a cache hit) and may modify the segment SGa.

[0064] In the third operation ③, the memory controller 110 may update the mapping information MP in response to a cache miss (e.g., when the segment corresponding to the write request does not exist in the first region R1). For example, in response to a cache miss, the memory controller 110 may modify the first mapping entry MP1 corresponding to the logical address and physical address associated with the write request WREQ in the mapping information MP stored in the first cache memory 131.

[0065] In the fourth operation ④, the memory controller 110 may load a segment into the first region R1. For example, the memory controller 110 may update the mapping information MP (e.g., the first mapping entry MP1) corresponding to the write request WREQ, and then may load the m-th segment SGm corresponding to the write request WREQ into the first region R1. In response to a cache miss, the memory controller 110 may load the m-th segment SGm into the first region R1 via a background operation after updating the mapping information MP, instead of loading the m-th segment SGm, thereby immediately reducing overhead and improving write performance.

[0066] In the fifth operation ⑤, the memory controller 110 may invalidate a portion of the mapping information. For example, after loading the m-th segment SGm into the first region R1, the memory controller 110 may, in response to receiving an additional write request WREQ for the m-th segment SGm, invalidate the first mapping entry MP1 corresponding to the write request WREQ. By invalidating the first mapping entry MP1, the memory controller 110 can free up more space within the first cache memory 131.

[0067] In some embodiments, when the memory controller 110 has not received any additional write request WREQ for the m-th segment SGm after loading the m-th segment SGm into the first region R1 and before a subsequent mapping update operation, the memory controller 110 may retain the first mapping entry MP1 (without invalidating the first mapping entry MP1).

[0068] Figure 5 This is a flowchart illustrating an operation method of a storage device 100 according to some embodiments of the disclosed technology. (See also:) Figure 4 and Figure 5 The memory controller 110 can modify the segment SG or update the mapping information MP that has been loaded into the first region R1 based on whether a cache hit or a cache miss occurs.

[0069] In step S210, the memory controller 110 may receive a write request WREQ. For example, the memory controller 110 may receive a write request WREQ corresponding to at least one segment SG.

[0070] In step S220, the memory controller 110 may determine whether a cache hit has occurred. For example, the memory controller 110 may determine whether a cache hit or a cache miss has occurred. A cache hit indicates that the segment SG corresponding to the write request WREQ is loaded in the first region R1, and a cache miss indicates that the segment SG corresponding to the write request WREQ is not loaded in the first region R1.

[0071] In some embodiments, when the received write request WREQ is the first write request WREQ received after the allocation of the first region R1, the memory controller 110 can determine a cache miss. In this case, a cache miss can be determined even if it is uncertain whether a cache miss has occurred. If the received write request WREQ is the first write request WREQ received after the allocation of the first region R1, the memory controller 110 can perform the operation of step S240. When the first region R1 is first allocated, there may be no loaded segment SG within the first region R1, making it unnecessary to determine whether a cache miss has occurred.

[0072] In some embodiments, one or more segment SGs may correspond to a write request WREQ. For example, when two or more segment SGs correspond to a write request WREQ, the memory controller 110 may determine whether a cache hit has occurred for all segment SGs. In other words, the memory controller 110 may determine whether a cache hit has occurred based on whether all segment SGs corresponding to the write request WREQ have been loaded into the first region R1. The memory controller 110 may determine a cache miss in response to determining that at least one segment SG has not been loaded into the first region R1.

[0073] In some embodiments, when a portion of the second cache memory 132 (e.g., the first region R1) is allocated to the mapping information MP, the memory controller 110 can determine whether a cache hit has occurred. When the size of the workload (or the number of segments SG) corresponding to the write request WREQ is less than or equal to a threshold, the memory controller 110 can allocate the first region R1 to the mapping information MP. Therefore, when the size of the workload (or the number of segments SG) corresponding to the write request WREQ is less than or equal to the threshold, the memory controller 110 can determine whether a cache hit has occurred for a segment SG. When the size of the workload (or the number of segments SG) is greater than the threshold, the memory controller 110 can deallocate the first region R1 and perform a mapping update operation or update the mapping information MP.

[0074] In step S230, the memory controller 110 may modify the segment SG in response to a cache hit. For example, the memory controller 110 may modify the segment SG in response to determining that the segment SG corresponding to the write request WREQ has been loaded into the first region R1. In some embodiments, when two or more segment SGs correspond to the write request WREQ, the memory controller 110 may modify all segment SGs.

[0075] In step S240, the memory controller 110 may update the mapping information MP in response to a cache miss. For example, in response to a cache miss, the memory controller 110 may update the mapping information MP by modifying the portion of the mapping information MP stored in the first cache memory 131 that corresponds to the logical address and physical address associated with the write request WREQ.

[0076] In step S250, the memory controller 110 may load the segment SG into the first region R1. For example, after updating the mapping information MP corresponding to the write request WREQ, the memory controller 110 may load the segment SG corresponding to the write request WREQ into the first region R1. By loading the segment SG by a background operation after updating the mapping information MP, rather than immediately loading the segment SG into the first region R1 in response to a cache miss, the memory controller 110 can reduce the overhead of the storage device 100 and improve overall write performance.

[0077] In some embodiments, when two or more segment SGs correspond to a write request WREQ, the memory controller 110 may load all segment SGs into the first region R1. When some of the segment SGs out of two or more segment SGs have already been loaded into the first region R1, the memory controller 110 may load the remaining segment SGs into the first region R1.

[0078] In some embodiments, after the segment SG is loaded into the first region R1, the memory controller 110 may invalidate a portion of the mapping information MP corresponding to the write request WREQ (or segment SG).

[0079] The memory controller 110 may repeat steps S210 to S250. In some embodiments, after loading the segment SG in step S250, when a subsequent write request WREQ corresponding to the same segment SG is received, the memory controller 110 may modify the segment SG in response to a cache hit.

[0080] Figure 6 This is a schematic diagram illustrating a storage device 100 according to some embodiments of the disclosed technology. Reference Figure 6 In response to determining that an event has occurred, the memory controller 110 may release the portion of the second cache memory 132 allocated for the mapping information MP (e.g., the first region R1).

[0081] refer to Figures 2 to 5 The memory controller 110 can allocate a portion (e.g., a first region R1) of a second cache memory 132 for storing segments (loaded during read operations) of the mapping information MP. Instead of updating the mapping between the logical and physical addresses corresponding to the write request WREQ in the mapping information MP, the memory controller 110 can store the segment corresponding to the write request WREQ in the first region R1. By doing so, the mapping update cycle can be increased, and the performance of the storage device 100 can be improved.

[0082] However, indiscriminately allocating a portion of the second cache memory 132 to the mapping information MP may cause performance degradation. For example, as described below, allocating a portion of the second cache memory 132 to the mapping information MP may cause performance degradation when a specific event occurs.

[0083] In some embodiments, when the workload corresponding to a write request WREQ exhibits low locality and requires loading or modifying many segments, this can incur more overhead than updating the mapping information MP in the first cache memory 131, resulting in inefficient space usage. For example, loading or modifying the segments corresponding to the write request WREQ into a portion of the second cache memory 132 (e.g., the first region R1) can be inefficient when the size of the workload corresponding to the write request WREQ (e.g., the number of segments) exceeds a threshold.

[0084] In some embodiments, updating or storing the mapping information MP in a different manner may be more efficient when the write request WREQ is a sequential write operation.

[0085] Furthermore, allocating the second cache memory 132 for the mapping information MP during write operations means using additional components (e.g., the second cache memory 132) besides the first cache memory 131 during write operations, which may increase the overall power consumption of the storage device 100. Therefore, when a power reduction request is received from the external host device 11, the allocation of a portion of the second cache memory 132 (e.g., the first region R1) for the mapping information MP can be limited or disabled.

[0086] In some embodiments, when the storage device 100 performs internal operations that require a large amount of space in the second cache memory 132 (e.g., garbage collection operations, free block operations, etc.), the allocation of a portion of the second cache memory 132 (e.g., the first region R1) for the mapping information MP can be restricted or prohibited.

[0087] The events described above are exemplary and for illustrative purposes to aid in understanding the disclosed technology, and the scope of the disclosed technology is not limited thereto.

[0088] The memory controller 110 may, in response to determining that an event has occurred (e.g., at least one of the aforementioned events that disallows or restricts the allocation of a portion of the second cache memory 132), deallocate a portion of the second cache memory 132 (e.g., the first region R1). For example, the memory controller 110 may deallocate the first region R1 that has been allocated for mapping information MP, and then, upon receiving a subsequent write request WREQ, may update the mapping information MP stored in the first cache memory 131.

[0089] In some embodiments, the memory controller 110 may, in response to determining that an event (e.g., at least one of the events described above) has occurred, set a portion (e.g., the first region R1) of the second cache memory 132 to be unallocable for a specific time interval. The unallocable state may refer to a state where, even if the requirements for allocating mapping information (MP) are met, the portion of the second cache memory 132 (e.g., the first region R1) is not allocated for mapping information (MP). Since the event can occur repeatedly during the specific time interval, the memory controller 110 may, in response to the first occurrence of the event, set a portion of the second cache memory 132 (e.g., the first region R1) to be unallocable.

[0090] The memory controller 110 can perform a countdown operation to set a portion of the second cache memory 132 (e.g., the first region R1) as unallocable for a specific time interval. For example, in response to deallocation of the first region R1, the memory controller 110 can perform a countdown operation and set the first region R1 as unallocable during the countdown operation.

[0091] After the countdown operation is completed (e.g., after the count reaches zero), the memory controller 110 can either make the first region R1 available or reallocate the first region R1 for the mapping information MP. When the first region R1 is available, the memory controller 110 can allocate a portion of the second cache memory 132 (e.g., the first region R1) for the mapping information MP in response to determining that the requirement to allocate the first region R1 for the mapping information MP is met.

[0092] In some embodiments, the memory controller 110 may perform a countdown operation for different time intervals (or counts) for each type of event. For example, in response to determining that a first type of event has occurred among multiple event types, the memory controller 110 may perform a countdown operation for a first time interval (or a first count). In response to determining that a second type of event has occurred, the memory controller 110 may perform a countdown operation for a second time interval (or a second count).

[0093] In some embodiments, during a countdown operation (e.g., before the countdown operation completes or before the count reaches zero), the memory controller 110 may exceptionally make a portion of the second cache memory 132 that is in an unallocable state (e.g., the first region R1) available. Because the event can recur within a specific time period, the memory controller 110 makes a portion of the second cache memory 132 (e.g., the first region R1) unallocable for a specific time interval (e.g., until the countdown operation completes). However, if the probability of the event recurring within a specific time interval is low or nonexistent, the memory controller 110 may make a portion of the second cache memory 132 that is in an unallocable state (e.g., the first region R1) available without performing a countdown operation. For example, the memory controller 110 may make a portion of the second cache memory 132 (e.g., the first region R1) available after a predetermined time period following the event.

[0094] In some embodiments, the memory controller 110 may store information about the size of the workload corresponding to a subsequent write request WREQ during a countdown operation (e.g., when the first region R1 is in an unallocable state). For example, the memory controller 110 may update information about whether each size (or number of segments) of the workload corresponding to a subsequent write request WREQ is less than or equal to a first threshold.

[0095] In some embodiments, the memory controller 110 may set the first region R1 to allocatable before the countdown operation completes, based on information about the size of the workload corresponding to the subsequent write request WREQ. For example, the memory controller 110 may set the first region R1 to allocatable before the countdown operation completes, in response to determining that the number of subsequent write request WREQs, which includes a workload (or the number of segments) less than or equal to a first threshold, is greater than a second threshold.

[0096] The memory controller 110 may include a counter 111 and may store workload information WI. In some embodiments, the counter 111 performs a countdown operation, and when the countdown operation is complete (e.g., when the count reaches zero), the counter 111 may provide a signal indicating that the countdown operation is complete to the memory controller 110. Furthermore, the memory controller 110 may store information about the size of the workload corresponding to a subsequent write request WREQ as the workload information WI.

[0097] In some embodiments, the memory controller 110 may perform a mapping update operation in response to determining that the remaining space in the first region R1 is less than a threshold. For example, since the space in the first region R1 is limited, the number of segments loaded into the first region R1 may be limited. Therefore, by determining whether the remaining space in the first region R1 is less than the threshold, the memory controller 110 can determine whether additional segments can be loaded into the first region R1. When the remaining space in the first region R1 is less than the threshold, the memory controller 110 may perform a mapping update operation to refresh all segments loaded into the first region R1 to the first memory device 120.

[0098] The operations described below (e.g., operations ① through ⑦) are exemplary and used to illustrate examples of the disclosed technology, and do not limit the scope of the disclosed technology.

[0099] In the first operation ①, the memory controller 110 may release the first region R1. For example, the memory controller 110 may release the first region R1 in response to determining that an event (e.g., at least one of the events described above that disallows or restricts allocation) has occurred.

[0100] In the second operation ②, the memory controller 110 may perform a mapping update operation. For example, the memory controller 110 may perform a mapping update operation in response to determining that an event has occurred and that the first region R1 has been deallocated. To perform the mapping update operation, the memory controller 110 may control the second memory device 130 to refresh the mapping information MP stored in the first cache memory 131 and the segments loaded into the first region R1 in the second cache memory 132 to the first memory device 120.

[0101] In the third operation ③, the second memory device 130 can perform a refresh operation. For example, under the control of the memory controller 110, the second memory device 130 can refresh the mapping information MP stored in the first cache memory 131 and the segments loaded into the first region R1 in the second cache memory 132 to the first memory device 120. After the refresh operation, the segments loaded into the first region R1 may no longer exist. The first memory device 120 can store the refreshed mapping information MP and segments as metadata MD.

[0102] In the fourth operation ④, the memory controller 110 or the counter 111 may perform a countdown operation. For example, the memory controller 110 or the counter 111 may perform a countdown operation in response to determining that an event has occurred. The memory controller 110 or the counter 111 may determine the count value of the countdown operation based on the type of the event. Therefore, the memory controller 110 or the counter 111 may perform countdown operations at different time intervals depending on the event type.

[0103] In the fifth operation ⑤, the memory controller 110 may set the first region R1 to unallocable during the countdown operation. Therefore, the memory controller 110 cannot reallocate the first region R1 for the mapping information MP until the countdown operation is completed (e.g., until the count reaches zero).

[0104] In the sixth operation (⑥), the memory controller 110 may store workload information WI. For example, during a countdown operation (e.g., when the first region R1 is in an unallocable state), the memory controller 110 may store information about the size of the workload corresponding to subsequent write requests WREQ. For example, the memory controller 110 may update the workload information WI with information indicating whether the number of segments corresponding to each subsequent write request WREQ is less than or equal to a first threshold.

[0105] In the seventh operation (⑦), the memory controller 110 may determine whether to set the first region R1 as allocatable based on the workload information WI. For example, the memory controller 110 may determine whether to set the first region R1 as allocatable before the countdown operation is completed, based on the workload information WI. For example, the memory controller 110 may determine, by referring to the workload information WI, whether the number WREQ of subsequent write requests including the number of segments less than or equal to a first threshold is greater than a second threshold, and based on this result, may determine whether to set the first region R1 as allocatable before the countdown operation is completed.

[0106] Figure 7 This is a flowchart illustrating an operation method of a storage device 100 according to some embodiments of the disclosed technology. (Reference) Figure 6 and Figure 7 The memory controller 110 can set the first region R1 to be unallocable, and exceptionally set the first region R1 to be allocable again.

[0107] In step S310, the memory controller 110 may deallocate the first region R1. For example, the memory controller 110 may respond to a determination event (e.g., Figure 6 At least one of the events described in the document has occurred, and the first region R1 allocated to the mapping information MP has been unassigned.

[0108] In some embodiments, the memory controller 110 may perform a mapping update operation in response to deallocating the first region R1. For example, in response to deallocating the first region R1, the memory controller 110 may perform a mapping update operation to refresh all segments loaded into the first region R1 corresponding to the write request WREQ to the first memory device 120.

[0109] In step S320, the memory controller 110 may perform a countdown operation. For example, the memory controller 110 may perform a countdown operation in response to determining that an event has occurred.

[0110] In some embodiments, the memory controller 110 may determine the countdown operation based on the type of event. For example, when a first type of event occurs, the memory controller 110 may perform a countdown operation for a first count duration, and when a second type of event occurs, perform a countdown operation for a second count duration. Therefore, the memory controller 110 or the counter 111 may perform countdown operations for different time intervals depending on the event type.

[0111] In step S330, the memory controller 110 may set the first region R1 to be unallocable. For example, the memory controller 110 may set the first region R1 to be unallocable during a countdown operation. Therefore, the memory controller 110 cannot reallocate the first region R1 for the mapping information MP until the countdown operation is complete (e.g., until the count reaches zero).

[0112] In some embodiments, when the first region R1 is in an unallocable state, even if the requirements for allocating the first region R1 are met (e.g., when the number of segments corresponding to the write request WREQ is less than or equal to a threshold), the memory controller 110 cannot allocate the first region R1 for the mapping information MP.

[0113] In step S340, the memory controller 110 can determine whether the count has reached zero. For example, the memory controller 110 can decrement the count by one unit during the countdown operation and determine whether the countdown operation is complete when the count has reached zero. The memory controller 110 can maintain the first region R1 in an unallocable state until the count reaches zero.

[0114] In step S350, the memory controller 110 may determine whether to set the first region R1 to allocatable. For example, the memory controller 110 may determine to set the first region R1 to allocatable by exception in response to determining that the count has not yet reached zero (e.g., the countdown operation has not yet completed).

[0115] In some embodiments, the memory controller 110 may store information about the size of the workload corresponding to a subsequent write request WREQ during a countdown operation (e.g., when the first region R1 is in an unallocable state). The memory controller 110 may determine, based on the information about the size of the workload corresponding to each subsequent write request WREQ, whether to make the first region R1 allotable before the countdown operation completes.

[0116] For example, memory controller 110 may set the first region R1 to allocatable before the countdown operation is completed, in response to determining that the number of subsequent write requests WREQ including segments less than or equal to a first threshold is greater than a second threshold.

[0117] In response to determining that the first region R1 is not set to allocatable, the memory controller 110 may repeat and execute step S340. The memory controller 110 may then determine again whether the count has reached zero.

[0118] In step S360, the memory controller 110 may set the first region R1 to be allocable in response to determining that the count has reached zero or that the first region R1 has been set to be allocable. In response to determining that the requirement to allocate the first region R1 for the mapping information MP is met, the memory controller 110 may reallocate the first region R1 for the mapping information MP.

[0119] Figure 8 This is a flowchart illustrating an operation method of a storage device 100 according to some embodiments of the disclosed technology. (Reference) Figure 2 and Figure 8 The memory controller 110 can modify the segment SG loaded into the first region R1 based on whether a cache hit occurs, or it can update the mapping information MP in the first cache memory 131.

[0120] In step S410, the memory controller 110 may receive a write request WREQ from the external host device 11. Before receiving the write request WREQ, the memory controller 110 may allocate some regions of the second cache memory 132 (e.g., the first region R1) for the mapping information MP corresponding to the write request WREQ. However, when processing the workload corresponding to the write request WREQ (e.g., when performing a write operation on data DATA), the memory controller 110 may need to determine whether to update the mapping information MP in the first cache memory 131 or modify the segment SG loaded into the first region R1.

[0121] In step S420, the memory controller 110 can determine whether a cache hit has occurred. For example, the memory controller 110 can determine whether a cache hit has occurred by determining whether the segment SG corresponding to the write request WREQ has been loaded into the first region R1. Based on whether a cache hit has occurred, the memory controller 110 can determine whether to update the mapping information MP of the first cache memory 131 or modify the segment SG loaded into the first region R1.

[0122] In step S430, the memory controller 110 may modify the segment SG in response to a cache hit. For example, the memory controller 110 may modify the segment SG loaded in the first region R1 in response to determining that the segment SG corresponding to the write request WREQ has been loaded into the cache in the first region R1.

[0123] In step S440, the memory controller 110 may update the mapping information MP in response to a cache miss. For example, the memory controller 110 may update the mapping information MP stored in the first cache memory 131 in response to a cache miss determined that the segment SG corresponding to the write request WREQ has not yet been loaded into the first region R1. In some embodiments, after updating the mapping information MP, the memory controller 110 may load the segment corresponding to the write request WREQ into the first region R1 as a background operation.

[0124] Figure 9 This is a flowchart illustrating an operation method of a storage device 100 according to some embodiments of the disclosed technology. (Reference) Figure 6 and Figure 9 When an event occurs, the memory controller 110 can release the first region R1.

[0125] In step S510, the memory controller 110 may determine that an event has occurred that disallows or restricts the allocation of a portion of the second cache memory for the mapping information MP. For example, the memory controller 110 may determine that at least one of various types of events has occurred.

[0126] In some embodiments, the event may include at least one of the following: determining that the size of the segment corresponding to the write request WREQ is greater than a threshold size, determining that the write request WREQ is a sequential write operation, or receiving a power reduction request from an external host device; however, these are exemplary and the scope of the disclosed technology is not limited thereto.

[0127] In step S520, the memory controller 110 may deallocate the first region R1. For example, in response to determining that an event (e.g., at least one of the event types described above) has occurred, the memory controller 110 may deallocate the first region R1 allocated for the mapping information MP.

[0128] In step S530, the memory controller 110 may perform a countdown operation. For example, the memory controller 110 may perform a countdown operation in response to determining that an event has occurred. The memory controller 110 may set the first region R1 to unallocable during the countdown operation. Therefore, the memory controller 110 cannot reallocate the first region R1 for the mapping information MP until the countdown operation is complete (e.g., until the count reaches zero).

[0129] In some embodiments, the memory controller 110 can determine the count of the countdown operation based on the event type. For example, when a first type of event occurs, the memory controller 110 can perform a countdown operation of a first count number (e.g., until the count of the countdown operation reaches the first count number), and when a second type of event occurs, it can perform a countdown operation of a second count number (e.g., until the count of the countdown operation reaches the second count number). Therefore, the memory controller 110 can perform countdown operations at different time intervals depending on the event type.

[0130] By setting the first region R1 to be unallocatable at different time intervals based on event type, the memory controller 110 can prevent performance degradation of the storage device 100 due to unnecessary allocation of the first region R1.

[0131] Figure 10 This is a schematic diagram illustrating a second memory device 230 according to some embodiments of the disclosed technology. Reference Figure 10 The second memory device 230 may include a cache memory 231. The cache memory 231 is implemented as follows: Figure 2 The first cache memory 131 and the second cache memory 132, which are single cache memories, are illustrated here. Therefore, redundant descriptions of them are omitted.

[0132] The cache memory 231 can store mapping information MP and segment SG. For example, the cache memory 231 may include a first region R1 to a third region R3 distinguished by write pointers (e.g., a first write pointer WP1 and a second write pointer WP2), and the mapping information MP and segment SG can be stored in the first region R1 to the third region R3.

[0133] In some embodiments, the third region R3 can be used for storage. Figure 2The storage device 100 has a cache area for the mapping information MP of write operations, and the first area R1 and the second area R2 can be used for storage. Figure 2 The storage device 100 has a segmented cache area of ​​SG for read operations.

[0134] In some embodiments, Figure 2 The memory controller 110 can use the first region R1, which is one of the first region R1 and the second region R2, to process Figure 2 The workload of the memory controller 110's write request WREQ. For example, when from... Figure 2 The requests received by host device 11 are mainly write requests (WREQ) or when the workload of read requests is low. Figure 2 The memory controller 110 can allocate some regions (e.g., the first region R1) in the first region R1 and the second region R2 for the mapping information MP, load the segments corresponding to the write request WREQ, and cache these segments.

[0135] In some embodiments, the size of regions within cache memory 231 (e.g., first regions R1 to third regions R3) can be varied as needed. For example, the size of the third region R3 can be increased as more mapping information MP is written to the first write pointer WP1 within cache memory 231. Furthermore, the size of the first region R1 can be increased as more segments SG corresponding to write requests WREQ are written to the second write pointer WP2 within cache memory 231 (and as segments SG stored in the second region R2 are rewritten).

[0136] In some embodiments, when performing internal operations that require a large amount of space in the second cache memory 132 (e.g., garbage collection operations, free block operations, etc.), Figure 2 The storage device 100 can change the size of the first region R1 to the third region R3. For example, the sizes of the second region R2 and the third region R3 can be increased, and the size of the third region R3 can be decreased. The sizes of the first region R1 to the third region R3 are not limited to... Figure 10 The proportions shown in the example are as follows.

[0137] Figure 11 This is a block diagram illustrating a memory card system 300 that applies some embodiments of a storage device according to the disclosed technology. Reference Figure 11 The memory card system 300 may include a memory controller 310, a memory device 320, and a connector 330.

[0138] Memory controller 310 can be coupled to memory device 320. Memory controller 310 can access memory device 320. For example, memory controller 310 can control programming, reading, erasing, and background operations of memory device 320. Memory controller 310 can provide an interface between memory device 320 and a host computer. Memory controller 310 can drive firmware used to control memory device 320. Memory controller 310 can be configured as described above. Figure 1 The memory controller 110 described is configured in the same manner.

[0139] For example, the memory controller 310 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0140] The memory controller 310 can communicate with external devices via connector 330. The memory controller 310 can communicate with external devices (e.g., host devices) based on specific communication protocols. For example, the memory controller 310 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, and / or Non-Volatile Fast Memory (NVMe) protocols. In embodiments, connector 330 may be defined by at least one of the aforementioned communication protocols.

[0141] The memory device 320 can be implemented using various types of non-volatile memory elements, such as electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR non-volatile memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM).

[0142] The memory controller 310 and memory device 320 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 310 and memory device 320 can be integrated into a single semiconductor device to form a memory card such as a PCMCIA card, a compact flash memory (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), a universal flash memory (UFS), etc.

[0143] Figure 12 This is a block diagram illustrating an electronic system 40 according to an embodiment of the disclosed technology. (Reference) Figure 12 The electronic system 40 may include a host device 41 and a storage device 400. The storage device 400 may exchange signals with the host device 41 via a signal connector 401 and may receive power via a power connector 402. The storage device 400 may include a memory controller 410, a plurality of non-volatile memories 421 to 42n, an auxiliary power supply 430, and a buffer memory device 440.

[0144] According to an embodiment, the memory controller 410 can be used as described above. Figure 1 The memory controller 110 is described.

[0145] The memory controller 410 can control multiple non-volatile memories 421 to 42n in response to signals received from the host device 41. In embodiments, the signals can be based on the interface between the host device 41 and the storage device 400. For example, the signals can be defined by at least one of a variety of interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, or Non-Volatile Fast Memory (NVMe) interfaces.

[0146] Auxiliary power supply 430 can be coupled to host device 41 via power connector 402. Auxiliary power supply 430 can be supplied and charged by power from host device 41. When power cannot be stably supplied from host device 41, auxiliary power supply 430 can supply power to storage device 400. In embodiments, auxiliary power supply 430 can be located inside or outside storage device 400. For example, auxiliary power supply 430 can be disposed in the motherboard and provide auxiliary power to storage device 400.

[0147] Buffer memory device 440 can be used as a buffer memory for storage device 400. For example, buffer memory device 440 can temporarily store data received from host device 41 or data received from multiple non-volatile memories 421 to 42n, or it can temporarily store metadata (e.g., mapping information or segments) of non-volatile memories 421 to 42n. Buffer memory device 440 may include volatile memories such as DRAM, SDRAM, DDR SDRAM and LPDDR SDRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM and PRAM.

[0148] According to the disclosed technology, a storage device and its operation method are provided, wherein the storage device allocates a portion of the cache memory for data stored in another cache memory.

[0149] In addition, a storage device and a method of operating the same are provided, which increases the mapping update cycle and provides improved write performance by allocating a portion of another cache memory to workloads that satisfy locality conditions.

[0150] Only examples of embodiments implementing the disclosed technology have been described. Variations can be made to the disclosed embodiments and other examples of embodiments based on the disclosure in this patent document.

Claims

1. A storage device, the storage device comprising: A first memory device, configured to store data; The second memory device includes a first cache memory configured to store mapping information between physical data addresses and logical data addresses of the stored data, and a second cache memory configured to store segments of the mapping information. as well as A memory controller, which communicates with the first memory device and the second memory device, and is configured to update the mapping information in response to a write request received from an external host device. The memory controller is configured to allocate a first region for the mapping information in a region of the second cache memory in response to determining that the size of the workload corresponding to the write request is less than or equal to a first threshold.

2. The storage device according to claim 1, wherein the memory controller is configured to: Determine whether a cache hit or cache miss occurred for the segment corresponding to the write request. In response to the cache hit for the segment, modify the segment, and In response to a cache miss for the segment, the mapping information is updated.

3. The storage device of claim 2, wherein the memory controller is further configured to load the segment into the first region after updating the mapping information.

4. The storage device of claim 3, wherein the memory controller is configured to load the segment into the first region and, in response to receiving a write request corresponding to the segment, invalidate a portion of the mapping information corresponding to the segment.

5. The storage device of claim 1, wherein the memory controller is configured to release the first region in response to determining that the size of the workload corresponding to the write request is greater than the first threshold.

6. The storage device of claim 5, wherein the memory controller is configured to perform a mapping update operation in response to deallocating the first region.

7. The storage device of claim 5, wherein the memory controller is configured to: In response to the deallocation of the first region, a countdown operation is performed, and During the countdown operation, the first region is set to be unallocable.

8. The storage device of claim 7, wherein the memory controller is further configured to: During the countdown operation, information about the size of the workload corresponding to each subsequent write request is stored, and Based on the information, determine whether to set the first region as allocatable before the countdown operation is completed.

9. The storage device of claim 1, wherein the memory controller is further configured to deallocate the first region in response to determining that the write request indicates a sequential write operation.

10. The storage device of claim 1, wherein the write request indicates a random write operation.

11. The storage device of claim 1, wherein the memory controller performs a mapping update operation in response to determining that the remaining space in the first region is less than a second threshold.

12. The storage device of claim 1, wherein the memory controller is configured to: In response to receiving a read request from the external host device, determine whether a cache hit has occurred for the segment corresponding to the read request, and In response to a cache hit for the segment, a read operation is performed on the read data corresponding to the segment.

13. A storage device, the storage device comprising: A first memory device, configured to store data; The second memory device includes a first cache memory configured to store mapping information between physical data addresses and logical data addresses of the stored data, and a second cache memory configured to store segments of the mapping information. as well as A memory controller, which communicates with the first memory device and the second memory device, and is configured to allocate a first region for the mapping information within a region of the second cache memory. The memory controller is configured to: In response to receiving a write request from an external host device, determine whether a cache hit or cache miss occurred for the segment corresponding to the write request. In response to the cache hit for the segment, modify the segment, and In response to a cache miss for the segment, the mapping information is updated.

14. The storage device of claim 13, wherein the memory controller is further configured to: After updating the mapping information, the segment is loaded into the first region, and After the segment is loaded into the first region, in response to receiving the write request corresponding to the segment, a portion of the mapping information corresponding to the segment is invalidated.

15. The storage device of claim 13, wherein the memory controller is configured to: In response to the occurrence of the event, the first region is released and a countdown operation is performed. During the countdown operation, the first region is set to be unallocable.

16. The storage device of claim 15, wherein the type of said event includes at least one of the following: It is determined that the size of the segment is greater than the threshold size; The write request is a sequential write operation; and A power reduction request was received from the external host device.

17. The storage device of claim 15, wherein the memory controller determines the count of the countdown operation based on the type of the event.

18. The storage device of claim 15, wherein the memory controller is configured to: During the countdown operation, information about the size of the workload corresponding to each subsequent write request is stored, and Based on the information, determine whether to set the first region as allocatable before the countdown operation is completed.

19. The storage device of claim 13, wherein the memory controller is configured to: In response to receiving a read request from the external host device, determine whether a cache hit has occurred for the segment corresponding to the read request, and In response to a cache hit for the segment, a read operation is performed on the read data corresponding to the segment.

20. A method of operating a storage device, the method comprising: A first region is allocated within the region of the second cache memory that stores the mapping information in the first cache memory; Receive write requests from external host devices; In response to receiving the write request, determine whether a cache hit has occurred for the segment in the first region corresponding to the write request; In response to a cache hit for the segment, the segment is modified; as well as In response to a cache miss for the segment, the mapping information is updated.

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