Laser chip, method for manufacturing laser chip, and optical module

Abstract

The laser chip, the preparation method of the laser chip and the optical module provided by the present disclosure relate to the technical field of optical elements and facilitate the guarantee of the butt joint quality of the light emitting area and the modulation area. The laser chip comprises a light emitting area and a modulation area, and the modulation area is located at the light emitting end of the light emitting area. The preparation method of the laser chip comprises: dry etching an epitaxial layer of the laser chip to remove the epitaxial layer of the laser chip in the modulation area, and the dry etching stops at a first active layer or a first buffer layer; forming a second dielectric film on the sidewall of the epitaxial layer of the laser chip after the dry etching, and the second dielectric film covers the side surface of an electron blocking layer; etching the first active layer or the first buffer layer exposed by the modulation area by using an etching liquid to remove the first active layer or the first buffer layer, and the second dielectric film blocks the etching liquid from etching the electron blocking layer; removing the second dielectric film; forming a modulation epitaxial layer above the first buffer layer or the substrate in the modulation area; removing a first dielectric film and growing a waveguide layer above the light emitting area and the modulation area.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a laser chip, a method for fabricating the laser chip, and an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] Laser chips are one of the core components of optical modules for generating optical signals. Laser chips can be made from electro-absorption modulated lasers (EMLs), etc. Summary of the Invention

[0004] Some embodiments provide a laser chip, a method for fabricating the laser chip, and an optical module, which facilitates ensuring the docking quality between the light-emitting region and the modulation region.

[0005] Some embodiments provide a method for fabricating a laser chip, the laser chip including a light-emitting region and a modulation region, the modulation region being located at the light-emitting end of the light-emitting region; the method includes: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer and an electron blocking layer from bottom to top. The electron blocking layer is an InAlAs layer. An initial dielectric film is deposited above the epitaxial layer of the laser chip; The initial dielectric film is patterned to form a first dielectric film, which covers the light-emitting area and exposes the modulation area. Based on the first dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer. A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching, and the second dielectric film covers the sidewall of the electron blocking layer. The first active layer or the first buffer layer exposed by the modulation region is etched with an etchant to remove the first active layer or the first buffer layer, and the second dielectric film prevents the etchant from etching the electron blocking layer. Remove the second dielectric film; A modulation epitaxial layer is formed above the first buffer layer or substrate within the modulation region; Remove the first dielectric film and grow a waveguide layer over the light-emitting region and the modulation region.

[0006] One of the above technical solutions has the following advantages or beneficial effects: An electron blocking layer is set above the first active layer. During the operation of the laser chip, electrons move upward from the substrate to the first active layer. If too many electrons are injected into the first active layer, the excess electrons will continue to move upward, resulting in electron waste. The electron blocking layer can block the electrons, keeping them in the first active layer for light emission, thus ensuring the optical power of the light-emitting area of ​​the laser chip. After dry etching and before wet etching, a second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip. The second dielectric film covers the side of the electron blocking layer. During wet etching, the second dielectric film can isolate the etchant and the electron blocking layer. Furthermore, the second dielectric film can prevent the etchant from corroding the electron blocking layer, reducing the risk of the electron blocking layer being eroded and reducing the damage to the interface between the light-emitting area and the modulation area caused by wet etching. This ensures the quality of the interface between the light-emitting area and the modulation area and improves the fabrication yield of the laser chip.

[0007] In some embodiments, a method for fabricating a laser chip is provided, wherein a second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching, the second dielectric film covering the sidewall of the electron blocking layer, including: A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching. The second dielectric film includes a first covering portion and a second covering portion. The first covering portion covers the sidewall of the electron blocking layer, and the second covering portion covers the top of the first active layer or the first buffer layer exposed in the modulation region. Remove the second cover.

[0008] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: The second dielectric film includes a first cover portion and a second cover portion, which facilitates the deposition and formation of the first dielectric film. However, when the second cover portion covers the first active layer or the first buffer layer exposed in the modulation area, it will affect the subsequent processing operations in the corresponding area. By removing the second cover portion and only retaining the first cover portion covering the side of the electron blocking layer, the protective function of the second dielectric film in preventing the corrosive liquid from penetrating the electron blocking layer can be preserved, and the subsequent processing steps in the modulation area will not be hindered.

[0009] In some embodiments, a method for fabricating a laser chip is provided, wherein a second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching, the second dielectric film covering the sidewall of the electron blocking layer, including: During the dry etching process of the epitaxial layer of the laser chip, the first dielectric film is etched, and the material of the first dielectric film is sputtered and deposited on the sidewall of the epitaxial layer of the laser chip to form a second dielectric film, which covers the sidewall of the electron blocking layer.

[0010] Another technical solution mentioned above has the following advantages or beneficial effects: During the dry etching of the epitaxial layer of the laser chip, the sputtering products generated from etching the first dielectric film are simultaneously deposited on the sidewall to form a second dielectric film. This eliminates the need for an additional independent process step to deposit the second dielectric film, simplifying the fabrication process, shortening the fabrication time, and improving fabrication efficiency. Furthermore, the second dielectric film formed in this way directly covers the sidewall of the electron blocking layer. Without additional adjustment of the deposition position, it precisely covers and protects the sidewall of the electron blocking layer, preventing the etching solution from penetrating the electron blocking layer during subsequent etching processes and avoiding corrosion damage to the electron blocking layer.

[0011] In some embodiments, a method for fabricating a laser chip is provided, wherein the thickness of the first dielectric film is 50nm-500nm, the thickness of the second dielectric film is 10nm-100nm, and the thickness of the first dielectric film is greater than twice the thickness of the second dielectric film.

[0012] Another technical solution described above has the following advantages or beneficial effects: controlling the thickness of the first dielectric film within the range of 50nm-500nm and the thickness of the second dielectric film within the range of 10nm-100nm facilitates the formation of first and second dielectric films that meet the thickness requirements. A second dielectric film within the 10nm-100nm range avoids the possibility of etchant penetration and etching of the electron blocking layer due to excessive thickness. This allows the second dielectric film to effectively protect the sidewalls of the electron blocking layer and avoids increasing etching difficulty due to excessive thickness of the second dielectric film. It also facilitates control over the process difficulty of fabrication and avoids material waste, thus controlling the overall fabrication cost of the laser chip. A first dielectric film within the 50nm-500nm range and a thickness more than twice that of the second dielectric film ensures sufficient etching allowance in subsequent process steps, preventing damage to the first dielectric film during removal of the second dielectric film and providing stable mask support for subsequent processes. By rationally controlling the thickness ratio of the two dielectric films, the process window can be optimized while ensuring the protective effect, thereby improving the stability and repeatability of the overall preparation process.

[0013] In some embodiments, a method for fabricating a laser chip is provided, in which a modulation epitaxial layer is formed above the first buffer layer or the substrate within the modulation region when dry etching stops at the first buffer layer, including: A second buffer layer, a second active layer, and a P-InP layer are sequentially formed above the substrate in the modulation region. The bottom of the second active layer is lower than the bottom of the first active layer, and the top of the second active layer is higher than the top of the first active layer.

[0014] Another technical solution mentioned above has the following advantages or beneficial effects: by controlling the bottom of the second active layer to be lower than the bottom of the first active layer and the top of the second active layer to be higher than the top of the first active layer, the overlap between the optical field in the modulation region and the active region can be increased, thereby improving the modulation efficiency of the laser chip. At the same time, the optical field distribution between the gain region and the modulation region can be reasonably allocated, balancing the gain and modulation performance, reducing optical field crosstalk between different functional regions, and helping to improve the overall output performance and working stability of the laser chip.

[0015] In some embodiments, a method for fabricating a laser chip is provided, wherein the material of the first dielectric film is SiON, the material of the second dielectric film is SiO2, and the thickness of the first dielectric film is greater than the thickness of the second dielectric film; removing the second dielectric film includes: The second dielectric film was etched using BOE.

[0016] Another technical solution described above has the following advantages or beneficial effects: By using a combination of a first dielectric film (SiON) and a second dielectric film (SiO2), and leveraging the difference in their corrosion rates in the BOE etching solution, selective removal of the second dielectric film can be achieved, reducing the corrosion of the first dielectric film by BOE. Furthermore, the fact that the thickness of the first dielectric film is greater than that of the second dielectric film ensures that the first dielectric film provides sufficient etching allowance in subsequent process steps, preventing excessive damage to the first dielectric film during the removal of the second dielectric film, and enabling the first dielectric film to provide stable mask support for subsequent processes.

[0017] In some embodiments, a method for fabricating a laser chip is provided in which the thickness of the first dielectric film is greater than the thickness of the first covering portion and the thickness of the first dielectric film is greater than the thickness of the second covering portion. Removing the second cover portion includes: using RIE etching to remove the second cover portion covering the first active layer or the first buffer layer, while retaining the first cover portion.

[0018] Another technical solution described above has the following advantages or beneficial effects: the thickness of the first dielectric film is greater than the thickness of both the first and second covering portions, which facilitates reserving sufficient margin for the first dielectric film. This ensures that the first dielectric film can withstand over-etching when removing the second covering portion, guaranteeing sufficient etching margin in subsequent process steps. It also ensures that removing the second covering portion does not cause excessive damage to the first dielectric film, providing stable mask support for subsequent processes. Furthermore, combined with RIE etching, which allows for precise control of the etching depth, the thickness difference provides sufficient process error space during the removal of the second covering portion, preventing over-etching damage to the remaining first covering portion and ensuring the structural integrity of the first covering portion as a mask.

[0019] In some embodiments, a method for fabricating a laser chip is provided, in which the dry etching stops at the first active layer, the etching solution is sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, or citric acid-hydrogen peroxide-aqueous solution; When dry etching stops at the first buffer layer, the etching solution is a mixture of phosphoric acid and hydrochloric acid, a mixture of phosphoric acid and hydrobromic acid, an aqueous solution of hydrochloric acid, or an aqueous solution of hydrobromic acid.

[0020] Another technical solution mentioned above has the following advantages or beneficial effects: the etching solution can be selected from sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, citric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrochloric acid mixture, phosphoric acid-hydrobromic acid mixture, hydrochloric acid aqueous solution, or hydrobromic acid aqueous solution. By matching the corresponding components of the etching solution to different etching stop positions, different etching depth requirements can be specifically adapted. While ensuring the efficiency of wet etching in removing the target material, it avoids erroneous etching of non-target layer structures. This ensures the cleanliness of the removed target material, meets the precision requirements of the process preparation, and further reduces the risk of damage to the core functional layer of the laser chip. It adapts to the fabrication process requirements of laser chips with different structures, improving process adaptability and fabrication yield. It facilitates ensuring that the etching rate of the first active layer and the first buffer layer is controllable during wet etching, avoids excessive consumption of the second dielectric film while etching the first active layer and the first buffer layer, stably maintains the protective effect of the second dielectric film on the electron blocking layer, reduces the impact of process parameter fluctuations on the fabrication effect, and further ensures the stability of the etching process and the yield of the finished device.

[0021] In some embodiments, a laser chip is provided, wherein the laser chip is prepared by the method provided in the above embodiments.

[0022] Another technical solution described above has the following advantages or beneficial effects: The laser chip prepared by the method provided in the above embodiments ensures that the side of the electron blocking layer is flush with the side of the first active layer, thus facilitating the connection quality between the light-emitting region and the modulation region. During the operation of the laser chip, electrons move upwards from the substrate to the first active layer. If too many electrons are injected into the first active layer, the excess electrons will continue to move upwards, leading to electron waste. The electron blocking layer can block the electrons, keeping them in the first active layer for light emission, thus ensuring the optical power of the light-emitting region of the laser chip.

[0023] In some embodiments, an optical module is provided, including a laser chip, wherein the laser chip is the laser chip provided in the above embodiments, and the laser chip is used to generate optical signals.

[0024] Another technical solution in the above technical solution has the following advantages or beneficial effects: the laser chip in the optical module is the laser chip provided in the above embodiment. Since the side of the electron blocking layer of the laser chip is flush with the side of the first active layer, the docking quality between the light-emitting area and the modulation area is guaranteed. The electron blocking layer can also effectively block excess electrons from overflowing and confine the electrons in the first active layer for light emission, thereby ensuring the output light power of the light-emitting area and thus ensuring the stable light output performance of the entire optical module. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments; Figure 2 This is a partial structural diagram of a switch according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is a partial schematic diagram of a light emitting component according to some embodiments; Figure 6 This is a structural diagram of a laser assembly according to some embodiments; Figure 7 This is a structural diagram of a laser chip according to some embodiments; Figure 8A This is a cross-sectional view of a laser chip according to some embodiments; Figure 8B This is a cross-sectional view of another laser chip according to some embodiments; Figure 9A This is a flowchart of a method for fabricating a laser chip according to some embodiments. Figure 1 ; Figure 9B This is a flowchart of a method for fabricating a laser chip according to some embodiments. Figure 2 ; Figure 10A This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 1 ; Figure 10B This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 2 ; Figure 11A This is a diagram showing the usage state of a second dielectric membrane according to some embodiments; Figure 11B This is a diagram showing the usage state of another second dielectric membrane according to some embodiments; Figure 12A This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 1 ; Figure 12B This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 2 .

[0027] Among them: 100-Switch, 101-Fiber Optic Fiber, 102-PCB Circuit Board, 103-Cage, 104-Heat Discharge Unit, 200-Optical Module, 201-Upper Housing, 2011-Cover Plate, 202-Lower Housing, 2021-Base Plate, 2022-Lower Side Plate, 203-Electrical Interface, 204-Optical Interface, 300-Circuit Board, 301-Gold Finger, 302-Mounting Hole, 303-DSP Chip, 400-Optical Emitting Component, 400a-Laser Assembly, 400b-Carrier, 400c-Laser Chip, 410-Emitting Area, 420-Modulation Area 411-Light-emitting electrode, 421-Modulation electrode, 401-Substrate, 402-First buffer layer, 403-First active layer, 404-Electron blocking layer, 405-Grate layer, 406-Second buffer layer, 407-Second active layer, 408-P-InP layer, 409-Waveguide layer, 412a-Initial dielectric film, 412-First dielectric film, 4010-Second dielectric film, 4011-First cover portion, 4012-Second cover portion, 4013-Third cover portion, 500-Light receiving component, 600-Unlocking component, 700-Light transmission component. Detailed Implementation

[0028] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0029] Unless the context otherwise requires, throughout this specification, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applies to" or "is configured to" implies open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0030] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through this equipment, allowing for long-distance transmission with relatively low power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0031] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0032] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0033] Information processing equipment connected to optical modules can also be referred to as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0034] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. For example... Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0035] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0036] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0037] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0038] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structures related to the switch 100 and the optical module 200 are shown. (For example...) Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0039] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat for the optical module; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0040] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0041] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0042] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0043] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0044] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a housing. The housing may include an upper housing 201 and a lower housing 202. The upper housing 201 covers the lower housing 202, forming two openings, one of which is an electrical interface and the other is an optical interface. In some embodiments, the housing forms an opening that serves as both an electrical interface and an optical interface.

[0045] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which is beneficial for achieving electromagnetic shielding and heat dissipation.

[0046] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of circuit boards 300 and other components into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the aforementioned devices.

[0047] In some embodiments, the direction of the connection between the electrical interface 203 and the optical interface 204 may be consistent with or inconsistent with the length direction of the optical module 200. For example, the electrical interface 203 is located at the end of the optical module 200. Figure 3 (At the right end), the optical interface 204 is also located at the end of the optical module 200. Figure 3 (The left end). Alternatively, the electrical interface 203 is located at the end of the optical module 200, while the optical interface 204 is located on the side of the optical module 200.

[0048] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0049] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0050] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), or power management chips, etc.

[0051] In some embodiments, the circuit board includes a rigid circuit board. Due to its relatively rigid material, the rigid circuit board can also serve a load-bearing function, such as stably supporting the aforementioned electronic components and chips; the rigid circuit board can also be easily inserted into the electrical connector within the cage 103.

[0052] In some embodiments, the circuit board may further include a flexible circuit board. The flexible circuit board can be used independently or in conjunction with a rigid circuit board.

[0053] In some embodiments, the circuit board further includes gold fingers 301 formed on its end surface, the gold fingers 301 being composed of a plurality of independent pins.

[0054] In some embodiments, the gold fingers 301 are disposed on a surface on one side of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some embodiments, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to applications with high pin count requirements.

[0055] In some embodiments, the gold fingers 301 of the circuit board 300 extend from the electrical interface and are inserted into the electrical connector of the switch 100; the circuit board is inserted into the cage 103, and the gold fingers are connected to the electrical connector inside the cage 103. The gold fingers 301 are configured to establish an electrical connection with the switch, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0056] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the switch, or to release the fixed connection between the optical module 200 and the switch.

[0057] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 103 of the switch 100. When the optical module 200 is inserted into the cage 103, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 103; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the switch, so as to release the fixation between the optical module 200 and the switch, thereby allowing the optical module 200 to be pulled out of the cage 103.

[0058] In some embodiments, the optical module includes a light emitting component 400. In some embodiments, the optical module includes a light receiving component 500.

[0059] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0060] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0061] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0062] In some embodiments, the optical module 200 further includes an optical transmission component 700 disposed within the housing. The optical transmission component 700 is used to connect with an external optical fiber 101 (hereinafter referred to as the external optical fiber) to establish an optical connection between the optical emitting component 400, the optical receiving component 500 and the external optical fiber, so that the optical signal generated by the optical emitting component 400 can be coupled to the external optical fiber, and the optical signal input from the external optical fiber can be coupled to the optical receiving component.

[0063] In some embodiments, the optical transmission component 700 includes an optical fiber adapter and an optical fiber, which may also be referred to as an internal optical fiber relative to an external optical fiber. One end of the optical fiber is connected to the optical fiber adapter, and the other end is connected to the optical transmitting component 400 or the optical receiving component 500. Exemplarily, the optical transmission component 700 includes multiple optical fiber adapters and multiple optical fibers. The optical transmitting component 400 can be connected to one or more optical fiber adapters via multiple optical fibers, and the optical receiving component 500 can be connected to multiple optical fiber adapters via multiple optical fibers. Of course, in this embodiment, the structure of the optical fiber adapter is not limited to one type; it can also be an LC connector, where the optical fiber adapter connects to one optical fiber.

[0064] In some embodiments, the optical transmission component 700 may include two optical fiber adapters and multiple optical fibers, each optical fiber adapter being connected to the optical transmitting component 400 and the optical receiving component 500 via the multiple optical fibers.

[0065] In some embodiments, a mounting hole 302 is provided on the circuit board 300, and the light emitting component 400 is assembled and connected to the mounting hole 302. For example, the light emitting component 400 is embedded in the mounting hole 302.

[0066] In some embodiments, the mounting hole 302 can be a through hole, such that the top of the light emitting component 400 is above the mounting hole 302 and the bottom of the light emitting component 400 is below the mounting hole 302.

[0067] In some embodiments, a DSP chip 303 may be disposed on the front side of the circuit board 300; the DSP chip 303 is used to transmit high-frequency signals to the light emitting component 400, etc. The light emitting component 400 receives the high-frequency signals transmitted by the DSP chip 303 to generate light signals. Two opposing surfaces on the circuit board 300 are the main bearing surfaces of the circuit board 300; one of these surfaces is called the front surface of the circuit board 300, facing the cover plate 2011; the other surface is the back surface of the circuit board 300, facing the base plate 2021. The front and back surfaces of the circuit board 300 are opposing surfaces.

[0068] In some embodiments, the light receiving component 500 is disposed on the back side of the circuit board 300. Of course, in this embodiment, the light receiving component 500 is not limited to being disposed on the back side of the circuit board 300, but may also be disposed on the front side of the circuit board 300.

[0069] In some embodiments, the optical transmission component 700 may include a fiber optic adapter and multiple optical fibers. The optical transmitting component 400 can be optically connected to the fiber optic adapter through a portion of the multiple optical fibers, and the optical receiving component 500 can be optically connected to the fiber optic adapter through a portion of the multiple optical fibers.

[0070] Figure 5 This is a partial schematic diagram of a light emitting component according to some embodiments. Figure 5 The present invention illustrates the structure of a light emitting component, but the structure of the light emitting component in this embodiment is not limited to that described above. Figure 5 The structure shown. (As illustrated) Figure 5 As shown, in some embodiments, the optical emitting component 400 includes a laser component 400a, which generates an optical signal. The optical signal output by the laser component 400a can be coupled to an optical fiber after passing through a lens or other device, and then transmitted to an optical fiber adapter via the optical fiber.

[0071] In some embodiments, the light emitting component 400 may include a plurality of laser components 400a arranged side by side. Exemplarily, four, eight, or sixteen laser components 400a may be arranged side by side on the emitting base.

[0072] In some embodiments, a lens, such as a collimating lens or a converging lens, may be provided in the output direction of the laser component 400a to converge the optical signal, so as to facilitate the coupling of the optical signal generated by the laser component 400a into the optical fiber.

[0073] Figure 6 This is a structural diagram of a laser assembly according to some embodiments. Figure 6As shown, in some embodiments, the laser assembly 400a includes a carrier 400b and a laser chip 400c. A circuit pattern is formed on the carrier 400b, and the laser chip 400c is disposed on the carrier 400b. The laser chip 400c can be electrically connected to the circuit pattern on the carrier 400b. The circuit pattern on the carrier 400b can be electrically connected to a circuit board 300, so that the laser chip 400c can be electrically connected to the circuit board 300 through the circuit pattern on the carrier 400b. The laser chip 400c is used to generate optical signals. Matching resistors or matching capacitors, etc., can be disposed on the carrier 400b.

[0074] In some embodiments, the laser chip 400c can be a distributed feedback laser (DFB). DFB uses direct modulation to load the signal, which is simple in structure, low in cost, and low in power consumption.

[0075] In some embodiments, the laser chip 400c can employ an EML. The EML is monolithically integrated with a DFB and an electroabsorption modulator. Its bandwidth is primarily limited by its parasitic parameters, rather than its relaxation resonant frequency; therefore, the bandwidth of an EML can be relatively high. In recent years, with the rapid growth of data volume and the increasing demand for network speed upgrades, EMLs have become increasingly popular.

[0076] Figure 7 This is a structural diagram of a laser chip according to some embodiments. Figure 7 A basic EML structure is shown, with the direction of arrow X indicating the optical field transmission direction. (See diagram.) Figure 7 As shown, in some embodiments, the laser chip 400c includes a light-emitting region 410 and a modulation region 420. One end of the light-emitting region 410 is connected to the modulation region 420, and the other end of the light-emitting region 410 is away from the modulation region 420. The modulation region 420 is located at the light-emitting end of the light-emitting region 410. The light-emitting region 410 generates light without carrying a signal and transmits it to the modulation region 420. The modulation region 420 can modulate the light emitted by the light-emitting region 410 to generate an optical signal.

[0077] A light-emitting electrode 411 may be disposed on the top of the light-emitting region 410. The light-emitting electrode 411 is used to load a bias current, thereby providing charge carriers to the first active layer of the light-emitting region 410, so that the light-emitting region 410 generates light. A modulation electrode 421 is disposed on the top of the modulation region 420. The modulation electrode 421 is used to load a modulation signal, thereby providing a modulation current to the modulation region 420, so that the modulation region 420 modulates the light generated by the light-emitting region 410.

[0078] Figure 8A This is a cross-sectional view of a laser chip according to some embodiments. Figure 8B This is a cross-sectional view of another laser chip according to some embodiments. Figure 8A and Figure 8B The cross-sectional structures of the laser chip along the optical field propagation direction are shown respectively. For example... Figure 8A and Figure 8B As shown, in some embodiments, the laser chip 400c may include a substrate 401. The substrate 401 spans the light-emitting region 410 and the modulation region 420. The substrate 401 may be made of InP material.

[0079] In some embodiments, the laser chip 400c may include a first buffer layer 402 located above the substrate 401. The first buffer layer 402 may be located in the light-emitting region 410, and the length of the first buffer layer 402 is less than the length of the substrate 401; alternatively, the first buffer layer 402 may span the light-emitting region 410 and the modulation region 420, and the length of the first buffer layer 402 is equal to the length of the substrate 401. The first buffer layer 402 may be an N-InP layer.

[0080] In some embodiments, an N-InGaAsP layer may be disposed between the first buffer layer 402 and the substrate 401. The N-InGaAsP layer can be wet-etched for positioning.

[0081] In some embodiments, the laser chip 400c may include a first active layer 403, which is located above the first buffer layer 402. The first active layer 403 may be located in the light-emitting region 410. The first active layer 403 may be made of AlInGaAs or InGaAsP, etc. The first active layer 403 may include a quantum barrier, a quantum well, a quantum barrier, a quantum well, and a quantum barrier stacked sequentially.

[0082] In some embodiments, the laser chip 400c may include an electron blocking layer 404. The electron blocking layer 404 is located in the light-emitting region 410 and is situated above the first active layer 403. The electron blocking layer 404 blocks electrons, causing them to remain in the first active layer 403. During the operation of the laser chip 400c, electrons move upwards from the substrate 401 to the first active layer 403. If too many electrons are injected into the first active layer 403, the excess electrons will continue to move upwards, resulting in electron waste. The electron blocking layer 404 can block the electrons, causing them to remain in the first active layer 403 for light emission. The electron blocking layer 404 may be made of InAlAs. InAlAs is not doped with N-type impurities such as Si.

[0083] In some embodiments, the laser chip 400c may include a grating layer 405. The grating layer 405 is located in the light-emitting region 410 and is situated above the first active layer 403. A P-InGaAsP layer may be formed above the electron blocking layer 404, and the grating layer 405 may be formed using electron beam lithography or holographic lithography of the P-InGaAsP layer.

[0084] In some embodiments, the laser chip 400c may include a second buffer layer 406. The second buffer layer 406 is located in the modulation region 420. The second buffer layer 406 may be disposed above the first buffer layer 402, with its bottom connected to the first buffer layer 402; alternatively, the second buffer layer 406 may be disposed on the side of the first buffer layer 402, with its bottom connected to the substrate 401. The second buffer layer 406 may be an N-InP layer.

[0085] In some embodiments, the laser chip 400c may include a second active layer 407. The second active layer 407 is located in the modulation region 420 and is situated above the second buffer layer 406. The second active layer 407 may be made of AlInGaAs or InGaAsP, etc. The second active layer 407 may include sequentially stacked quantum barriers, quantum wells, quantum barriers, quantum wells, and quantum barriers. Exemplarily, the top of the second active layer 407 is higher than the top of the first active layer 403.

[0086] In some embodiments, the bottom of the second active layer 407 is lower than the bottom of the first active layer 403, and the top of the second active layer 407 is higher than the top of the first active layer 403. This facilitates the coupling of light generated by the first active layer 403 to the second active layer 407 with high coupling efficiency.

[0087] In some embodiments, the laser chip 400c may include a P-InP layer 408. The P-InP layer is located in the modulation region 420 and above the second active layer 407.

[0088] In some embodiments, the laser chip 400c may include a waveguide layer 409. The waveguide layer 409 is located above the P-InP layer 408 and the grating layer 405, and may span the light-emitting region 410 and the modulation region 420. The waveguide layer 409 may be formed using P-InP.

[0089] Based on the laser chip of the above embodiments, this disclosure also provides a method for preparing the laser chip provided in the above embodiments. Figure 9A This is a flowchart of a method for fabricating a laser chip according to some embodiments. Figure 1 , Figure 9B This is a flowchart of a method for fabricating a laser chip according to some embodiments. Figure 2 , Figure 10A This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 1 , Figure 10B This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 2 ; Figure 9A and Figure 9BThe image shows a cross-sectional structure corresponding to each step in the fabrication of a laser chip. Figure 10A and Figure 10B The image shows another cross-sectional structure corresponding to each step in the fabrication of a laser chip. For example... Figures 9A-10B As shown in the embodiment of this disclosure, a method for fabricating a laser chip includes: S100: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer, and an electron blocking layer. The first buffer layer is located below the first active layer, and the first active layer is located below the electron blocking layer.

[0090] In some embodiments, a first buffer layer 402, a first active layer 403, and an electron blocking layer 404 are sequentially grown on a substrate 401. Exemplarily, the first buffer layer 402, the first active layer 403, and the electron blocking layer 404 can be grown on the substrate 401 using metal-organic chemical vapor deposition (MOCVD). A P-InP layer and a P-InGaAsP layer are grown on the electron blocking layer 404, and the P-InGaAsP layer is photolithographically etched to form a grating layer 405.

[0091] In some embodiments, a P-InP layer may be grown above the grating layer 405. This P-InP layer can protect the grating layer 405.

[0092] S200: Deposit an initial dielectric film on top of the epitaxial layer of the laser chip.

[0093] In some embodiments, an initial dielectric film 412a is deposited on the P-InP layer above the grating layer 405, such that the initial dielectric film 412a covers the epitaxial layer of the laser chip. The initial dielectric film 412a may be made of SiO2 or SiN. x It can be formed by deposition of materials such as SiON. The initial dielectric film 412a can protect the epitaxial layer of the laser chip. The thickness of the initial dielectric film 412a can be 50-500 nm, such as 250-500 nm.

[0094] S300: The initial dielectric film is patterned to form a first dielectric film, which covers the light-emitting area and exposes the modulation area.

[0095] In some embodiments, a first dielectric film 412 can be formed by photolithography of the initial dielectric film. The first dielectric film 412 covers the top of the light-emitting region 410 to assist in the formation of the epitaxial layer of the light-emitting region 410. Exemplarily, photoresist is coated on the first dielectric film 412, and after exposure and development, the initial dielectric film 412a is etched using the photoresist as a mask to remove the initial dielectric film 412a above the modulation region 420, while retaining the initial dielectric film 412a above the light-emitting region 410, thus forming the first dielectric film 412.

[0096] S400: Based on the first dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer.

[0097] In some embodiments, using the first dielectric film 412 as a mask, the epitaxial layer of the laser chip within the modulation region 420 is removed by inductively coupled plasma (ICP) etching. Dry etching can be stopped at the first active layer 403 or the first buffer layer 402. During dry etching, a mixed gas such as Cl2, CH4, and H2 can be used as the etching gas. By precisely controlling the gas flow rate, RF power, and cavity pressure, precise control of the etching depth can be achieved, ensuring that the epitaxial layer of the modulation region 420 is completely removed while protecting the epitaxial layer of the light-emitting region 410 from damage. After dry etching is completed, the modulation region 420 exposes the surface of the first active layer 403 or the first buffer layer 402, making the first active layer 403 or the first buffer layer 402 step-shaped.

[0098] S500: The first active layer or first buffer layer exposed by etching the modulation region using an etchant.

[0099] In some embodiments, the etchant used in wet etching can be a selective etchant, such as sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, citric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen acid mixture, phosphoric acid-hydrobromic acid mixture, hydrochloric acid aqueous solution, or hydrobromic acid aqueous solution. Wet etching exposes the first active layer 403 or the first buffer layer 402 in the modulation region to remove the exposed first active layer 403 or the first buffer layer 402, thereby eliminating the stepped structure of the first active layer 403 or the first buffer layer 402. For example, when dry etching stops at the first active layer 403, the etchant is a sulfuric acid-hydrogen peroxide-aqueous solution, a phosphoric acid-hydrogen peroxide-aqueous solution, or a citric acid-hydrogen peroxide-aqueous solution, etc., which facilitates selective etching of the first active layer 403. When dry etching stops at the first buffer layer, the etchant is a phosphoric acid-hydrochloric acid mixture, a phosphoric acid-hydrobromic acid mixture, a hydrochloric acid aqueous solution, or a hydrobromic acid aqueous solution, etc., which facilitates selective etching of the first buffer layer 402. By matching the etchant with the corresponding components for different etching stop positions, different etching depth requirements can be specifically adapted. While ensuring the efficiency of wet etching in removing the target material, it avoids erroneous etching of non-target layer structures. This ensures the cleanliness of the removed target material, meets the precision requirements of the process preparation, and further reduces the risk of damage to the core functional layer of the laser chip. It adapts to the fabrication process requirements of laser chips with different structures, improving process adaptability and fabrication yield.

[0100] In some embodiments, when dry etching stops in the first buffer layer 402, wet etching is used to remove the first buffer layer 402 exposed in the modulation region 420, thereby exposing the surface of the substrate 401 of the modulation region 420. Wet etching has a high selectivity and can precisely remove the first buffer layer 402 exposed in the modulation region 420 without damaging the underlying structure.

[0101] In some embodiments, when dry etching stops in the first active layer 403, wet etching removes the first active layer 403 exposed in the modulation region 420, exposing the surface of the first buffer layer 402 of the modulation region 420. Wet etching has a high selectivity and can precisely remove the first active layer 403 exposed in the modulation region 420 without damaging the underlying first buffer layer 402.

[0102] S600: A modulation epitaxial layer is formed above the first buffer layer or substrate in the modulation region. The modulation epitaxial layer includes a second buffer layer, a second active layer and a P-InP layer. The second buffer layer is located above the first buffer layer or substrate, the second active layer is located above the second buffer layer, and the P-InP layer is located above the second active layer.

[0103] After wet etching removes the first active layer 403 or the first buffer layer 402 exposed within the modulation region 420, the area can be cleaned first, and then a modulation epitaxial layer can be formed above the first buffer layer 402 or the substrate 401. The sides of the modulation epitaxial layer are connected to the sides of the first active layer 403, the electron blocking layer 404, and the grating layer 405 to complete the docking of the light-emitting region 410 and the modulation region 420. A modulation epitaxial layer can be formed above the first buffer layer 402 or the substrate 401 of the modulation region 420 using a selective epitaxial growth process. For example, above the first buffer layer 402 or the substrate 401, a second buffer layer 406, a second active layer 407, and a P-InP layer 408 are sequentially epitaxially grown using MOCVD. The bottom of the second buffer layer 406 is connected to the first buffer layer 402 or the substrate 401, the bottom of the second active layer 407 is connected to the top of the second buffer layer 406, and the bottom of the P-InP layer 408 is connected to the top of the second active layer 407.

[0104] During selective epitaxial growth, parameters such as growth temperature, reaction gas flow rate and pressure can be controlled to ensure that the modulated epitaxial layer 421 grows only on the exposed modulated region 420 surface, while the first dielectric film 412 above the light-emitting region 410 effectively prevents material deposition, thereby achieving regional selective growth.

[0105] S700: Remove the first dielectric film above the light-emitting region and grow a waveguide layer above the light-emitting region and the modulation region.

[0106] After the modulation epitaxial layer is grown, the first dielectric film 412 above the light-emitting region 410 can be removed using a wet or dry etching process, exposing the surfaces of both the light-emitting region 410 and the modulation region 420. Subsequently, a waveguide layer 409 is epitaxially grown above the light-emitting region 410 and the modulation region 420. The waveguide layer 409 can cover the grating layer 405 and the P-InP layer 408. The waveguide layer 409 can be a P-InP layer.

[0107] When removing the first active layer 403 or the first buffer layer 402 exposed in the modulation region 420 by wet etching, the etchant will corrode the first active layer 403 or the first buffer layer 402, as well as the sides of the electron blocking layer 404 and the grating layer 405. The etchant has a lower etching rate on the grating layer 405, resulting in less lateral damage. However, the etchant has a relatively high etching rate on the electron blocking layer 404, which can easily lead to drilling and inward shrinkage of the electron blocking layer 404's edges, forming a stepped sidewall structure. This will worsen the mating morphology between the light-emitting region 410 and the modulation region 420, thereby degrading the performance of the laser chip 400c. Therefore, an etchant formulation with a lower etching rate on the electron blocking layer 404 is usually selected during wet etching. However, etchant formulations with a lower etching rate on the electron blocking layer 404 are relatively complex, take a long time to prepare, and are highly sensitive to process windows, which is not conducive to large-scale mass production.

[0108] To address the aforementioned issues, the laser chip fabrication method provided in this disclosure, prior to the exposure of the first active layer or first buffer layer in the wet etching modulation region, further includes: forming a second dielectric film on the sidewall of the laser chip epitaxial layer after dry etching, the second dielectric film covering the sidewall of the electron blocking layer; and removing the second dielectric film before forming the modulation epitaxial layer above the first buffer layer or substrate in the modulation region. The material of the second dielectric film can be SiO2 or SiN. x Or one or more of SiON. Before forming the modulation region, the second dielectric film is removed to minimize the impact of the residual second dielectric film on the quality of the modulation region and the light-emitting region. The second dielectric film can be selectively removed using a buffered oxide etch (BOE) or HF etch (DHF dilute hydrofluoric acid). By covering the side of the electron blocking layer 404 with the second dielectric film, when the first active layer 403 or the first buffer layer 402 exposed in the modulation region 420 is removed by wet etching, the second dielectric film can isolate the electron blocking layer 404 from the etchant, thereby preventing the etchant from penetrating the electron blocking layer 404.

[0109] In some embodiments, the epitaxial wafer after wet etching of the first active layer or the first buffer layer is first cleaned, then immersed in BOE or HF for a preset time, and then taken out and thoroughly cleaned to remove the second dielectric film.

[0110] In some embodiments, the material of the second dielectric film can be the same as that of the first dielectric film 412. For example, the material of the first dielectric film 412 is SiO2, and the material of the second dielectric film is SiO2; or, the material of the first dielectric film 412 is SiON, and the material of the second dielectric film is SiON.

[0111] In some embodiments, the material of the second dielectric film may be different from the material of the first dielectric film 412. For example, the material of the first dielectric film 412 may be SiO2, and the material of the second dielectric film may be SiON; or, the material of the first dielectric film 412 may be SiON, and the material of the second dielectric film may be SiO2.

[0112] Figure 11A This is a usage diagram of a second dielectric membrane according to some embodiments. Figure 11B This is a usage diagram of another second dielectric film according to some embodiments. Figure 11A and Figure 11B As shown, the second dielectric film 4010 covers the sidewall of the epitaxial layer of the laser chip, allowing it to cover the sidewall of the electron blocking layer 404. Exemplarily, the second dielectric film 4010 can extend from the sidewall of the grating layer 405 to the sidewall of the first active layer 403, or from the sidewall of the grating layer 405 to the sidewall of the first buffer layer 402, so that the second dielectric film 4010 can completely cover the sidewall of the electron blocking layer 404. After wet etching removes the first active layer 403 or the first buffer layer 402 in the modulation region 420, the second dielectric film 4010 is removed before the modulation epitaxial layer is formed in the modulation region 420, in order to reduce the adverse effects of the second dielectric film 4010 on the subsequent growth of the modulation epitaxial layer.

[0113] In some embodiments, when dry etching the epitaxial layer of the laser chip, the first dielectric film 412 is etched, so that the material etched from the first dielectric film 412 is sputtered onto the sidewall of the epitaxial layer of the laser chip to form a second dielectric film 4010, the second dielectric film 4010 covering the sidewall of the electron blocking layer 404.

[0114] In some embodiments, after dry etching the epitaxial layer of the laser chip, a second dielectric film 4010 is deposited on the surface of the epitaxial wafer. The second dielectric film 4010 is deposited on the sidewall of the epitaxial layer of the laser chip, so that the second dielectric film 4010 can cover the sidewall of the electron blocking layer 404.

[0115] In some embodiments, the thickness of the first dielectric film 412 is 50nm-500nm, and the thickness of the second dielectric film 4010 is 10nm-100nm, with the thickness of the first dielectric film 412 being greater than the thickness of the second dielectric film 4010. The thickness of the first dielectric film 412 can be greater than twice the thickness of the second dielectric film 4010, for example, five times the thickness of the second dielectric film 4010. Because the thickness of the first dielectric film 412 is greater than the thickness of the second dielectric film 4010, when removing the second dielectric film 4010, the etching time can be controlled to remove it completely, while the first dielectric film 412 retains sufficient thickness above the epitaxial layer of the laser chip without hindering its normal use. For example, the thickness of the first dielectric film 412 is 250nm-500nm, and the thickness of the second dielectric film 4010 is 50nm-100nm.

[0116] In some embodiments, a second dielectric film 4010 is deposited on the surface of the epitaxial wafer. The second dielectric film 4010 is deposited not only on the sidewalls of the laser chip epitaxial layer but also on the surface of the first active layer 403 or the first buffer layer 402 exposed in the modulation region 420. When the second dielectric film 4010 is deposited on the surface of the first active layer 403 or the first buffer layer 402, it needs to be removed before wet etching of the first active layer 403 or the first buffer layer 402 exposed in the modulation region. Exemplarily, conventional reactive ion etching (RIE) can remove the second dielectric film 4010 on the surface of the first active layer 403 or the first buffer layer 402 while retaining the second dielectric film 4010 on the sidewalls of the laser chip epitaxial layer.

[0117] Figure 12A This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 1 , Figure 12B This is a flowchart of another method for fabricating a laser chip according to some embodiments. Figure 2 , Figure 12A and Figure 12B The cross-sectional structures corresponding to each step in another laser chip fabrication process are shown. For example... Figure 12A and Figure 12B As shown, in some embodiments, a method for fabricating a laser chip provided by this disclosure includes: S01: A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching.

[0118] In some embodiments, the material of the second dielectric film 4010 is SiON, and the thickness is 10nm-100nm. The material of the second dielectric film 4010 may be different from that of the first dielectric film 412. The thickness of the first dielectric film 412 is greater than the thickness of the second dielectric film 4010.

[0119] In some embodiments, after dry etching the epitaxial layer of the laser chip to the first active layer 403 or the first buffer layer 402 of the modulation region 420, a second dielectric film 4010 is deposited on the surface of the post-etched epitaxial layer. The second dielectric film 4010 may include a first cover portion 4011. The thickness of the first cover portion 4011 is less than the thickness of the first dielectric film 412. Dry etching the epitaxial layer of the laser chip to the first active layer 403 or the first buffer layer 402 of the modulation region 420 may form a sidewall on one side of the light-emitting region 410 of the laser chip epitaxial layer. The first cover portion 4011 may be attached to this sidewall, allowing it to cover the side of the electron blocking layer 404. The first cover portion 4011 can prevent the etchant from penetrating the electron blocking layer 404. For example, the first cover portion 4011 may extend from the side of the first dielectric film 412 to the side of the first active layer 403; or, the first cover portion 4011 may extend from the side of the first dielectric film 412 to the side of the first buffer layer 402.

[0120] In some embodiments, the second dielectric film 4010 may include a second cover portion 4012. The second cover portion 4012 may cover the top surface of the first active layer 403 within the modulation region 420, with its bottom connected to the first active layer 403; alternatively, the second cover portion 4012 may cover the top surface of the first buffer layer 402 within the modulation region 420, with its bottom connected to the first buffer layer 402. The thickness of the second cover portion 4012 is less than the thickness of the first dielectric film 412.

[0121] In some embodiments, the second dielectric film 4010 may include a third cover portion 4013. The third cover portion 4013 may cover the top of the first dielectric film 412. Depositing the third cover portion 4013 on the top of the first dielectric film 412 may increase the thickness of the dielectric film on the top of the epitaxial wafer.

[0122] S02: Remove the second dielectric film on the top surface of the first active layer or the first buffer layer in the modulation region.

[0123] In some embodiments, before wet etching, the second cover portion 4012 on the top surface of the first active layer 403 or the first buffer layer 402 is removed to expose the first active layer 403 or the first buffer layer 402 within the modulation region 420, while retaining the first cover portion 4011 on the side of the laser chip epitaxial layer. Exemplarily, RIE can be used to selectively remove the second cover portion 4012 while retaining the first cover portion 4011. When removing the second cover portion 4012 via RIE, the dielectric film on top of the laser chip epitaxial layer will also be consumed. The third cover portion 4013 will be consumed first, and if the third cover portion 4013 is consumed, the first dielectric film 412 will continue to be consumed. Therefore, the thickness of the first dielectric film 412 is greater than the thickness of the second cover portion 4012 to ensure that the first dielectric film 412 retains sufficient thickness during the removal of the second cover portion 4012 and subsequently the removal of the first cover portion 4011, effectively protecting the top structure of the light-emitting region 410 in subsequent processes. For example, the thickness of the first dielectric film 412 can be set to 3 to 5 times the thickness of the second cover portion 4012.

[0124] S510: Use an etchant to etch the first active layer or the first buffer layer outside the light-emitting area.

[0125] In some embodiments, when dry etching reaches the first active layer 403, a first etchant is used to etch the first active layer 403 exposed within the modulation region 420 and the first active layer 403 covered by the first cover portion 4011, until the first active layer 403 within the modulation region 420 is completely removed, and the first buffer layer 402 within the modulation region 420 is exposed. The etching rate of the first etchant on the first active layer 403 is much greater than the etching rate on the first buffer layer 402, thereby reducing the etching of the first buffer layer 402 by the etchant. This effectively protects the surface flatness of the first buffer layer 402 while removing the first active layer 403, providing good interface conditions for subsequent epitaxial growth. The first etchant can be sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, or citric acid-hydrogen peroxide-aqueous solution, etc.

[0126] In some embodiments, the etching time of the first etchant is controlled to effectively reduce excessive etching of the first active layer 403 by the first etchant, and to prevent the first etchant from penetrating into the first active layer 403 within the light-emitting region 410. For example, the etching time can be set to 30-50 seconds.

[0127] In some embodiments, the thickness of the first cover portion 4011 matches the thickness of the first active layer 403 within the modulation region 420, that is, the thickness of the first cover portion 4011 matches the thickness of the remaining first active layer 403 within the modulation region 420 after dry etching, to ensure that during wet etching, the first cover portion 4011 can effectively block the first etchant from etching the first active layer 403 within the light-emitting region 410. For example, the thickness of the first cover portion 4011 can be set to 0.8 to 1.5 times the thickness of the first active layer 403 within the modulation region 420.

[0128] In some embodiments, when dry etching reaches the first buffer layer 402, a second etchant is used to etch the first buffer layer 402 exposed within the modulation region 420 and the first buffer layer 402 covered by the first cover portion 4011, until the first buffer layer 402 within the modulation region 420 is completely removed, exposing the substrate 401 within the modulation region 420. The etching rate of the second etchant on the first buffer layer 402 is much greater than the etching rate on the substrate 401, so as to effectively protect the surface quality of the substrate 401 while removing the first buffer layer 402, avoiding defects on the surface of the substrate 401 due to over-etching, and providing good interface conditions for subsequent epitaxial growth. The second etchant can be a phosphoric acid-hydrochloric acid mixture, a phosphoric acid-hydrobromic acid mixture, an aqueous hydrochloric acid solution, or an aqueous hydrobromic acid solution, etc.

[0129] In some embodiments, the etching time of the second etchant is controlled to effectively reduce excessive etching of the first buffer layer 402 by the second etchant, such as the second etchant penetrating into the first buffer layer 402 within the light-emitting region 410. For example, the etching time can be set to 30-50 seconds.

[0130] In some embodiments, the thickness of the first cover portion 4011 matches the thickness of the first buffer layer 402 within the modulation region 420, that is, the thickness of the first cover portion 4011 matches the thickness of the remaining first buffer layer 402 within the modulation region 420 after dry etching, to ensure that during wet etching, the first cover portion 4011 can effectively block the second etchant from etching the first buffer layer 402 within the light-emitting region 410. For example, the thickness of the first cover portion 4011 can be set to 0.8 to 1.5 times the thickness of the first buffer layer 402 within the modulation region 420.

[0131] S03: Remove the first covering portion.

[0132] Before growing the modulation epitaxial layer in the modulation region, the second dielectric film 4010 on the sidewall of the laser chip epitaxial layer is removed. After the second dielectric film 4010 on the sidewall of the laser chip epitaxial layer is completely removed, the modulation epitaxial layer is then grown inside and outside the modulation region 420. In some embodiments, the second dielectric film 4010 is etched using BOE or HF to completely remove the second dielectric film 4010 on the sidewall of the laser chip epitaxial layer. For example, the second dielectric film 4010 is etched using BOE or HF to completely remove the first covering portion 4011.

[0133] In some embodiments, the etching time of BOE or HF is controlled to reduce excessive etching of the first dielectric film 412 by BOE or HF while completely removing the first cover portion 4011, so as to retain a sufficiently thick first dielectric film 412 on top of the epitaxial layer of the laser chip, thereby effectively protecting the epitaxial layer structure within the light-emitting region 410 in subsequent processes. Exemplarily, the etching time of BOE or HF can be set to 30-60 seconds.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser chip, characterized in that, The laser chip includes a light-emitting region and a modulation region, wherein the modulation region is located at the light-emitting end of the light-emitting region; the method includes: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer and an electron blocking layer from bottom to top. The electron blocking layer is an InAlAs layer. An initial dielectric film is deposited above the epitaxial layer of the laser chip; The initial dielectric film is patterned to form a first dielectric film, which covers the light-emitting area and exposes the modulation area. Based on the first dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer. A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching, and the second dielectric film covers the sidewall of the electron blocking layer. The first active layer or the first buffer layer exposed by the modulation region is etched with an etchant to remove the first active layer or the first buffer layer, and the second dielectric film prevents the etchant from etching the electron blocking layer. Remove the second dielectric film; A modulation epitaxial layer is formed above the first buffer layer or substrate within the modulation region; Remove the first dielectric film and grow a waveguide layer over the light-emitting region and the modulation region.

2. The method according to claim 1, characterized in that, A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching. The second dielectric film covers the sidewall of the electron blocking layer, including: A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching. The second dielectric film includes a first covering portion and a second covering portion. The first covering portion covers the sidewall of the electron blocking layer, and the second covering portion covers the top of the first active layer or the first buffer layer exposed in the modulation region. Remove the second cover.

3. The method according to claim 1, characterized in that, A second dielectric film is formed on the sidewall of the epitaxial layer of the laser chip after dry etching. The second dielectric film covers the sidewall of the electron blocking layer, including: During the dry etching process of the epitaxial layer of the laser chip, the first dielectric film is etched, and the material of the first dielectric film is sputtered and deposited on the sidewall of the epitaxial layer of the laser chip to form a second dielectric film, which covers the sidewall of the electron blocking layer.

4. The method according to claim 1 or 2, characterized in that, The thickness of the first dielectric film is 50nm-500nm, the thickness of the second dielectric film is 10nm-100nm, and the thickness of the first dielectric film is more than twice the thickness of the second dielectric film.

5. The method according to claim 1, characterized in that, When dry etching stops at the first buffer layer, a modulation epitaxial layer is formed above the first buffer layer or the substrate within the modulation region, including: A second buffer layer, a second active layer, and a P-InP layer are sequentially formed above the substrate in the modulation region. The bottom of the second active layer is lower than the bottom of the first active layer, and the top of the second active layer is higher than the top of the first active layer.

6. The method according to claim 1 or 2, characterized in that, The first dielectric film is made of SiON, the second dielectric film is made of SiO2, and the thickness of the first dielectric film is greater than the thickness of the second dielectric film. Removing the second dielectric film includes: The second dielectric film was etched using BOE.

7. The method according to claim 2, characterized in that, The thickness of the first dielectric film is greater than the thickness of the first covering portion and the thickness of the first dielectric film is greater than the thickness of the second covering portion; Removing the second cover portion includes: using RIE etching to remove the second cover portion covering the first active layer or the first buffer layer, while retaining the first cover portion.

8. The method according to claim 1, characterized in that, When dry etching stops at the first active layer, the etching solution is sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, or citric acid-hydrogen peroxide-aqueous solution; When dry etching stops at the first buffer layer, the etching solution is a mixture of phosphoric acid and hydrochloric acid, a mixture of phosphoric acid and hydrobromic acid, an aqueous solution of hydrochloric acid, or an aqueous solution of hydrobromic acid.

9. A laser chip, characterized in that, The laser chip is a laser chip prepared by the method described in any one of claims 1-8.

10. An optical module, characterized in that, It includes a laser chip, wherein the laser chip is the laser chip described in claim 9 above, and the laser chip is used to generate optical signals.

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