Laser chip, method for manufacturing laser chip, and optical module

Abstract

The laser chip, the preparation method of the laser chip and the optical module provided by the present disclosure relate to the technical field of optical elements and meet the demand of the optical module for the laser. The laser chip comprises an N-type InP layer, an active region, a grating layer and a waveguide region. The waveguide region comprises a first wide P-type InP layer, a narrow P-type InP layer, a first N-type InP layer, a second N-type InP layer and a second wide P-type InP layer. The narrow P-type InP layer, the first N-type InP layer and the second N-type InP layer are located in the same layer. The first wide P-type InP layer, the narrow P-type InP layer and the second wide P-type InP layer are sequentially arranged from bottom to top. P-type carriers are sequentially injected downward to the active region through the second wide P-type InP layer, the narrow P-type InP layer and the first wide P-type InP layer, the fundamental mode obtains high gain, the high-order mode cannot obtain sufficient gain, and the chip is single-mode lasing. The second wide P-type InP layer has a large width and thickness, and the thermal resistance and series resistance are reduced.

Description

Technical Field

[0001] This disclosure relates to the field of optical communication technology, and in particular to a laser chip, a method for fabricating the laser chip, and an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] Some optical modules include a light source and an optical modulation chip. The light generated by the light source is transmitted to the optical modulation chip, which modulates the light to generate an optical signal. The light source is usually a laser chip. In laser chips with a ridge waveguide structure, the ridge waveguide width determines both the electrical injection range and the limitation of the transverse optical field. To maintain a stable transverse fundamental mode output, the ridge waveguide width must be limited to an extremely narrow range. However, an extremely narrow ridge width results in extremely high series resistance and thermal resistance in the chip. Summary of the Invention

[0004] In some embodiments, a laser chip, a method for fabricating the laser chip, and an optical module are provided to achieve single-mode lasing of the chip while increasing the ridge waveguide width.

[0005] In some embodiments, a laser chip is provided, comprising: N-type InP layer; The active region is located above the N-type InP layer and is configured to receive N-type carriers output from the N-type InP layer. A grating layer is disposed above the active region; A waveguide region, disposed above the grating layer and protruding upward relative to the grating layer, includes: A first wide P-type InP layer is connected to the upper surface of the grating layer, and the width of the first wide P-type InP layer is smaller than the width of the grating layer; the first wide P-type InP layer includes: First connection area; The second connection region is connected to the first connection region and aligned with the center region of the active region; The third connection area is connected to the second connection area; A narrow P-type InP layer is located above the second connection region, and the width of the narrow P-type InP layer is smaller than the width of the first wide P-type InP layer. The first N-type InP layer is located on one side of the narrow P-type InP layer and above the first connection region, so that the first N-type InP layer and the first connection region form a first reverse bias PN junction; The second N-type InP layer is located on the other side of the narrow P-type InP layer and above the third connection region, so that the second N-type InP layer and the third connection region form a second reverse bias PN junction; A second wide P-type InP layer is located above the narrow P-type InP layer. The width of the second wide P-type InP layer is greater than the width of the narrow P-type InP layer, and the thickness of the second wide P-type InP layer is greater than the thickness of the first wide P-type InP layer. The second wide P-type InP layer is configured to output P-type carriers to the active region so that the P-type carriers recombine with the N-type carriers in the active region to generate photons. The P-type carriers are injected downward into the active region via the second wide P-type InP layer, the narrow P-type InP layer, and the second connection region.

[0006] One of the above technical solutions has the following advantages or beneficial effects: The laser chip includes an N-type InP layer, an active region, a grating layer, and a waveguide region stacked from bottom to top. The waveguide region includes a first wide P-type InP layer, a narrow P-type InP layer, a first N-type InP layer, a second N-type InP layer, and a second wide P-type InP layer. The narrow P-type InP layer, the first N-type InP layer, and the second N-type InP layer are located on the same layer, with the first N-type InP layer and the second N-type InP layer located on opposite sides of the narrow P-type InP layer. The first wide P-type InP layer, the narrow P-type InP layer, and the second wide P-type InP layer are stacked sequentially from bottom to top. The first wide P-type InP layer includes a first connection region, a second connection region, and a third connection region. The second connection region is located between the first and third connection regions and is aligned with the center region of the active region. The narrow P-type InP layer is located above the second connection region. On one hand, the first N-type InP layer is located above the first connection region, and the second N-type InP layer is located above the third connection region. A built-in electric field is established between the first N-type InP layer and the first connection region, pointing from the N-type region to the P-type region. The same built-in electric field is established between the second N-type InP layer and the third connection region. When the laser chip is working normally, the P-region is connected to a positive voltage, and the N-region is connected to a negative voltage. At this time, the direction of the applied electric field is consistent with the direction of the built-in electric field of the PN junction, making the PN junction in a reverse bias state. Thus, a first reverse bias PN junction is formed between the first N-type InP layer and the first connection region, and a second reverse bias PN junction is formed between the second N-type InP layer and the third connection region. The reverse bias PN junction has extremely high impedance, which can effectively block the current from passing through. Therefore, the current is laterally squeezed to the narrow P-type InP layer and injected downwards. Then, the P-type carriers output from the second wide P-type InP layer are sequentially injected vertically downwards into the active region through the second wide P-type InP layer, the narrow P-type InP layer, and the second connection region. The second connection region is aligned with the center region of the active region. The narrow P-type InP layer is located above the second connection region. Therefore, the narrow P-type InP layer and the fundamental mode optical field are vertically coincident. This restricts the gain region to the fundamental mode optical field region of the active region, resulting in high gain for the fundamental mode, which easily reaches the threshold and lases, ensuring single-mode lasing of the laser chip. The higher-order mode optical field is vertically coincident with the first N-type InP layer and the second N-type InP layer. Current cannot be injected into the higher-order mode optical field through these layers, resulting in insufficient gain and severe suppression, thus preventing lasing and ensuring single-mode lasing of the laser chip. On the other hand, the second wide P-type InP layer has a larger width and thickness, creating a weak equivalent refractive index difference between the waveguide region and its sides. This increases the volume of the fundamental mode and decreases the optical power density. Furthermore, the wide ridge structure significantly increases the heat dissipation area and reduces thermal resistance; the wide ridge also reduces series resistance, thereby enabling high-power laser output.Based on the above, the embodiments of this disclosure can achieve decoupling of wide ridge light guiding and narrow window power limiting. The wide ridge, together with the narrow P-type InP layer, accurately pumps the fundamental mode, thereby achieving high-power single-mode light output.

[0007] In some embodiments, the thickness of the narrow P-type InP layer is less than the thickness of the second wide P-type InP layer.

[0008] One of the above technical solutions has the following advantages or beneficial effects: the narrow P-type InP layer is thinner, thus having a higher lateral resistance, preventing the current from spreading laterally within the narrow P-type InP layer, and forcing the current to be injected downwards with hysteresis into the second connection region.

[0009] In some embodiments, the narrow P-type InP layer is aligned with the center of the first wide P-type InP layer and the second wide P-type InP layer, respectively.

[0010] One of the above technical solutions has the following advantages or beneficial effects: the narrow P-type InP layer is aligned with the center of the first wide P-type InP layer and the second wide P-type InP layer respectively, and the center of the first wide P-type InP layer is aligned with the center region of the active region, thereby ensuring that the current injected through the narrow P-type InP layer is injected into the center region of the active region, ensuring that the fundamental mode obtains sufficient gain.

[0011] In some embodiments, the first N-type InP layer and the second N-type InP layer are symmetrically distributed relative to the narrow P-type InP layer.

[0012] One of the above technical solutions has the following advantages or beneficial effects: the first N-type InP layer and the second N-type InP layer are symmetrically arranged, so that the current compression force applied from both sides to the central narrow P-type InP layer is the same. The fundamental mode optical field is stimulated amplified under a symmetrical gain distribution, and the peak position, beam waist width, and equiphase surface of its mode spot will not be laterally shifted or tilted, thereby ensuring the pointing stability and circular symmetry of the laser chip output beam.

[0013] In some embodiments, a method for fabricating a laser chip is provided, comprising: An active region and a grating layer are epitaxially grown upward along the surface of the N-type InP layer, and periodic grooves are etched on the surface of the grating layer. A first wide P-type InP layer is epitaxially grown upward along the surface of the grating layer. The first wide P-type InP layer buries the periodic grooves of the grating layer and has a first growth thickness. An N-type InP inversion layer is epitaxially grown upward along the surface of the first wide P-type InP layer; A developing region is formed by photolithography along the surface of the N-type InP inversion layer, and the developing region is etched to expose the upper surface of the first P-type InP layer. The unetched areas are then formed into the first N-type InP layer and the second N-type InP layer, respectively. Along the surfaces of the first N-type InP layer and the second N-type InP layer, and the bottom surface of the etched area, a P-type InP material is epitaxially grown upwards. The P-type InP material fills the etched area to form a narrow P-type InP layer. The P-type InP material covers the surfaces of the first N-type InP layer, the second N-type InP layer, and the narrow P-type InP layer to form a second wide P-type InP layer. The second wide P-type InP layer has a second growth thickness, which is greater than the first growth thickness. A mask is photolithographically formed on the surface of the second wide P-type InP layer in the direction perpendicular to the narrow P-type InP layer, and the two sides of the mask are etched to expose the surface of the grating layer to form a waveguide region, wherein the width of the narrow P-type InP layer is smaller than the width of the second wide P-type InP layer.

[0014] One of the above technical solutions has the following advantages or beneficial effects: An active region and a grating layer are epitaxially grown upwards along the surface of an N-type InP layer, and periodic grooves are etched on the surface of the grating layer to form a Bragg grating for selecting a specific wavelength. Then, a first wide P-type InP layer is epitaxially grown upwards along the surface of the grating layer. This first wide P-type InP layer completely covers the periodic grooves on the surface of the grating layer, ensuring that the periodic grooves are fully filled with P-type InP material. The upper surface of the first wide P-type InP layer exceeds the upper surface of the grating layer by a certain thickness to provide a flat surface for subsequent epitaxial growth; this excess thickness also participates in the formation of the subsequent reverse-biased PN junction. Then, an N-type InP inversion layer is epitaxially grown upwards along the surface of the first P-type InP layer. A developing region is formed along the surface of the N-type InP inversion layer by photolithography, and the developing region is etched until the upper surface of the first P-type InP layer is exposed. The unetched areas then form the first N-type InP layer and the second N-type InP layer, respectively. P-type InP material is epitaxially grown upwards along the surfaces of the first and second N-type InP layers, as well as the bottom surface of the etched area. The P-type InP material fills the etched area to form a narrow P-type InP layer. This P-type InP material covers the surfaces of the first, second, and narrow P-type InP layers, thus forming a second wide P-type InP layer. The second wide P-type InP layer has a second growth thickness, greater than the first growth thickness. This larger width and thickness of the second wide P-type InP layer creates a weak equivalent refractive index difference between the waveguide region and its two sides, increasing the fundamental mode volume and decreasing the optical power density. Furthermore, the wide ridge structure significantly increases the heat dissipation area, reducing thermal resistance, and also reduces series resistance, thereby enabling high-power laser output. A mask is photolithographically formed on the surface of the second wide P-type InP layer in the direction perpendicular to the narrow P-type InP layer. The two sides of the mask are etched to expose the surface of the grating layer to form a waveguide region. The width of the narrow P-type InP layer is smaller than the width of the second wide P-type InP layer to achieve narrow window power limiting. The current flowing through the narrow P-type InP layer is injected into the central region of the active region, so the fundamental mode gets a high gain, while the higher-order modes cannot get sufficient gain, thus ensuring that the laser chip emits light in a single fundamental mode.

[0015] In some embodiments, the epitaxial growth of the active region and grating layer upward along the surface of the N-type InP layer includes: The following layers are grown sequentially from bottom to top along the surface of the N-type InP substrate: an N-InP buffer layer, a lower confinement layer, an active region containing multiple quantum wells, an upper confinement layer, an InP spacer layer, and a grating layer.

[0016] One of the above technical solutions has the following advantages or beneficial effects: The following layers are grown sequentially from bottom to top along the surface of the N-type InP substrate: an N-InP buffer layer, a lower confinement layer, an active region containing multiple quantum wells, an upper confinement layer, an InP spacer layer, and a grating layer. The lower and upper confinement layers are used to confine the optical field and charge carriers within the multiple quantum well region, thereby improving gain efficiency.

[0017] In some embodiments, the narrow P-type InP layer is aligned with the center of the active region.

[0018] One of the above technical solutions has the following advantages or beneficial effects: when the narrow P-type InP layer is aligned with the center of the active region, the narrow P-type InP layer and the fundamental mode optical field position coincide longitudinally, and the gain region is limited to the fundamental mode optical field region of the active region. The fundamental mode obtains a high gain, which can easily reach the threshold and lasing, so as to ensure single-mode lasing of the laser chip.

[0019] In some embodiments, the following are included: A P-plane ohmic contact layer and a P-plane metal electrode layer are grown along the surface of the waveguide region. The bottom surface of the N-type InP layer is masked and polished to reduce the thickness of the N-type InP layer; and an N-plane metal electrode layer is deposited on the bottom surface of the thinned N-type InP layer.

[0020] One of the above technical solutions has the following advantages or beneficial effects: The fabrication method further includes: growing a P-plane ohmic contact layer and a P-plane metal electrode layer along the surface of the waveguide region to achieve electrical connection in the P-type region. The bottom surface of the N-type InP layer is masked and polished to reduce the thickness of the N-type InP layer; and an N-plane metal electrode layer is deposited on the bottom surface of the thinned N-type InP layer.

[0021] In some embodiments, an optical module is provided, including a laser chip, any of the laser chips described above, or the laser chip is a laser chip prepared by any of the laser chip preparation methods described above.

[0022] One of the above technical solutions has the following advantages or beneficial effects: integrating the laser chip or the laser chip prepared by the above method into the optical module, the laser chip has both single-mode and high-power characteristics. The single-mode characteristics ensure the signal transmission quality and integrity, while the high-power characteristics meet the stringent requirements of high-speed optical communication systems for light source power. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments; Figure 2 This is a partial structural diagram of a switch according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is an internal structural diagram of an optical module according to some embodiments; Figure 6 This is a three-dimensional structural diagram of a laser chip according to some embodiments; Figure 7 This is a cross-sectional structural diagram of a laser chip according to some embodiments; Figure 8 for Figure 7 A partial structural diagram; Figure 9 This is a schematic diagram illustrating the working principle of a laser chip according to some embodiments. Figure 1 ; Figure 10 This is a schematic diagram illustrating the working principle of a laser chip according to some embodiments. Figure 2 ; Figure 11 This is a flowchart of a method for fabricating a laser chip according to some embodiments; Figure 12 This is a structural diagram of a laser chip fabrication according to some embodiments; Figure 13 This is a comparative spectrum diagram of a laser chip according to some embodiments; Figure 14 This is a schematic diagram comparing the resistance and optical power of a laser chip according to some embodiments. Detailed Implementation

[0025] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0027] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through this equipment, allowing for long-distance transmission with relatively low power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0028] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0029] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0030] Information processing equipment connected to optical modules is also known as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0031] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. For example... Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0032] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0033] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0034] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0035] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structure of the switch 100 related to the optical module 200 is shown. (Example) Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0036] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat for the optical module; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0037] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0038] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0039] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0040] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0041] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which comprises an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming an opening 204 and another opening 205, one of which is an electrical interface and the other is an optical interface. In some embodiments, the shell forms an opening that serves as both an electrical interface and an optical interface.

[0042] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0043] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the above-mentioned devices.

[0044] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200. Figure 3 (The right end), opening 205 is also located at the end of optical module 200 ( Figure 3 (The left end). Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.

[0045] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0046] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0047] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0048] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the switch 100.

[0049] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0050] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.

[0051] In some implementations, the gold fingers 301 are disposed on the surface of one side of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some implementations, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to applications with high pin count requirements.

[0052] In some implementations, the gold fingers of the circuit board extend from the electrical interface and insert into the electrical connector of the switch 100; the circuit board is inserted into the cage 106, and the gold fingers 301 are connected to the electrical connector inside the cage 106. The gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0053] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0054] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the switch 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0055] In some embodiments, the optical module includes a light emitting component 400. In some embodiments, the optical module includes a light receiving component 500.

[0056] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.

[0057] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0058] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0059] Figure 5 This is an internal structural diagram of an optical module according to some embodiments. Figure 5 As shown, in some embodiments, a laser chip 900, a coherent optical component 1100, and a DSP chip 1200 are respectively disposed on the surface of the circuit board 300. The coherent optical component 1100 includes an optical modulator, which is used to modulate and demodulate optical signals. Exemplarily, the optical modulator is a silicon-based optical modulator or a thin-film lithium niobate-based optical modulator.

[0060] The optical modulator itself has no light source; the laser chip 900 serves as an external light source for the optical modulator. The laser chip 900 emits light from its side, and the emitted light enters the optical modulator. The laser chip 900 can output light of different wavelengths.

[0061] The host computer transmits electrical signals to the DSP chip 1200 via the gold finger 301. In some embodiments, optical signals may experience distortion during transmission through the fiber optic link. In the above embodiments of this disclosure, the DSP chip 1200 is used to combat and compensate for distortion, reducing its impact on the system's bit error rate. The DSP chip 1200 can perform various signal compensation processes, such as chromatic dispersion compensation and polarization mode dispersion compensation. For example, the DSP chip 1200 converts the 16-channel PAM-4 electrical signals sent by the host computer into four-channel transmitter PAM-4 electrical signals. The optical modulator modulates the received four-channel PAM-4 electrical signals onto the light emitted by the laser chip 900, thereby generating a transmitted optical signal.

[0062] Figure 6 This is a three-dimensional structural diagram of a laser chip according to some embodiments. Figure 7 This is a cross-sectional structural diagram of a laser chip according to some embodiments. Figure 8 for Figure 7 A local structural diagram. For example... Figures 6-8As shown, the laser chip 900 can be a ridge waveguide (RWG) laser. Ridge waveguide lasers can confine current and optical field to a narrow region, enabling low-threshold current lasing and high-efficiency laser output.

[0063] In some embodiments, the laser chip 900 may include an N-side metal electrode layer 910. The N-side metal electrode layer 910 is formed on the bottom surface of the laser chip 900. The N-side metal electrode layer 910 is used to realize electrical connections in the N-type region and provide an electron injection channel for the active region.

[0064] In some embodiments, the laser chip 900 may include an N-type InP layer 920. The N-type InP layer 920 is disposed above the N-plane metal electrode layer 910. The N-type InP layer 920 is electrically connected to the N-plane metal electrode layer 910, and the N-type InP layer 920 injects N-type charge carriers, including electrons, into the active region 930.

[0065] In some embodiments, the laser chip 900 may include an active region 930. The active region 930 is disposed above the N-type InP layer 920. The active region 930 includes a multiple quantum well structure and may be made of aluminum gallium indium arsenide. P-type carriers and N-type carriers are injected into the active region 930, respectively, and the P-type carriers and N-type carriers recombine in the active region 930 to generate photons. Specifically, N-type carriers are injected into the active region 930 from the N-type InP layer 920.

[0066] In some embodiments, the laser chip 900 may include a grating layer 940. The grating layer 940 is disposed above the active region 930. The grating layer 940 has a periodic groove structure, which forms a Bragg grating. The refractive index of the Bragg grating changes periodically, causing the refractive index of the grating layer 940 to change periodically along the direction of light propagation. Broad-spectrum light, when propagating, is amplified by the Bragg grating within the cavity. Light of a specific wavelength satisfying the Bragg condition undergoes constructive interference at each grating period, ultimately forming a stable and single laser output, achieving wavelength selection. Light of other wavelengths cannot establish effective positive feedback due to destructive interference.

[0067] In some embodiments, when growing the epitaxial structure, the following layers can be grown sequentially from bottom to top along the surface of the N-type InP layer 920: an N-InP buffer layer, a lower confinement layer, an active region 930 containing multiple quantum wells, an upper confinement layer, an InP spacer layer, and a grating layer 940. The lower and upper confinement layers are used to confine the optical field and charge carriers within the multiple quantum well region, thereby improving gain efficiency.

[0068] In some embodiments, the laser chip 900 may include a waveguide region 950. The waveguide region 950 is disposed above the grating layer 940. The waveguide region 950 protrudes upward relative to the grating layer 940, and both sides of the waveguide region 950 are in contact with air, thus the waveguide region 950 stands above the grating layer 940 as a ridge-shaped waveguide. The waveguide width of the waveguide region 950 is limited within a preset range to ensure lateral single-mode output. For example, the width of the waveguide region 950 is less than 2.5 μm to ensure single-mode lasing of the laser chip 900. However, the narrow waveguide region 950 results in extremely high series resistance and thermal resistance in the laser chip 900, causing a sharp increase in the internal junction temperature of the laser chip 900, saturation of optical output power, and inability to break through the optical power bottleneck of more than 100mW.

[0069] In some embodiments, the waveguide region 950 may include a first wide P-type InP layer 951. The first wide P-type InP layer 951 is connected to the upper surface of the grating layer 940. The width of the first wide P-type InP layer 951 is smaller than the width of the grating layer 940.

[0070] In some embodiments, waveguide region 950 may include a narrow P-type InP layer 953. The narrow P-type InP layer 953 is disposed above the first wide P-type InP layer 951. The width of the narrow P-type InP layer 953 is smaller than the width of the first wide P-type InP layer 951, resulting in a narrower current passage range.

[0071] In some embodiments, waveguide region 950 may include a second wide P-type InP layer 955. The second wide P-type InP layer 955 is disposed above a narrow P-type InP layer 953, which is sandwiched between the first wide P-type InP layer 951 and the second wide P-type InP layer 955. The second wide P-type InP layer 955 is used to output P-type carriers. The second wide P-type InP layer 955 and the N-type InP layer 920 form a PN junction. The concentration difference of the carriers causes diffusion, resulting in the second wide P-type InP layer 955 containing holes and negative ions, and the N-type InP layer 920 containing electrons and positive ions. Based on the principle of charge, holes are driven downwards into the active region 930, and electrons are driven upwards into the active region 930. Holes and electrons recombine in the active region 930 to generate photons. Light of a specific wavelength is reflected by a Bragg grating to form positive feedback and lasing.

[0072] In some embodiments, the waveguide region 950 may include a first N-type InP layer 952 and a second N-type InP layer 954. The first N-type InP layer 952 and the second N-type InP layer 954 are respectively located at the same horizontal level as the narrow P-type InP layer 953. The first N-type InP layer 952 is disposed on one side of the narrow P-type InP layer 953, and the second N-type InP layer 954 is disposed on the other side of the narrow P-type InP layer 953. The materials grown on this layer from left to right are, in sequence: N-type InP material, P-type InP material, and N-type InP material. For example, a continuous N-type InP layer can be grown at the epitaxial growth site of the laser chip. Then, the first N-type InP layer 952 and the second N-type InP layer 954 are formed by etching the unetched areas. The etched areas are then filled with P-type InP material to form the narrow P-type InP layer 953.

[0073] In some embodiments, the first N-type InP layer 952 and the second N-type InP layer 954 are designed above the active region 930. When etching the narrow P-type InP layer 953, the active region 930 is not damaged or exposed, thus avoiding the oxidation of the aluminum component in the active region 930 and affecting the chip performance.

[0074] In some embodiments, the first N-type InP layer 952, the narrow P-type InP layer 953, and the second N-type InP layer 954 are all disposed above the first wide P-type InP layer 951, thus dividing the first wide P-type InP layer 951 into a first connection area 9511, a second connection area 9512, and a third connection area 9513. The second connection area 9512 is disposed between the first connection area 9511 and the third connection area 9513, with one end connected to the first connection area 9511 and the other end connected to the third connection area 9513. The first connection area 9511 is vertically aligned with the first N-type InP layer 952, the second connection area 9512 is vertically aligned with the narrow P-type InP layer 953, and the third connection area 9513 is vertically aligned with the second N-type InP layer 954.

[0075] In some embodiments, a first N-type InP layer 952 is disposed above a first connection region 9511. When the two are in direct contact, a PN junction is formed. Since the electron concentration in the N-type region is much higher than that in the P-type region, and the hole concentration in the P-type region is much higher than that in the N-type region, the concentration gradient drives the majority carriers to diffuse. Electrons in the N-type region diffuse into the P-type region, and holes in the P-type region diffuse into the N-type region, forming a space charge region composed of ionized donors and ionized acceptors near the interface, and establishing a built-in electric field from the N-type region to the P-type region. When the laser chip is working normally, the P-region is connected to a positive voltage, and the N-region is connected to a negative voltage. At this time, the direction of the applied electric field is consistent with the direction of the built-in electric field of the PN junction, so that the PN junction is in a reverse bias state.

[0076] In some embodiments, a second N-type InP layer 954 is disposed above a third connection region 9513. When the two are in direct contact, a PN junction is formed. Based on the same principle described above, the second N-type InP layer 954 and the third connection region 9513 form a reverse-biased PN junction.

[0077] In some embodiments, the reverse-biased PN junction is in a reverse-biased state under normal laser chip operation. Current blocking barriers are built on both sides of the narrow P-type InP layer 953 to achieve lateral current restriction, forcing the injected current to be injected vertically into the active region 930 along the narrow P-type InP layer 953 at the center.

[0078] In some embodiments, a narrow P-type InP layer 953 is disposed above the second connection region 9512. The second wide P-type InP layer 955, the narrow P-type InP layer 953, and the second connection region 9512 form a longitudinal current path. The second connection region 9512 is aligned with the center of the active region 930, so current is injected longitudinally into the active region 930, thereby limiting the gain region to the central region of the active region 930 to ensure gain for the fundamental mode. During current injection, P-type carriers are injected downwards along the narrow P-type InP layer 953 into the second connection region 9512. No current is injected into the first connection region 9511 and the third connection region 9513, and there is very little lateral diffusion current from the second connection region 9512.

[0079] In some embodiments, the width of the second wide P-type InP layer 955 is greater than the width of the narrow P-type InP layer 953, and the width of the second wide P-type InP layer 955 may be equal to the width of the first wide P-type InP layer 951. The area above and below the narrow P-type InP layer 953 is a relatively wide region. Current is injected downwards sequentially along the longitudinal channel formed by the second wide P-type InP layer 955, the narrow P-type InP layer 953, and the first wide P-type InP layer 951. During the injection process, the current first diffuses over a wide area of ​​the second wide P-type InP layer 955, then concentrates and injects into the narrow window region corresponding to the narrow P-type InP layer 953, and continues to be injected downwards into the corresponding layer of the first wide P-type InP layer 951. The narrow P-type InP layer 953 serves to confine and restrict the current.

[0080] In some embodiments, the thickness of the second wide P-type InP layer 955 is greater than the thickness of the first wide P-type InP layer 951. Therefore, the bottom position of the narrow P-type InP layer 953 is closer to the lower active region 930 in the vertical direction. Consequently, the current transport path inside the first wide P-type InP layer 951 is shortened, and the charge carriers can maintain a more concentrated beam shape within a shorter transport distance. This effectively suppresses the lateral diffusion effect of current within the first wide P-type InP layer 951, ultimately ensuring that the current flowing out of the narrow P-type InP layer 953 is injected more concentratedly into the active region 930. For example, most of the current flowing out of the narrow P-type InP layer 953 is injected vertically downwards through the second connection region 9512. The second wide P-type InP layer 955, the narrow P-type InP layer 953, and the second connection region 9512 form a vertical channel, along which the current is concentratedly injected into the central region of the active region 930.

[0081] In some embodiments, the second connection region is aligned with the central region of the active region 930. A narrow P-type InP layer 953 is located above the second connection region, thus aligning the narrow P-type InP layer with the central region of the active region 930. The fundamental mode is distributed at the center of the active region 930, and higher-order modes are symmetrically distributed off-center on both sides of the fundamental mode. Therefore, the narrow P-type InP layer 953 longitudinally coincides with the fundamental mode optical field, and the first N-type InP layer 952 and the second N-type InP layer 954 longitudinally coincide with the higher-order mode optical field, ensuring that P-type carriers are strictly confined within the longitudinal channel aligned with the central region of the active region 930.

[0082] In some embodiments, the fundamental mode optical field position coincides with the longitudinal direction of the narrow P-type InP layer 953. Current is forcibly concentrated and vertically injected from the narrow P-type InP layer 953. The gain region is limited to the fundamental mode optical field region below the narrow P-type InP layer 953, i.e., the active region 930. The fundamental mode obtains high gain, easily reaching the threshold and lasing, thus ensuring single-mode lasing of the laser chip. The higher-order mode optical field position coincides longitudinally with the first N-type InP layer 952 and the second N-type InP layer 954. Current cannot be injected into the higher-order mode optical field through the first N-type InP layer 952 and the second N-type InP layer 954. Without current injection into the higher-order mode optical field, the higher-order mode cannot obtain sufficient gain, thus severely suppressing it and preventing lasing. Based on the above, single-mode lasing of the laser chip 900 can be guaranteed.

[0083] In some embodiments, the width of the narrow P-type InP layer 953 is a preset width, which can be the width corresponding to the single fundamental mode output of the laser chip. The width of the second wide P-type InP layer 955 can be significantly larger than the width of the narrow P-type InP layer 953. For example, the width of the second wide P-type InP layer 955 can be 1.5 to 4 times that of the narrow P-type InP layer 953.

[0084] In some embodiments, on the one hand, the width of the second wide P-type InP layer 955 is greater than the width of the narrow P-type InP layer 953. The wide ridge waveguide forms a weak equivalent refractive index difference with its two sides, increasing the volume of the fundamental mode and decreasing the optical power density. Furthermore, the wide ridge structure significantly increases the heat dissipation area and reduces thermal resistance. The wide ridge also reduces series resistance, thereby achieving high-power laser output. For example, the laser chip provided in this embodiment has a power of not less than 100mW, which is convenient for meeting the high-power laser requirements of high-speed optical modules. On the other hand, the extremely narrow narrow P-type InP layer 953 ensures single-mode laser output. Based on the above, the laser chip provided in this embodiment achieves decoupling between wide ridge light guiding and narrow window power limiting. The wide ridge, combined with the narrow P-type InP layer 953, provides precise pumping of the fundamental mode, enabling stable output of a single-mode with optical power exceeding 100mW even at 80°C.

[0085] In some embodiments, the thickness of the narrow P-type InP layer 953 is less than the thickness of the second wide P-type InP layer 955. The thinner narrow P-type InP layer 953 has a higher lateral resistance, which prevents the current from spreading laterally within the narrow P-type InP layer 953 and forces the current to be injected downwards with hysteresis into the second connection region.

[0086] In some embodiments, the narrow P-type InP layer 953 is aligned with the center of the first wide P-type InP layer 951 and the second wide P-type InP layer 955, respectively, and the center of the first wide P-type InP layer 951 is aligned with the center region of the active region 930, thereby ensuring that the current injected through the narrow P-type InP layer 953 is injected into the center region of the active region 930, ensuring that the fundamental mode obtains sufficient gain.

[0087] In some embodiments, the first N-type InP layer 952 and the second N-type InP layer 954 are symmetrically arranged, such that the current compression force applied from both sides to the central narrow P-type InP layer 953 is the same. The fundamental mode optical field is stimulated amplified under a symmetrical gain distribution, and the peak position, beam waist width, and equiphase surface of its mode spot will not be laterally shifted or tilted, thereby ensuring the pointing stability and circular symmetry of the laser chip output beam.

[0088] In some embodiments, the laser chip 900 may include a p-side metal electrode layer 960. The p-side metal electrode layer 960 is disposed above the waveguide region 950. The p-side metal electrode layer 960 is used to realize electrical connection of the p-type region and provide a hole injection channel for the active region 930. The p-side metal electrode layer 960 is electrically connected to the waveguide region 950.

[0089] Figure 9 This is a schematic diagram illustrating the working principle of a laser chip according to some embodiments. Figure 1 , Figure 10 This is a schematic diagram illustrating the working principle of a laser chip according to some embodiments. Figure 2.like Figure 9 and Figure 10 As shown, the dashed arrow indicates the direction of the current. The location where the current is injected is the fundamental mode spot, and the two sides of the fundamental mode spot are the higher-order mode spots.

[0090] In some embodiments, when a positive bias voltage is applied to the laser chip 900, the current is concentrated and injected vertically along the longitudinal channel composed of the second wide P-type InP layer 955, the narrow P-type InP layer 953 and the second connection region 9512, which restricts the carrier concentration to the center of the waveguide, so that the fundamental mode obtains a large gain due to its overlap with the high gain region, and the higher-order modes are completely suppressed because they are not pumped by carriers.

[0091] In some embodiments, the width of the second wide P-type InP layer 955 is greater than the width of the narrow P-type InP layer 953, and the thickness of the second wide P-type InP layer 955 is greater than the thickness of the first wide P-type InP layer 951. Therefore, the carriers achieve a higher concentration in the second wide P-type InP layer 955. Furthermore, the second wide P-type InP layer 955 has a larger cross-sectional area, thereby providing a larger heat dissipation channel for the high concentration of carriers.

[0092] In some embodiments, carriers are collected over a wide area in the second wide P-type InP layer 955, then windowed at the narrow P-type InP layer 953, and then vertically injected into the active region 930 along the second connection region 9512, effectively confining the gain region to the central region of the active region 930, thereby gaining the fundamental mode.

[0093] To facilitate the fabrication of the laser chip provided in this embodiment, this embodiment also provides a method for fabricating the laser chip. Figure 11 This is a flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 12 This is a structural diagram illustrating the fabrication of a laser chip according to some embodiments. For example... Figure 11 and Figure 12 As shown, in some embodiments, the method for fabricating a laser chip provided in this disclosure includes: S110: An active region and a grating layer are epitaxially grown upward along the surface of the N-type InP layer, and periodic grooves are etched on the surface of the grating layer.

[0094] In some embodiments, when growing the epitaxial structure, the epitaxial structure may include an N-type InP substrate, an N-InP buffer layer, a lower confinement layer, an active region 930, an upper confinement layer, an InP spacer layer, and a grating layer 940 stacked from bottom to top. The active region 930 includes multiple quantum wells.

[0095] In some embodiments, photoresist is coated on the surface of the grating layer, a periodic grating mask pattern is defined, and then periodic grooves are etched, the period of which satisfies the Bragg condition to form a Bragg grating. Exemplarily, a photoresist grating mask pattern is formed on the surface of the grating layer 940 using holographic exposure or electron beam lithography, and then the mask pattern is transferred to the grating layer 940 using wet etching or dry etching. The period of the grooves is determined according to the Bragg condition based on the target lasing wavelength.

[0096] S120: A first wide P-type InP layer is epitaxially grown upward along the surface of the grating layer. The first wide P-type InP layer buries the periodic grooves of the grating layer, and the first wide P-type InP layer has a first growth thickness.

[0097] In some embodiments, a first wide P-type InP layer 951 is epitaxially grown upward along the surface of the grating layer 940. The first wide P-type InP layer 951 has a first growth thickness. The first wide P-type InP layer 951 can not only completely bury the periodic grooves on the surface of the grating layer 940, so that the periodic grooves are fully filled with P-type InP material; in another direction, the upper surface of the first P-type InP layer 952 exceeds the upper surface of the grating layer 940 by a certain thickness, so as to provide a flat surface for subsequent epitaxial growth, and at the same time, the excess thickness participates in the formation of the PN reverse bias junction.

[0098] S130: An N-type InP inversion layer is epitaxially grown upward along the surface of the first wide P-type InP layer.

[0099] In some embodiments, an N-type InP inversion layer 970 is epitaxially grown upward along the surface of the first wide P-type InP layer 951 to subsequently fabricate a current blocking structure.

[0100] S140: A developing region is formed by photolithography along the surface of the N-type InP inversion layer, and the developing region is etched to expose the upper surface of the first P-type InP layer. The unetched areas are respectively formed into the first N-type InP layer and the second N-type InP layer.

[0101] In some embodiments, a photoresist layer is coated along the surface of the N-type InP inversion layer 970. After exposure and development, a development region is formed in a predetermined area of ​​the N-type InP inversion layer 970. The photoresist outside the development region is retained as a mask layer for subsequent etching.

[0102] In some embodiments, the photoresist mask layer is used to etch the developing area using wet etching or dry etching processes. During the etching process, the first wide P-type InP layer 951 is used as the etching stop layer. When the etching depth reaches the surface of the first wide P-type InP layer 951, the etching endpoint is controlled so that the etching stops precisely on the upper surface of the first wide P-type InP layer 951, thereby removing all the N-type InP inversion layer 970 in the developing area and exposing the upper surface of the underlying first wide P-type InP layer 951. The etched area forms a window.

[0103] In some embodiments, after etching is completed, the remaining photoresist mask layer is removed. A first N-type InP layer 952 and a second N-type InP layer 954 are formed on the unetched side regions, respectively. The first N-type InP layer 952 and the second N-type InP layer 954 are located above the first wide P-type InP layer 951 and are situated on the left and right sides of the etching window, respectively.

[0104] S150: Along the surfaces of the first N-type InP layer and the second N-type InP layer, and the bottom surface of the etched area, a P-type InP material is epitaxially grown upwards. The P-type InP material fills the etched area to form a narrow P-type InP layer. The P-type InP material covers the surfaces of the first N-type InP layer, the second N-type InP layer, and the narrow P-type InP layer to form a second wide P-type InP layer. The second wide P-type InP layer has a second growth thickness, which is greater than the first growth thickness.

[0105] In some embodiments, a P-type InP material is epitaxially grown upward along the surfaces of the first N-type InP layer and the second N-type InP layer, and along the bottom surface of the etched area. The P-type InP material fills the etched area to form a narrow P-type InP layer 953.

[0106] In some embodiments, the P-type InP material continues to grow epitaxially upwards, covering the surfaces of the first N-type InP layer 952, the second N-type InP layer 954, and the narrow P-type InP layer 953, and a second wide P-type InP layer 955 is obtained when the material grows to a second growth thickness. The lower surface of the second wide P-type InP layer 955 is connected to the upper surfaces of the first N-type InP layer 952, the second N-type InP layer 954, and the narrow P-type InP layer 953.

[0107] In some embodiments, by epitaxially growing P-type InP material in the above two steps, a narrow P-type InP layer 953 is disposed between the first wide P-type InP layer 951 and the second wide P-type InP layer 955 to form a current injection window region.

[0108] In some embodiments, the first N-type InP layer 952 and the second N-type InP layer 954 respectively form a reverse bias PN junction with the corresponding region of the lower first wide P-type InP layer 951. The reverse bias PN junction is in a reverse bias state under normal laser chip operation. Current blocking barriers are built on both sides of the narrow P-type InP layer 953 to achieve lateral current restriction, forcing the injected current to be injected vertically into the active region 930 along the narrow P-type InP layer 953.

[0109] S160: A mask is photolithographically formed on the surface of the second wide P-type InP layer in the direction perpendicular to the narrow P-type InP layer, and the two sides of the mask are etched to expose the surface of the grating layer to form a waveguide region, wherein the width of the narrow P-type InP layer is smaller than the width of the second wide P-type InP layer.

[0110] In some embodiments, after the epitaxial growth of the second wide P-type InP layer 955 is completed, a photoresist layer is coated along the upper surface of the second wide P-type InP layer 955, and exposure and development are performed using a photomask to form a mask layer on the surface of the second wide P-type InP layer 955. The mask layer is located vertically above the narrow P-type InP layer 953, and the projection of the pattern of the mask layer in the vertical direction covers the area where the narrow P-type InP layer 953 is located.

[0111] In some embodiments, to ensure alignment accuracy, a front-side overlay process using a photolithography machine is employed, with the position of the narrow P-type InP layer 953 serving as the alignment mark, aligning the centerline of the mask layer with the centerline of the narrow P-type InP layer 953 in the vertical direction. The width of the mask layer is configured to be greater than the width of the narrow P-type InP layer 953 to define the final width of the subsequent ridge structure.

[0112] In some embodiments, after forming the mask layer, the mask layer is used as an etching barrier layer to anisotropically etch the second wide P-type InP layer 955, the first N-type InP layer 952 on one side, the second N-type InP layer 954 on the other side, and the first wide P-type InP layer 951. During the etching process, the upper surface of the grating layer 940 is used as the etching stop layer. Since there is a certain selectivity ratio in etching rate between the grating layer 940 and the InP material, when the etching depth reaches the surface of the grating layer 940, the etching endpoint is monitored in real time using endpoint detection technology. This ensures that the second wide P-type InP layer 955, the first N-type InP layer 952 on one side, the second N-type InP layer 954 on the other side, and the first wide P-type InP layer 951 on both sides of the mask are completely removed, exposing the surface of the underlying grating layer 940, while the area below the mask is preserved, resulting in the waveguide region 950.

[0113] In some embodiments, the width of the second wide P-type InP layer 955 is greater than the width of the narrow P-type InP layer 953, and the width of the second wide P-type InP layer 955 may be equal to the width of the first wide P-type InP layer 951. The area above and below the narrow P-type InP layer 953 is a relatively wide region. Current is injected downwards sequentially along the longitudinal channel formed by the second wide P-type InP layer 955, the narrow P-type InP layer 953, and the first wide P-type InP layer 951. During the injection process, the current first diffuses over a wide area of ​​the second wide P-type InP layer 955, then concentrates and injects into the narrow window region corresponding to the narrow P-type InP layer 953, and continues to be injected downwards into the corresponding layer of the first wide P-type InP layer 951. The narrow P-type InP layer 953 serves to confine and restrict the current.

[0114] In some embodiments, if the second growth thickness is greater than the first growth thickness, the bottom position of the narrow P-type InP layer 953 is closer to the lower active region 930 in the vertical direction. This shortens the current transport path within the first wide P-type InP layer 951, allowing carriers to maintain a more concentrated beam shape within a shorter transport distance. This effectively suppresses the lateral diffusion effect of current within the first wide P-type InP layer 951, ultimately ensuring that the current flowing out of the narrow P-type InP layer 953 is injected more concentratedly into the active region 930. For example, most of the current flowing out of the narrow P-type InP layer 953 is injected vertically downwards through the first wide P-type InP layer 951. The second wide P-type InP layer 955, the narrow P-type InP layer 953, and the first wide P-type InP layer 951 form a vertical channel along which the current is concentratedly injected into the central region of the active region 930.

[0115] In some embodiments, the fundamental mode optical field position coincides with the longitudinal direction of the narrow P-type InP layer 953. Current is forcibly concentrated and vertically injected from the narrow P-type InP layer 953. The gain region is limited to the fundamental mode optical field region below the narrow P-type InP layer 953, i.e., the active region 930. The fundamental mode obtains high gain, easily reaching the threshold and lasing, thus ensuring single-mode lasing of the laser chip. The higher-order mode optical field position coincides longitudinally with the first N-type InP layer 952 and the second N-type InP layer 954. Current cannot be injected into the higher-order mode optical field through the first N-type InP layer 952 and the second N-type InP layer 954. Without current injection into the higher-order mode optical field, the higher-order mode cannot obtain sufficient gain, thus severely suppressing it and preventing lasing. Based on the above, single-mode lasing of the laser chip 900 can be guaranteed.

[0116] In some embodiments, the width of the second wide P-type InP layer 955 is greater than the width of the narrow P-type InP layer 953. The wide ridge waveguide forms a weak equivalent refractive index difference with its two sides, which increases the volume of the fundamental mode and reduces the optical power density. In addition, the wide ridge structure greatly increases the heat dissipation area and reduces the thermal resistance. Furthermore, the wide ridge can reduce the series resistance, thereby realizing high-power laser output. For example, the laser chip power provided in the embodiments of this disclosure is not less than 100mW, which is convenient to meet the requirements of high-speed optical modules for high-power lasers.

[0117] The laser chip provided in this embodiment achieves decoupling between wide ridge light guiding and narrow window power limiting. The wide ridge, combined with the narrow P-type InP layer 953, provides precise pumping of the fundamental mode, and can still stably output a single fundamental mode with an optical power of over 100mw at 80°C.

[0118] In some embodiments, after forming the waveguide region 950, the following steps may be included: depositing an insulating dielectric layer on the exposed grating layer 940 as an electrical isolation and protection layer for the device surface; opening an electrode contact window on the top of the ridge-shaped P-type InP layer 954 by photolithography and etching, depositing a P-side metal electrode layer 960 and annealing it to form an ohmic contact; thinning and polishing the bottom surface of the N-type InP layer 920, depositing an N-side metal electrode layer 910 and annealing it to form an ohmic contact.

[0119] Figure 13 This is a comparative spectrum diagram of a laser chip according to some embodiments. For example... Figure 13 As shown, in some embodiments, in the laser chip corresponding to the spectrum identified by letter a in the figures, the width of the second wide P-type InP layer 955 is 4 μm, and the width of the narrow P-type InP layer 953 is 2 μm. In the laser chip corresponding to the spectrum identified by letter b, no narrow current injection window is formed, and the waveguide width is 4 μm. From Figure 13 As can be seen, when the waveguide width is 4μm, single-mode lasing can be achieved by forming a narrow P-type InP layer 953 as an electrical injection window; without forming a narrow current injection window, multi-mode lasing is achieved.

[0120] Figure 14 This is a schematic diagram comparing the resistance and optical power of a laser chip according to some embodiments. Figure 14 As shown, in some embodiments, in the laser chip corresponding to the spectrum identified by letter a in the figures, the width of the second wide P-type InP layer 955 is 4 μm, and the width of the narrow P-type InP layer 953 is 2 μm. In the laser chip corresponding to the spectrum identified by letter b, no narrow current injection window is formed, and the waveguide width is 2 μm. From Figure 14 As can be seen, the laser chip identified by the letter 'a' has lower resistance and higher output optical power due to its larger waveguide width.

[0121] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A laser chip, characterized in that, include: N-type InP layer; An active region is located above the N-type InP layer, and the active region is configured to receive N-type carriers output by the N-type InP layer; A grating layer is disposed above the active region; A waveguide region, disposed above the grating layer and protruding upward relative to the grating layer, includes: A first wide P-type InP layer is connected to the upper surface of the grating layer, and the width of the first wide P-type InP layer is smaller than the width of the grating layer; the first wide P-type InP layer includes: First connection area; The second connection region is connected to the first connection region and aligned with the center region of the active region; The third connection area is connected to the second connection area; A narrow P-type InP layer is located above the second connection region, and the width of the narrow P-type InP layer is smaller than the width of the first wide P-type InP layer. The first N-type InP layer is located on one side of the narrow P-type InP layer and above the first connection region, so that the first N-type InP layer and the first connection region form a first reverse bias PN junction; The second N-type InP layer is located on the other side of the narrow P-type InP layer and above the third connection region, so that the second N-type InP layer and the third connection region form a second reverse bias PN junction; A second wide P-type InP layer is located above the narrow P-type InP layer. The width of the second wide P-type InP layer is greater than the width of the narrow P-type InP layer, and the thickness of the second wide P-type InP layer is greater than the thickness of the first wide P-type InP layer. The second wide P-type InP layer is configured to output P-type carriers to the active region so that the P-type carriers recombine with the N-type carriers in the active region to generate photons. The P-type carriers are injected downward into the active region via the second wide P-type InP layer, the narrow P-type InP layer, and the second connection region.

2. The laser chip according to claim 1, characterized in that, The thickness of the narrow P-type InP layer is less than the thickness of the second wide P-type InP layer.

3. The laser chip according to claim 1, characterized in that, The narrow P-type InP layer is aligned with the center of the first wide P-type InP layer and the second wide P-type InP layer, respectively.

4. The laser chip according to claim 1, characterized in that, The first N-type InP layer and the second N-type InP layer are symmetrically distributed relative to the narrow P-type InP layer.

5. A method for fabricating a laser chip, characterized in that, include: An active region and a grating layer are epitaxially grown upward along the surface of the N-type InP layer, and periodic grooves are etched on the surface of the grating layer. A first wide P-type InP layer is epitaxially grown upward along the surface of the grating layer. The first wide P-type InP layer buries the periodic grooves of the grating layer and has a first growth thickness. An N-type InP inversion layer is epitaxially grown upward along the surface of the first wide P-type InP layer; A developing region is formed by photolithography along the surface of the N-type InP inversion layer, and the developing region is etched to expose the upper surface of the first P-type InP layer. The unetched areas are then formed into the first N-type InP layer and the second N-type InP layer, respectively. Along the surfaces of the first N-type InP layer and the second N-type InP layer, and the bottom surface of the etched area, a P-type InP material is epitaxially grown upwards. The P-type InP material fills the etched area to form a narrow P-type InP layer. The P-type InP material covers the surfaces of the first N-type InP layer, the second N-type InP layer, and the narrow P-type InP layer to form a second wide P-type InP layer. The second wide P-type InP layer has a second growth thickness, which is greater than the first growth thickness. A mask is photolithographically formed on the surface of the second wide P-type InP layer in the direction perpendicular to the narrow P-type InP layer, and the two sides of the mask are etched to expose the surface of the grating layer to form a waveguide region, wherein the width of the narrow P-type InP layer is smaller than the width of the second wide P-type InP layer.

6. The method for fabricating a laser chip according to claim 5, characterized in that, The epitaxial growth of the active region and grating layer along the surface of the N-type InP layer includes: The following layers are grown sequentially from bottom to top along the surface of the N-type InP substrate: an N-InP buffer layer, a lower confinement layer, an active region containing multiple quantum wells, an upper confinement layer, an InP spacer layer, and a grating layer.

7. The method for fabricating a laser chip according to claim 5, characterized in that, The narrow P-type InP layer is aligned with the center of the active region.

8. The method for fabricating a laser chip according to claim 5, characterized in that, include: A P-plane ohmic contact layer and a P-plane metal electrode layer are grown along the surface of the waveguide region. The bottom surface of the N-type InP layer is masked and polished to reduce the thickness of the N-type InP layer; and an N-plane metal electrode layer is deposited on the bottom surface of the thinned N-type InP layer.

9. An optical module, characterized in that, Includes a laser chip, wherein the laser chip is the laser chip according to any one of claims 1-4, or the laser chip is a laser chip prepared by the method of preparing the laser chip according to any one of claims 5-8.

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