A numerical control ethercat master station bandwidth adaptive scheduling and link fault bypass control system and method

Abstract

The application provides a numerical control EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method, belongs to the numerical control system industrial Ethernet bus control technical field, and the system comprises a heterogeneous multi-core processor, a field programmable gate array, a local bus, a gigabit Ethernet physical layer unit and a storage unit; the heterogeneous multi-core processor contains a high-performance computing core and a low-power control core, is interconnected with the field programmable gate array through the local bus, and executes physically isolated task scheduling; the field programmable gate array solidifies message preprocessing filtering, message hardware shunting, bandwidth clipping and a multi-channel hardware bypass switch array module, each module is cascaded in cooperation according to a data flow direction, message hardware unloading, bandwidth dynamic adjustment and fault bypass topology reconstruction are realized. The application reduces bus cycle jitter, improves bandwidth utilization efficiency and link fault tolerance capability, and is suitable for high-end numerical control machine tool multi-axis linkage control scenes.

Description

Technical Field

[0001] This application belongs to the field of industrial Ethernet bus control technology for CNC systems, specifically relating to a CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method. Background Technology

[0002] EtherCAT real-time industrial Ethernet, with its high synchronization accuracy and low communication latency, has been widely used in multi-axis servo linkage and remote input / output control scenarios of high-end CNC systems. The bus cycle jitter level, bandwidth utilization efficiency and link fault tolerance are factors that determine the machining accuracy and operational stability of CNC machine tools.

[0003] Currently, most EtherCAT master stations use general-purpose processors to implement protocol parsing and data processing purely in software. Although a few improved solutions supplement this with programmable logic devices for auxiliary processing, they lack a collaborative architecture that physically isolates heterogeneous core tasks and offloads bus functions to hardware. This results in deficiencies in real-time performance, resource adaptability, and fault tolerance: real-time control tasks and non-real-time management tasks are scheduled in a mixed manner; message filtering, classification, and distribution are highly dependent on software execution; and in scenarios with multiple slave stations, computing power contention is prominent, leading to increased bus cycle jitter and high processor load, making it difficult to meet the real-time requirements of high-precision machining. Bus bandwidth is mostly configured statically and cannot adapt to changes in CNC machining conditions such as idle, roughing, and finishing. Under idle conditions, bandwidth resources are redundantly wasted, while under heavy load conditions, insufficient bandwidth can easily lead to data packet loss, making it difficult to balance resource utilization efficiency and transmission reliability. Link fault detection and topology reconstruction both rely on software processes. When a single slave station experiences a communication failure, it can easily trigger a shutdown of the entire bus, causing machining interruptions and workpiece scrapping. The link fault tolerance cannot meet the application requirements of continuous production of high-end CNC equipment.

[0004] Therefore, there is an urgent need for an EtherCAT master station control scheme that combines task isolation scheduling, dynamic bandwidth adaptation, and hardware-level link fault tolerance to improve the real-time performance, resource utilization efficiency, and operational reliability of high-end CNC bus systems. Summary of the Invention

[0005] The purpose of this invention is to address the problems in the prior art, such as large cycle jitter caused by mixed real-time and non-real-time task scheduling in CNC EtherCAT master stations, difficulty in adapting static bus bandwidth configuration to multi-condition requirements, and insufficient fault tolerance capability of link fault handling relying on software. This invention provides a CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method.

[0006] In a first aspect, embodiments of this application provide a CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system, the system comprising: Heterogeneous multi-core processor, field-programmable gate array, local bus, gigabit Ethernet physical layer unit and storage unit; The heterogeneous multi-core processor is connected to a field-programmable gate array via a local bus and is also connected to a memory unit. The heterogeneous multi-core processor includes at least two high-performance computing cores and at least two low-power control cores, and is used to perform physically isolated task scheduling. The field-programmable gate array is connected to a gigabit Ethernet physical layer unit, which is used to interface with external EtherCAT bus servo slaves and remote input / output slaves. The field-programmable gate array (FPGA) internally integrates a message preprocessing and filtering module, a hardware splitting module for process data objects and service data objects, a bandwidth pruning module, and a multi-channel hardware bypass switch array. The message preprocessing and filtering module is connected to the Gigabit Ethernet physical layer unit and the hardware splitting module for process data objects and service data objects, respectively. The hardware splitting module for process data objects and service data objects is connected to the heterogeneous multi-core processor and the bandwidth pruning module, respectively. The multi-channel hardware bypass switch array is connected to each slave station link.

[0007] Furthermore, the high-performance computing core is bound to hard real-time tasks such as EtherCAT periodic process data object message parsing, multi-axis trajectory interpolation calculation, and servo position closed-loop control, and is set as the highest preemptive scheduling priority of the system. The low-power control core is bound to non-real-time management tasks such as bus load statistics, processing condition identification, bandwidth parameter calculation, link fault determination, and log data storage, and adopts a time-slice round-robin scheduling strategy.

[0008] Furthermore, the message preprocessing and filtering module is used to perform frame filtering on all EtherCAT bus messages input through the Gigabit Ethernet physical layer unit, and eliminate redundant broadcast messages, invalid duplicate messages and non-protocol compliant messages by matching frame header features, retaining only valid processing messages containing processing control data and outputting them to the process data object and service data object message hardware splitting module. The process data object and service data object message hardware splitting module is used to perform hardware identification and classification of valid messages, transmit the real-time motion control message of the process data object to the high-performance computing core through the local bus, and transmit the configuration management message of the service data object to the low-power control core through the local bus.

[0009] Furthermore, the bandwidth trimming module receives bandwidth adjustment instructions from the low-power control core and directly modifies the payload length and bus transmission time slot of the process data object message at the hardware logic layer. The bandwidth trimming module matches the three typical machining conditions of the CNC system: no-load, roughing, and finishing, and performs corresponding adjustment operations such as bandwidth shrinkage, bandwidth increase, and bandwidth locking.

[0010] Furthermore, the multi-channel hardware bypass switch array sets an independent bypass switch node for each slave link, which is used to collect the response frame signal and communication status data of each slave. When the slave link is detected to meet the preset fault judgment condition, the bypass switch of the corresponding channel is triggered to close instantly, physically shorting the upstream and downstream bus links of the faulty slave, isolating the faulty node and automatically reconstructing the EtherCAT closed-loop bus topology. When the faulty slave link resumes normal communication, it receives the bypass cancellation command issued by the low-power control core, disconnects the corresponding bypass switch, and restores the original bus topology.

[0011] Secondly, embodiments of this application also provide a method for adaptive bandwidth scheduling and link fault bypass control of a CNC EtherCAT master station, the method comprising: S1. The heterogeneous multi-core processor performs system self-test and operating system kernel startup. The field-programmable gate array loads the pre-fixed hardware logic program, performs local bus link handshake and synchronizes running parameters, traverses all slave stations of the EtherCAT bus to complete slave station enumeration, address allocation and topology identification, generates initial bus topology parameters and then enters standby ready state. S2. After the processing task is started, all EtherCAT bus messages are input into the field programmable gate array via the gigabit Ethernet physical layer unit. The message preprocessing and filtering module performs hardware filtering to obtain valid processing messages. Then, the message hardware splitting module classifies and splits the valid messages into process data objects and service data objects. The two types of messages after splitting are transmitted to the corresponding cores of the heterogeneous multi-core processor through the local bus to perform data processing. S3. The low-power control core of the heterogeneous multi-core processor reads the machining status data of the CNC system in real time, identifies the current machining condition and generates corresponding bandwidth adjustment instructions, which are then sent to the bandwidth trimming module of the field programmable gate array to adjust the bandwidth of the process data object message transmission. S4. The field-programmable gate array (FPGA) collects the response signals and communication status data of all slave stations in real time to determine whether a slave station link has failed. If a single slave station link is determined to have failed, the hardware bypass switch of the corresponding channel is triggered to isolate the faulty slave station and reconstruct the closed-loop bus topology. The remaining normal slave stations continue to operate in the original standard communication cycle. S5. When the fault is repaired at the station and the link communication is restored to normal, the low-power control core detects the link recovery status, issues a bypass cancellation command to the field programmable gate array, disconnects the corresponding hardware bypass switch, and the bus restores its original topology and standard bandwidth configuration.

[0012] Furthermore, the specific steps of step S1 include: S11. The heterogeneous multi-core processor boots up a real-time operating system that can preempt real-time patches and completes kernel parameter configuration and interrupt priority settings. S12. Bind the EtherCAT message parsing, interpolation operation, and servo closed-loop hard real-time tasks to the high-performance computing core and set them as the highest scheduling priority of the system; S13. Bind non-real-time management tasks such as load statistics, operating condition identification, and fault determination to the low-power control core and set them as time-slice round-robin scheduling rules; S14. Configure the basic communication cycle, fault judgment threshold and initial bandwidth parameters of the field programmable gate array synchronization bus; S15. Traverse all servo slaves and remote input / output slaves on the EtherCAT bus, assign slave physical addresses, map process data object data fields, record bus topology connection relationships, and generate an initial bus topology table to store in the storage unit.

[0013] Furthermore, the specific steps of step S2 include: S21. The message preprocessing and filtering module performs frame header recognition and protocol feature matching on all input EtherCAT messages, filtering out broadcast frames, duplicate frames and non-protocol compliant frames, and retaining only valid messages containing processing control commands and feedback data. S22. The message hardware splitting module performs hardware parsing on the type field of valid messages. If it is identified as a process data object real-time motion control message, it is directly transmitted to the high-performance computing core through the low-latency real-time channel of the local bus. The high-performance computing core performs servo position closed-loop calculation and interpolation data update. S23. If the message is identified as a non-real-time configuration message for a service data object, it is transmitted to the low-power control core through the ordinary data channel of the local bus, and the low-power control core performs slave parameter configuration and operation status inspection.

[0014] Furthermore, the specific steps of step S3 include: S31. The low-power control core collects data on the machining code running status, spindle speed, feed rate and number of linkage axes of the CNC system to determine whether it is currently in no-load condition, roughing condition or finishing condition. S32. When the condition is determined to be no-load, a bandwidth reduction command is issued to adjust the effective bandwidth of the process data object bus to 30% of the rated bandwidth; S33. When the condition is determined to be a roughing heavy load condition, a bandwidth increase command is issued to adjust the effective bandwidth of the process data object bus to 90% of the rated bandwidth; S34. When the condition is determined to be a high-precision finishing process, a bandwidth lock command is issued to stably lock the effective bandwidth of the process data object bus to 70% of the rated bandwidth.

[0015] Furthermore, the specific steps of step S4 include: S41. The field-programmable gate array (FPGA) collects the response frame return status of each slave station in parallel and counts the number of lost packets of a single slave station on a cycle-by-cycle basis. S42. When the cumulative packet loss rate of a single slave station for a preset number of consecutive communication cycles is detected to be ≥ preset percentage, it is determined that the slave station link has a communication failure, and a bypass trigger signal is immediately generated to close the bypass switch of the corresponding channel. S43. Physically short-circuit the input and output bus ports of the faulty slave station. After isolating the faulty node, the remaining slave stations continue to operate with the original standard communication cycle. At the same time, the faulty slave station's location information is reported to the low-power control core and a pop-up alarm is triggered in the CNC system.

[0016] As can be seen from the above technical solutions, the present invention has the following advantages: In the CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method of the present invention, a heterogeneous multi-core processor is used to physically isolate and schedule the high-performance computing core and the low-power control core. Combined with the built-in message preprocessing and filtering module and message hardware diversion module of the field-programmable gate array (FPGA), message filtering, classification, and diversion are completed by hardware, avoiding computational power contention between real-time control tasks and non-real-time management tasks, reducing processor load, minimizing bus cycle jitter, and meeting the stringent real-time requirements of high-precision machining. Furthermore, the bandwidth shaving module of the FPGA can adjust the EtherCAT bandwidth according to the machining conditions. The bus's transmission bandwidth adapts to the transmission requirements of different machining stages, including no-load, roughing, and finishing. This eliminates the redundant waste of bandwidth resources under no-load conditions and avoids data packet loss caused by insufficient bandwidth under heavy-load conditions, balancing bus resource utilization efficiency and transmission reliability. Through a multi-channel hardware bypass switch array of the field-programmable gate array, fault node isolation and bus topology reconstruction can be quickly completed when a single slave station experiences a communication failure. Fault handling does not rely on software process execution, avoiding the problem of a single slave station failure causing the entire bus to stop, ensuring continuous operation of the machining process, reducing the risk of production interruption and workpiece scrap, and improving the continuous production reliability of CNC equipment. Attached Figure Description

[0017] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system of this application; Figure 2 This is a schematic diagram of the Phytium E2000Q quad-core heterogeneous processor in an embodiment of this application; Figure 3 This is a flowchart illustrating the CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control method of this application. Figure 4 This is a schematic diagram of the internal logic of the Gowin GW2A-55K FPGA in the embodiments of this application. Detailed Implementation

[0019] Various embodiments of the invention will be described more fully in the following detailed description of the CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method. The invention may have various embodiments, and adjustments and modifications may be made therein. However, it should be understood that there is no intention to limit the various embodiments of the invention to the specific embodiments disclosed herein, but rather the invention should be understood to cover all modifications, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of the invention.

[0020] To make the objectives, features, and advantages of this invention more apparent and understandable, specific embodiments and accompanying drawings will be used to clearly and completely describe the technical solutions protected by this invention. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] Please see Figure 1 The diagram shows a CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system. The system includes: Heterogeneous multi-core processor, field-programmable gate array, local bus, gigabit Ethernet physical layer unit and storage unit; The heterogeneous multi-core processor is connected to a field-programmable gate array via a local bus and is also connected to a memory unit. The heterogeneous multi-core processor includes at least two high-performance computing cores and at least two low-power control cores, and is used to perform physically isolated task scheduling. The field-programmable gate array is connected to a gigabit Ethernet physical layer unit, which is used to interface with external EtherCAT bus servo slaves and remote input / output slaves. The field-programmable gate array (FPGA) internally integrates a message preprocessing and filtering module, a hardware splitting module for process data objects and service data objects, a bandwidth pruning module, and a multi-channel hardware bypass switch array. The message preprocessing and filtering module is connected to the Gigabit Ethernet physical layer unit and the hardware splitting module for process data objects and service data objects, respectively. The hardware splitting module for process data objects and service data objects is connected to the heterogeneous multi-core processor and the bandwidth pruning module, respectively. The multi-channel hardware bypass switch array is connected to each slave station link.

[0022] It should be noted that the heterogeneous multi-core processor achieves physical isolation scheduling of real-time and non-real-time tasks through two types of cores; the field-programmable gate array has built-in message preprocessing and filtering, message hardware diversion, bandwidth pruning and multi-channel hardware bypass switch array to complete message hardware offloading, operating condition linkage bandwidth adjustment and fault link bypass reconstruction.

[0023] In some embodiments, a combination of a Phytium E2000Q quad-core heterogeneous processor and a Gowin GW2A-55K domestic FPGA is used. The two processors interact via Localbus, forming a fully domestically produced EtherCAT master station hardware platform. The FTC664 high-performance core exclusively handles high real-time tasks such as EtherCAT real-time PDO parsing, servo closed-loop control, and trajectory interpolation transmission; the FTC310 low-power core exclusively handles non-real-time management tasks such as bus load statistics, operating condition identification, bandwidth calculation, and fault determination. The FPGA internally incorporates four hardware logic units: message hardware filtering, PDO / SDO hardware load splitting, hardware bandwidth trimming, and a multi-channel bypass switch array. The system automatically adjusts the EtherCAT bus PDO payload and transmission time slots based on three operating conditions: CNC no-load, roughing, and finishing. Upon detecting a slave communication anomaly, the hardware logic momentarily short-circuits the links before and after the faulty slave, isolating the faulty node, reconstructing the bus closed-loop topology, and achieving fault-tolerant operation without downtime.

[0024] As a refinement and extension of the specific implementation methods described above, and to fully illustrate the specific implementation process in this embodiment, another Flying CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system is provided. This system includes: Heterogeneous multi-core processor, field-programmable gate array, local bus, gigabit Ethernet physical layer unit and storage unit; The heterogeneous multi-core processor is connected to a field-programmable gate array via a local bus and is also connected to a memory unit. The heterogeneous multi-core processor includes at least two high-performance computing cores and at least two low-power control cores, and is used to perform physically isolated task scheduling. It should be noted that, as Figure 2As shown, the system utilizes a Phytium E2000Q quad-core heterogeneous processor, comprising two 2.0GHz FTC664 high-performance computing cores and two 1.5GHz FTC310 low-power control cores. The chip has a rated power consumption of 11W and supports industrial-grade operation within a wide temperature range of -40℃ to 85℃. The coprocessor is a domestically produced Gowin GW2A-55K FPGA, featuring 55K programmable logic units and built-in high-speed I / O interfaces, meeting the logic resource deployment requirements for EtherCAT message hardware parsing, bandwidth shaving, and bypass switch arrays. The E2000Q and GW2A-55K are interconnected point-to-point via a Localbus bus with a transmission bandwidth of 8GT / s. Peripherals are paired with an industrial-grade gigabit Ethernet PHY chip to build an EtherCAT real-time bus. The bus topology can connect multiple servo slaves and multiple remote I / O slaves, adapting to multi-axis linkage control scenarios in five-axis machining centers. External industrial-grade DDR4 memory and NVMe solid-state storage ensure the stability of real-time computing and data storage.

[0025] The field-programmable gate array is connected to a gigabit Ethernet physical layer unit, which is used to interface with external EtherCAT bus servo slaves and remote input / output slaves. The field-programmable gate array (FPGA) internally integrates a message preprocessing and filtering module, a hardware splitting module for process data objects and service data objects, a bandwidth pruning module, and a multi-channel hardware bypass switch array. The message preprocessing and filtering module is connected to the Gigabit Ethernet physical layer unit and the hardware splitting module for process data objects and service data objects, respectively. The hardware splitting module for process data objects and service data objects is connected to the heterogeneous multi-core processor and the bandwidth pruning module, respectively. The multi-channel hardware bypass switch array is connected to each slave station link. All modules work together in tandem according to the data flow direction to achieve message hardware offloading, bandwidth adjustment, and fault bypass topology reconstruction.

[0026] In some embodiments, the high-performance computing core is bound to hard real-time tasks such as EtherCAT periodic process data object message parsing, multi-axis trajectory interpolation calculation, and servo position closed-loop control, and is set as the highest preemptive scheduling priority of the system. The low-power control core is bound to non-real-time management tasks such as bus load statistics, processing condition identification, bandwidth parameter calculation, link fault determination, and log data storage, and adopts a time-slice round-robin scheduling strategy.

[0027] It should be noted that the scheduling of the two core tasks is independent of each other, and there is no competition for computing resources or interference with execution timing during operation.

[0028] In some embodiments, the message preprocessing and filtering module is used to perform frame filtering on all EtherCAT bus messages input through the Gigabit Ethernet physical layer unit, and eliminate redundant broadcast messages, invalid duplicate messages and non-protocol compliant messages by frame header feature matching, retaining only valid processing messages containing processing control data and outputting them to the process data object and service data object message hardware splitting module. The process data object and service data object message hardware splitting module is used to perform hardware identification and classification of valid messages, and transmit the real-time motion control messages of the process data object directly to the high-performance computing core through the real-time channel of the local bus, and transmit the configuration management messages of the service data object to the low-power control core through the non-real-time channel of the local bus.

[0029] In some embodiments, the bandwidth trimming module receives a bandwidth adjustment instruction issued by the low-power control core and directly modifies the payload length and bus transmission time slot of the process data object message at the hardware logic layer. The bandwidth trimming module matches the three typical machining conditions of the CNC system: no-load, roughing, and finishing. It performs bandwidth shrinkage, bandwidth increase, and bandwidth locking adjustments accordingly, so as to adapt the bus bandwidth to the machining process requirements.

[0030] In some embodiments, the multi-channel hardware bypass switch array sets an independent bypass switch node for each slave link, which is used to collect the response frame signal and communication status data of each slave. When the slave link is detected to meet the preset fault judgment condition, the bypass switch of the corresponding channel is triggered to close instantly, physically shorting the upstream and downstream bus links of the faulty slave, isolating the faulty node and automatically reconstructing the EtherCAT closed-loop bus topology. When the faulty slave link resumes normal communication, the bypass cancellation command issued by the low-power control core is received, the corresponding bypass switch is disconnected, and the original bus topology is restored.

[0031] Please see Figure 3 The diagram illustrates a method for adaptive bandwidth scheduling and link fault bypass control in CNC EtherCAT master stations. This method includes the following steps: S1. The heterogeneous multi-core processor performs system self-test and operating system kernel startup. The field-programmable gate array loads the pre-fixed hardware logic program, performs local bus link handshake and synchronizes running parameters, traverses all slave stations of the EtherCAT bus to complete slave station enumeration, address allocation and topology identification, generates initial bus topology parameters and then enters standby ready state. S2. After the processing task is started, all EtherCAT bus messages are input into the field programmable gate array via the gigabit Ethernet physical layer unit. The message preprocessing and filtering module performs hardware filtering to obtain valid processing messages. Then, the message hardware splitting module classifies and splits the valid messages into process data objects and service data objects. The two types of messages after splitting are transmitted to the corresponding cores of the heterogeneous multi-core processor through the local bus to perform data processing. S3. The low-power control core of the heterogeneous multi-core processor reads the machining status data of the CNC system in real time, identifies the current machining condition and generates corresponding bandwidth adjustment instructions, which are then sent to the bandwidth trimming module of the field programmable gate array to adjust the bandwidth of the process data object message transmission. S4. The field-programmable gate array (FPGA) collects the response signals and communication status data of all slave stations in real time to determine whether a slave station link has failed. If a single slave station link is determined to have failed, the hardware bypass switch of the corresponding channel is triggered to isolate the faulty slave station and reconstruct the closed-loop bus topology. The remaining normal slave stations continue to operate in the original standard communication cycle. S5. When the fault is repaired at the station and the link communication is restored to normal, the low-power control core detects the link recovery status, issues a bypass cancellation command to the field programmable gate array, disconnects the corresponding hardware bypass switch, and the bus restores its original topology and standard bandwidth configuration.

[0032] As a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process of this embodiment, another method for adaptive bandwidth scheduling and link fault bypass control of CNC EtherCAT master station is provided, which includes the following steps: S1. The heterogeneous multi-core processor performs system self-test and operating system kernel startup. The field-programmable gate array loads the pre-fixed hardware logic program, performs local bus link handshake and synchronizes running parameters, traverses all slave stations of the EtherCAT bus to complete slave station enumeration, address allocation and topology identification, generates initial bus topology parameters and then enters standby ready state. The specific steps of step S1 include: S11. The heterogeneous multi-core processor boots up a real-time operating system that can preempt real-time patches and completes kernel parameter configuration and interrupt priority settings. S12. Bind the EtherCAT message parsing, interpolation operation, and servo closed-loop hard real-time tasks to the high-performance computing core and set them as the highest scheduling priority of the system; S13. Bind non-real-time management tasks such as load statistics, operating condition identification, and fault determination to the low-power control core and set them as time-slice round-robin scheduling rules; S14. Configure the basic communication cycle, fault judgment threshold and initial bandwidth parameters of the field programmable gate array synchronization bus; S15. Traverse all servo slaves and remote input / output slaves on the EtherCAT bus, assign slave physical addresses, map process data object data fields, record bus topology connection relationships, and generate an initial bus topology table to store in the storage unit.

[0033] S2. After the processing task starts, all EtherCAT bus messages are input to the field-programmable gate array (FPGA) via the Gigabit Ethernet physical layer unit. The message preprocessing and filtering module performs hardware filtering to obtain valid processing messages. Then, the message hardware splitting module classifies and splits the valid messages into process data objects and service data objects. The two types of messages are then transmitted via the local bus to the corresponding cores of the heterogeneous multi-core processor for data processing. Figure 4 As shown; The specific steps of step S2 include: S21. The message preprocessing and filtering module performs frame header recognition and protocol feature matching on all input EtherCAT messages, filtering out broadcast frames, duplicate frames and non-protocol compliant frames, and retaining only valid messages containing processing control commands and feedback data. S22. The message hardware splitting module performs hardware parsing on the type field of valid messages. If it is identified as a process data object (PDO) real-time motion control message, it is directly transmitted to the high-performance computing core through the low-latency real-time channel of the local bus. The high-performance computing core then performs servo position closed-loop calculation and interpolation data update. S23. If the message is identified as a Service Data Object (SDO) non-real-time configuration message, it is transmitted to the low-power control core through the ordinary data channel of the local bus, and the low-power control core performs slave parameter configuration and operation status inspection.

[0034] S3. The low-power control core of the heterogeneous multi-core processor reads the machining status data of the CNC system in real time, identifies the current machining condition and generates corresponding bandwidth adjustment instructions, which are then sent to the bandwidth trimming module of the field programmable gate array to adjust the bandwidth of the process data object message transmission. The specific steps of step S3 include: S31. The low-power control core collects data on the machining code running status, spindle speed, feed rate and number of linkage axes of the CNC system to determine whether it is currently in no-load condition, roughing condition or finishing condition. In some embodiments, the determination rules are as follows: When the machining code is in standby, program paused, or no valid interpolation instruction is executed, and the feed rate is 0 or lower than the preset no-load feed threshold, it is determined to be a no-load condition; at this time, the spindle is stopped or in a low-speed idling state, and each linkage axis has no continuous motion output.

[0035] When the machining code is running continuously, and the spindle speed is lower than the preset speed threshold, the feed rate is higher than the preset feed threshold, and the number of linked axes does not exceed the preset number of axes threshold, it is determined to be a roughing condition. This condition corresponds to the material removal stage with large cutting volume and high feed, and the bus data interaction volume is large and the bandwidth requirement is high.

[0036] When the machining code is running continuously, and the spindle speed is higher than the preset speed threshold, the feed rate is lower than the preset feed threshold, and the number of linked axes is not lower than the preset number of axes threshold, it is determined to be a finishing condition. This condition corresponds to the small cutting amount and high-precision surface forming stage, which has strict requirements for bus transmission stability and cycle jitter.

[0037] S32. When the no-load condition is determined, a bandwidth reduction command is issued to adjust the effective bandwidth of the process data object bus to 30% of the rated bandwidth, thereby reducing bus resource consumption and system power consumption. S33. When the roughing heavy load condition is determined, a bandwidth increase command is issued to adjust the effective bandwidth of the process data object bus to 90% of the rated bandwidth, so as to ensure the reliability of multi-axis data transmission under heavy load conditions and avoid bandwidth overflow and packet loss. S34. When the machining is determined to be a high-precision machining condition, a bandwidth lock command is issued to stably lock the effective bandwidth of the process data object bus to 70% of the rated bandwidth, thereby optimizing the utilization of bus resources while ensuring machining accuracy.

[0038] S4. The field-programmable gate array (FPGA) collects the response signals and communication status data of all slave stations in real time to determine whether a slave station link has failed. If a single slave station link is determined to have failed, the hardware bypass switch of the corresponding channel is triggered to isolate the faulty slave station and reconstruct the closed-loop bus topology. The remaining normal slave stations continue to operate in the original standard communication cycle. The specific steps of step S4 include: S41. The field-programmable gate array (FPGA) collects the response frame return status of each slave station in parallel in units of bus communication cycle, and counts the number of packet loss of a single slave station cycle by cycle. S42. When the cumulative packet loss rate of a single slave station for a preset number of consecutive communication cycles is detected to be ≥ preset percentage, it is determined that the slave station link has a communication failure, and a bypass trigger signal is immediately generated to close the bypass switch of the corresponding channel. S43. Physically short-circuit the input and output bus ports of the faulty slave station. After isolating the faulty node, the remaining slave stations continue to operate with the original standard communication cycle. At the same time, the faulty slave station's location information is reported to the low-power control core and a pop-up alarm is triggered in the CNC system.

[0039] S5. When the fault is repaired at the station and the link communication is restored to normal, the low-power control core detects the link recovery status, issues a bypass cancellation command to the field programmable gate array, disconnects the corresponding hardware bypass switch, restores the bus to its original topology and standard bandwidth configuration, and the processing flow continues to operate seamlessly.

[0040] It should be noted that after the faulty slave station is repaired and reconnected to the bus, the field-programmable gate array (FPGA) detects that the slave station's response frame has returned to normal and the packet loss rate has been lower than the fault judgment threshold for several consecutive cycles. It then reports the link recovery status to the low-power control core. After the low-power control core confirms that the link is stable, it issues a bypass cancellation command. The FPGA disconnects the corresponding bypass switch, the bus restores the original topology connection, and the bandwidth configuration of the corresponding operating condition is restored synchronously. The processing continues uninterrupted.

[0041] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0042] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system, characterized in that, The system includes: Heterogeneous multi-core processor, field-programmable gate array, local bus, gigabit Ethernet physical layer unit and storage unit; The heterogeneous multi-core processor is connected to a field-programmable gate array via a local bus and is also connected to a memory unit. The heterogeneous multi-core processor includes at least two high-performance computing cores and at least two low-power control cores, and is used to perform physically isolated task scheduling. The field-programmable gate array is connected to a gigabit Ethernet physical layer unit, which is used to interface with external EtherCAT bus servo slaves and remote input / output slaves. The field-programmable gate array (FPGA) internally integrates a message preprocessing and filtering module, a hardware splitting module for process data objects and service data objects, a bandwidth pruning module, and a multi-channel hardware bypass switch array. The message preprocessing and filtering module is connected to the Gigabit Ethernet physical layer unit and the hardware splitting module for process data objects and service data objects, respectively. The hardware splitting module for process data objects and service data objects is connected to the heterogeneous multi-core processor and the bandwidth pruning module, respectively. The multi-channel hardware bypass switch array is connected to each slave station link.

2. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system according to claim 1, characterized in that, The high-performance computing core is bound to hard real-time tasks such as EtherCAT periodic process data object message parsing, multi-axis trajectory interpolation calculation, and servo position closed-loop control, and is set as the highest preemptive scheduling priority of the system. The low-power control core is bound to non-real-time management tasks such as bus load statistics, processing condition identification, bandwidth parameter calculation, link fault determination, and log data storage, and adopts a time-slice round-robin scheduling strategy.

3. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system according to claim 1, characterized in that, The message preprocessing and filtering module is used to perform frame filtering on all EtherCAT bus messages input through the Gigabit Ethernet physical layer unit. It removes redundant broadcast messages, invalid duplicate messages and non-protocol compliant messages by matching frame header features, and retains only valid processing messages containing processing control data and outputs them to the process data object and service data object message hardware splitting module. The process data object and service data object message hardware splitting module is used to perform hardware identification and classification of valid messages, transmit the real-time motion control message of the process data object to the high-performance computing core through the local bus, and transmit the configuration management message of the service data object to the low-power control core through the local bus.

4. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system according to claim 1, characterized in that, The bandwidth trimming module receives bandwidth adjustment instructions from the low-power control core and directly modifies the payload length and bus transmission time slot of the process data object message at the hardware logic layer. The bandwidth trimming module matches the three typical machining conditions of the CNC system: no-load, roughing, and finishing, and performs corresponding adjustment operations such as bandwidth shrinkage, bandwidth increase, and bandwidth locking.

5. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system according to claim 1, characterized in that, The multi-channel hardware bypass switch array sets an independent bypass switch node for each slave link, which is used to collect the response frame signal and communication status data of each slave. When the slave link is detected to meet the preset fault judgment conditions, the bypass switch of the corresponding channel is triggered to close instantly, physically shorting the upstream and downstream bus links of the faulty slave, isolating the faulty node and automatically reconstructing the EtherCAT closed-loop bus topology. Once the faulty slave link resumes normal communication, it receives a bypass cancellation command from the low-power control core, disconnects the corresponding bypass switch, and restores the original bus topology.

6. A method for adaptive bandwidth scheduling and link fault bypass control of a CNC EtherCAT master station, characterized in that, The method is applied to the system as described in any one of claims 1 to 5, and the method includes the following steps: S1. The heterogeneous multi-core processor performs system self-test and operating system kernel startup. The field-programmable gate array loads the pre-fixed hardware logic program, performs local bus link handshake and synchronizes running parameters, traverses all slave stations of the EtherCAT bus to complete slave station enumeration, address allocation and topology identification, generates initial bus topology parameters and then enters standby ready state. S2. After the processing task is started, all EtherCAT bus messages are input into the field programmable gate array via the gigabit Ethernet physical layer unit. The message preprocessing and filtering module performs hardware filtering to obtain valid processing messages. Then, the message hardware splitting module classifies and splits the valid messages into process data objects and service data objects. The two types of messages after splitting are transmitted to the corresponding cores of the heterogeneous multi-core processor through the local bus to perform data processing. S3. The low-power control core of the heterogeneous multi-core processor reads the machining status data of the CNC system in real time, identifies the current machining condition and generates corresponding bandwidth adjustment instructions, which are then sent to the bandwidth trimming module of the field programmable gate array to adjust the bandwidth of the process data object message transmission. S4. The field-programmable gate array (FPGA) collects the response signals and communication status data of all slave stations in real time to determine whether a slave station link has failed. If a single slave station link is determined to be faulty, the hardware bypass switch of the corresponding channel is triggered to isolate the faulty slave station and reconstruct the closed-loop bus topology. The remaining normal slave stations continue to operate in the original standard communication cycle. S5. When the fault is repaired at the station and the link communication is restored to normal, the low-power control core detects the link recovery status, issues a bypass cancellation command to the field programmable gate array, disconnects the corresponding hardware bypass switch, and the bus restores its original topology and standard bandwidth configuration.

7. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control method according to claim 6, characterized in that, The specific steps of step S1 include: S11. The heterogeneous multi-core processor boots up a real-time operating system that can preempt real-time patches and completes kernel parameter configuration and interrupt priority settings. S12. Bind the EtherCAT message parsing, interpolation operation, and servo closed-loop hard real-time tasks to the high-performance computing core and set them as the highest scheduling priority of the system; S13. Bind non-real-time management tasks such as load statistics, operating condition identification, and fault determination to the low-power control core and set them as time-slice round-robin scheduling rules; S14. Configure the basic communication cycle, fault judgment threshold and initial bandwidth parameters of the field programmable gate array synchronization bus; S15. Traverse all servo slaves and remote input / output slaves on the EtherCAT bus, assign slave physical addresses, map process data object data fields, record bus topology connection relationships, and generate an initial bus topology table to store in the storage unit.

8. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control method according to claim 6, characterized in that, The specific steps of step S2 include: S21. The message preprocessing and filtering module performs frame header recognition and protocol feature matching on all input EtherCAT messages, filtering out broadcast frames, duplicate frames and non-protocol compliant frames, and retaining only valid messages containing processing control commands and feedback data. S22. The message hardware splitting module performs hardware parsing on the type field of valid messages. If it is identified as a process data object real-time motion control message, it is directly transmitted to the high-performance computing core through the low-latency real-time channel of the local bus. The high-performance computing core performs servo position closed-loop calculation and interpolation data update. S23. If the message is identified as a non-real-time configuration message for a service data object, it is transmitted to the low-power control core through the ordinary data channel of the local bus, and the low-power control core performs slave parameter configuration and operation status inspection.

9. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control method according to claim 6, characterized in that, The specific steps of step S3 include: S31. The low-power control core collects data on the machining code running status, spindle speed, feed rate and number of linkage axes of the CNC system to determine whether it is currently in no-load condition, roughing condition or finishing condition. S32. When the condition is determined to be no-load, a bandwidth reduction command is issued to adjust the effective bandwidth of the process data object bus to 30% of the rated bandwidth; S33. When the condition is determined to be a roughing heavy load condition, a bandwidth increase command is issued to adjust the effective bandwidth of the process data object bus to 90% of the rated bandwidth; S34. When the condition is determined to be a high-precision finishing process, a bandwidth lock command is issued to stably lock the effective bandwidth of the process data object bus to 70% of the rated bandwidth.

10. The CNC EtherCAT master station bandwidth adaptive scheduling and link fault bypass control method according to claim 6, characterized in that, The specific steps of step S4 include: S41. The field-programmable gate array (FPGA) collects the response frame return status of each slave station in parallel and counts the number of lost packets of a single slave station on a cycle-by-cycle basis. S42. When the cumulative packet loss rate of a single slave station for a preset number of consecutive communication cycles is detected to be ≥ preset percentage, it is determined that the slave station link has a communication failure, and a bypass trigger signal is immediately generated to close the bypass switch of the corresponding channel. S43. Physically short-circuit the input and output bus ports of the faulty slave station. After isolating the faulty node, the remaining slave stations continue to operate with the original standard communication cycle. At the same time, the faulty slave station's location information is reported to the low-power control core and a pop-up alarm is triggered in the CNC system.

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