Memory structure
By designing a double-sided capacitor layout in the memory structure, the problem of shrinking the memory cell area was solved, the capacitor area and capacitance were maximized, and the performance of the memory was improved.
Patent Information
- Application Number
- CN202510252455.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-24
- Filing Date
- 2025-03-05
- Publication Date
- 2026-08-25
AI Technical Summary
How to effectively reduce the area of memory cells, especially to increase the capacitance of capacitors, in the context of the continuous miniaturization of memory components?
By designing the first and second capacitor structures to be located on different surfaces of the substrate in the memory structure, and by maximizing the area of the capacitors through a special layout of the dielectric structure and word line structure, the capacitance is increased.
This effectively reduces the area of the storage unit and maximizes the area and capacitance of the capacitor, thereby improving the overall performance of the capacitor.
Smart Images
Figure CN122641010A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a memory structure. Background Technology
[0002] Memory components are widely used in electronic products. However, with the continuous miniaturization of memory components, effectively reducing the area of memory cells remains a constant goal. Summary of the Invention
[0003] This invention provides a memory structure that can effectively reduce the area of memory cells.
[0004] This invention proposes a memory structure, including a substrate, a first word line structure, a second word line structure, a bit line structure, a first contact window structure, a first capacitor structure, a second contact window structure, and a second capacitor structure. The substrate includes a first surface and a second surface opposite to each other. The first word line structure and the second word line structure are located within the substrate. The bit line structure is located on the first surface and between the first word line structure and the second word line structure. The first contact window structure is located on the first surface and to one side of the bit line structure. The first capacitor structure is located on the first surface and on the first contact window structure. The second contact window structure is located on the second surface. The second capacitor structure is located on the second surface and on the second contact window structure.
[0005] According to an embodiment of the present invention, in the above-described memory structure, the first word line structure and the second word line structure are electrically insulated from the substrate.
[0006] According to an embodiment of the present invention, in the above memory structure, the first word line structure may be located between the bit line structure and the first contact window structure.
[0007] According to an embodiment of the present invention, in the above-described memory structure, the first word line structure and the second word line structure can extend from the first surface to the second surface.
[0008] According to one embodiment of the present invention, in the above-described memory structure, the depth of the second word line structure may be greater than the depth of the first word line structure.
[0009] According to one embodiment of the present invention, in the above-described memory structure, the bit line structure can be connected to the substrate.
[0010] According to one embodiment of the present invention, in the above-described memory structure, the bit line structure may include bit lines and contact windows. The bit lines are located on the substrate. The contact windows are located between the bit lines and the substrate.
[0011] According to an embodiment of the present invention, in the above-described memory structure, the first contact window structure may be connected to the substrate.
[0012] According to an embodiment of the present invention, in the above-described memory structure, the first contact window structure may include a first contact window, a second contact window, and a barrier layer. The first contact window is connected to the substrate. The second contact window is located on the first contact window. The barrier layer is located between the first contact window and the second contact window.
[0013] According to an embodiment of the present invention, in the above-described memory structure, the first capacitor structure can be electrically connected to the first contact window structure.
[0014] According to an embodiment of the present invention, in the above-described memory structure, the first capacitor structure may include a first electrode layer, a second electrode layer, and a dielectric layer. The first electrode layer is electrically connected to a first contact window structure. The second electrode layer is located on the first electrode layer. The dielectric layer is located between the first electrode layer and the second electrode layer.
[0015] According to one embodiment of the present invention, in the above-described memory structure, the second contact window structure can be connected to the substrate.
[0016] According to one embodiment of the present invention, in the above-described memory structure, the second contact window structure may extend into the substrate.
[0017] According to an embodiment of the present invention, in the above-described memory structure, the top view of the second contact window structure can overlap with the top view of the second word line structure.
[0018] According to an embodiment of the present invention, in the above-described memory structure, the second contact window structure may include a first contact window, a second contact window, and a barrier layer. The first contact window is connected to the substrate. The second contact window is located on the first contact window. The barrier layer is located between the first contact window and the second contact window.
[0019] According to one embodiment of the present invention, in the above-described memory structure, the second capacitor structure can be electrically connected to the second contact window structure.
[0020] According to an embodiment of the present invention, in the above-described memory structure, the second capacitor structure may include a first electrode layer, a second electrode layer, and a dielectric layer. The first electrode layer is electrically connected to the second contact window structure. The second electrode layer is located on the first electrode layer. The dielectric layer is located between the first electrode layer and the second electrode layer.
[0021] According to one embodiment of the present invention, the memory structure described above may further include a first dielectric structure and a second dielectric structure. The first dielectric structure and the second dielectric structure are located in a substrate. A first word line structure may be located in the first dielectric structure. A second word line structure may be located in the second dielectric structure.
[0022] According to an embodiment of the present invention, in the above-described memory structure, the first dielectric structure and the second dielectric structure may extend from the first surface to the second surface.
[0023] According to one embodiment of the present invention, in the above-described memory structure, the depth of the second dielectric structure may be greater than the depth of the first dielectric structure.
[0024] Based on the above, in the memory structure proposed in this invention, since the first contact window structure and the first capacitor structure are located on the first surface, and the second contact window structure and the second capacitor structure are located on the second surface, the area of the memory cell can be effectively reduced. Furthermore, since the first capacitor structure and the second capacitor structure are located on the first surface and the second surface respectively, the area of the first capacitor structure and the area of the second capacitor structure can be maximized, thereby increasing the capacitance of the first capacitor structure and the capacitance of the second capacitor structure.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figure 1 This is a top view of the memory structure according to some embodiments of the present invention;
[0027] Figures 2A to 2F For along Figure 1 A cross-sectional view of the manufacturing process of a memory structure with the I-I' section line.
[0028] Symbol Explanation
[0029] 10: Memory Structure
[0030] 100: Base
[0031] 102A, 102B: Dielectric structure
[0032] 104A, 104B: Word line structure
[0033] 106A, 106B: Word lines
[0034] 108A, 108B: Barrier Layer
[0035] 110: Top Cover Layer
[0036] 112, 122, 124, 142, 144: Contact windows
[0037] 114: Bitline
[0038] 116: Bitline Structure
[0039] 118, 134, 136, 138, 154, 156: Dielectric layers
[0040] 120, 140: Contact window structure
[0041] 126, 146: Barrier Layer
[0042] 128, 148: Capacitor Structure
[0043] 130, 132, 150, 152: Electrode layers
[0044] 200: Substrate
[0045] AA: Active Zone
[0046] D1, D2, D3, D4: Depth
[0047] S1: First Page
[0048] S2: Second side Detailed Implementation
[0049] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.
[0050] Figure 1 This is a top view of a memory structure according to some embodiments of the present invention. Figures 2A to 2F For along Figure 1 A cross-sectional view of the manufacturing process of a memory structure along the I-I' section line. Figure 1 in, omit Figures 2A to 2F Some components in the text are explained clearly. Figure 1 The setting relationship between components.
[0051] Please refer to Figure 1 and Figure 2A A substrate 100 is provided. The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. In some embodiments, the first surface S1 may be the front surface of the substrate 100, and the second surface S2 may be the back surface of the substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have desired doped regions (not shown), the description of which is omitted here.
[0052] Next, dielectric structures 102A and 102B can be formed in the substrate 100. Dielectric structure 102B can define an active region AA in the substrate 100. In some embodiments, dielectric structures 102A and 102B can extend from a first surface S1 to a second surface S2. In some embodiments, the depth D2 of dielectric structure 102B can be greater than the depth D1 of dielectric structure 102A. In some embodiments, dielectric structures 102A and 102B can be shallow trench isolation structures. In some embodiments, the materials of dielectric structures 102A and 102B are, for example, silicon oxide.
[0053] Please refer to Figure 1 and Figure 2B A word line structure 104A can be formed in dielectric structure 102A, and a word line structure 104B can be formed in dielectric structure 102B. Thus, word line structures 104A and 104B can be formed in substrate 100. Word line structures 104A and 104B are electrically insulated from substrate 100. For example, word line structure 104A can be electrically insulated from substrate 100 through dielectric structure 102A, and word line structure 104B can be electrically insulated from substrate 100 through dielectric structure 102B. In some embodiments, word line structures 104A and 104B can extend from a first surface S1 to a second surface S2. In some embodiments, the depth D4 of word line structure 104B can be greater than the depth D3 of word line structure 104A.
[0054] In some embodiments, word line structure 104A may include word line 106A. Word line 106A is located within dielectric structure 102A. In some embodiments, word line structure 104A may further include barrier layer 108A. Barrier layer 108A is located between word line 106A and dielectric structure 102A. In some embodiments, the material of word line 106A is, for example, tungsten. In some embodiments, the material of barrier layer 108A is, for example, titanium, titanium nitride, or a combination thereof.
[0055] In some embodiments, word line structure 104B may include word line 106B. Word line 106B is located within dielectric structure 102B. In some embodiments, word line structure 104B may further include barrier layer 108B. Barrier layer 108B is located between word line 106B and dielectric structure 102B. In some embodiments, the material of word line 106B is, for example, tungsten. In some embodiments, the material of barrier layer 108B is, for example, titanium, titanium nitride, or a combination thereof.
[0056] Next, a capping layer 110 may be formed on the substrate 100, dielectric structure 102A, dielectric structure 102B, word line structure 104A, and word line structure 104B. In some embodiments, the material of the capping layer 110 is, for example, silicon nitride.
[0057] Please refer to Figure 1 and Figure 2C A contact window 112 can be formed in the top cover layer 110. The contact window 112 can be connected to the substrate 100. In some embodiments, the material of the contact window 112 is, for example, doped polysilicon. Next, a bit line 114 can be formed on the contact window 112. In some embodiments, the material of the bit line 114 is, for example, tungsten. By the above method, a bit line structure 116 can be formed on the first surface S1. The bit line structure 116 is located on the first surface S1 and between the word line structure 104A and the word line structure 104B. The bit line structure 116 may include the bit line 114 and the contact window 112. The bit line structure 116 can be connected to the substrate 100. The bit line 114 is located on the substrate 100. The contact window 112 is located between the bit line 114 and the substrate 100. The contact window 112 can be connected to the substrate 100.
[0058] Next, a dielectric layer 118 may be formed on the top cap layer 110 and the bit line structure 116. In some embodiments, the material of the dielectric layer 118 is, for example, silicon nitride.
[0059] Please refer to Figure 1 and Figure 2D A contact window structure 120 can be formed in the dielectric layer 118 and the top cap layer 110. Thus, the contact window structure 120 can be formed on the first surface S1. The contact window structure 120 is located on one side of the bit line structure 116. The contact window structure 120 can be connected to the substrate 100. Furthermore, the word line structure 104A can be located between the bit line structure 116 and the contact window structure 120. In some embodiments, the contact window structure 120 may include a contact window 122, a contact window 124, and a barrier layer 126. The contact window 122 can be connected to the substrate 100. In some embodiments, the material of the contact window 122 is, for example, doped polysilicon. The contact window 124 is located on the contact window 122. In some embodiments, the material of the contact window 124 is, for example, tungsten. The barrier layer 126 is located between the contact window 122 and the contact window 124, and may be located between the contact window 124 and the dielectric layer 118. In some embodiments, the material of the barrier layer 126 is, for example, titanium, titanium nitride, or a combination thereof.
[0060] Next, a capacitor structure 128 may be formed on the first surface S1. The capacitor structure 128 is located on the contact window structure 120. The capacitor structure 128 is electrically connected to the contact window structure 120. In some embodiments, the capacitor structure 128 may include an electrode layer 130, an electrode layer 132, and a dielectric layer 134. The electrode layer 130 is electrically connected to the contact window structure 120. In some embodiments, the material of the electrode layer 130 is, for example, titanium, titanium nitride, or a combination thereof. The electrode layer 132 is located on the electrode layer 130. In some embodiments, the material of the electrode layer 132 is, for example, titanium, titanium nitride, or a combination thereof. The dielectric layer 134 is located between the electrode layer 130 and the electrode layer 132. In some embodiments, the material of the dielectric layer 134 is, for example, a high dielectric constant material.
[0061] Then, a dielectric layer 136 may be formed on the dielectric layer 118 and the capacitor structure 128. In some embodiments, the material of the dielectric layer 136 is, for example, silicon oxide.
[0062] Please refer to Figure 2E The dielectric layer 136 can be bonded to the carrier substrate 200. Then, a thinning process can be performed on the second surface S2 of the substrate 100 to reduce the thickness of the substrate 100.
[0063] Please refer to Figure 1 and Figure 2F A dielectric layer 138 can be formed on the second surface S2 and in the substrate 100. The dielectric layer 138 can be a single-layer structure or a multi-layer structure. Next, a contact window structure 140 can be formed in the dielectric layer 138. Thus, the contact window structure 140 can be formed on the second surface S2. The contact window structure 140 can be connected to the substrate 100. In some embodiments, the contact window structure 140 can extend into the substrate 100. In some embodiments, the top view of the contact window structure 140 can overlap the top view of the word line structure 104B. In some embodiments, the contact window structure 140 may include a contact window 142, a contact window 144, and a barrier layer 146. The contact window 142 is connected to the substrate 100. The contact window 142 can be located in the substrate 100. In some embodiments, the material of the contact window 142 is, for example, doped polysilicon. The contact window 144 is located on the contact window 142. In some embodiments, the material of the contact window 144 is, for example, tungsten. The barrier layer 146 is located between the contact window 142 and the contact window 144, and may be located between the contact window 144 and the dielectric layer 138. In some embodiments, the material of the barrier layer 146 is, for example, titanium, titanium nitride, or a combination thereof.
[0064] Next, a capacitor structure 148 can be formed on the second surface S2. The capacitor structure 148 is located on the contact window structure 140. The capacitor structure 148 is electrically connected to the contact window structure 140. In some embodiments, the capacitor structure 148 may include an electrode layer 150, an electrode layer 152, and a dielectric layer 154. The electrode layer 150 is electrically connected to the contact window structure 140. In some embodiments, the material of the electrode layer 150 is, for example, titanium, titanium nitride, or a combination thereof. The electrode layer 152 is located on the electrode layer 150. In some embodiments, the material of the electrode layer 152 is, for example, titanium, titanium nitride, or a combination thereof. The dielectric layer 154 is located between the electrode layer 150 and the electrode layer 152. In some embodiments, the material of the dielectric layer 154 is, for example, a high dielectric constant material.
[0065] Then, a dielectric layer 156 can be formed on the dielectric layer 138 and the capacitor structure 148. In some embodiments, the material of the dielectric layer 156 is, for example, silicon oxide. Furthermore, the carrier substrate 200 can be removed.
[0066] The following is through Figure 1 and Figure 2F The memory structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the memory structure 10 is described using the above method as an example, the present invention is not limited thereto.
[0067] Please refer to Figure 1 and Figure 2F The memory structure 10 includes a substrate 100, word line structures 104A and 104B, a bit line structure 116, a contact window structure 120, a capacitor structure 128, a contact window structure 140, and a capacitor structure 148. The memory structure 10 is applicable to wafer-on-wafer (WoW) fabrication and through-substrate via (TSV) fabrication processes. The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. Word line structures 104A and 104B are located within the substrate 100. The bit line structure 116 is located on the first surface S1 and between word line structures 104A and 104B. The contact window structure 120 is located on the first surface S1 and to one side of the bit line structure 116. The capacitor structure 128 is located on the first surface S1 and on the contact window structure 120. The contact window structure 140 is located on the second surface S2. Capacitor structure 148 is located on the second surface S2 and on the contact window structure 140. Furthermore, memory structure 10 may further include dielectric structures 102A and 102B. Dielectric structures 102A and 102B are located in substrate 100. Word line structure 104A may be located in dielectric structure 102A. Word line structure 104B may be located in dielectric structure 102B.
[0068] Furthermore, the remaining components in the memory structure 10 can be described with reference to the above embodiments. Additionally, the details of each component in the memory structure 10 (e.g., materials and forming methods) have been described in detail in the above embodiments and will not be repeated here.
[0069] As can be seen from the above embodiments, in the memory structure 10 proposed in this invention, since the contact window structure 120 and the capacitor structure 128 are located on the first surface S1, and the contact window structure 140 and the capacitor structure 148 are located on the second surface S2, the area of the memory cell can be effectively reduced. Furthermore, since the capacitor structure 128 and the second capacitor structure 148 are located on the first surface S1 and the second surface S2 respectively, the area of the capacitor structure 128 and the area of the second capacitor structure 148 can be maximized, thereby increasing the capacitance of the capacitor structure 128 and the capacitance of the capacitor structure 148.
[0070] In summary, the memory structure of the above embodiments includes a substrate, a first word line structure, a second word line structure, a bit line structure, a first contact window structure, a first capacitor structure, a second contact window structure, and a second capacitor structure. The substrate includes a first surface and a second surface opposite to each other. The first word line structure and the second word line structure are located within the substrate. The bit line structure is located on the first surface and between the first word line structure and the second word line structure. The first contact window structure is located on the first surface and on one side of the bit line structure. The first capacitor structure is located on the first surface and on the first contact window structure. The second contact window structure is located on the second surface. The second capacitor structure is located on the second surface and on the second contact window structure. Therefore, the area of the memory cell can be effectively reduced. Furthermore, the area of the first capacitor structure and the area of the second capacitor structure can be maximized, thereby increasing the capacitance of the first capacitor structure and the capacitance of the second capacitor structure.
[0071] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A memory structure, comprising: The base includes the first and second surfaces that are opposite to each other; The first character line structure and the second character line structure are located in the substrate; The bit line structure is located on the first surface and between the first word line structure and the second word line structure; The first contact window structure is located on the first surface and on one side of the bit line structure; A first capacitor structure is located on the first surface and on the first contact window structure; The second contact window structure is located on the second surface; as well as The second capacitor structure is located on the second surface and on the second contact window structure.
2. The memory structure of claim 1, wherein the first word line structure and the second word line structure are electrically insulated from the substrate.
3. The memory structure of claim 1, wherein the first word line structure is located between the bit line structure and the first contact window structure.
4. The memory structure of claim 1, wherein the first word line structure and the second word line structure extend from the first surface to the second surface.
5. The memory structure of claim 4, wherein the depth of the second word line structure is greater than the depth of the first word line structure.
6. The memory structure of claim 1, wherein the bit line structure is connected to the substrate.
7. The memory structure of claim 1, wherein the bit line structure comprises: Bit lines are located on the substrate; as well as A contact window is located between the bit line and the substrate.
8. The memory structure of claim 1, wherein the first contact window structure is connected to the substrate.
9. The memory structure of claim 1, wherein the first contact window structure comprises: A first contact window is connected to the substrate; The second contact window is located on top of the first contact window; as well as A barrier layer is located between the first contact window and the second contact window.
10. The memory structure of claim 1, wherein the first capacitor structure is electrically connected to the first contact window structure.
11. The memory structure of claim 1, wherein the first capacitor structure comprises: The first electrode layer is electrically connected to the first contact window structure; The second electrode layer is located on the first electrode layer; as well as A dielectric layer is located between the first electrode layer and the second electrode layer.
12. The memory structure of claim 1, wherein the second contact window structure is connected to the substrate.
13. The memory structure of claim 1, wherein the second contact window structure extends into the substrate.
14. The memory structure of claim 1, wherein the top view of the second contact window structure overlaps with the top view of the second word line structure.
15. The memory structure of claim 1, wherein the second contact window structure comprises: A first contact window is connected to the substrate; The second contact window is located on top of the first contact window; as well as A barrier layer is located between the first contact window and the second contact window.
16. The memory structure of claim 1, wherein the second capacitor structure is electrically connected to the second contact window structure.
17. The memory structure of claim 1, wherein the second capacitor structure comprises: The first electrode layer is electrically connected to the second contact window structure; The second electrode layer is located on the first electrode layer; as well as A dielectric layer is located between the first electrode layer and the second electrode layer.
18. The memory structure of claim 1, further comprising: The first dielectric structure and the second dielectric structure are located in the substrate, wherein The first word line structure is located within the first dielectric structure, and The second word line structure is located within the second dielectric structure.
19. The memory structure of claim 18, wherein the first dielectric structure and the second dielectric structure extend from the first surface to the second surface.
20. The memory structure of claim 19, wherein the depth of the second dielectric structure is greater than the depth of the first dielectric structure.