Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor chip technology, and aims to solve the problem of short circuits in the gate layers on both sides of a gate isolation structure. The semiconductor structure includes a stacked structure and a gate isolation structure. The stacked structure includes a core region and a connection region; the stacked structure includes a gate stacked structure and a dielectric stacked structure, with a portion of the gate stacked structure located in the core region, and the dielectric stacked structure and a portion of the gate stacked structure located in the connection region; the gate isolation structure includes an isolation layer and a body, the body extending along a first direction and penetrating the gate stacked structure located in the core region and the gate stacked structure located in the connection region along a second direction, the isolation layer being located between the body and the gate stacked structure; the sidewalls of the body include a plurality of first arc-shaped surfaces connected along the first direction. With the above configuration, the gate isolation structure extends along the first direction without interruption, which helps prevent short circuits in the gate layers on both sides of the gate isolation structure along a third direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor structure is provided. The semiconductor structure includes a stacked structure and a gate isolation structure. The stacked structure includes a core region and a connection region, the core region and the connection region being arranged along a first direction. The stacked structure includes a gate stacked structure and a dielectric stacked structure. The gate stacked structure includes a plurality of gate layers and a plurality of first dielectric layers alternately stacked along a second direction. The dielectric stacked structure includes a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked along the second direction. A portion of the gate stacked structure is located in the core region, and the dielectric stacked structure and a portion of the gate stacked structure are located in the connection region. The gate isolation structure includes an isolation layer and a body. The body extends along the first direction and penetrates along the second direction through the gate stacked structure located in the core region and the gate stacked structure located in the connection region. The isolation layer is located between the body and the gate stacked structure. The sidewall of the body includes a plurality of first arcuate surfaces connected along the first direction. The first direction intersects the second direction.

[0007] In some embodiments, the body includes a first end face and a second end face disposed opposite to each other along the second direction. In the first direction, the first end face includes alternating planes and arcuate surfaces. In the second direction, the maximum distance between the second arcuate surface and the second end face is equal to the distance between the plane and the second end face.

[0008] In some embodiments, the size of the isolation layer located between the second arcuate surface and the gate stack structure in the third direction is less than or equal to the spacing between the second arcuate surface and the gate stack structure in the third direction; the third direction intersects the plane containing the first direction and the second direction.

[0009] In some embodiments, the semiconductor structure further includes: a third dielectric layer located on one side of the stacked structure along the second direction, the third dielectric layer having a protrusion located between the isolation layer and the body.

[0010] In some embodiments, the body includes a first end face and a second end face disposed opposite to each other along the second direction, the spacing between the second end face and the third dielectric layer being greater than the spacing between the first end face and the third dielectric layer; the protrusion has a first end and a second end arranged along the second direction, the second end being closer to the second end face than the first end; the dimension of the first end in the third direction is greater than the dimension of the second end in the third direction; wherein the third direction intersects the plane containing the first direction and the second direction.

[0011] In some embodiments, the semiconductor structure further includes: a fourth dielectric layer located between the third dielectric layer and the stacked structure, between the bump and the isolation layer, and between the bump and the body.

[0012] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: forming a first stacked structure, the first stacked structure including a core region and a connection region, the core region and the connection region being arranged along a first direction, the first stacked structure including a plurality of sacrificial layers and a plurality of dielectric layers alternately stacked along a second direction; wherein the second direction is the thickness direction of the dielectric layers, and the first direction intersects the second direction; forming a plurality of first holes, the plurality of first holes being spaced apart along the first direction, a portion of the first holes penetrating the first stacked structure located in the core region, and a portion of the first holes penetrating the first stacked structure located in the connection region; removing a portion of the first stacked structure through the plurality of first holes to make the plurality of first holes interconnected, thereby forming a gate trench; replacing the sacrificial layer located in the core region and a portion of the sacrificial layer located in the connection region with gate layers to form a gate stacked structure; sequentially forming an isolation layer and a body in the gate trench, the isolation layer being located between the body and the gate stacked structure; the sidewall of the body including a plurality of first arcuate surfaces connected along the first direction.

[0013] In some embodiments, forming a gate spacer includes: removing a portion of a first stacked structure located in the core region through a portion of the first hole to form a first spacer; filling the first spacer with a sacrificial material; removing a portion of the first stacked structure located in the connection region through a portion of the first hole to form a second spacer, the first spacer and the second spacer together constituting the gate spacer; forming a support layer located on one side of the first stacked structure along the second direction, the support layer having a plurality of second holes spaced apart along the first direction, the second holes exposing at least a portion of the gate spacer.

[0014] In some embodiments, after forming the second partition and before forming the support layer, the method further includes: removing a portion of the sacrificial layer located in the connection region through the second partition to form a first fill space; replacing the sacrificial layer located in the core region and the portion of the sacrificial layer located in the connection region with a gate layer includes: filling the first fill space with sacrificial material through a portion of the second hole and the second partition; removing the sacrificial layer located in the core region through a portion of the second hole and the first partition to form a second fill space; removing the sacrificial material located in the first fill space through a portion of the second hole and the second partition to make the first fill space, the second fill space and the gate partition connected; and forming a gate layer in the first fill space and the second fill space through the second hole and the gate partition.

[0015] In some embodiments, the step of sequentially forming an isolation layer and a body in the gate trench includes: sequentially depositing an isolation material and a semiconductor material in the gate trench through the second hole to form the isolation layer and the body.

[0016] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above, and a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

[0017] On the other hand, an electronic device is provided, including the storage system described above. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0019] Figure 1 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0020] Figure 2 This is a top view of a semiconductor structure according to some embodiments;

[0021] Figure 3 for Figure 2 A splicing diagram of sections AA and BB;

[0022] Figure 4 A cross-sectional view of a semiconductor structure according to some embodiments;

[0023] Figure 5 This is a top view of a gate isolation structure according to some embodiments;

[0024] Figure 6 This is a schematic diagram of a gate isolation structure according to some embodiments;

[0025] Figure 7 A partial schematic diagram of the first end face according to some embodiments Figure 1 ;

[0026] Figure 8 A partial schematic diagram of the first end face according to some embodiments Figure 2 ;

[0027] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0028] Figure 10 This is a top view after the formation of the first stacked structure according to some embodiments;

[0029] Figure 11 for Figure 10 A splicing diagram of sections C1-C1 and C2-C2 in the image;

[0030] Figure 12 This is a top view after the first hole has been formed according to some embodiments;

[0031] Figure 13 for Figure 12 A splicing diagram of sections D1-D1 and D2-D2 in the image;

[0032] Figure 14 This is a top view after the trench structure has been formed according to some embodiments;

[0033] Figure 15 for Figure 14 A splicing diagram of sections E1-E1 and E2-E2 in the image;

[0034] Figure 16 A top view after the removal of the first sacrificial pillar located in the core area, according to some embodiments;

[0035] Figure 17 for Figure 16 A splicing diagram of sections F1-F1 and F2-F2 in the image;

[0036] Figure 18 This is a top view after the first slot has been formed according to some embodiments;

[0037] Figure 19 for Figure 18 A splicing diagram of sections G1-G1 and G2-G2 in the image;

[0038] Figure 20 A top view after the sacrificial material has been formed in the first septum according to some embodiments;

[0039] Figure 21 for Figure 20 A splicing diagram of sections H1-H1 and H2-H2 in the image;

[0040] Figure 22 A top view after removing the first sacrificial column located in the connection area according to some embodiments;

[0041] Figure 23 for Figure 22 A splicing diagram of sections I1-I1 and I2-I2 in the image;

[0042] Figure 24 This is a top view after the second partition has been formed according to some embodiments;

[0043] Figure 25 for Figure 24 A splicing diagram of sections J1-J1 and J2-J2 in the image;

[0044] Figure 26 A top view of the gate spacer after filling it with sacrificial material according to some embodiments;

[0045] Figure 27 for Figure 26 A splicing diagram of sections K1-K1 and K2-K2 in the image;

[0046] Figure 28 This is a schematic diagram of the structure of the support layer according to some embodiments;

[0047] Figure 29 This is a top view after the support layer has been formed according to some embodiments;

[0048] Figure 30 for Figure 29A splicing diagram of the L1-L1 section and the L2-L2 section;

[0049] Figure 31 for Figure 29 A splicing diagram of the L3-L3 section and the L4-L4 section;

[0050] Figure 32 A top view after removing sacrificial material from the gate spacer according to some embodiments;

[0051] Figure 33 for Figure 32 A splicing diagram of sections M1-M1 and M2-M2 in the diagram;

[0052] Figure 34 This is a top view after sacrificial material has been filled into the first filling space according to some embodiments;

[0053] Figure 35 for Figure 34 A splicing diagram of sections N1-N1 and N2-N2 in the image;

[0054] Figure 36 This is a top view after the second filling space has been formed according to some embodiments;

[0055] Figure 37 for Figure 36 A splicing diagram of sections O1-O1 and O2-O2 in the image;

[0056] Figure 38 A top view after removing sacrificial material from the first filling space according to some embodiments;

[0057] Figure 39 for Figure 38 A splicing diagram of sections P1-P1 and P2-P2 in the image;

[0058] Figure 40 This is a top view after the gate layer has been formed according to some embodiments;

[0059] Figure 41 for Figure 40 A splicing diagram of sections Q1-Q1 and Q2-Q2 in the image;

[0060] Figure 42 This is a top view after forming a gate isolation structure according to some embodiments;

[0061] Figure 43 for Figure 42 A splicing diagram of sections R1-R1 and R2-R2 in the diagram;

[0062] Figure 44 This is a block diagram of a storage system according to some embodiments;

[0063] Figure 45 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0064] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0065] In the description of this disclosure, it should be understood that the terms "upper", "lower", "front", "rear", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0066] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0067] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0068] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0069] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0070] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0071] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0072] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0073] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0076] The term "three-dimensional memory" refers to a semiconductor structure formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0077] Figure 1 This is a cross-sectional view of a three-dimensional memory according to some embodiments. It should be noted that... Figure 1 In this context, the three-dimensional memory 10 is located in the XYZ three-dimensional coordinate system and extends in the XZ plane. The first direction X and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line, and the third direction Z is, for example, the extension direction of the bit line. The second direction Y is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XZ plane.

[0078] As used in embodiments of this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of the semiconductor device in the third direction Z when the substrate or source layer SL is located in the lowest plane of the semiconductor device in the third direction Z. The same concepts are applied throughout the embodiments of this disclosure to describe spatial relationships.

[0079] In order to show the structure of the device more clearly, in Figure 1 The image shows a view of the core region CA and a view of the connecting region SS. The view of the core region CA is based on the left coordinate system, while the view of the connecting region SS is based on the right coordinate system. That is, the view of the core region CA shows the cross-sectional structure along the Z direction, while the view of the connecting region SS shows the cross-sectional structure along the X direction.

[0080] See Figure 1 Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and an array interconnect layer 290. The three-dimensional memory 10 may also include peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the array interconnect layer 290 away from the source layer SL.

[0081] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0082] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell string 400”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0083] See also Figure 1 In some embodiments, the array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor in the memory cell string 400.

[0084] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT, drain select gate contacts, and gate line contacts 293. The bit line contacts BL-CNT are coupled to bit lines, the drain select gate contacts are coupled to drain select gates, and the gate line contacts 293 are coupled to the gate layer. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include multiple interconnect lines, such as bit lines, and word line interconnect lines coupled to word lines. The materials of the first interconnect conductor layers 291 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other suitable materials.

[0085] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device (e.g., semiconductor structure 200), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0086] For example, in some embodiments, peripheral device 100 may include substrate 110, transistor 120 disposed on substrate 110, and peripheral interconnect layer 130 disposed on substrate 110. Peripheral circuitry may include transistor 120.

[0087] The substrate 110 may be made of monocrystalline silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0088] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 includes insulating materials, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0089] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. In some examples, because the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to enable the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled together.

[0090] This disclosure also provides a semiconductor structure 200 in some embodiments, which can serve as the semiconductor structure 200 in the aforementioned three-dimensional memory 10, or the semiconductor structure 200 can serve as the aforementioned three-dimensional memory 10. The following description, in conjunction with... Figures 2 to 8 The semiconductor structure 200 in some embodiments will be explained and described.

[0091] Figure 2 This is a top view of a semiconductor structure according to some embodiments. Figure 3 for Figure 2 A splicing diagram of sections AA and BB. Figure 3 The section to the left of the dashed line is the AA cross-section. Figure 3 The section to the right of the dashed line is the BB cross-section. Please refer to it. Figure 1 , Figure 2 and Figure 3 In some embodiments, the semiconductor structure 200 includes a stacked structure 40 and a gate isolation structure 50. The stacked structure 40 includes a core region CA and a connection region SS, the core region CA and the connection region SS being arranged along a first direction X, for example, the core region CA and the connection region SS being adjacent to each other along the first direction X.

[0092] The stacked structure 40 includes a gate stacked structure 410 and a dielectric stacked structure 420. The gate stacked structure 410 includes a plurality of gate layers 411 and a plurality of first dielectric layers 412 alternately stacked along the second direction Y. The dielectric stacked structure 420 includes a plurality of first dielectric layers 412 and a plurality of second dielectric layers 421 alternately stacked along the second direction Y. A portion of the gate stacked structure 410 is located in the core region CA, and the dielectric stacked structure 420 and a portion of the gate stacked structure 410 are located in the connection region SS. Exemplarily, the second dielectric layer 421 may be located on the same layer as the gate layer 411, that is, the second dielectric layer 421 may be located on the same plane as the gate layer 411.

[0093] Here, alternating stacking means that the gate layer 411 and the first dielectric layer 412 are stacked and arranged alternately; for example, along the direction from the bottom layer to the top layer of the gate stack structure 410, a gate layer 411 is first set, a first dielectric layer 412 is then set on the gate layer 411, and then another gate layer 411 is set on the first dielectric layer 412, and so on, to form the gate stack structure 410.

[0094] The specific number of stacked layers of gate layer 411 / first dielectric layer 412 can be set according to actual conditions. Gate layer 411 can be made of conductive material, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide, or other suitable conductive material.

[0095] Both the first dielectric layer 412 and the second dielectric layer 421 can be made of insulating materials. The insulating materials can include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0096] The core area CA has storage capabilities. For example, refer to... Figure 2 The semiconductor structure 200 may include multiple channel structures 413, which penetrate the gate stack structure 410. The channel structures 413 may be located in the core region CA and the connection region SS. In some embodiments, the channel structure 413 located in the core region CA may be used for data storage. For example, the channel structure 413 may be generally columnar, such as an oxide-nitride-oxide-polysilicon (OxiDe-NitriDe-OxiDe-Poly, ONOP) structure may be sequentially stacked. In this case, the material of the channel barrier layer may include, for example, silicon oxide; the material of the storage layer may include, for example, silicon nitride; the material of the tunneling layer may include, for example, silicon oxide; and the material of the channel layer may include, for example, polysilicon. In the above steps, thin film deposition processes such as CVD, PVD, or ALD may also be used to form a filling layer, such as silicon oxide, within the channel hole 602 where the storage layer and channel layer are formed. The channel structure 413 having the channel barrier layer, storage layer, tunneling layer, channel layer, and filling layer may be referred to as an "ONOPO" structure. The gate layer 411 is used to control the channel structure 413. The gate layer 411 can be led out to the corresponding control circuit in the connection area SS, thereby realizing functions such as reading, erasing, writing, and programming.

[0097] In some other embodiments, the channel structure 413 located in the connection region SS may include a virtual channel structure. Of course, in other embodiments, multiple virtual channel structures may also be located in the core region CA; this embodiment does not impose such limitations. The virtual channel structure may be the same as or different from the channel structure 413; this embodiment does not impose such limitations. It should be noted that the virtual channel structure may not actually be used as a storage unit, but rather serves to provide mechanical support and / or load balancing for the semiconductor structure 200.

[0098] In this embodiment, reference Figure 2 and Figure 3 The semiconductor structure 200 also includes a gate isolation structure 50, which extends along a first direction X and penetrates along a second direction Y through the gate stack structure 410 located in the core region CA and the gate stack structure 410 located in the connection region SS. It should be noted that the fact that the gate isolation structure 50 extends along the first direction X and penetrates the core region CA and the connection region SS means that the constituent materials of the gate isolation structure 50 are continuous, coherent, and uninterrupted in the first direction X.

[0099] In some embodiments, reference Figure 2 and Figure 3 The gate isolation structure 50 can be integrally molded, meaning that a complete structure is formed in a single process. For example, the gate isolation structure 50 may consist only of insulating material. The steps for forming the gate isolation structure 50 include completely filling the gate trench 640 with insulating material, such as silicon oxide. The gate trench 640 extends along the second direction Y through the gate stack structure 410 located in the core region CA and the gate stack structure 410 located in the connection structure, and the gate trench 640 is connected, thus forming a gate isolation structure 50 extending along the first direction X. In this embodiment, the shape of the sidewalls of the gate isolation structure 50 depends on the shape of the gate trench 640. For example, the sidewalls of the gate isolation structure 50 may include multiple arcuate surfaces connected along the first direction X.

[0100] In some other embodiments, the gate isolation structure 50 may include an isolation layer 520 and a body 510. The body 510 extends along a first direction X and penetrates along a second direction Y through the gate stack structure 410 located in the core region CA and the gate stack structure 410 located in the connection region SS. It should be noted that the body 510 extends along the first direction X and passes through the core region CA and the connection region SS, meaning that the constituent materials of the body 510 are continuous, coherent, and uninterrupted in the first direction X. The isolation layer 520 is located between the body 510 and the gate stack structure 410. The isolation layer 520 may be made of an insulating material, which can be as described in the above embodiments and will not be repeated here. The body 510 may be made of a conductive material, which can be as described in the above embodiments and will not be repeated here. Conductive materials, such as metals, generally have greater stress than insulating materials. Therefore, by setting the main body 510, it is beneficial to improve the structural stability and support capability of the gate isolation structure 50, thereby better supporting the semiconductor structure 200 and preventing the gate stack structure located on both sides of the gate isolation structure 50 along the third direction Z from bending and deformation, thereby improving the structural stability of the semiconductor structure 200.

[0101] In this embodiment, the sidewall of the main body 510 includes a plurality of first arcuate surfaces 5101 connected along a first direction X. The plurality of first arcuate surfaces 5101 are sequentially connected along the first direction X. For example, if the center of the arc of the plurality of first arcuate surfaces 5101 is located inside the main body 510, then the first arcuate surface 5101 is an outwardly protruding arc 531. The curvature of the plurality of first arcuate surfaces 5101 can be the same or different; this embodiment does not limit this. The isolation layer 520 can be disposed in conjunction with the sidewall of the main body 510, and correspondingly, the isolation layer 520 can also include a plurality of arcuate surfaces connected along the first direction X.

[0102] Here, during the fabrication of the gate isolation structure 50, a gate isolation trench can be formed by enlarging multiple vias. The sidewall edge shape of the gate isolation trench is arc-shaped. Correspondingly, the sidewalls of the isolation layer 520 and the main body 510, formed sequentially in the gate isolation trench, also have multiple first arc-shaped surfaces 5101 connected along the first direction X. This allows for easier formation of a gate isolation trench connected along the first direction X by setting the position, number, and spacing of multiple vias during the fabrication of the gate isolation structure 50, thus simplifying the fabrication process of the gate isolation structure 50.

[0103] In this embodiment, the main body 510 extends along the first direction X, and the main body 510 is continuous, coherent, and uninterrupted along the first direction X. The main body 510 may be integrally molded. The isolation layer 520 also extends along the first direction X, and the isolation layer 520 is continuous, coherent, and uninterrupted along the first direction X. The isolation layer 520 may be integrally molded.

[0104] With the above configuration, the gate isolation structure 50 extends along the first direction X and penetrates the gate stack structure 410 located in the core region CA and the gate stack structure 410 located in the connection region SS along the second direction Y. This is beneficial for better isolating the gate layers 411 located on both sides of the gate isolation structure 50 along the third direction Z, preventing short circuits in the gate layers 411 located on both sides of the gate isolation structure 50 along the third direction Z, improving the isolation capability of the gate isolation structure 50 for the gate layers 411, and thus improving the storage stability of the semiconductor structure 200.

[0105] In some embodiments, reference Figure 3 and Figure 4 The main body 510 includes a first end face 511 and a second end face 512 disposed opposite to each other along the second direction Y, that is, the first end face 511 and the second end face 512 are respectively the surfaces of the two ends of the main body 510 in the second direction Y. (Reference) Figure 3 and Figure 4 The first end face 511 is the top end face of the main body 510, and the second end face 512 is the bottom end face of the main body 510. It should be noted that the first end face 511 and the second end face 512 are the surfaces of the two ends of the main body 510 in the second direction Y, respectively, and the specific positions of the first end face 511 and the second end face 512 are determined according to the shape of the main body 510. In some examples, such as... Figure 3 and Figure 4 As shown, the second end face 512 is the end face of the bottom of the main body 510. In some other examples, the main body 510 may not be... Figure 3 and Figure 4 The regular structure shown, for example in Figure 3 and Figure 4 The bottom end face of the main body 510 also has a protruding structure. In this case, the second end face 512 can be the bottom end face of the protruding structure. However, the structural morphology of the main body 510 in the semiconductor structure 200 provided in this disclosure is not limited to the structural morphology of the main body 510 in this embodiment. When determining the first end face 511 and the second end face 512 of the main body 510, the end faces at both ends of the main body 510 along the second direction Y can be respectively determined as the first end face 511 and the second end face 512.

[0106] Continue to refer to Figure 3 and Figure 4 and combined Figure 5 and Figure 6 In the first direction X, the first end face 511 includes alternating planes 5111 and second arcuate surfaces 5112. For example, starting from one end of the first end face 511 along the first direction X, planes 5111, second arcuate surfaces 5112, planes 5111, second arcuate surfaces 5112 are arranged sequentially, and so on, with planes 5111 and second arcuate surfaces 5112 alternating. The number of planes 5111 and second arcuate surfaces 5112 is not limited in this disclosure. In the second direction Y, the maximum distance d1 between the second arcuate surface 5112 and the second end face 512 is equal to the distance d2 between the planes 5111 and the second end face 512.

[0107] In this embodiment, reference Figure 8 The orthographic projection of the main body 510 onto the third direction Z is rectangular. The orthographic projection of the second arcuate surface 5112 onto the first direction X is arcuate. The orthographic projection of the second arcuate surface 5112 onto the second direction Y is rectangular. The orthographic projection of the second arcuate surface 5112 onto the third direction Z is rectangular.

[0108] It should be noted that the maximum distance d1 between the second arcuate surface 5112 and the second end face 512 in the second direction Y is the distance from the vertex of the second arcuate surface 5112 to the second end face 512, and this distance is equal to the distance d2 between the plane 5111 and the second end face 512 in the second direction Y. Therefore, the second arcuate surface 5112 is an upwardly convex second arcuate surface 5112, rather than a downwardly concave second arcuate surface 5112. Furthermore, the plane 5111 is tangent to the second arcuate surface 5112.

[0109] refer to Figure 5 , Figure 6 and Figure 7 When preparing the gate isolation structure 50, a support layer can be formed above the gate partition trench to prevent the stacked structure of the gate partition trench from tilting or collapsing along the third direction Z. After the gate isolation structure 50 is formed in the gate partition trench, the first end face 511 that is shielded by the support layer forms the second arc-shaped surface 5112, and the first end face 511 that is not shielded by the support layer forms the plane 5111.

[0110] refer to Figure 3 and Figure 4Since the maximum distance d1 between the second arcuate surface 5112 and the second end surface 512 in the second direction Y is equal to the distance d2 between the plane 5111 and the second end surface 512, the blocking height of the gate isolation structure 50 (part of the first end surface 511 being the plane 5111) on the gate stack structure 410 is the same as the blocking height of the gate isolation structure 50 (part of the first end surface 511 being the second arcuate surface 5112) on the gate stack structure 410. Therefore, the isolation capability of the gate isolation structure 50 on the gate stack structure 410 in the third direction Z remains unchanged. At the same time, fabricating a portion of the first end surface 511 as the second arcuate surface 5112 helps reduce the amount of material used, thereby saving costs. Furthermore, it also helps to expand the process fabrication window of the gate isolation structure 50 and reduce the fabrication difficulty of the gate isolation structure 50.

[0111] In some embodiments, reference Figure 3 , Figure 7 and Figure 8 The size d3 of the isolation layer 520 located between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z is less than or equal to the spacing d4 between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z.

[0112] Here, the dimension d3 of the isolation layer 520 in the third direction Z refers to the thickness of the isolation layer 520 in the third direction Z. The interval d4 between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z refers to the vertical distance between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z.

[0113] It should be noted that the isolation layer 520 located between the second arcuate surface 5112 and the gate stack structure 410 has many dimensions d3 in the third direction Z, and the spacing d4 between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z also has many dimensions d4. Here, the dimension d3 of the isolation layer 520 located between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z and the spacing d4 between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z are compared on the same third direction Z. For example, by using an XZ cross section, the second arc-shaped surface 5112, the gate stack structure 410, and the isolation layer 520 located between the second arc-shaped surface 5112 and the gate stack structure 410 are cut off. Then, the dimension d3 of the isolation layer in the third direction Z and the perpendicular distance between the second arc-shaped surface 5112 and the gate stack structure 410 in the third direction Z are compared. At this time, the dimension d3 of the isolation layer 520 located between the second arc-shaped surface 5112 and the gate stack structure 410 in the third direction Z is less than or equal to the spacing d4 between the second arc-shaped surface 5112 and the gate stack structure 410 in the third direction Z.

[0114] For example, in the direction from the second end face 512 to the first end face 511, the isolation layer 520 located between the second arcuate surface 5112 and the gate stack structure 410 can gradually become thinner.

[0115] In this embodiment, the isolation layer 520 covers the sidewall of the gate stack structure 410. Since the dimension d3 of the isolation layer 520 located between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z is less than or equal to the distance d4 between the second arcuate surface 5112 and the gate stack structure 410 in the third direction Z, the isolation layer 520 does not completely fill the gap between the second arcuate surface 5112 and the gate stack structure, resulting in a gap between the isolation layer 520 and the main body 510. This arrangement creates a gap between the isolation layer 520 and the main body 510, which is beneficial for reserving space for other materials. For example, a material layer can be formed above the semiconductor structure 200, covering the top of the semiconductor structure 200 and extending into the gap, thereby providing support for the semiconductor structure 200 and improving its structural stability. Filling the gap with a material with high adhesive strength also helps improve the adhesion between the main body 510 and the isolation layer 520.

[0116] In some embodiments, reference Figure 7 and Figure 8 The semiconductor structure 200 also includes a third dielectric layer 530. The third dielectric layer 530 is located on one side of the stacked structure along the second direction Y, and the third dielectric layer 530 has a protrusion 531 located between the isolation layer 520 and the body 510.

[0117] For example, the material of the third dielectric layer 530 may include an insulating material, such as silicon nitride. The material of the third dielectric layer 530 is different from the material of the insulating layer 520. The material of the third dielectric layer 530 may be the same as the material of the second dielectric layer 421, and this disclosure is not limiting in this regard.

[0118] With the above configuration, the protrusion 531 of the third dielectric layer 530 extends between the isolation layer 520 and the main body 510, which helps to provide support for the semiconductor structure 200 and thereby improves the structural stability of the semiconductor structure 200.

[0119] In some embodiments, reference Figure 3 , Figure 4 , Figure 7 and Figure 8Referring to the figure, the main body 510 includes a first end face 511 and a second end face 512 disposed opposite each other along the second direction Y. The distance between the second end face 512 and the third dielectric layer 530 is greater than the distance between the first end face 511 and the third dielectric layer 530, so the second end face 512 is farther away from the third dielectric layer 530 than the first end face 511. For example, the first end face 511 can be the end face of the top of the main body 510, and the second end face 512 can be the end face of the bottom of the main body 510.

[0120] The protrusion 531 has a first end 5311 and a second end 5312 arranged along the second direction Y, with the second end 5312 being closer to the second end face 512 than the first end 5311. The dimension d5 of the first end 5311 in the third direction Z is greater than the dimension d6 of the second end 5312 in the third direction Z. Here, the dimension d5 of the first end 5311 in the third direction Z can be understood as the width of the first end 5311 in the third direction Z. The dimension d6 of the second end 5312 in the third direction Z can be understood as the width of the second end 5312 in the third direction Z.

[0121] In this embodiment, the isolation layer 520 that contacts the first end 5311 and the isolation layer 520 that contacts the second end 5312 are different in that the isolation layer 520 that contacts the first end 5311 is thinner and the isolation layer 520 that contacts the second end 5312 is thicker.

[0122] With the above configuration, the protrusion 531 can contact the main body 510 and the isolation layer 520. The protrusion 531 fills the gap between the main body 510 and the isolation layer 520. By eliminating the gap between the main body 510 and the isolation layer 520, the structural stability of the semiconductor structure 200 is further improved.

[0123] In some embodiments, reference Figure 8 The semiconductor structure 200 also includes a fourth dielectric layer 540. The fourth dielectric layer 540 is located between the third dielectric layer 530 and the stacked structure, between the protrusion 531 and the isolation layer 520, and between the protrusion 531 and the body 510.

[0124] For example, the constituent material of the fourth dielectric layer 540 may include an insulating material, which may be as described in the above embodiments and will not be repeated here. The constituent material of the fourth dielectric layer 540 is different from that of the third dielectric layer 530. In this embodiment, the material of the fourth dielectric layer 540 is a nitride, and the material of the third dielectric layer 530 is an oxide.

[0125] With the above configuration, the gap between the main body 510 and the isolation layer 520 is filled by the third dielectric layer 530 and the fourth dielectric layer 540. By eliminating the gap between the main body 510 and the isolation layer 520, the structural stability of the semiconductor structure 200 is further improved. Furthermore, forming the third dielectric layer 530 and the fourth dielectric layer 540 on one side of the stacked structure along the second direction Y also helps to protect the morphological integrity of the stacked structure.

[0126] This disclosure also provides a method for fabricating a semiconductor structure 200 in some embodiments, which will be described below in conjunction with... Figures 9 to 43 The preparation method of a semiconductor structure 200 is explained.

[0127] like Figure 9 As shown, the method for fabricating the semiconductor structure 200 includes: S1 to S5.

[0128] S1. A first stacked structure is formed, the first stacked structure includes a core region and a connecting region, the core region and the connecting region are arranged along a first direction, the first stacked structure includes multiple sacrificial layers and multiple dielectric layers alternately stacked along a second direction; wherein, the second direction is the thickness direction of the dielectric layer, and the first direction intersects with the second direction.

[0129] The embodiments disclosed herein are illustrated using the example of the first direction X, the second direction Y, and the third direction Z being mutually perpendicular.

[0130] In this step, refer to Figure 10 and Figure 11 The first stacked structure 60 can be formed by alternately forming a sacrificial layer 620 and a dielectric layer 630 on the substrate 610 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0131] Since part of the sacrificial layer 620 needs to be removed in subsequent fabrication processes, the material of the sacrificial layer 620 needs to have an etching selectivity ratio with the material of the dielectric layer 630. For example, different materials can be selected to prepare the sacrificial layer 620 and the dielectric layer 630 in order to selectively remove the sacrificial layer 620.

[0132] For example, the material of the dielectric layer 630 may include oxides, and the material of the sacrificial layer 620 may include nitrides.

[0133] For example, the substrate 610 may be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. Alternatively, the substrate material may also be a compound semiconductor. For example, the substrate may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. Alternatively, the substrate 610 may also be made of other semiconductor materials commonly used in the art, and this disclosure does not limit the scope of the embodiments.

[0134] In this embodiment, the substrate 610 can provide support for the fabrication of the first stacked structure 60, and alternatively, the substrate 610 can be removed in subsequent fabrication processes.

[0135] In other embodiments, reference continues. Figure 10 and Figure 11 A second stacked structure 70 can be formed on the substrate 610. The second stacked structure 70 includes a fifth dielectric layer 710 and a semiconductor layer 720 stacked along a first direction X. The second stacked structure 70 is stacked with the first stacked structure 60 along the first direction X, and the second stacked structure 70 is located between the substrate 610 and the first stacked structure 60. For example, the fifth dielectric layer 710 and the semiconductor layer 720 can be sequentially formed on the substrate 610 using CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the second stacked structure 70. In this case, when forming the first stacked structure 60 on the second stacked structure 70, the dielectric layer needs to be formed first to ensure that the gate layer 411 and the semiconductor layer 720 are insulated from each other.

[0136] For example, the material of the fifth dielectric layer 710 includes an insulating material. The material of the fifth dielectric layer 710 can be the same as the material of the dielectric layer, for example, the material of the fifth dielectric layer 710 may also include oxides. Of course, the material of the fifth dielectric layer 710 can also be different from the material of the dielectric layer, and this embodiment does not limit this.

[0137] For example, the material of the semiconductor layer 720 may include polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compounds, and other suitable semiconductor materials.

[0138] The semiconductor layer 720 formed by the above preparation steps can protect the structure above the semiconductor layer 720 from being damaged in subsequent preparation processes (such as back-side processes to bring out the channel structure 413).

[0139] S2. Multiple first holes are formed, and the multiple first holes are spaced apart along a first direction. Some first holes penetrate the first stacked structure located in the core area, and some first holes penetrate the first stacked structure located in the connecting area.

[0140] refer to Figure 12 and Figure 13 and combined Figure 10 and Figure 11 In this step, multiple first holes 601 can be formed in one process. These first holes 601 can be arranged in a row along the first direction X, with intervals between them. Some first holes 601 penetrate the first stacked structure 60 located in the core region CA along the second direction Y, and some first holes 601 penetrate the first stacked structure 60 located in the connecting region SS along the second direction Y. By controlling the interval between adjacent first holes 601, the multiple first holes 601 can be interconnected during subsequent hole enlargement. Exemplarily, the multiple first holes 601 can also be arranged in multiple rows along the first direction X; this embodiment does not limit the number of first holes 601.

[0141] The first hole 601 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the first stacked structure 60. The patterned photoresist layer can expose the portion of the first stacked structure 60 used to form the first hole 601. A suitable etching process can be performed to remove the portion of the first stacked structure 60 used to form the first hole 601. For example, the etching process can include a dry etching process.

[0142] In some embodiments, a plurality of first holes 601 and a plurality of channel holes 602 may be formed in a single process. The plurality of channel holes 602 are arranged in an array along a first direction X and a third direction Z, and some channel holes 602 may be located on one side of the plurality of first holes 601 along the third direction Z. In subsequent fabrication processes, channel structures 413 or virtual channel structures may be formed in the channel holes 602.

[0143] In this embodiment, after forming the first via 601 and the channel via 602, sacrificial material can be filled into the first via 601 and the channel via 602 in a single process using CVD, PVD, ALD, or any combination thereof, to form a first sacrificial pillar 6011 and a second sacrificial pillar. Exemplarily, an etching process can be used to remove the second sacrificial pillar to expose the channel via 602. Exemplarily, when the material of the second sacrificial pillar includes carbon, the process for removing all the second sacrificial pillars within the channel via 602 may include ashing to remove all the second sacrificial pillars within the channel via 602.

[0144] refer to Figure 14 and Figure 15 The channel structure 413 and the virtual channel structure can be formed in the channel hole 602 by using CVD, PVD, ALD or any combination of thin film deposition processes.

[0145] S3. Remove part of the first stacked structure through multiple first holes to connect the multiple first holes and form a gate spacer.

[0146] refer to Figures 16 to 26 In this step, a portion of the first stacked structure 60 around the first hole 601 can be removed using a wet etching process, connecting adjacent first holes 601 and ultimately connecting all the first holes 601 to form a gate separator 640. For example, an acidic substance can be selected as the etchant, and the etchant is injected into each of the first holes 601. The etchant can uniformly etch the hole walls (i.e., the first stacked structure 60) of the first holes 601, thereby connecting adjacent first holes 601. By injecting the etchant into each of the first holes 601, the first stacked structure 60 between adjacent first holes 601 is removed, forming the gate separator 640. Since the rate at which the etchant removes the first stacked structure 60 is relatively uniform, it is beneficial to maintain the uniformity of the edge of the gate separator 640.

[0147] In some embodiments, reference Figure 16 , Figure 17 , Figure 18 and Figure 19 A portion of the first stacked structure 60 located in the core region CA can be removed through a portion of the first hole 601 to form a first slot 641.

[0148] In this step, an etchant can be injected into the first hole 601 located in the core region CA to remove part of the first stacked structure 60 located in the core region CA, so that the first hole 601 located in the core region CA is connected to form the first partition 641.

[0149] In some embodiments, a small amount of etching solution may be injected into the first septum 641 to remove a small amount of dielectric layer 630, thereby reducing the thickness of the dielectric layer 630 located on the wall of the first septum 641. This can be understood as the thinning of the thickness of the end of the dielectric layer 630 exposed in the first septum 641, resulting in a larger opening between adjacent dielectric layers 630, thereby exposing more of the sacrificial layer 620 in the first septum 641, so that the sacrificial layer 620 can be removed in subsequent fabrication processes.

[0150] In some other embodiments, reference is made to Figure 18 and Figure 19 A second stacked structure 70 is also disposed between the substrate 610 and the first stacked structure 60. Therefore, when the etching solution is injected into the first hole 601 located in the core region CA, part of the fifth dielectric layer 710 is also removed, exposing part of the semiconductor layer 720 to the first partition 641. A protective layer can be formed on the surface of the semiconductor layer 720 through the first partition 641 using an ALD process. The material of the protective layer includes, for example, silicon oxide, to protect the semiconductor layer 720 from damage in subsequent fabrication processes.

[0151] It is worth noting that when the material of the protective layer is the same as that of the dielectric layer, for example, when both the material of the protective layer and the material of the dielectric layer include silicon oxide, the step of forming the protective layer on the surface of the semiconductor layer 720 should be performed after the step of thinning the dielectric layer to prevent the protective layer from being accidentally removed.

[0152] After forming the first partition 641, refer to Figure 18 , Figure 19 , Figure 20 and Figure 21 It also includes: forming a second sacrificial layer 650 using CVD, PVD, ALD, or any combination thereof thin film deposition processes, the second sacrificial layer 650 covering the trench wall of the first partition 641. The first partition 641 is filled with a sacrificial material. The sacrificial material may be, for example, carbon or polycrystalline silicon with doped ions. Experiments have shown that phosphorus-doped polycrystalline silicon can be selected as the sacrificial material. Phosphorus-doped polycrystalline silicon has a different etching rate than the semiconductor layer 720, thus, the structural morphology of the semiconductor layer 720 can be preserved when removing the sacrificial material.

[0153] refer to Figure 22 , Figure 23 , Figure 24 and Figure 25 After forming the first partition 641, the method further includes: removing a portion of the first stacked structure 60 located in the connection region SS through a portion of the first hole 601 to form a second partition 642. The first partition 641 and the second partition 642 together constitute the gate partition 640.

[0154] In this step, a portion of the first stacked structure 60 located in the connection region SS can be removed through a partial first hole 601 to form a first partition 641. Exemplarily, an etchant can be injected into the first hole 601 located in the connection region SS to remove a portion of the first stacked structure 60 located in the connection region SS, making the first hole 601 connected and forming a second partition 642. At this time, a portion of the sacrificial material in the first partition 641 is exposed in the second partition 642 to ensure communication between the first partition 641 and the second partition 642, thereby forming a gate partition 640.

[0155] It should be noted that both the first partition 641 and the second partition 642 are formed by wet etching to enlarge the first hole 601, thereby connecting multiple first holes 601. Generally, in the XZ plane 5111, the shape of the first hole 601 is circular. Therefore, the trench walls of the gate partition 640 are formed as multiple arc-shaped edges connected in sequence.

[0156] After the second partition 642 is formed, a portion of the sacrificial layer 620 located in the connection region SS can be removed through the second partition 642 to form the first filling space 671. For example, a wet etching process can be used to inject etching solution into the second partition 642 to remove a portion of the sacrificial layer 620 located in the connection region SS.

[0157] In some embodiments, a small amount of etching solution may be injected into the second partition 642 to remove a small amount of dielectric layer, thereby reducing the thickness of the dielectric layer located on the wall of the second partition 642. This can be understood as the thickness of the end of the dielectric layer exposed in the second partition 642 being reduced, thus forming a larger opening between adjacent dielectric layers, so that the subsequent fabrication process can form the gate layer 411 in the first filling space 671.

[0158] In some other embodiments, a second stacked structure 70 is also provided between the substrate 610 and the first stacked structure 60. Therefore, when the etching solution is injected into the first hole 601 located in the connection region SS, part of the fifth dielectric layer 710 will also be removed, exposing part of the semiconductor layer 720 to the second trench 642.

[0159] In some embodiments, reference Figure 24 , Figure 25 , Figure 26 and Figure 27 After forming the first filling space 671, sacrificial material can be filled into the second slot 642 and the first filling space 671. The sacrificial material is, for example, carbon or phosphorus-doped polycrystalline silicon. This is so that the structural morphology of the semiconductor layer 720 is not damaged when the sacrificial material is removed in subsequent fabrication processes.

[0160] refer to Figure 28 , Figure 29 , Figure 30 and Figure 31 After the second partition 642 and the first filling space 671 are filled with sacrificial material, a support layer 660 is formed. The support layer 660 is located on one side of the first stacked structure 60 along the second direction Y. The support layer 660 has a plurality of second holes 661, which are spaced apart along the first direction X. The second holes 661 expose at least a portion of the gate partition 640.

[0161] In this step, a support layer 660 can be formed over the first stacked structure 60 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. In some embodiments, the gate spacer 640 is filled with sacrificial material, which facilitates the deposition of the support layer 660 over the first stacked structure 60. The second vias 661 expose at least a portion of the sacrificial material located in the gate spacer 640. A wet etching process can be used to inject etching solution into the plurality of second vias 661 to remove the sacrificial material in the gate spacer 640, thereby exposing at least a portion of the gate spacer 640 in the second vias 661.

[0162] For example, the material of the support layer 660 may include an insulating material, such as an oxide.

[0163] Since the gate spacer 640 penetrates the first stacked structure 60 along the second direction Y, and extends along the second direction Y through the core region CA and the connection region SS, the first stacked structure 60 located on both sides of the gate spacer 640 along the third direction Z may be at risk of bending, tilting, or even short-circuiting closer to the gate spacer 640. The support layer 660 prepared through the above steps can fix the top of the first stacked structure 60. The support layer 660 between two adjacent second holes 661 is similar to a "bridge 662" connecting the first stacked structures 60 located on both sides of the gate spacer 640 along the third direction Z, so that the support layer 660 can support the first stacked structure 60, prevent the first stacked structure 60 from bending or tilting closer to the gate spacer 640, and improve the stability and reliability of the first stacked structure 60. To facilitate observation of the structural changes, a schematic diagram of the structure without the support layer is shown in the following figures.

[0164] S4. Replace the sacrificial layer located in the core region and part of the sacrificial layer located in the connection region with the gate layer to form a gate stack structure.

[0165] In this step, refer to Figure 29 , Figure 30 and Figure 31 The sacrificial material can be filled in the first filling space 671 through a portion of the second hole 661 and the second septum 642. For example, the sacrificial material can be filled in the first filling space 671 using CVD, PVD, ALD, or any combination thereof thin film deposition process.

[0166] In some embodiments, reference Figure 32 and Figure 33 and combined Figure 28 The method for fabricating the semiconductor structure further includes forming a protective layer on the surface of the semiconductor layer 720 exposed in the gate spacer 640 through the second hole 661 and the gate spacer 640, so as to protect the semiconductor layer 720 from being damaged in subsequent fabrication steps.

[0167] refer to Figure 34 , Figure 35 , Figure 36 and Figure 37 After the first filling space 671 is filled with sacrificial material, the sacrificial layer 620 located in the core region CA is removed through part of the second hole 661 and the first slot 641 to form the second filling space 672.

[0168] In this step, for example, a wet etching process can be used to remove the sacrificial layer 620 located in the core region CA by injecting etching solution into part of the second hole 661 and the first septum 641.

[0169] It should be noted that the sacrificial material filling the first filling space 671 is different from the material of the sacrificial layer 620. For example, the material of the sacrificial layer 620 filling the first filling space 671 may include polysilicon or carbon, while the material of the sacrificial layer 620 may include nitrides, such as silicon nitride. With this configuration, the sacrificial material filling the first filling space 671 in this step can protect the sacrificial layer 620 located in the connection region SS from being removed.

[0170] In some embodiments, this step further includes removing the second sacrificial layer 650 covering the wall of the first partition 641.

[0171] refer to Figure 38 and Figure 39 After removing the sacrificial layer 620 located in the core region CA, the sacrificial material located in the first filling space 671 can be removed through part of the second hole 661 and the second partition 642, so that the first filling space 671, the second filling space 672 and the gate partition 640 are connected.

[0172] For example, when the sacrificial material located in the first filling space 671 includes carbon, the process for removing the sacrificial material located in the first filling space 671 may include ashing.

[0173] refer to Figure 40 and Figure 41 After connecting the first filling space 671, the second filling space 672 and the gate partition 640, a gate layer 411 is formed in the first filling space 671 and the second filling space 672 through the second hole 661 and the gate partition 640.

[0174] In this step, conductive materials can be deposited in the first filling space 671 and the second filling space 672 using, for example, CVD, PVD, ALD or any combination thereof, to form a gate layer 411, thereby forming a gate stack structure 410.

[0175] In this step, the sacrificial layer 620 that is not removed serves as the second dielectric layer 421 in some of the above embodiments, thereby forming the dielectric stack structure 420 in some of the above embodiments.

[0176] S5. An isolation layer and a body are sequentially formed in a gate trench. The body extends along the first direction and penetrates the gate stack structure located in the core region and the gate stack structure located in the connection region along the second direction. The sidewall of the body includes a plurality of first arcuate surfaces connected along the first direction. The isolation layer is located between the body and the gate stack structure.

[0177] refer to Figure 40 , Figure 41 , Figure 42 and Figure 43 and structure Figure 3 and Figure 4 In this step, CVD, PVD, ALD or any combination thereof thin film deposition processes can be used to sequentially deposit insulating material and semiconductor material in the gate trench 640 to form isolation layer 520 and body 510.

[0178] In some embodiments, this step includes: sequentially depositing an isolation material (e.g., silicon oxide) and a semiconductor material (e.g., polysilicon) in a gate trench 640 through a second hole 661 using an ALD process to form an isolation layer 520 and a body 510. Since the gate trench 640 is formed by injecting etchant into a plurality of first holes 601 to enlarge the apertures of the first holes 601 until the first holes 601 are connected, and generally, the first holes 601 are circular holes, the trench walls of the formed gate trench 640 include a plurality of sequentially connected arcuate surfaces. Therefore, in this step, the sidewalls of the isolation layer 520 and the body 510 formed in the gate trench 640 using the ALD process also have a plurality of sequentially connected arcuate surfaces. The arcuate surface of the sidewall of the body 510 is the first arcuate surface 5101.

[0179] In this step, since part of the support layer 660 shields part of the gate spacer 640 in the second direction Y, material is deposited into the gate spacer 640 through the second hole 661 to form the gate isolation structure 50. In the gate spacer 640 shielded by the support layer 660, the material cannot easily fill all the gaps, causing the first end face 511 of the gate isolation structure 50 at this location to form a second arc-shaped surface 5112. Meanwhile, the first end face 511 of the gate isolation structure 50 not shielded by the support layer 660 forms a flat surface 5111.

[0180] In some embodiments, reference Figure 40 , Figure 41 , Figure 42 and Figure 43 and structure Figure 3and Figure 4 The surface of the first stacked structure 60 can be planarized by chemical mechanical polishing (CMP) to remove the support layer 660, making the surface of the first stacked structure 60 flush with the surface of the gate isolation structure 50. Then, the plane 5111 of the first end face 511 of the gate isolation structure 50 and the second arcuate surface 5112 are tangent. In some examples, an insulating material can be deposited on the first stacked structure 60 using a deposition process to form a third dielectric layer 530. The third dielectric layer 530 has protrusions 531 located between the isolation layer 520 and the body 510. Alternatively, a deposition process can be used to deposit different insulating materials on the first stacked structure 60 to form a fourth dielectric layer 540 and a third dielectric layer 530. The third dielectric layer 530 has a protrusion 531 located between the insulating layer 520 and the body 510. The fourth dielectric layer 540 is located between the third dielectric layer 530 and the stacked structure, between the protrusion 531 and the insulating layer 520, and between the protrusion 531 and the body 510.

[0181] In some other embodiments, the support layer 660 may not be removed in order to reduce the number of process steps.

[0182] The semiconductor structure 200 prepared through the above embodiments has an isolation layer 520 of its gate isolation structure 50 prepared in one process, and a main body 510 of its gate isolation structure 50 prepared in one process. Both the extension layer and the main body 510 extend along the first direction X and are continuous, coherent, and uninterrupted. The gate isolation structure 50 has no barrier structure and extends along the second direction Y through the gate stack structure 410 located in the core region CA and the gate stack structure 410 located in the connection region SS. The gate isolation structure 50 prepared by the above method is beneficial for better isolating the gate layers 411 located on both sides of the gate isolation structure 50 along the third direction Z, preventing short circuits between the gate layers 411 located on both sides of the gate isolation structure 50 along the third direction Z, improving the isolation capability of the gate isolation structure 50 to the gate layers 411, and thus improving the storage stability of the semiconductor structure 200. Furthermore, by providing the support layer 660, it is beneficial to prevent the gate stack structure 410 and the dielectric stack structure 420 from bending, tilting, and short-circuiting, thereby improving the stability and reliability of the semiconductor structure 200. In addition, the above fabrication process does not require additional board opening or additional processes, which helps to reduce the fabrication difficulty and has a cost advantage.

[0183] Figure 44 This is a block diagram of a storage system according to some embodiments. Figure 45 This is a block diagram of a storage system according to some other embodiments.

[0184] Please see Figure 44 and Figure 45 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 as described in some of the embodiments above. The controller 20 is coupled to the three-dimensional memory 10 to control the storage of data in the three-dimensional memory 10. The three-dimensional memory 10 includes the semiconductor structure 200 described in some of the embodiments above.

[0185] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0186] In some embodiments, see Figure 44 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0187] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0188] In other embodiments, see Figure 45 The storage system 1000 includes a controller 20 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0189] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0190] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0191] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0192] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0193] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0194] Since the three-dimensional memory 10 includes the semiconductor structure 200 provided in some of the above embodiments, the memory system 1000 also has good stability and reliability.

[0195] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0196] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache. If the electronic device includes the storage system 1000 described above, then the electronic device also possesses good stability and reliability.

[0197] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A stacked structure includes a core region and a connection region, the core region and the connection region being arranged along a first direction; the stacked structure includes a gate stacked structure and a dielectric stacked structure, the gate stacked structure including a plurality of gate layers and a plurality of first dielectric layers alternately stacked along a second direction, the dielectric stacked structure including a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked along the second direction; a portion of the gate stacked structure is located in the core region, and the dielectric stacked structure and a portion of the gate stacked structure are located in the connection region; A gate isolation structure includes an isolation layer and a body, the body extending along a first direction and penetrating along a second direction through the gate stack structure located in the core region and the gate stack structure located in the connection region, the isolation layer being located between the body and the gate stack structure; the sidewall of the body includes a plurality of first arcuate surfaces connected along the first direction; The first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The main body includes a first end face and a second end face disposed opposite to each other along the second direction. In the first direction, the first end face includes alternating planes and arc-shaped surfaces. In the second direction, the maximum distance between the second arcuate surface and the second end face is equal to the distance between the plane and the second end face.

3. The semiconductor structure according to claim 2, characterized in that, The size of the isolation layer located between the second arcuate surface and the gate stack structure in the third direction is less than or equal to the spacing between the second arcuate surface and the gate stack structure in the third direction; the third direction intersects the plane containing the first direction and the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A third dielectric layer is located on one side of the stacked structure along the second direction, and the third dielectric layer has a protrusion located between the insulating layer and the body.

5. The semiconductor structure according to claim 4, characterized in that, The main body includes a first end face and a second end face disposed opposite to each other along the second direction, wherein the spacing between the second end face and the third dielectric layer is greater than the spacing between the first end face and the third dielectric layer; The protrusion has a first end and a second end arranged along a second direction, the second end being closer to the second end face than the first end; the dimension of the first end in the third direction is greater than the dimension of the second end in the third direction; The third direction intersects the plane containing the first direction and the second direction.

6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: The fourth dielectric layer is located between the third dielectric layer and the stacked structure, between the protrusion and the isolation layer, and between the protrusion and the main body.

7. A method for fabricating a semiconductor structure, characterized in that, include: A first stacked structure is formed, the first stacked structure including a core region and a connecting region, the core region and the connecting region being arranged along a first direction, the first stacked structure including a plurality of sacrificial layers and a plurality of dielectric layers alternately stacked along a second direction; wherein, the second direction is the thickness direction of the dielectric layers, and the first direction intersects the second direction; A plurality of first holes are formed, the plurality of first holes being spaced apart along a first direction, some of the first holes penetrating the first stacked structure located in the core region, and some of the first holes penetrating the first stacked structure located in the connecting region; By removing a portion of the first stacked structure through the plurality of first holes, the plurality of first holes are connected to form a gate spacer. The sacrificial layer located in the core region and a portion of the sacrificial layer located in the connection region are replaced with gate layers to form a gate stack structure; An isolation layer and a body are sequentially formed in the gate trench. The body extends along the first direction and penetrates the gate stack structure located in the core region and the gate stack structure located in the connection region along the second direction. The sidewall of the body includes a plurality of first arcuate surfaces connected along the first direction. The isolation layer is located between the body and the gate stack structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of the gate spacer includes: By partially removing the first layer structure located in the core region through the first hole, a first partition groove is formed. The first compartment is filled with sacrificial material; By partially removing part of the first layer structure located in the connection area through the first hole, a second partition is formed, wherein the first partition and the second partition together constitute the gate partition. A support layer is formed on one side of the first stacked structure along the second direction. The support layer has a plurality of second holes spaced apart along the first direction, and the second holes expose at least a portion of the gate spacer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After the formation of the second slot and before the formation of the support layer, the method further includes: The second septum removes a portion of the sacrificial layer located in the connection area to form a first filling space; The step of replacing the sacrificial layer located in the core region and a portion of the sacrificial layer located in the connection region with a gate layer includes: Sacrificial material is filled into the first filling space through a portion of the second hole and the second slot; The sacrificial layer located in the core region is removed through a portion of the second hole and the first slot to form a second filling space; By partially passing through the second hole and the second slot, the sacrificial material located in the first filling space is removed, so that the first filling space, the second filling space and the gate slot are connected; A gate layer is formed in the first filling space and the second filling space through the second hole and the gate spacer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The process of sequentially forming an isolation layer and a body in the gate trench includes: Through the second hole, an isolation material and a semiconductor material are sequentially deposited in the gate trench to form the isolation layer and the body.

11. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-6; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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