Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are provided. The memory device includes a first source line, a first drain line, a charge storage layer, a first word line, and a first channel layer. The charge storage layer is laterally disposed between the first word line and the first channel layer. The first word line and the first channel layer extend along a second direction perpendicular to a first direction. The first source line and the first drain line pass through the first channel layer. The first channel layer laterally surrounds the first source line and the first drain line. The first source line and the first drain line extend along the first direction.

Description

Technical Field

[0001] This invention relates to a memory device and a method for manufacturing the same. In particular, this invention relates to a method for manufacturing a NOR memory device. Background Technology

[0002] NOR flash memory is a commonly used type of flash memory in the industry. Its fast random access capability makes it particularly suitable for storing and executing program code. With the miniaturization of manufacturing processes, many manufacturers are actively developing new memory structures to reduce the size of semiconductor devices without compromising memory performance. Currently, high-density and highly integrated three-dimensional (3D) memory structures are receiving increasing attention and are becoming a key direction for advancing memory technology. Summary of the Invention

[0003] According to some embodiments of the present invention, a memory device includes a first source line, a first drain line, a charge storage layer, a first word line, and a first channel layer. The first source line and the first drain line extend along a first direction. The first word line and the first channel layer extend along a second direction perpendicular to the first direction. The first source line and the first drain line pass through the first channel layer, and the first channel layer laterally surrounds the first source line and the first drain line. The charge storage layer is laterally disposed between the first word line and the first channel layer.

[0004] According to some embodiments of the present invention, a method for manufacturing a memory device includes the following steps: forming a first channel layer, a second channel layer, and a spacer structure, wherein the first channel layer and the second channel layer are arranged along a first direction and separated from each other by the spacer structure; etching the sidewalls of the first channel layer and the second channel layer to form a first recess and a second recess; forming a charge storage layer in the first recess and the second recess; forming a first conductive material layer on the charge storage layer; etching the first conductive material layer to form a first word line and a second word line, wherein the charge storage layer is laterally disposed between the first word line and the first channel layer, and laterally disposed between the second word line and the second channel layer; forming a plurality of first openings through the first channel layer and the second channel layer; forming a first source line and a first drain line in the plurality of first openings, wherein the first source line and the first drain line extend along a first direction, and the first channel layer and the second channel layer laterally surround the first source line and the first drain line.

[0005] To make the foregoing easier to understand, several embodiments are described in detail below with reference to the illustrations. Attached Figure Description

[0006] Figures 1A to 1C Various perspective views of a memory device according to some embodiments of the present disclosure are shown;

[0007] Figures 2A to 17C Various perspective views are shown illustrating methods of manufacturing a memory device according to some embodiments of the present disclosure;

[0008] Figure 18 A perspective view of a memory device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0009] Figure 1A This is a top perspective view of the memory device 10. Figure 1B and Figure 1C This is a vertical cross-sectional view of the memory device 10, corresponding to... Figure 1A The positions of b-b' and c-c' along the middle line. Figure 1A The top view in the middle is consistent with Figure 1B and Figure 1C The position of line a-a' in the diagram. (Refer to...) Figures 1A to 1C The memory device 10 includes one or more source lines S1, one or more drain lines D1, a charge storage layer 130, a word line 142, and a channel layer 122. In this embodiment, the memory device 10 also includes spacers 112, 114, 116, a channel layer 124, one or more source lines S2, one or more drain lines D2, a dielectric structure 150, an isolation structure 160, semiconductor layers SM1 and SM2, and one or more auxiliary electrodes AE.

[0010] Spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116 are stacked sequentially along direction Z and on substrate 100. Channel layer 122 and channel layer 124 are separated by spacer 114. Spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116 extend along direction X, which is perpendicular to direction Z. In one embodiment, direction Z is perpendicular to the top surface 100t of substrate 100, while direction X is parallel to the top surface 100t of substrate 100.

[0011] In one embodiment, spacers 112, 114, and 116 are composed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a combination of the foregoing or other suitable dielectric materials. Channel layers 122 and 124 are composed of silicon or other suitable semiconductor materials. In one embodiment, channel layers 122 and 124 are silicon layers formed epitaxially. Compared to polycrystalline silicon, these epitaxial silicon layers reduce electron scattering problems and provide better conductivity.

[0012] In one embodiment, channel layer 122 and channel layer 124 may be referred to as nanosheets. For example, the thickness of each of channel layer 122 and channel layer 124 is in the range of 5 nm to 100 nm.

[0013] The isolation structure 160 is located on the substrate 100 and extends continuously from the spacer 112 through the channel layer 122, the spacer 114, and the channel layer 124 to the spacer 116. The isolation structure 160 is laterally disposed between the first portion 112a and the second portion 112b of the spacer 112, between the first portion 122a and the second portion 122b of the channel layer 122, between the first portion 114a and the second portion 114b of the spacer 114, between the first portion 124a and the second portion 124b of the channel layer 124, and between the first portion 116a and the second portion 116b of the spacer 116.

[0014] In one embodiment, the isolation structure 160 is composed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a combination of the foregoing or other suitable dielectric materials.

[0015] Source line S1, drain line D1, source line S2, and drain line D2 are located on substrate 100. Source line S1, drain line D1, source line S2, and drain line D2 extend in direction Z and from channel layer 122 to channel layer 124. Source line S1, drain line D1, source line S2, and drain line D2 pass through spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116. Each of spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116 laterally surrounds source line S1, drain line D1, source line S2, and drain line D2.

[0016] In this embodiment, the isolation structure 160 is laterally located between source lines S1 and S2, and between drain lines D1 and D2. Source line S1 and drain line D1 pass through the first portion 112a of spacer 112, the first portion 122a of channel layer 122, the first portion 114a of spacer 114, the first portion 124a of channel layer 124, and the first portion 116a of spacer 116. Conversely, source line S2 and drain line D2 pass through the second portion 112b of spacer 112, the second portion 122b of channel layer 122, the second portion 114b of spacer 114, the second portion 124b of channel layer 124, and the second portion 116b of spacer 116.

[0017] An auxiliary electrode AE ​​is located on the substrate 100 and embedded in the isolation structure 160. The auxiliary electrode AE ​​extends in the Z direction and passes through the spacer 112, the channel layer 122, the spacer 114, the channel layer 124, and the spacer 116. The auxiliary electrode AE ​​is laterally disposed between the first portion 112a and the second portion 112b of the spacer 112, between the first portion 122a and the second portion 122b of the channel layer 122, between the first portion 114a and the second portion 114b of the spacer 114, between the first portion 124a and the second portion 124b of the channel layer 124, and between the first portion 116a and the second portion 116b of the spacer 116.

[0018] In one embodiment, the source line S1, drain line D1, source line S2, drain line D2, and auxiliary electrode AE ​​are composed of metals, such as copper, tungsten, aluminum, gold, silver, or alloys of one or more of these metals, or combinations of at least two of these metals. In other embodiments, the source line S1, drain line D1, source line S2, drain line D2, and auxiliary electrode AE ​​may comprise other conductive materials, such as metal oxides or metal nitrides.

[0019] In one embodiment, the sidewalls of the source line S1 and the drain line D1 have protruding structures P1 extending toward the channel layer 122 and the channel layer 124. In one embodiment, the sidewalls of the source line S2 and the drain line D2 have protruding structures P2 extending toward the channel layer 122 and the channel layer 124. In one embodiment, the sidewall of the auxiliary electrode AE ​​has a protruding structure P3 extending toward the channel layer 122 and the channel layer 124.

[0020] Semiconductor layer SM1 is disposed on the sidewalls of source line S1, drain line D1, source line S2, and drain line D2. Semiconductor layer SM1 is located between source line S1 and channel layer 122, between drain line D1 and channel layer 122, between source line S1 and channel layer 124, between drain line D1 and channel layer 124, between source line S2 and channel layer 122, between drain line D2 and channel layer 122, between source line S2 and channel layer 124, and between drain line D2 and channel layer 124.

[0021] Semiconductor layer SM2 is disposed on the sidewall of auxiliary electrode AE. Semiconductor layer SM2 is located between auxiliary electrode AE ​​and channel layer 122 and between auxiliary electrode AE ​​and channel layer 124.

[0022] Semiconductor layers SM1 and SM2 have different doping types. For example, both semiconductor layers SM1 and SM2 are doped silicon semiconductors, one being n-type doped and the other p-type doped. In one embodiment, semiconductor layer SM1 is n-type doped, while semiconductor layer SM2 is p-type doped. Furthermore, in one embodiment, channel layers 122 and 124 are also p-type semiconductors; however, their doping concentration is lower than that of semiconductor layer SM2.

[0023] In one embodiment, the configuration of semiconductor layer SM1 facilitates the formation of ohmic contacts between the source line and the channel layer, and between the drain line and the channel layer. Similarly, the configuration of semiconductor layer SM2 allows for the formation of ohmic contacts between the auxiliary electrode AE ​​and the channel layer.

[0024] Word lines 142, 144, 146, and 148 are located on substrate 100 and extend in direction X. In one embodiment, word lines 142, 144, 146, and 148 are composed of a metal, such as copper, tungsten, aluminum, gold, silver, or an alloy of one or more of these metals or a combination of at least two of these metals. In other embodiments, word lines 142, 144, 146, and 148 may comprise other conductive materials, such as metal oxides or metal nitrides.

[0025] Channel layer 122 is laterally located between auxiliary electrode AE ​​and word line 142, and laterally located between auxiliary electrode AE ​​and word line 146. Channel layer 124 is laterally located between auxiliary electrode AE ​​and word line 144, and laterally located between auxiliary electrode AE ​​and word line 148. Auxiliary electrode AE ​​is used to apply a bias voltage or ground voltage to channel layers 122 and 124, thereby preventing floating body potential in the channel layers.

[0026] The charge storage layer 130 is laterally disposed between word line 142 and channel layer 122, between word line 144 and channel layer 124, between word line 146 and channel layer 122, and between word line 148 and channel layer 124. The charge storage layer 130 extends from between word line 142 and channel layer 122 to between word line 144 and channel layer 124, and from between word line 146 and channel layer 122 to between word line 148 and channel layer 124.

[0027] In one embodiment, the charge storage layer 130 is disposed vertically between the top surface 142t of the spacer 114 and the word line 142, and vertically between the bottom surface 144b of the spacer 114 and the word line 144. Similarly, the charge storage layer 130 is disposed vertically between the top surface 146t of the spacer 114 and the word line 146, and vertically between the bottom surface 148b of the spacer 114 and the word line 148.

[0028] The charge storage layer 130 is, for example, an oxide / nitride / oxide (ONO) composite layer. That is, the charge storage layer 130 includes a barrier oxide layer 132, a charge storage layer 134, and a tunneling oxide layer 136.

[0029] Figures 2A to 17C It shows Figures 1A to 1C Various perspective views of the manufacturing method of the memory device 10 shown. Figures 2A to 17C In the diagram, figure “A” shows a top perspective view of the workpiece along line a-a' at various stages of the manufacturing process of the memory device, while figures “B” and “C” correspond to vertical sectional views along lines b-b' and c-c', respectively.

[0030] Reference Figure 2A and Figure 2B The sacrificial layer 221', semiconductor material layer 122', semiconductor material layer 124', and sacrificial layer 223' are sequentially formed above the substrate 100, possibly by epitaxy. In one embodiment, the materials of the sacrificial layers 221', 222', and 223' are different from the materials of the semiconductor material layers 122' and 124'. For example, the sacrificial layers 221', 222', and 223' may be composed of silicon-germanium, while the semiconductor material layers 122' and 124' are composed of silicon.

[0031] Reference Figure 3A and Figure 3B A stacked structure consisting of sacrificial layer 221', semiconductor material layer 122', sacrificial layer 222', semiconductor material layer 124', and sacrificial layer 223' is patterned (e.g., by wet or dry etching) to form a semiconductor stack consisting of patterned sacrificial layer 221, channel layer 122, patterned sacrificial layer 222, channel layer 124, and patterned sacrificial layer 223, exposing the underlying layers. Figure 3BIn this embodiment, the stacked structure is patterned to expose the substrate 100; however, this disclosure is not limited thereto. In other embodiments, additional structures (not shown in the figures) may exist between the stacked structure and the substrate 100, and the patterning process exposes these intermediate structures. In one embodiment, the patterning process removes portions of the stacked structure corresponding to locations where word lines will later be formed.

[0032] Reference Figure 4A and Figure 4B A support structure SP is formed around and in contact with the patterned sacrificial layers 221, 122, 124, and 223. In one embodiment, the support structure SP is composed of an oxide (such as silicon oxide) or other insulating material.

[0033] Reference Figure 5A and Figure 5B The support structure SP is patterned to expose the sidewalls of the patterned sacrificial layer 221, channel layer 122, patterned sacrificial layer 222, channel layer 124, and patterned sacrificial layer 223. In one embodiment, the patterning process removes portions of the support structure SP corresponding to locations where word lines will later be formed.

[0034] Next, the patterned sacrificial layers 221, 222, and 223 are removed using a wet etching process. In this process, the support structure SP provides support for the channel layers 122 and 124 to prevent structural collapse.

[0035] Reference Figure 6A and Figure 6B A dielectric spacer layer 110 is formed around the channel layers 122 and 124 and fills the space between the channel layers 122 and 124 to insulate the channel layers 122 and 124 from each other. In one embodiment, the dielectric spacer layer 110 is composed of an oxide (such as silicon oxide) or other insulating material.

[0036] Reference Figure 7A and Figure 7B The dielectric spacer layer 110 is patterned (e.g., by wet or dry etching) to expose the sidewalls of the channel layers 122 and 124. In one embodiment, the patterning process removes portions of the dielectric spacer layer 110 corresponding to locations where word lines will later be formed. The dielectric spacer layer 110 is patterned to form spacers 112, 114, and 116.

[0037] Reference Figure 8A and Figure 8BThe sidewalls of trench layer 122 and trench layer 124 are etched to form recesses RE1 to RE4. Specifically, the exposed sidewalls of trench layer 122 are etched using a wet etching process to form recesses RE1 and RE3. Similarly, the exposed sidewalls of trench layer 124 are etched using a wet etching process to form recesses RE2 and RE4.

[0038] Reference Figure 9A and Figure 9B A charge storage layer 130 is compliantly formed on the sidewalls of spacers 112, channel layer 122, spacers 114, channel layer 124, and spacers 116. As shown, the charge storage layer 130 is compliantly formed in recesses RE1 to RE4. Next, a conductive material layer M1 is formed around the charge storage layer 130. As shown, the conductive material layer M1 surrounds the charge storage layer 130 and fills the recesses RE1 to RE4.

[0039] Reference Figure 10A and Figure 10B The conductive material layer M1 is etched to form word lines 142, 144, 146, and 148. Word lines 142 and 146 overlap with word lines 144 and 148 in the Z direction. Word lines 142 and 146 are separated from word lines 144 and 148 by spacers 114.

[0040] The dielectric structure 150 fills the space left by the removal of the conductive material layer M1, thereby covering word lines 142, 144, 146, and 148 with the dielectric structure 150 and the charge storage layer 130. In one embodiment, the dielectric structure 150 is composed of an oxide (such as silicon oxide) or other insulating material.

[0041] Reference Figure 11A and Figure 11B A trench TR is formed through spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116. Spacer 112, channel layer 122, spacer 114, channel layer 124, spacer 116, and trench TR extend in the direction X.

[0042] The trench TR is laterally disposed between the first portion 112a and the second portion 112b of spacer 112, between the first portion 122a and the second portion 122b of trench layer 122, between the first portion 114a and the second portion 114b of spacer 114, between the first portion 124a and the second portion 124b of trench layer 124, and between the first portion 116a and the second portion 116b of spacer 116.

[0043] Reference Figure 12A and Figure 12BAn isolation structure 160 is formed in the trench TR.

[0044] Reference Figures 13A to 13C An opening O1 is formed through spacer 112, channel layer 122, spacer 114, channel layer 124, and spacer 116. The opening O1 can be formed by one or more etching processes. In addition, an opening O2 is formed through isolation structure 160 to expose channel layer 122 and channel layer 124.

[0045] Reference Figures 14A to 14C The sidewalls of channel layers 122 and 124 are etched through openings O1. This results in the width of opening O1 at the locations corresponding to channel layers 122 and 124 being greater than its width at the locations corresponding to spacers 112, 114, and 116. Each sidewall of opening O1 has a recess RC1 extending toward channel layer 122 and a recess RC2 extending toward channel layer 124.

[0046] On the other hand, the sidewalls of channel layers 122 and 124 are etched through openings O2. This results in the width of openings O2 at the locations corresponding to channel layers 122 and 124 being greater than the width at the locations corresponding to spacers 112, 114, and 116. Each sidewall of opening O2 has a recess RC3 extending toward channel layer 122 and a recess RC4 extending toward channel layer 124.

[0047] In some embodiments, the etching processes performed in openings O1 and O2 may be performed simultaneously or separately.

[0048] Reference Figures 15A to 15C Semiconductor material SM1' is formed in opening O1, and semiconductor material SM2' is formed in opening O2. Semiconductor materials SM1' and SM2' have different doping types.

[0049] Reference Figures 16A to 16C The semiconductor materials SM1' and SM2' are etched (e.g., dry etched) such that the remaining portions of the semiconductor materials SM1' and SM2' are substantially aligned with spacers 112, 114, and 116. In other words, the remaining semiconductor material SM1' (i.e., semiconductor layer SM1) substantially fills the recesses RC1 and RC2 on the sidewall of opening O1, while the remaining semiconductor material SM2' (i.e., semiconductor layer SM2) substantially fills the recesses RC3 and RC4 on the sidewall of opening O2.

[0050] Reference Figures 17A to 17COptionally, a recessing process can be performed to further etch semiconductor layers SM1 and SM2, recessing them relative to spacers 112, 114, and 116. In some embodiments, the etching or recessing processes involved in forming semiconductor layers SM1 and SM2 can be performed simultaneously or separately.

[0051] Finally, refer to the return Figures 1A to 1C Source line S1, drain line D1, source line S2, and drain line D2 are formed in opening O1, while auxiliary electrode AE ​​is formed in opening O2. Source line S1, drain line D1, source line S2, drain line D2, and auxiliary electrode AE ​​extend along direction X. In some embodiments, conductive material is first deposited into openings O1 and O2. Then, excess conductive material beyond openings O1 and O2 is removed, leaving conductive material in the openings to form source line S1, drain line D1, source line S2, drain line D2, and auxiliary electrode AE.

[0052] Figure 18 A perspective view of a memory device 10 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 18 The memory device 10 includes multiple contacts WC, SC, DC, and AC. Contact WC connects a word line to a corresponding pickup line PL1. Contact SC connects a source line to a corresponding pickup line PL2 (also called a source line), while contact DC connects a drain line to a corresponding pickup line PL3 (also called a bit line). Contact AC connects an auxiliary electrode to a corresponding signal line GL (e.g., a ground signal line).

[0053] In the memory device 10 of the present invention, word lines, source lines and bit lines can be decoded in different directions, which facilitates easier decoding while maintaining the integrity of the 3D structure.

[0054] In one embodiment, the auxiliary electrode is connected to a ground signal via a top signal line GL, but this disclosure is not limited thereto. In other embodiments, the auxiliary electrode is electrically connected downwards to a substrate, which is used for grounding.

[0055] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of the disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations as long as they fall within the scope of the claims and their equivalents.

Claims

1. A memory device, characterized in that, include: The first source line and the first drain line extend along the first direction; A first word line and a first channel layer extend along a second direction perpendicular to the first direction, wherein the first source line and the first drain line pass through the first channel layer, and the first channel layer laterally surrounds the first source line and the first drain line. as well as A charge storage layer is disposed laterally between the first word line and the first channel layer.

2. The memory device according to claim 1, further comprising: A substrate, wherein the first word line, the first channel layer, the charge storage layer, the first source line, and the first drain line are located above the substrate, wherein a first direction is perpendicular to the top surface of the substrate, and a second direction is parallel to the top surface of the substrate.

3. The memory device according to claim 1, further comprising: The second word line and the second channel layer extend along the second direction, wherein the charge storage layer extends from between the first word line and the first channel layer to between the second word line and the second channel layer, and wherein the first source line and the first drain line extend from the first channel layer to the second channel layer along the first direction.

4. The memory device according to claim 3, further comprising: A spacer, wherein the first channel layer and the second channel layer are separated by the spacer.

5. The memory device of claim 1, wherein the sidewalls of the first source line and the sidewalls of the first drain line have protruding structures extending toward the first channel layer.

6. The memory device according to claim 1, further comprising: An auxiliary electrode extends along the first direction, wherein the first channel layer is located between the auxiliary electrode and the first word line.

7. The memory device of claim 6, wherein the sidewall of the auxiliary electrode has a protruding structure extending toward the first channel layer.

8. The memory device of claim 6, further comprising: The first semiconductor layer is located between the first source line and the first channel layer, and between the first drain line and the first channel layer. as well as A second semiconductor layer is located between the auxiliary electrode and the first channel layer, wherein the first semiconductor layer and the second semiconductor layer have different doping types.

9. The memory device of claim 6, further comprising: An isolation structure is laterally disposed between a first portion of the first channel layer and a second portion of the first channel layer, wherein the auxiliary electrode is embedded in the isolation structure.

10. A method for manufacturing a memory device, characterized in that, include: A first channel layer, a second channel layer, and spacers are formed, wherein the first channel layer and the second channel layer are arranged along a first direction and separated from each other by the spacers; The sidewalls of the first trench layer and the sidewalls of the second trench layer are etched to form a first recess and a second recess; A charge storage layer is formed in the first and second recesses; A first conductive material layer is formed on the charge storage layer; The first conductive material layer is etched to form a first word line and a second word line, wherein the charge storage layer is laterally disposed between the first word line and the first channel layer, and laterally disposed between the second word line and the second channel layer; Multiple first openings are formed to penetrate the first trench layer and the second trench layer; as well as A first source line and a first drain line are formed in the plurality of first openings, wherein the first source line and the first drain line extend along the first direction, and the first channel layer and the second channel layer laterally surround the first source line and the first drain line.

11. The manufacturing method according to claim 10, further comprising: A trench is formed in the first trench layer, the second trench layer, and the spacer, wherein the first trench layer, the second trench layer, and the trench extend along a second direction; as well as An isolation structure is formed in the trench.

12. The manufacturing method according to claim 11, further comprising: A second opening is formed in the isolation structure to expose the first trench layer and the second trench layer; as well as An auxiliary electrode is formed in the second opening, wherein the auxiliary electrode extends along the first direction, and the first channel layer is located between the auxiliary electrode and the first word line.

13. The manufacturing method according to claim 12, further comprising: Before forming the first source line and the first drain line, a first semiconductor layer is formed in the plurality of first openings; as well as Before forming the auxiliary electrode, a second semiconductor layer is formed in the second opening, wherein the first semiconductor layer and the second semiconductor layer have different doping types.

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