Semiconductor memory, electronic device, and data read / write method

Abstract

The application provides a semiconductor memory, an electronic device and a data read-write method. The semiconductor memory comprises: a first storage array, the first storage array comprising a plurality of first storage units; a second storage array, the second storage array comprising a plurality of second storage units; the first storage units and the second storage units correspond to each other, and each first storage unit is arranged opposite to a second storage unit; wherein a first end of the first storage unit is connected to a first bit line, a second end is connected to a source line, and a control end is connected to a word line; a first end of the second storage unit is connected to a second bit line, a second end is connected to the source line, and a control end is connected to the word line. In the application, the integration of the double-layer storage array and the double-layer storage array sharing metal tracks is used to improve the integration of the memory, and the storage capacity per unit area is significantly improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor memory, electronic device, and data read / write method. Background Technology

[0002] With the rapid development of information technology, the amount of data in modern society is growing exponentially. In order to efficiently store, access, and process such massive amounts of data, new storage technologies have gradually become a research hotspot.

[0003] However, as feature sizes continue to shrink, new memory based on planar processes are gradually approaching their physical limits, and there is an urgent need to develop three-dimensional (3D) integration technology to break through the density bottleneck. Summary of the Invention

[0004] This application provides a semiconductor memory, an electronic device, and a data read / write method, which can improve the integration of the memory by integrating a dual-layer memory array and using shared metal traces between the dual-layer memory arrays, thereby significantly increasing the storage capacity per unit area.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a semiconductor memory, including: a first memory array including a plurality of first memory cells; a second memory array including a plurality of second memory cells; the first memory cells and the second memory cells are in one-to-one correspondence, and each first memory cell is disposed opposite to one of the second memory cells; wherein, a first end of the first memory cell is connected to a first bit line, a second end is connected to a source line, and a control end is connected to a word line; a first end of the second memory cell is connected to a second bit line, a second end is connected to a source line, and a control end is connected to a word line.

[0007] This application provides an electronic device, including a circuit board and the aforementioned semiconductor memory, wherein the semiconductor memory is disposed on the circuit board.

[0008] This application provides a data read / write method applied to the aforementioned semiconductor memory. The method includes performing the following operations on a target memory cell to be accessed in the semiconductor memory and a reference memory cell on the back side of the target memory cell: setting the voltage of the word line connected to the target memory cell to a positive voltage; setting the voltage of the bit line connected to the target memory cell to a read voltage; setting the voltage of the source line connected to the target memory cell to zero; floating the bit line connected to the reference memory cell; and detecting the current signal of the source line connected to the target memory cell to read the target data of the target memory cell.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, the semiconductor memory includes a dual-layer memory array composed of a first memory array and a second memory array. The first and second memory cells in the dual-layer array correspond one-to-one, with each first memory cell positioned opposite to a second memory cell. This effectively improves the symmetry and compactness of the memory cell layout, increasing the number of memory cells per unit area. Furthermore, the second ends of the first and second memory cells can be connected to the same source line, and the control terminals of the first and second memory cells can be connected to the same word line. This reduces the wiring complexity of the dual-layer memory array, further shrinking the overall area of ​​the semiconductor memory and significantly increasing the storage capacity per unit area.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 The circuit schematic of the storage array of the semiconductor memory provided in the embodiments of this application is shown.

[0014] Figure 2 A top front view of a semiconductor memory provided in an embodiment of this application.

[0015] Figure 3 This is a top rear view of a semiconductor memory provided in an embodiment of this application.

[0016] Figure 4 A cross-section of a semiconductor memory provided in an embodiment of this application. Figure 1 .

[0017] Figure 5 A cross-section of a semiconductor memory provided in an embodiment of this application. Figure 2 .

[0018] The reference numerals and names in the figure are as follows:

[0019] 1. Semiconductor memory; 2. First memory array; 3. Second memory array; 4. First memory cell; 5. Second memory cell; 6. First bit line; 7. Source line; 8. Word line; 9. Second bit line; 11. First memory cell group; 12. Second memory cell group; 13. Fin structure; 14. Drain structure; 15. Gate structure; 16. Source structure; 17. First memory device; 18. Second memory device. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] Currently, the main new memory architectures are 1S1R arrays and 1T1R arrays. In a 1S1R array, a selector is connected in series in each memory cell to suppress write crosstalk and leakage paths during array operation. While the introduction of the selector can suppress leakage paths, it still faces several challenges: first, inherent defects such as poor durability, large fluctuations, and material incompatibility remain unresolved; second, the operating and read voltages increase significantly; and third, leakage problems persist. Furthermore, voltage drops on the conductors further limit the integration density improvement of 1S1R arrays. In contrast, the 1T1R array architecture is more mainstream. In the 1T1R array architecture, transistors, acting as selectors, can effectively shut off leakage paths, thereby improving the stability of the memory cell. However, due to the large area overhead of the transistors themselves and the high complexity of transistor wiring, 1T1R arrays occupy a larger area than 1S1R arrays. Simultaneously, the density of a 1T1R array also depends on the transistor arrangement density, making increasing the transistor arrangement density key to improving the integration density of the 1T1R array.

[0024] However, as feature sizes continue to shrink, new memory based on planar processes are gradually approaching their physical limits, and there is an urgent need to explore new 3D integration technologies to further break through the bottleneck of integration density.

[0025] To address the aforementioned technical problems, embodiments of this application provide a semiconductor memory, an electronic device, and a data read / write method, which improves the integration of the memory by integrating a dual-layer memory array and sharing metal traces between the dual-layer memory arrays, thereby significantly increasing the storage capacity per unit area.

[0026] In a first aspect, embodiments of this application provide a semiconductor memory.

[0027] In some embodiments, a semiconductor memory may include a memory array, an address decoder, a read / write control circuit, an I / O buffer, and timing and control logic circuits. The memory array is the core component of the semiconductor memory used for actual data storage. The address decoder converts the input address signal into a corresponding row / column selection signal to locate the specific memory cell in the memory array. The read / write control circuit controls the read and write operations of data in the memory array. The I / O buffer coordinates the input and output of data between the memory array and the external data bus. The timing and control logic circuit generates various control signals to coordinate the timing of each component, ensuring the orderly operation of the memory array.

[0028] In some embodiments, the semiconductor memory provided in this application includes:

[0029] A first storage array, the first storage array comprising a plurality of first storage cells;

[0030] The second storage array includes multiple second storage cells; the first storage cells and the second storage cells are in one-to-one correspondence, and each first storage cell is positioned opposite to one second storage cell; wherein,

[0031] The first end of the first memory cell is connected to the first bit line, the second end is connected to the source line, and the control end is connected to the word line;

[0032] The first end of the second memory cell is connected to the second bit line, the second end is connected to the source line, and the control end is connected to the word line.

[0033] In this embodiment, the semiconductor memory includes a dual-layer memory array composed of a first memory array and a second memory array. The first and second memory cells in the dual-layer array correspond one-to-one, with each first memory cell positioned opposite to a second memory cell. This effectively improves the symmetry and compactness of the memory cell layout, increasing the number of memory cells placed per unit area. Simultaneously, the second ends of the first and second memory cells can be connected to the same source line, and the control terminals of the first and second memory cells can also be connected to the same source line. This reduces the wiring complexity of the dual-layer memory array, further shrinking the overall area of ​​the semiconductor memory and significantly increasing the storage capacity per unit area.

[0034] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0035] Figure 1 A circuit schematic of a storage array for a semiconductor memory provided in an embodiment of this application. See also... Figure 1 As shown, the semiconductor memory 1 may include a first part represented by dark black lines and a second part represented by light black lines. The first part is a first memory array 2 and wiring on one side of the wafer (which may be the front or back side of the wafer), and the first memory array 2 includes a plurality of first memory cells 4. The second part is a second memory array 3 and wiring on the other side of the wafer, and the second memory array 3 includes a plurality of second memory cells 5. The first memory cells 4 and the second memory cells 5 are in one-to-one correspondence, and each first memory cell 4 is positioned opposite to one second memory cell 5.

[0036] In some embodiments, the first storage unit 4 and the second storage unit 5 are in a one-to-one correspondence, which may mean that one first storage unit 4 and one second storage unit 5 are opposite each other, and the devices in the first storage unit 4 are also opposite to the devices in the second storage unit 5.

[0037] In some embodiments, each first memory cell 4 is positioned opposite to a second memory cell 5, thereby flip-chip stacking in a vertical direction (perpendicular to the wafer surface). This flip-chip stacking structure, formed by vertically flip-chip stacking of the first memory cells 4 and the second memory cells 5, is based on wafer flipping technology and is achieved by simultaneously fabricating the first memory cell 4 on one side of the wafer and the second memory cell 5 on the other side of the wafer.

[0038] In some embodiments, the process of implementing a flip-chip stacked structure may include: forming a first memory cell 4 on the front side of a wafer, then flipping the wafer so that the back side of the wafer faces upwards, then forming a second memory cell 5 on the back side of the wafer, and finally flipping the wafer again so that the front side of the wafer faces upwards. In other embodiments, the process of implementing a flip-chip stacked structure may include: forming a second memory cell 5 on the front side of a wafer and forming a first memory cell 4 on the back side of the wafer.

[0039] Understandably, using this flip-chip stacking structure in semiconductor memory can effectively improve the integration of the memory array within the semiconductor memory, thereby increasing the number of memory cells that can be placed per unit area.

[0040] It should be noted that the following description uses the example of fabricating the first memory cell 4 on the front side of the wafer and the second memory cell 5 on the back side of the wafer to illustrate the structure of the semiconductor memory. Those skilled in the art should understand that this should not limit the scope of protection of this application.

[0041] In some embodiments, the first end of the first storage unit 4 is connected to the first bit line 6, the second end is connected to the source line 7, and the control end is connected to the word line 8; the first end of the second storage unit 5 is connected to the second bit line 9, the second end is connected to the source line 7, and the control end is connected to the word line 8.

[0042] Understandably, the first terminal of the first storage cell 4 can be a power-on terminal. This power-on terminal can be used for data read / write and connected to the first bit line 6. The second terminal of the first storage cell 4 can be a power-off terminal. This power-off terminal can be used as a voltage reference terminal and connected to the source line 7. The control terminal of the first storage cell 4 can be a strobe terminal. This strobe terminal can be used for switch control and connected to the word line 8. Similarly, the first terminal of the second storage cell 5 can be a power-on terminal, which is connected to the second bit line 9. The second terminal of the second storage cell 5 can be a power-off terminal, which is connected to the source line 7. The control terminal of the first storage cell 4 can be a strobe terminal, which is connected to the word line 8.

[0043] In the embodiments of this application, the first storage unit and the second storage unit are independently connected to their respective bit lines, and the first storage unit and the second storage unit can share the same source line and the same word line, thereby reducing the source line routing overhead, increasing the array integration density, and reducing the complexity of the peripheral driving circuit while ensuring the independence of read and write operations.

[0044] In some embodiments, see still Figure 1 The first memory cell 4 may include a first transistor and a first memory device. The first terminal of the first memory device is connected to the drain structure of the first transistor, the second terminal of the first memory device serves as the first terminal of the first memory cell 4 and is connected to the first bit line 6, the source structure of the first transistor serves as the second terminal of the first memory cell 4 and is connected to the source line 7, and the gate structure of the first transistor serves as the control terminal of the first memory cell 4 and is connected to the word line 8.

[0045] The second memory cell 5 may include: a second transistor and a second memory device; wherein, the first end of the second memory device is connected to the drain structure of the second transistor, the second end of the second memory device serves as the first end of the second memory cell 5 and is connected to the second bit line 9, the source structure of the second transistor serves as the second end of the second memory cell 5 and is connected to the source line 7, and the gate structure of the second transistor serves as the control terminal of the second memory cell 5 and is connected to the word line 8.

[0046] Understandably, the first transistor can be a device in the first memory cell 4 that enables cell selection and shutdown, and the first memory device can be a device in the first memory cell 4 that enables data storage. The first terminal of the first memory device can be connected to the drain structure of the first transistor, and the second terminal of the first memory device can be connected to the first bit line 6 as the first terminal of the first memory cell 4. Thus, the first bit line 6 is connected to the drain structure of the first transistor, thereby utilizing the high drive capability and low leakage characteristics of the drain structure to realize data access of the first memory device. Simultaneously, the source structure of the first transistor serves as the second terminal of the first memory cell 4, connected to the source line 7, to provide a stable current loop, and the gate structure of the first transistor serves as the control terminal of the first memory cell 4, connected to the word line 8, to control the channel conduction state.

[0047] Similarly, the second transistor in the second storage cell 5 can have the same function as the first transistor, and the second storage device can have the same function as the first storage device. For the sake of brevity, this will not be elaborated further here.

[0048] Understandably, the first memory cell 4 and the second memory cell 5 are in a one-to-one correspondence, with each first memory cell 4 positioned opposite to one second memory cell 5. Thus, when the first memory cell 4 includes a first transistor and a first memory device, and the second memory cell 5 includes a second transistor and a second memory device, the first transistor and the second transistor are positioned opposite to each other, as are the first memory device and the second memory device. In other words, the first transistor on the front side of the wafer is facing forward, and the second transistor on the back side of the wafer is facing backward. Furthermore, the forward-facing first transistor and the backward-facing second transistor can form a flip-chip stacked transistor configuration.

[0049] In some embodiments, the flip-chip stacked transistor is based on wafer flipping technology, which is achieved by simultaneously fabricating a first transistor on one side of the wafer and a second transistor on the other side of the wafer.

[0050] As is understandable, the implementation process of flip-chip stacked transistors can be found in the description of the implementation process of the flip-chip stacked structure above, and will not be repeated here for the sake of brevity. Using flip-chip stacked transistors in semiconductor memories can effectively improve the integration density of transistors within the semiconductor memory, thereby enhancing the integration performance of the semiconductor memory.

[0051] In some embodiments, the semiconductor memory can be a novel type of memory, such as resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM). Then, the first memory device can be a resistor, capacitor, or similar device. Similarly, the second memory device can also be a resistor, capacitor, or similar device. The second memory device can be the same as the first memory device.

[0052] Understandably, resistive random access memory (RRAM) achieves data storage based on variable resistance, meeting the storage requirements of high-density in-memory computing and neuromorphic computing. Phase-change memory (PCM) achieves data storage based on the reversible phase transition between crystalline and amorphous states of chalcogenide compounds (such as germanium-antimony-tellurium materials), meeting the storage requirements of high-speed persistent memory and large-capacity cache replacement. Magnetoresistive memory (MRAM) achieves data storage based on the tunneling magnetoresistive effect of magnetic tunnel junctions, meeting the storage requirements of ultra-high reliability and unlimited write cycles. Ferroelectric memory (FEMemory) achieves data storage based on the polarization direction of ferroelectric materials, meeting the storage requirements of ultra-low power consumption and high-frequency write cycles.

[0053] For example, when the semiconductor memory is a resistive random access memory (RRAM), the first and second memory devices can be resistors. When the semiconductor memory is a ferroelectric memory (FRAM), the first and second memory devices can be capacitors.

[0054] In some embodiments, the first and second memory devices can be fabricated using existing complementary metal-oxide-semiconductor (CMOS) processes.

[0055] In some embodiments, the source structures of the first transistor and the second transistor are connected to the same source line 7, and a common-source structure can be used between the first transistor and the second transistor. A common-source structure refers to coupling the source structures of the first transistor and the second transistor together. Here, the source structures of the first transistor and the second transistor can be directly coupled together, or they can be coupled together through metal wires, interconnect structures, or other structures; this application embodiment does not limit this.

[0056] In some embodiments, the gate structures of the first transistor and the second transistor are connected to the same word line 8, and a common gate structure can be used between the first transistor and the second transistor. A common gate structure means that the gate structures of the first transistor and the second transistor are coupled together. Here, the gate structures of the first transistor and the second transistor can be directly coupled together, or they can be coupled together through metal wires, interconnect structures, or other structures. This application embodiment does not limit this.

[0057] In the embodiments of this application, the semiconductor memory can adopt novel memory architectures such as 1T1R and 1T1C, and further extend to a three-dimensional integration scheme through flip-chip stacking technology. This not only effectively suppresses leakage current in the memory array through the gating characteristics of transistors, improving the operational stability and read reliability of memory cells, but also further enhances the integration performance of the semiconductor memory.

[0058] In some embodiments, the first transistor is an N-type transistor and the second transistor is an N-type transistor; or, the first transistor is a P-type transistor and the second transistor is a P-type transistor.

[0059] Understandably, the first and second transistors have the same conductivity type. An N-type transistor can be an N-channel transistor, conducting electrons. A P-type transistor can be a P-channel transistor, conducting holes.

[0060] In some embodiments, when the first transistor is an N-type metal-oxide-semiconductor field-effect transistor (NMOS), the second transistor is an NMOS; conversely, when the first transistor is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), the second transistor is a PMOS.

[0061] Understandably, both the first and second transistors use N-type transistors, forming a homogeneous stacked transistor structure. This homogeneous stacked transistor structure requires only a single N-type well region and N+ doping process, avoiding the P-type well and N-well isolation process required for PMOS, significantly simplifying the manufacturing process and reducing manufacturing costs. Simultaneously, since both the first and second transistors are electronically conductive, their carrier mobility is consistent, resulting in a high degree of matching between on-resistance and switching speed, which is beneficial for precise timing control. Furthermore, the elimination of the need for an N-well isolation region effectively reduces the layout area and increases the integration density of the memory array. Similarly, using a P-type transistor for both the first and second transistors can achieve the same technical effect.

[0062] In the embodiments of this application, the first transistor and the second transistor have the same conductivity type, which can further improve the storage density of the memory array.

[0063] Figure 2 A top front view of a semiconductor memory provided in an embodiment of this application. Figure 3 A rear top view of a semiconductor memory provided for an embodiment of this application. See also... Figure 2 As shown in the top view, the first memory array 2 on the front side of the wafer is arranged in an array, that is, multiple first memory cells 4 are arranged along a first horizontal direction (the extension direction of the fin structure 13, or the channel direction), and multiple first memory cells 4 are arranged along a second horizontal direction (perpendicular to the first horizontal direction). See also Figure 3 As shown in the top view of the back side, a second memory array 3 with an array arrangement is shown on the back side of the wafer, that is, multiple second memory cells 5 are arranged along the first horizontal direction and multiple second memory cells 5 are arranged along the second horizontal direction.

[0064] In some embodiments, see Figures 1 to 3As shown, in the first storage array 2, every two adjacent first storage cells 4 form a first storage cell group 11, and the two first transistors in the first storage cell group 11 can adopt a common source structure. In the second storage array 3, every two adjacent second storage cells 5 form a second storage cell group 12, and the two second transistors in the second storage cell group 12 can adopt a common source structure.

[0065] Understandably, a common-source structure can refer to coupling the source structures of two first transistors together. Here, the source structures of the second first transistor can be directly coupled together, or they can be coupled together through metal wires, interconnect structures, or other structures; this embodiment does not limit this. Thus, the two first transistors in the first memory cell group 11 can share a source line 7, and the first transistor and its opposite second transistor can also share a source line 7, thereby further reducing the wiring overhead of the source line 7 and increasing the integration density of the memory array. Similarly, the same technical effect can be achieved when a common-source structure is used between two second transistors.

[0066] In some embodiments, when the two first transistors in the first memory cell group 11 adopt a common-source structure, the two first transistors can be arranged symmetrically in the horizontal direction. In one example, in the horizontal direction, the two first transistors in the first memory cell group 11 are arranged in a mirror symmetrical manner: in the first transistor, the drain structure, gate structure, and source structure are arranged sequentially along the first horizontal direction; in the second transistor, the source structure, gate structure, and drain structure are arranged sequentially along the first horizontal direction.

[0067] Figure 4 A cross-section of a semiconductor memory provided in an embodiment of this application. Figure 1 , Figure 5 A cross-section of a semiconductor memory provided in an embodiment of this application. Figure 2 .in, Figure 4 This is a cross-sectional view along the first horizontal direction. Figure 5 This is a cross-sectional view along the second horizontal direction. See also... Figures 1 to 5As shown, in the first memory array 2, every two adjacent first memory cells 4 form a first memory cell group 11. The two first transistors in the first memory cell group 11 share a source structure 16. Similarly, in the second memory array 3, every two adjacent second memory cells 5 form a second memory cell group 12. The two second transistors in the second memory cell group 12 share a source structure 16. The first memory device 17 in the first transistor is connected to the drain structure 14 in the first transistor. The second memory device 18 in the second transistor is connected to the drain structure 14 in the second transistor. The word line 8 is simultaneously connected to the gate structure 15 in both the first and second transistors.

[0068] In some embodiments, the two first transistors in the first memory cell group 11 are configured to share a common source structure 16.

[0069] Understandably, when two first transistors in the first memory cell group 11 share a single source structure 16, the two first transistors can be arranged symmetrically in the first horizontal direction. In one example, in the first horizontal direction, the drain structure 14, gate structure 15, source structure 16, gate structure 15, and drain structure 14 are arranged sequentially in the first memory cell group 11. The source structure 16 is a structure shared by both first transistors. Here, the scheme of coupling the two first transistors by sharing a single source structure 16, compared to the scheme of coupling the two first transistors through two source structures 16 (such as two source structures 16 directly coupled together, or two source structures 16 coupled together through a metal interconnect), can reduce the device structure within the memory cell, further reduce the unit area of ​​the memory cell, and improve the integration performance of the semiconductor memory. Similarly, the same technical effect can be achieved when two second transistors in the second memory cell group 12 share a single source structure 16.

[0070] In some embodiments, every two adjacent first memory cells 4 in the first memory array 2 constitute a first memory cell group 11; the two first transistors in the first memory cell group 11 share a source structure 16. Alternatively, every two adjacent second memory cells 5 in the second memory array 3 constitute a second memory cell group 12; the two second transistors in the second memory cell group 12 share a source structure 16.

[0071] Understandably, when the two first transistors in the first memory cell group 11 share a common source structure 16, the two second transistors in the second memory cell group 12 can use metal interconnects to implement a common source structure. Alternatively, when the two first transistors in the first memory cell group 11 use metal interconnects to implement a common source structure, the two second transistors in the second memory cell group 12 can share a common source structure 16.

[0072] In the embodiments of this application, every two adjacent first memory cells and / or every two adjacent second memory cells can share a source structure, thereby improving the symmetry and compactness of the transistor layout in the memory cell, reducing the overall area of ​​the memory cell, and achieving a significant increase in storage capacity per unit area; at the same time, through the common source structure, the redundant structure between memory cells can be reduced, further realizing a high-density memory array.

[0073] In some embodiments, see Figures 1 to 5 As shown, the first memory cell group 11 and the second memory cell group 12 are in one-to-one correspondence, and each first memory cell group 11 is arranged opposite to one second memory cell group 12; wherein, the source structure 16 of the first transistor in the first memory cell group 11 is connected to the source structure 16 of the second transistor in the second memory cell group 12; the drain structure 14 of the first transistor in the first memory cell group 11 is connected to the drain structure 14 of the second transistor in the second memory cell group 12; and the gate structure 15 of the first transistor in the first memory cell group 11 is connected to the gate structure 15 of the second transistor in the second memory cell group 12.

[0074] Understandably, when the first memory cell group 11 and the second memory cell group 12 are arranged in a one-to-one correspondence and opposite directions, the first transistor in the first memory cell group 11 and the second transistor in the second memory cell 5 can adopt a common source structure 16 and be connected to the same source line 7, or they can adopt a common drain structure and a common gate structure.

[0075] Thus, the drain structure 14 of the first transistor and the drain structure 14 of the second transistor are electrically connected to the same node, and the gate structure 15 of the first transistor and the gate structure 15 of the second transistor are electrically connected to the same node, so that the first transistor and the second transistor are synchronously turned on in the selected state, and the channel current is superimposed in parallel at the drain node, which effectively increases the driving current capability.

[0076] In some embodiments, the first transistor and the second transistor share the same gate structure 15, which can be integrally formed by a single deposition process.

[0077] In the embodiments of this application, the electrical performance of the semiconductor memory can be further improved by connecting the source structure, drain structure and gate structure of the first transistor and the second transistor in two memory cell groups arranged in opposite directions.

[0078] In some embodiments, see Figures 1 to 5 As shown, the source / drain regions and gate regions in the first transistor are alternately arranged in the first horizontal direction, and the source / drain regions and gate regions in the second transistor are also alternately arranged in the first horizontal direction. The first horizontal direction is the channel direction. Thus, the first bit line 6 and the second bit line 9 in the semiconductor memory 1 can extend along the first horizontal direction; the word line 8 can extend along the second horizontal direction; and the source line 7 can extend along the first horizontal direction and / or the second horizontal direction.

[0079] Understandably, the bit lines in semiconductor memory 1 are used to transmit data in and out of memory cells and participate in the selection of column direction. By setting double-sided bit lines, the first memory cell 4 or the second memory cell 5 can be selected independently, ensuring that the target memory cell can be selected.

[0080] Understandably, word lines in semiconductor memory 1 are used to select a specific row of memory cells in the memory array. By setting word lines, a first memory cell 4 and a second memory cell 5 can be selected simultaneously, ensuring that the target memory cell can be activated.

[0081] In some embodiments, the first bit line 6 may be connected to the second end of the first memory device in the first memory cell 4, and the second bit line 9 may be connected to the second end of the second memory device in the second memory cell 5. The word line 8 may be connected to the gate structure 15 of the first transistor in the first memory cell 4, or the word line 8 may be connected to the gate structure 15 of the second transistor in the second memory cell 5.

[0082] In some embodiments, the gate structure 15 of the first transistor in the first memory cell 4 and the gate structure 15 of the second transistor in the second memory cell 5 can both be controlled by the same word line 8. The first bit line 6 is connected to the second terminal of the first memory device in the first memory cell 4, and the second bit line 9 is connected to the second terminal of the first memory device in the first memory cell 4. When the word line 8 activates both the first transistor and the second transistor simultaneously, the first bit line 6 is turned on, forming a conduction path with the first memory device, thus enabling operation of the first memory cell 4; the second bit line 9 is floating, and cannot form a conduction path with the second memory device, thereby not operating the second memory cell 5.

[0083] In some embodiments, a first memory cell group 11 may include two first memory cells 4, which may be controlled by different word lines, i.e., the two first memory cells 4 in a first memory cell group 11 may be connected to different word lines 8 respectively. Similarly, the two second memory cells 5 in a second memory cell group 12 may be connected to different word lines 8 respectively.

[0084] Understandably, the two first storage cells 4 in the first storage cell group 11 are respectively connected to the corresponding word lines 8, enabling the two first storage cells 4 to operate independently, thereby precisely controlling each first storage cell 4 in the first storage cell group 11. Similarly, the two second storage cells 5 in the second storage cell group 12 are respectively connected to the corresponding word lines 8, enabling precise control of each second storage cell 5 in the second storage cell group 12.

[0085] In some embodiments, the word line 8 can be disposed on the front side of the wafer or on the back side of the wafer; this application embodiment does not limit this. For example, the word line 8 can be located in the first memory cell 4 or in the second memory cell 5.

[0086] In some embodiments, the semiconductor memory may further include a source line 7. The main function of the source line 7 is to connect the source of the transistor, forming a complete current loop together with the bit line, which is crucial for read / write stability. The source line 7 can be connected to the source structure 16 of the first transistor in the first memory cell 4 and the source structure 16 of the second transistor in the second memory cell 5.

[0087] In some embodiments, the source line 7 can be disposed on the front side of the wafer or on the back side of the wafer; this application embodiment does not limit this. For example, the source line 7 can be located in the first memory cell 4 or in the second memory cell 5.

[0088] In some embodiments, there are multiple first storage cells 4 arranged in an array. Thus, multiple first storage cells 4 can be arranged in a first horizontal direction, and / or multiple first storage cells 4 can be arranged in a second horizontal direction.

[0089] In some embodiments, a plurality of first storage cells 4 arranged in a first horizontal direction share the same first bit line 6. Therefore, two first storage cells 4 within the same first storage cell group 11 can share the same first bit line 6, and first storage cells 4 in two adjacent first storage cell groups 11 in the first horizontal direction also share the same first bit line 6. Similarly, a plurality of second storage cells 5 arranged in the first horizontal direction share the same second bit line 9.

[0090] In some embodiments, a plurality of first storage cells 4 arranged in the second horizontal direction share the same word line 8, while two first storage cells 4 within the same first storage cell group 11 are connected to different word lines 8. Similarly, a plurality of second storage cells 5 arranged in the first horizontal direction share the same word line 8, while two second storage cells 5 within the same second storage cell group 12 are connected to different word lines 8. The plurality of first storage cells 4 and the plurality of second storage cells 5 arranged in the second horizontal direction share the same word line 8.

[0091] In this embodiment, bit lines and word lines are arranged orthogonally, forming a cross-array architecture for the semiconductor memory. Furthermore, by providing double-sided bit lines and double-sided word lines, it can be adapted to double-sided memory arrays, improving the read / write reliability of the semiconductor memory. Source lines connect to the source structure within the first memory cell, thereby constructing a stable reference potential and a closed current loop, ensuring the read / write reliability of the semiconductor memory.

[0092] Secondly, embodiments of this application provide an electronic device.

[0093] The electronic device includes a circuit board and a semiconductor memory as described in any embodiment of the first aspect. The semiconductor memory is disposed on the circuit board.

[0094] Here, the specific structure of the semiconductor memory can be found in the description of any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0095] Secondly, embodiments of this application provide a data read / write method.

[0096] In the embodiments of this application, the data read / write method can be applied to a semiconductor memory according to any embodiment of the first aspect. The data read / write method may include, for a target memory cell to be accessed in the semiconductor memory and a reference memory cell on the back side of the target memory cell, performing the following operations: setting the voltage of the word line connected to the target memory cell to a positive voltage; setting the voltage of the bit line connected to the target memory cell to a read voltage; setting the voltage of the source line connected to the target memory cell to zero; setting the voltage of the word line connected to the reference memory cell to zero; floating the bit line connected to the reference memory cell; and detecting the current signal of the source line connected to the target memory cell to read the target data of the target memory cell.

[0097] Understandably, a read operation can be performed on a target memory cell (i.e., the first or second memory cell) in a semiconductor memory. By setting the voltage of the word line connected to the target memory cell to a positive voltage, setting the voltage of the bit line connected to the target memory cell to a read voltage, setting the voltage of the source line connected to the target memory cell to zero, setting the voltage of the word line connected to the reference memory cell to zero, and floating the bit line connected to the reference memory cell, the transistors in the target and reference memory cells can be turned on, and the bit line connected to the target memory cell can be connected to the memory device in the target memory cell. By detecting the current signal of the source line connected to the target memory cell, data can be read from the target memory cell.

[0098] Here, when the target memory cell is located in the first memory cell, the bit line connected to the target memory cell can be the first bit line, the word line connected to the target memory cell can be the first word line, and the bit line connected to the reference memory cell can be the second bit line, and the word line connected to the reference memory cell can be the second word line. When the target memory cell is located in the second memory cell, the bit line connected to the target memory cell can be the second bit line, the word line connected to the target memory cell can be the second word line, the bit line connected to the reference memory cell can be the first bit line, and the word line connected to the reference memory cell can be the first word line.

[0099] Understandably, since the target memory cell and the reference memory cell share a word line, during a read operation, the word line can control the transistors in both the target and reference memory cells to be turned on simultaneously. Because the voltage on the word line of the target memory cell is set to the read voltage, while the voltage of the reference memory cell is set to floating, the target data in the target memory cell can be selectively read, thus independently completing the read operation on the target memory cell. Similarly, this application can also independently complete the write operation on the target memory cell.

[0100] In some embodiments, the data read / write method may further include: setting the voltage of a word line connected to a target memory cell to a positive voltage; setting the voltage of a bit line connected to the target memory cell to a set voltage; using the set voltage to write target data of a first value to the target memory cell; setting the voltage of a source line connected to the target memory cell to zero; setting the voltage of a word line connected to a reference memory cell to zero; floating the bit line connected to the reference memory cell; and detecting the current signal of the source line connected to the target memory cell to determine that the target data has been written to the target memory cell.

[0101] Understandably, a write operation is performed on the target memory cell within the first memory cell. By setting the voltage of the word line connected to the target memory cell to a positive voltage, setting the voltage of the bit line connected to the target memory cell to a set voltage, setting the voltage of the source line connected to the target memory cell to zero, setting the voltage of the word line connected to the reference memory cell to zero, and floating the bit line connected to the reference memory cell, the transistors in the target memory cell and the reference memory cell can be turned on, and the bit line connected to the target memory cell and the memory device in the target memory cell can be connected, thereby writing the target data of the first value into the target memory cell in a specific state (usually a low-resistance state).

[0102] In some embodiments, the target data for the first value can be a single-bit value or a multi-bit value, and this application does not limit this. In some embodiments, a single-bit value can be 0 or 1. A multi-bit value can be 00, 01, 10, or 11.

[0103] In some embodiments, during a write operation, the current signal of the source line connected to the target memory cell can be detected to determine whether the target data of the first value has been successfully written to the target memory cell.

[0104] In some embodiments, the data read / write method may further include: setting the voltage of the word line connected to the target memory cell to a positive voltage; setting the voltage of the source line connected to the target memory cell to a reset voltage; using the reset voltage to write target data of a second value to the target memory cell; setting the voltage of the bit line connected to the target memory cell to zero; setting the voltage of the word line connected to the reference memory cell to zero; floating the bit line connected to the reference memory cell; and detecting the current signal of the source line connected to the target memory cell to determine that the target data is written to the target memory cell.

[0105] Understandably, a reset operation can be performed on the target memory cell within the first memory cell. By setting the voltage of the word line connected to the target memory cell to a positive voltage, setting the voltage of the source line connected to the target memory cell to a reset voltage, setting the voltage of the bit line connected to the target memory cell to zero, setting the voltage of the word line connected to the reference memory cell to zero, and floating the bit line connected to the reference memory cell, the transistors in the target memory cell and the reference memory cell can be turned on, and the source line connected to the target memory cell and the memory device in the target memory cell can be connected, thereby writing the target data of the second value into the target memory cell in a specific state (usually a high-impedance state).

[0106] In some embodiments, the target data for the second value can be a single-bit value or a multi-bit value, and this application does not limit this. In some embodiments, the target data for the first value can be 1, and the target data for the second value can be 0.

[0107] In some embodiments, during a reset operation, the current signal of the source line connected to the target memory cell can be detected to determine whether the target data of the second value has been successfully written to the target memory cell.

[0108] In some embodiments, during the process of reading stored data from the target memory cell or writing stored data to the target memory cell, the method further includes: setting the voltage of bit lines not connected to the target memory cell and the reference memory cell to zero; setting the voltage of word lines located on the same side of the wafer as the target memory cell and not connected to the target memory cell to zero; and setting the voltage of word lines located on the same side of the wafer as the reference memory cell and not connected to the reference memory cell to a high voltage.

[0109] Understandably, in order to ensure the orderly operation of the memory array in the semiconductor memory, when performing the above-mentioned read operation, write operation or reset operation, the voltage of the bit line not connected to the target memory cell and the reference memory cell can be set to zero, the voltage of the word line on the same side of the wafer as the target memory cell but not connected to the target memory cell can be set to zero, and the voltage of the word line on the same side of the wafer as the reference memory cell but not connected to the reference memory cell can be set to high voltage.

[0110] The following is a specific example illustrating the semiconductor memory and data read / write method in the embodiments of this application.

[0111] See Figures 2 to 3 As shown in the top front view, four first memory cell groups 11 are arranged in a 2×2 array on the front side of the wafer, namely two first memory cell groups 11 arranged along a first horizontal direction and two first memory cell groups 11 arranged along a second horizontal direction. Each first memory cell group 11 includes two first memory cells 4 symmetrically arranged along the first horizontal direction. The two first memory cells 4 share a source structure. The top front view also shows a fin structure 13 extending along the first horizontal direction, a first bit line 6 extending along the first horizontal direction, a word line 8 extending along the second horizontal direction, and a source line 7 extending along the second horizontal direction.

[0112] The rear top view shows four second memory cell groups 12 arranged in a 2×2 array on the wafer, namely two second memory cell groups 12 arranged along a first horizontal direction and two second memory cell groups 12 arranged along a second horizontal direction. Each second memory cell 5 includes two second memory cells 5 symmetrically arranged along the first horizontal direction. The two second memory cells 5 share a source structure. The rear top view also shows a fin structure 13 extending along the first horizontal direction, a second bit line 9 extending along the first horizontal direction, and a gate structure extending along the second horizontal direction.

[0113] In this design, four first memory cell groups 11 on the front side of the wafer and four second memory cell groups 12 on the back side of the wafer correspond one-to-one, with each first memory cell group 11 positioned opposite to one second memory cell group 12. The first transistors on the front side of the wafer and the second transistors on the back side of the wafer employ common-source, common-gate, and common-drain structures, respectively. Thus, the two first memory cell groups 11 arranged along the first horizontal direction on the front side of the wafer share the same first bit line 6, and the two first memory cells 4 and two second memory cells 5 arranged along the second horizontal direction on both the front and back sides of the wafer share the same word line 8. The two second memory cell groups 12 arranged along the first horizontal direction on the back side of the wafer share the same second bit line 9. Furthermore, the two first memory cells 4 and two second memory cells 5 arranged along the second horizontal direction on both the front and back sides of the wafer share the same source line 7.

[0114] In other words, the first memory cell group 11 on the front side of the wafer is a standard memory cell containing two first transistors sharing a source line 7. The gate structures of the two first transistors are connected to two different word lines 8. Each standard memory cell on the front side of the wafer contains two first memory cells 4, i.e., two novel memories, both connected to the same first bit line 6. The second memory cell group 12 on the back side of the wafer is also a standard memory cell. No word lines 8 are provided on the back side of the wafer because the gate structures of the second transistors are already connected to the gate structures of the first transistors, so the second transistors can share a word line 8 with the first transistors. No source lines 7 are provided on the back side of the wafer because the source structures of the second transistors are already connected to the source structures of the first transistors, so the second transistors can share a source line 7 with the first transistors. Each standard memory cell on the back side of the wafer contains two second memory cells 5, i.e., two novel memories, both connected to the same second bit line 9.

[0115] Taking an NMOS transistor as the first transistor, a PMOS transistor as the second transistor, and a resistive random access memory (RRAM) as an example, when performing a read operation on a target memory cell (any first memory cell 4 on the front side of the wafer), a read voltage needs to be applied to the first bit line 6 (i.e., the bit line connected to the target memory cell), and a positive voltage needs to be applied to the word line 8. The voltage of the source line 7 where the target memory cell is located is set to zero, and the second bit line 9 where the reference memory cell (i.e., the second memory cell 5 opposite to the target memory cell) is located is floated, and the voltage of the word line 8 where the reference memory cell is located is set to zero. The voltages of the remaining word lines 8 are set to zero, the voltage of word lines 8 not connected to the target memory cell is set to zero, and the voltage of word lines 8 not connected to the reference memory cell is set to high voltage. By reading the current on the source line 7, it is determined that the read operation on the target memory cell was successfully executed. When performing a read operation on the reference memory cell on the back side of the wafer, the operations of the first bit line 6 connected to the target memory cell and the second bit line 9 connected to the reference memory cell are swapped, and the remaining routing operations are the same.

[0116] When performing a write (SET) or reset (RESET) operation, the voltage applied to the bit line and source line 7 depends on the connection of the memory cell. Taking a positively connected memory cell as an example, to perform a write operation on a target memory cell located on the front side of the wafer, a write voltage needs to be applied to the first bit line 6 where the target memory cell is located, and a positive voltage needs to be applied to the word line 8 where the target memory cell is located. The voltage of the source line 7 where the target memory cell is located is set to zero, and the second bit line 9 where the reference memory cell is located is floated, and the voltage of the word line 8 where the reference memory cell is located is set to zero. The voltages of the remaining word lines 8 are set to zero, the voltage of word lines 8 not connected to the target memory cell is set to zero, and the voltage of word lines 8 not connected to the reference memory cell is set to high voltage. The write operation on the target memory cell is confirmed to have been successfully performed by reading the current on the source line 7. When performing a write operation on a reference memory cell on the back side of the wafer, the operations of the first bit line 6 connected to the target memory cell and the second bit line 9 connected to the reference memory cell are swapped, and the remaining routing operations are the same.

[0117] Taking a positively connected memory cell as an example, to perform a reset operation on a target memory cell located on the front side of the wafer, a reset voltage needs to be applied to the source line 7 where the target memory cell is located, and a positive voltage needs to be applied to the word line 8 where the target memory cell is located. The voltage of the first bit line 6 where the target memory cell is located is set to zero, and the second bit line 9 where the reference memory cell is located is floated, with the voltage of the word line 8 where the reference memory cell is located set to zero. The voltage of the remaining word lines 8 is set to zero, the voltage of word lines 8 not connected to the target memory cell is set to zero, and the voltage of word lines 8 not connected to the reference memory cell is set to a high voltage. By reading the current magnitude on the source line 7, it is confirmed that the reset operation on the target memory cell was successfully performed.

[0118] In the embodiments of this application, the first or second storage unit of the array can be selected independently, and each first or second storage unit can also be addressed independently, thereby achieving precise operation of a single storage unit and effectively improving the integration density and operational reliability of the array.

[0119] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A semiconductor memory, characterized in that, include: A first storage array, the first storage array comprising a plurality of first storage cells; A second storage array, the second storage array comprising a plurality of second storage cells; The first storage unit and the second storage unit correspond one-to-one, and each first storage unit is arranged opposite to one second storage unit; wherein, The first end of the first memory cell is connected to the first bit line, the second end is connected to the source line, and the control end is connected to the word line; The first end of the second storage unit is connected to the second bit line, the second end is connected to the source line, and the control end is connected to the word line.

2. The semiconductor memory according to claim 1, characterized in that, The first memory cell includes: a first transistor and a first memory device; wherein, The first end of the first memory device is connected to the drain structure of the first transistor, the second end of the first memory device is connected to the first bit line as the first end of the first memory cell, the source structure of the first transistor is connected to the source line as the second end of the first memory cell, and the gate structure of the first transistor is connected to the word line as the control terminal of the first memory cell. The second memory cell includes: a second transistor and a second memory device; wherein, The first end of the second memory device is connected to the drain structure of the second transistor, the second end of the second memory device serves as the first end of the second memory cell and is connected to the second bit line, the source structure of the second transistor serves as the second end of the second memory cell and is connected to the source line, and the gate structure of the second transistor serves as the control terminal of the second memory cell and is connected to the word line.

3. The semiconductor memory according to claim 2, characterized in that, The first transistor is an N-type transistor, and the second transistor is an N-type transistor; or, the first transistor is a P-type transistor, and the second transistor is a P-type transistor.

4. The semiconductor memory according to claim 2, characterized in that, In the first memory array, every two adjacent first memory cells form a first memory cell group; the two first transistors in the first memory cell group share a source structure. And / or, In the second memory array, every two adjacent second memory cells form a second memory cell group; the two second transistors in the second memory cell group share a source structure.

5. The semiconductor memory according to claim 4, characterized in that, The first storage unit group and the second storage unit group are in one-to-one correspondence, and each first storage unit group is arranged opposite to one second storage unit group; wherein, The source structure of the first transistor in the first memory cell group is connected to the source structure of the second transistor in the second memory cell group; The drain structure of the first transistor in the first memory cell group is connected to the drain structure of the second transistor in the second memory cell group; The gate structure of the first transistor in the first memory cell group is connected to the gate structure of the second transistor in the second memory cell group.

6. The semiconductor memory according to claim 2, characterized in that, The source / drain regions and gate regions in the first transistor and the second transistor are arranged alternately in the first horizontal direction; The first bit line and the second bit line extend along the first horizontal direction; The character line extends along the second horizontal direction; The second horizontal direction is perpendicular to the first horizontal direction; The source line extends along the first horizontal direction and / or the second horizontal direction.

7. An electronic device, characterized in that, It includes a circuit board and a semiconductor memory as described in any one of claims 1 to 6, wherein the semiconductor memory is disposed on the circuit board.

8. A data read / write method, characterized in that, The method, applied to a semiconductor memory as described in any one of claims 1 to 6, comprises: For the target memory cell to be accessed in the semiconductor memory and the reference memory cell on the back side of the target memory cell, the following operations are performed: Set the voltage of the word line connected to the target memory cell to a positive voltage; Set the voltage of the bit line connected to the target memory cell to the read voltage; Set the voltage of the source line connected to the target memory cell to zero; Float the bit line connected to the reference memory cell; The current signal of the source line connected to the target storage unit is detected in order to read the target data of the target storage unit.

9. The method according to claim 8, characterized in that, The method further includes: Set the voltage of the word line connected to the target memory cell to a positive voltage; The voltage of the bit line connected to the target memory cell is set to a set voltage; the set voltage is used to write target data of a first value into the target memory cell. Set the voltage of the source line connected to the target memory cell to zero; The bit lines connected to the reference memory cell are floated.

10. The method according to claim 8, characterized in that, The method further includes: Set the voltage of the word line connected to the target memory cell to a positive voltage; Set the voltage of the source line connected to the target storage unit to a reset voltage; the reset voltage is used to write the target data of the second value into the target storage unit. Set the voltage of the bit line connected to the target memory cell to zero; The bit lines connected to the reference memory cell are floated.

11. The method according to any one of claims 8 to 10, characterized in that, During the process of reading stored data from the target storage unit or writing stored data to the target storage unit, the method further includes: Set the voltage of the bit lines not connected to the target memory cell and the reference memory cell to zero; Set the voltage of word lines not connected to the target memory cell and the reference memory cell to zero.

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