Hvmos with lateral parasitic structure and method of fabrication

Abstract

The application discloses an HVMOS with a transverse parasitic structure and a preparation method, and belongs to the technical field of semiconductors, and comprises the following: a P-type substrate; an N-type buried layer formed on the surface of the P-type substrate; a P-type epitaxial layer formed on the surface of the N-type buried layer; a plurality of high-voltage N wells formed in the P-type epitaxial layer; wherein the surface of each high-voltage N well is formed with an N well, and the surface of each N well is formed with a first N-type heavily doped region; a P-type active region is formed between each two adjacent high-voltage N wells, the surface of the first P well of one active region is formed with a first P-type heavily doped region, the surface of the second P well of an adjacent active region is formed with a second P-type heavily doped region and a second N-type heavily doped region; the second P-type heavily doped region, the second N-type heavily doped region and the first N-type heavily doped region are electrically connected as a first electrode, and the first P-type heavily doped region is used as a second electrode. The structure of the application forms an extremely low-impedance path to discharge current, and relieves chip heating and burning.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an HVMOS with a lateral parasitic structure and its fabrication method. Background Technology

[0002] In the field of high-voltage power semiconductor devices, HVMOS (High Voltage Metal-Oxide-Semiconductor Field-Effect Transistor) is widely used in various power output scenarios due to its high voltage withstand capability. However, conventional HVMOS devices have significant structural defects: their body diode has poor freewheeling capability, and when current is injected into the device, a considerable portion of the current flows to the P-type substrate (PSUB) through the parasitic PNP transistor inside the device. This substrate current injection not only significantly reduces the output efficiency of the device but also introduces noise into the substrate, interfering with the normal operation of other circuits inside the chip. At the same time, the concentrated current injection into the substrate causes localized heating of the chip, and the heat accumulation over long-term operation can, in severe cases, cause the chip to burn out directly, greatly affecting the reliability, robustness, and market competitiveness of the product, and failing to meet the usage requirements of high-voltage power applications. Summary of the Invention

[0003] The purpose of this invention is to overcome the problem of poor freewheeling capability of diodes in the prior art, and to provide an HVMOS with a lateral parasitic structure and its fabrication method. By constructing a completely new ultra-low impedance path, unnecessary parasitic paths are bypassed, and the current that originally flowed to the P-type substrate is returned to the predetermined path, thereby improving the product output efficiency, alleviating chip heating and burn-out phenomena, and enhancing the product's competitiveness and robustness.

[0004] The first aspect of this application provides an HVMOS with a lateral parasitic structure, comprising: P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well, and a first N-type heavily doped region is formed on the surface of each N-well; In this configuration, a P-type active region is formed between two adjacent high-voltage N-wells, and at least one P-well is formed on the surface of each P-type active region. Furthermore, a first P-type heavily doped region is formed on the surface of the first P-well of one active region, and a second P-type heavily doped region and a second N-type heavily doped region are formed on the surface of the second P-well of an adjacent active region. The second P-type heavily doped region, the second N-type heavily doped region, and the first N-type heavily doped region are electrically connected as a first electrode, and the first P-type heavily doped region is used as a second electrode to form at least two lateral parasitic transistors between the two electrodes.

[0005] By employing differentiated injection designs for different P-wells within the P-type active region between adjacent high-voltage N-wells (one forming only the P+ region, and the other forming both the P+ and N+ regions), and combining this with a defined electrode connection method, additional parasitic transistor paths are constructed in the lateral direction of the device. These lateral paths are in a state of shutdown under normal low-current operation, without affecting the normal operation of the device. However, they are triggered when the input current is too large, providing an extremely low-impedance lateral discharge channel for excess carriers. This not only effectively bypasses the current that would otherwise flow excessively to the P-type substrate through the longitudinal parasitic PNPs, reducing substrate noise and heat accumulation, alleviating chip overheating and burn-out phenomena, but also improves the output efficiency under high current and enhances the robustness and competitiveness of the product under high current stress.

[0006] As described above, in an HVMOS with a lateral parasitic structure, optionally, the first P-type heavily doped region / P-type epitaxial layer, the N-type buried layer, and the P-type substrate electrically connected by the second electrode constitute a vertical parasitic PNP transistor for conducting current injected into the P-type substrate.

[0007] The vertical parasitic PNP transistor is the main parasitic path that causes current to flow to the substrate in conventional HVMOS. By designing the subsequent lateral parasitic transistor, the current in this path can be bypassed in a targeted manner, thereby reducing the proportion of current flowing to the P-type substrate, so as to solve problems such as substrate noise and chip heating. In addition, Q1 also provides a backup path for current conduction in the device, improving the stability of device operation.

[0008] In the HVMOS with lateral parasitic structure described above, optionally, the at least two lateral parasitic transistors include a lateral parasitic PNP transistor and a lateral parasitic NPN transistor.

[0009] By combining PNP and NPN transistors, a positive feedback loop can be formed, which enters a low-resistance conduction state after triggering, significantly reducing current conduction impedance. Compared with a single type of parasitic transistor, it can achieve faster current triggering and more efficient current discharge, improve the bypass effect on the longitudinal parasitic PNP transistor current, thereby improving output efficiency and alleviating heat generation problems.

[0010] In the HVMOS with lateral parasitic structure described above, optionally, the emitter of the lateral parasitic PNP transistor is a first P-type heavily doped region, the base is a high-voltage N-well, and the collector is a second P-type heavily doped region in a second P-well.

[0011] Lateral parasitic PNP transistors can quickly receive current from the second electrode and conduct it to the first electrode, forming a lateral current path. Their base is connected to a high-voltage N-well, enabling them to respond quickly to high-voltage stress.

[0012] In the HVMOS with lateral parasitic structure described above, optionally, the emitter of the lateral parasitic NPN transistor is a high-voltage N-well, the base is a P-type epitaxial layer, and the collector is an N-type buried layer.

[0013] Lateral parasitic PNP transistors and lateral parasitic NPN transistors work together to form a positive feedback loop. After being triggered, they can quickly enter a low-resistance conduction state, further reducing current conduction impedance and ensuring efficient bypass of the current of the longitudinal parasitic PNP transistor, reducing the current flowing to the substrate and alleviating substrate noise and chip heating.

[0014] In the HVMOS with lateral parasitic structure described above, optionally, the trigger voltage of the lateral parasitic PNP transistor and the lateral parasitic NPN transistor is lower than the breakdown voltage of the longitudinal parasitic PNP transistor.

[0015] During normal low-current operation, the voltage across the device is low, below the trigger voltage of the lateral parasitic PNP and NPN transistors. Therefore, the lateral path remains off, and current is conducted only through the longitudinal path. When the input current is too large, causing the voltage across the device to rise to near but not yet reach the breakdown voltage of the longitudinal parasitic PNP transistor, the lateral parasitic PNP and NPN transistors, with their even lower trigger voltages, will turn on first, prior to the breakdown of the longitudinal parasitic PNP transistor. Once the lateral parasitic PNP and NPN transistors are turned on, the low-impedance lateral path they form immediately diverts a large number of excess carriers, thereby clamping the voltage rise further and effectively suppressing the longitudinal current flowing to the P-type substrate. This not only protects the longitudinal parasitic PNP transistor in the longitudinal path from overcurrent surges but also provides a safe discharge path for large currents.

[0016] As described above, in an HVMOS with a lateral parasitic structure, a shallow trench for insulating isolation is optionally formed between two adjacent heavily doped regions.

[0017] The shallow trench is filled with insulating material (such as silicon dioxide) to ensure the insulation isolation between adjacent heavily doped regions, avoid leakage and parasitic conduction, improve the reliability and stability of the device, ensure that the lateral parasitic transistor can work stably, and achieve efficient current bypass.

[0018] As described above, in the HVMOS with lateral parasitic structure, the doping concentration of the high-voltage N-well is optionally higher than that of the P-type epitaxial layer. The high-concentration doped high-voltage N-well can improve its conductivity, reduce resistance during current conduction, further enhance the low impedance characteristics of the lateral parasitic path, and improve current discharge efficiency. Simultaneously, the high-concentration doped HVNW can better serve as the base of the lateral parasitic PNP transistor and the emitter of the lateral parasitic NPN transistor, ensuring that the two lateral parasitic transistors can be quickly triggered and turned on, improving the response speed of current bypass. Furthermore, high-concentration doping can also improve the high-voltage withstand capability of the high-voltage N-well, ensuring stable operation of the device in high-voltage applications and avoiding device failure due to high-voltage breakdown.

[0019] A second aspect of this application provides a method for fabricating an HVMOS with a lateral parasitic structure, comprising: P-type substrates are provided; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well, and a first N-type heavily doped region is formed on the surface of each N-well, and a P-type active region is formed between two adjacent high-voltage N-wells. At least one P-well is formed on the surface of each of the P-type active regions, and a first P-type heavily doped region is formed on the surface of the first P-well in one of the active regions, and a second P-type heavily doped region and a second N-type heavily doped region are formed on the surface of the second P-well in the adjacent active regions. The second P-type heavily doped region, the second N-type heavily doped region, and the first N-type heavily doped region are electrically connected as a first electrode, and the first P-type heavily doped region is used as a second electrode to form at least two lateral parasitic transistors between the two electrodes.

[0020] The above-mentioned fabrication method can precisely control the thickness, doping concentration, and position of each layer, ensuring that the fabricated HVMOS device meets the design requirements. Through stepwise ion implantation and annealing processes, doped ions can be effectively activated, lattice defects can be repaired, and the conductivity and stability of the device can be improved. At the same time, the process steps are simplified, eliminating the need for additional fabrication of P-type active regions, thus reducing fabrication costs and process difficulty. The fabricated device can stably form lateral parasitic transistor paths, realizing current bypass function and effectively solving the technical defects of conventional devices.

[0021] Optionally, the method for fabricating an HVMOS with a lateral parasitic structure as described above may further include: Shallow trenches are formed between two adjacent heavily doped regions for insulation.

[0022] The fabrication of shallow trench isolation ensures the insulation and isolation effect between adjacent heavily doped regions, avoids leakage and parasitic conduction, improves the reliability and stability of the device, ensures that lateral parasitic transistors can work stably, and achieves efficient current bypass. Attached Figure Description

[0023] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Appendix Figure 1 A schematic diagram of an HVMOS with a lateral parasitic structure provided in this application embodiment; Appendix Figure 2 This is a schematic flowchart illustrating a method for fabricating an HVMOS with a lateral parasitic structure, as provided in an embodiment of this application. 101-P-type substrate; 102-N-type buried layer; 103-P-type epitaxial layer; 104-High-voltage N-well; 105-N-well; 106-First heavily doped N-type region; 107-P-well; 108-First heavily doped P-type region; 109-Second heavily doped P-type region; 110-Second heavily doped N-type region; 111-Shallow trench; 1071-First P-well; 1072-Second P-well; 1031-P-type active region; A-First electrode; B-Second electrode. Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] In existing technologies, there are three methods to address the shortcomings of conventional HVMOS. The first is to address it from a process perspective by selecting a process with DTI (Distributed Tilting Induction) to weaken the effect of parasitic PNP. However, this process is relatively expensive and only supported by specific process manufacturers, thus lacking universality and cost-effectiveness. The second is to address it from the design perspective by having engineers modify the schematic to reduce the forward bias of the body diode, thereby weakening the effect of parasitic PNP. However, this approach relies heavily on the engineer's design experience and capabilities, making it difficult to promote its widespread application. The third method involves some FAB (Fabrication Equipment) manufacturers providing isolation ring structures that can reduce PNP injection. This approach can indeed alleviate the freewheeling effect of the body diode to some extent, but there is still a risk of failure in high-power, high-current scenarios. The protection it provides for certain products is very limited and insufficient to completely solve the problem.

[0026] Based on this, such as Figure 1 As shown, this embodiment provides an HVMOS with a lateral parasitic structure, which includes a P-type substrate 101, an N-type buried layer 102, a P-type epitaxial layer 103, a plurality of high-voltage N-wells 104 to connect electrodes (A and B); wherein, a P-type active region 1031 is formed between two adjacent high-voltage N-wells 104, and at least one P-well 107 is formed on the surface of each P-type active region 1031, and a plurality of heavily doped regions are formed on the surface of the P-well 107.

[0027] Specifically, the P-type substrate 101 serves as the device substrate, providing mechanical support and electrical foundation for the growth and fabrication of the entire structure; the N-type buried layer 102 is formed on the surface of the P-type substrate 101. The N-type buried layer 102 is a highly doped buried layer used to provide a low-resistance lateral current channel and isolate the upper device structure from the lower P-type substrate to reduce substrate noise coupling and latch-up risk during normal operation; the P-type epitaxial layer 103 is formed on the surface of the N-type buried layer 102. It is a low-doped P-type single-crystal silicon layer grown on the N-type buried layer, providing high-quality bulk material for the subsequent formation of active region devices.

[0028] Multiple high-voltage N-wells 104 are formed in a P-type epitaxial layer 103. These high-voltage N-wells 104 extend vertically downward from the surface of the P-type epitaxial layer 103 without penetrating the entire epitaxial layer (this can be adjusted according to design parameters). Each high-voltage N-well 104 has an N-well 105 formed on its surface region, and each N-well 105 has a first heavily doped N-type region 106 formed on its surface. The N-wells 105 and the first heavily doped N-type region 106 together constitute the N-type contact region of this region, used to form a low-resistance ohmic contact with the metal electrode.

[0029] Between two adjacent high-voltage N-wells 104, a region, namely a P-type active region, is naturally formed in the P-type epitaxial layer 103. At least one P-well 107 is formed on the surface of each P-type active region. Specifically, on the surface of the first P-well 1071 in one active region, only a first heavily doped P-type region 108 is formed, which serves as the subsequent second electrode B (e.g., drain D). On the surface of the second P-well 1072 in the adjacent active region, a second heavily doped P-type region 109 and a second heavily doped N-type region 110 are simultaneously formed.

[0030] When connecting the electrodes, the second P-type heavily doped region 109, the second N-type heavily doped region 110, and a first N-type heavily doped region 106 (i.e., the N+ region on the N-well near the active region) are electrically connected together by a metal interconnect, serving as the first electrode A (e.g., the source S), while the first P-type heavily doped region 108 serves as the second electrode B (e.g., the drain D). Through this connection method, multiple parasitic transistors are naturally formed inside the device, including one vertical parasitic transistor, which serves as the normal operating current path, and at least two lateral parasitic transistors (i.e.,... Figure 1 (Q2 - red and Q3 - gray in the diagram) The aforementioned lateral parasitic transistors (Q2), lateral parasitic transistors (Q3), and internal structures constitute a low-resistance discharge path (parasitic SCR structure) from terminal B to terminal A for current discharge.

[0031] It should be added that, attached Figure 1 The diagram illustrates an HVMOS with a symmetrical structure on both sides, and the internal structure in the middle is also a P-type active region. The two adjacent P-type active regions described above are isolated by a high-voltage N-well 104, such as the P-type active region on the left and the internal structure in the middle, or the P-type active region on the right and the internal structure in the middle.

[0032] In addition, the P-type well (PW) active region of the internal structure, located in the P-type epitaxial layer (PEPI), serves as the common connection node between Q2 and Q3 and participates in the formation of the SCR positive feedback loop.

[0033] This application constructs additional lateral parasitic transistor paths in the lateral direction of the device by performing differentiated injection designs on different P-wells in the P-type active region between adjacent high-voltage N-wells (one forms only a P+ region, and the other forms both a P+ region and an N+ region), and combining this with a set electrode connection method. Figure 1(Q2 and Q3 in the diagram). These lateral parasitic paths are in a turned-off state under normal low-current operating conditions and do not affect the normal operation of the device. However, they are triggered when the input current is too large, providing an extremely low-impedance lateral discharge channel for excess carriers. This not only effectively bypasses the current that would originally flow excessively to the P-type substrate through the longitudinal parasitic PNP, reducing substrate noise and heat accumulation, alleviating chip heating and burn-out, but also improves the output efficiency under high current and enhances the robustness and competitiveness of the product under high current stress.

[0034] In the HVMOS structure of this embodiment, a parasitic vertical PNP transistor is included. Figure 1 Q1 (blue schematic) is specifically composed of: an emitter connected to a first P-type heavily doped region 108 and a P-type epitaxial layer 103 electrically connected to the second electrode B, a base of an N-type buried layer 102, and a collector of a P-type substrate 101. That is, the first P-type heavily doped region / P-type epitaxial layer (P-type), the N-type buried layer (N-type), and the P-type substrate (P-type) together constitute a parasitic vertical PNP transistor (Q1). The main function of this transistor is to conduct the current originally injected into the P-type substrate.

[0035] The parasitic vertical PNP transistor is the main parasitic path that causes current to flow to the substrate in conventional HVMOS. By designing a subsequent lateral parasitic transistor, the current in this path is bypassed in a targeted manner, thereby reducing the proportion of current flowing to the P-type substrate, so as to solve problems such as substrate noise and chip heating. In addition, Q1 also provides a backup path for current conduction in the device, improving the stability of device operation.

[0036] In one embodiment, at least two lateral parasitic transistors are located between the two electrodes, specifically including a lateral parasitic PNP transistor (Q2) and a lateral parasitic NPN transistor (Q3). The two lateral parasitic transistors cooperate with each other to form a parasitic SCR structure, creating a current discharge path with extremely low impedance.

[0037] By combining PNP transistor (Q2) and NPN transistor (Q3), a positive feedback loop can be formed, which enters a low-resistance conduction state after triggering, greatly reducing the current conduction impedance. Compared with a single type of parasitic transistor, it can achieve faster current triggering and more efficient current discharge, improve the bypass effect on the parasitic vertical PNP transistor (Q1) current, so as to improve output efficiency and alleviate heat generation problems.

[0038] For example, the specific structure of the lateral parasitic PNP transistor (Q2) is as follows: the emitter is the first P-type heavily doped region 108, the base is the high-voltage N-well 104, and the collector is the second P-type heavily doped region 109 in the second P-well 1072 on the left. That is, the first P-type heavily doped region, the high-voltage N-well, and the second P-type heavily doped region constitute a complete lateral PNP transistor structure. Its current direction is that holes are injected from the emitter (first P-type heavily doped region), pass through the base (high-voltage N-well), and are collected by the collector (second P-type heavily doped region), realizing lateral current conduction.

[0039] The lateral parasitic NPN transistor (Q3) is specifically constructed as follows: the emitter is a high-voltage N-well 104, the base is a P-type epitaxial layer 103, and the collector is an N-type buried layer 102. That is, the complete lateral NPN transistor structure is composed of N-type (high-voltage N-well) - P-type (P-type epitaxial layer) - N-type (N-type buried layer). The current direction is that electrons are injected from the emitter (high-voltage N-well), pass through the base (P-type epitaxial layer), and are collected by the collector (N-type buried layer), thus realizing lateral current conduction.

[0040] By employing a complementary lateral parasitic structure with Q2 and Q3, Q2 can quickly receive the current from the second electrode and conduct it to the first electrode, forming a lateral current path. At the same time, the base of Q2 is connected to the high-voltage N-well, enabling it to respond quickly to high-voltage stress. Q3 and Q2 work together to form a positive feedback loop, which can quickly enter a low-resistance conduction state after triggering, further reducing the current conduction impedance and ensuring efficient bypassing of the current of the parasitic vertical PNP transistor (Q1), reducing the current flowing to the substrate, and alleviating substrate noise and chip heating.

[0041] like Figure 1 As shown, resistors Rp (P-well 107) and Rn (N-type buried layer 102) are also formed in the P-type epitaxial layer to adjust the base current of the lateral parasitic transistors Q2 and Q3 and optimize the SCR trigger characteristics.

[0042] Furthermore, when designing transistors, it is necessary to ensure that the trigger voltages (i.e., turn-on voltages) of the lateral parasitic PNP transistor (Q2) and the lateral parasitic NPN transistor (Q3) are lower than the breakdown voltage of the parasitic vertical PNP transistor (Q1). Specifically, during normal low-current operation, the voltage across the device is low and has not reached the trigger voltages of Q2 and Q3. Therefore, the lateral path remains off, and current is conducted only through the vertical path (Q1 and the main BVMOS). When the input current is too large, causing the voltage across the device to rise to near but not yet reach the breakdown voltage of Q1, Q2 and Q3, with their even lower trigger voltages, will turn on first, prior to the breakdown of Q1. Once Q2 and Q3 turn on, the low-impedance lateral path they form immediately diverts a large number of excess carriers, thereby clamping the voltage rise further and effectively suppressing the vertical current flowing to the P-type substrate. This not only protects the vertical path Q1 from overcurrent surges but also provides a safe discharge path for large currents.

[0043] Between two adjacent heavily doped regions (including the first N-type heavily doped region, the second N-type heavily doped region, the first P-type heavily doped region, and the second P-type heavily doped region), a shallow trench (STI) 111 is formed for insulation isolation. The shallow trench is filled with an insulating material (such as silicon dioxide) to ensure the insulation isolation effect between adjacent heavily doped regions, avoid leakage and parasitic conduction, improve the reliability and stability of the device, ensure that the lateral parasitic transistor can work stably, and achieve efficient current bypass.

[0044] In one embodiment, the doping concentration of the high-voltage N-well is higher than that of the P-type epitaxial layer. The high-concentration doped high-voltage N-well improves its conductivity, reduces resistance during current conduction, further enhances the low-impedance characteristics of the lateral parasitic path, and improves current discharge efficiency. Simultaneously, the high-concentration doped high-voltage N-well can better serve as the base of Q2 and the emitter of Q3, ensuring that the two lateral parasitic transistors can be quickly triggered and turned on, improving the response speed of current bypass. Furthermore, high-concentration doping also improves the high-voltage withstand capability of the high-voltage N-well, ensuring stable operation of the device in high-voltage applications and preventing device failure due to high-voltage breakdown.

[0045] Based on the same application concept, such as Figure 2 As shown in the figure, this embodiment also provides a method for fabricating an HVMOS with a lateral parasitic structure, including the following steps.

[0046] Step S10: Provide a P-type substrate; Step S20: Form an N-type buried layer on the surface of a P-type substrate; Step S30: Form a P-type epitaxial layer on the surface of the N-type buried layer; Step S40: Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well, and a first N-type heavily doped region is formed on the surface of each N-well, and a P-type active region is formed between two adjacent N-type deep wells. Step S50: At least one P-well is formed on the surface of each P-type active region, and a first P-type heavily doped region is formed on the surface of the first P-well in an active region, and a second P-type heavily doped region and a second N-type heavily doped region are formed on the surface of the second P-well in the adjacent active region. Step S60: Electrically connect the second P-type heavily doped region, the second N-type heavily doped region, and a first N-type heavily doped region as the first electrode, and the first P-type heavily doped region as the second electrode, to form at least two lateral parasitic transistors between the two electrodes.

[0047] Specifically, a P-type substrate is first provided, using a high-purity P-type single-crystal silicon wafer to ensure it is free of impurities and defects, providing a good substrate for the growth of subsequent layers and ensuring the electrical performance and reliability of the device. Then, an N-type buried layer is formed by implanting N-type dopant ions (such as phosphorus ions) onto the surface of the P-type substrate using an ion implantation process, followed by a high-temperature annealing process to uniformly diffuse and activate the N-type dopant ions, forming the N-type buried layer. The annealing process repairs lattice defects generated during ion implantation, improving the conductivity and stability of the N-type buried layer. Finally, a P-type epitaxial layer is formed on the surface of the N-type buried layer using an epitaxial growth process. The thickness and doping concentration of the epitaxial layer are controlled to ensure good interface bonding between the epitaxial layer and the N-type buried layer, providing a high-quality active region for the subsequent formation of high-voltage N-wells, P-wells, and other structures.

[0048] This process forms high-voltage N-wells and N-type contacts. In the P-type epitaxial layer, high-concentration N-type dopant ions are implanted through multiple ion implantation processes, combined with high-temperature annealing, to form multiple high-voltage N-wells. Subsequently, N-wells are formed on the surface of each high-voltage N-well as N-type contacts through ion implantation and annealing. High-concentration N-type ions are then implanted on the surface of each N-well to form the first heavily doped N-type region. At the same time, a P-type active region is naturally formed between two adjacent high-voltage N-wells, eliminating the need for separate fabrication and simplifying the process steps.

[0049] Continue to form P-wells and heavily doped regions. On the surface of each P-type active region, at least one P-well is formed through ion implantation and annealing. Specifically, on the surface of the first P-well in a P-type active region, a high concentration of P-type ions (such as boron ions) is implanted to form a first heavily doped P-type region. On the surface of the second P-well in an adjacent P-type active region, high concentrations of P-type ions and high concentrations of N-type ions are implanted respectively to form a second heavily doped P-type region and a second heavily doped N-type region, ensuring good ohmic contact performance in each heavily doped region.

[0050] Finally, the first and second electrodes are formed. A metal layer (such as aluminum or copper) is deposited on the device surface through a metal deposition process (such as sputtering or evaporation). Then, the metal layer is patterned through photolithography and etching processes. The second P-type heavily doped region, the second N-type heavily doped region, and a first N-type heavily doped region are electrically connected to form the first electrode of the device. The first P-type heavily doped region is led out through metal wiring to serve as the second electrode of the device. Through the above steps, at least two lateral parasitic transistors are formed between the two electrodes, and a complete HVMOS with a lateral parasitic structure is obtained.

[0051] This fabrication method features clear steps and mature technology, enabling precise control over the thickness, doping concentration, and location of each layer to ensure that the fabricated HVMOS device meets design requirements. Through stepwise ion implantation and annealing, the method effectively activates dopant ions, repairs lattice defects, and improves the device's conductivity and stability. Furthermore, the simplified process eliminates the need for additional P-type active region fabrication, reducing fabrication costs and process complexity. The fabricated device can stably form lateral parasitic transistor paths, enabling current bypass functionality, effectively addressing the technical deficiencies of conventional devices, and improving production efficiency and yield.

[0052] The above fabrication process also includes a step of forming shallow trenches (STIs) for insulation isolation between two adjacent heavily doped regions. Specifically, after forming each heavily doped region and before metal deposition, the position of the shallow trench is defined by photolithography. Then, the shallow trench is etched between the adjacent heavily doped regions by etching. The shallow trench is then filled with an insulating material (such as silicon dioxide). Finally, planarization is performed to complete the fabrication of the shallow trench isolation. This ensures the insulation isolation effect between adjacent heavily doped regions, avoids leakage and parasitic conduction, improves the reliability and stability of the device, ensures that the lateral parasitic transistor can work stably, and achieves efficient current bypass.

[0053] In the foregoing description of this application, unless otherwise expressly specified and limited, the terms "fixed," "installed," "connected," or "linked" should be interpreted broadly. For example, the term "linked" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; or it can refer to the internal communication of two components or the interaction between two components. Therefore, unless otherwise expressly limited in this application, those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0054] Based on the above description of this application, those skilled in the art will also understand that terms used, such as "upper," "lower," "length," "width," "top," "bottom," "inner," "outer," "axial," "longitudinal," "transverse," "clockwise," or "counterclockwise," indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings of this application. These terms are used only for the purpose of facilitating the explanation of the application and simplifying the description, and are not intended to imply that the device or element involved must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the aforementioned orientation or positional relationship terms should not be understood or interpreted as limitations on the application.

[0055] Furthermore, the terms "first" or "second," etc., used in this application to refer to numbers or ordinal numbers are for convenience of description only and should not be construed as explicitly or implicitly indicating relative importance or specifying the number of indicated technical features. Also, a feature specified as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, or more, unless otherwise explicitly specified.

[0056] While numerous embodiments of this application have been shown and described herein, it will be appreciated by those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise in the mind and spirit of this application without departing from its intent. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. An HVMOS with a lateral parasitic structure, characterized in that, include: P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well, and a first N-type heavily doped region is formed on the surface of each N-well; In this configuration, a P-type active region is formed between two adjacent high-voltage N-wells, and at least one P-well is formed on the surface of each P-type active region. Furthermore, a first P-type heavily doped region is formed on the surface of the first P-well of one active region, and a second P-type heavily doped region and a second N-type heavily doped region are formed on the surface of the second P-well of an adjacent active region. The second P-type heavily doped region, the second N-type heavily doped region, and the first N-type heavily doped region are electrically connected as a first electrode, and the first P-type heavily doped region is used as a second electrode to form at least two lateral parasitic transistors between the two electrodes.

2. The HVMOS with a lateral parasitic structure as described in claim 1, characterized in that, The second electrode is electrically connected to the first P-type heavily doped region / P-type epitaxial layer, the N-type buried layer, and the P-type substrate, forming a vertical parasitic PNP transistor for conducting current injected into the P-type substrate.

3. The HVMOS with a lateral parasitic structure as described in claim 2, characterized in that, The at least two lateral parasitic transistors include a lateral parasitic PNP transistor and a lateral parasitic NPN transistor.

4. The HVMOS with a lateral parasitic structure as described in claim 3, characterized in that, The emitter of the lateral parasitic PNP transistor is a first P-type heavily doped region, the base is a high-voltage N-well, and the collector is a second P-type heavily doped region in a second P-well.

5. The HVMOS with a lateral parasitic structure as described in claim 3, characterized in that, The emitter of the lateral parasitic NPN transistor is a high-voltage N-well, the base is a P-type epitaxial layer, and the collector is an N-type buried layer.

6. The HVMOS with a lateral parasitic structure as described in claim 3, characterized in that, The trigger voltage of lateral parasitic PNP transistors and lateral parasitic NPN transistors is lower than the breakdown voltage of longitudinal parasitic PNP transistors.

7. The HVMOS with a lateral parasitic structure as described in claim 1, characterized in that, Shallow trenches are formed between two adjacent heavily doped regions for insulation.

8. The HVMOS with a lateral parasitic structure as described in claim 1, characterized in that, The doping concentration of the high-voltage N-well is higher than that of the P-type epitaxial layer.

9. A method for fabricating an HVMOS with a lateral parasitic structure, characterized in that, include: P-type substrates are provided; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well, and a first N-type heavily doped region is formed on the surface of each N-well, and a P-type active region is formed between two adjacent high-voltage N-wells. At least one P-well is formed on the surface of each of the P-type active regions, and a first P-type heavily doped region is formed on the surface of the first P-well in one of the active regions, and a second P-type heavily doped region and a second N-type heavily doped region are formed on the surface of the second P-well in the adjacent active regions. The second P-type heavily doped region, the second N-type heavily doped region, and the first N-type heavily doped region are electrically connected as a first electrode, and the first P-type heavily doped region is used as a second electrode to form at least two lateral parasitic transistors between the two electrodes.

10. The method for fabricating an HVMOS with a lateral parasitic structure as described in claim 9, characterized in that, The method further includes: Shallow trenches are formed between two adjacent heavily doped regions for insulation.

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