LDMOS device and method of manufacturing the same

Abstract

The application discloses an LDMOS device, which comprises: an ultra-shallow trench isolation formed on a first-type substrate / first-type epitaxial layer; a second-type drift region below the ultra-shallow trench isolation; a first-type body region injection region beside the second-type drift region; a gate insulating medium layer covering the first-type body region injection region, and a gate polysilicon on the gate insulating medium layer; a second-type and a first-type heavily doped injection region formed in the first-type body region injection region; a metal silicification reaction blocking silicon oxide layer covering the second-type drift region and the ultra-shallow trench isolation; an ILD etching stop layer covering a device surface, and an interlayer dielectric layer on the ILD etching stop layer; a contact via connecting the gate polysilicon and the second-type heavily doped injection region through two layers of medium; a plurality of floating contact vias between a gate end and a drain end, connected to the blocking silicon oxide layer; a first metal layer connecting all the vias, and the floating vias and the first metal layer forming a floating metal block; a second metal layer short-circuiting the gate end or the source end and extending to above part of the floating metal block; an intermetallic dielectric layer on the interlayer dielectric layer, and an intermetallic via only connecting the contact via.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to an LDMOS device and its manufacturing method. Background Technology

[0002] DMOS (Double-diffused Metal-Oxide-Semiconductor) devices are widely used in power integrated circuits in power management, automotive electronics, and industrial control due to their excellent high-voltage withstand capability, high-current drive characteristics, and low power consumption. Among them, LDMOS (Lateral DMOS) devices have received significant attention and development in the field of medium- and high-voltage power devices because of their structural compatibility with standard CMOS processes and ease of integration.

[0003] The basic design concept of LDMOS devices is to set a laterally extending N-type drift region below the dielectric layer of the field plate. By adjusting the doping concentration and length of the drift region, the electric field distribution is modulated, thereby increasing the breakdown voltage and reducing the on-resistance to optimize device performance. However, due to the limitations of traditional device structures and process conditions, there is always an inverse relationship between the breakdown voltage and on-resistance of existing LDMOS devices. It is difficult for both to reach ideal levels simultaneously, and there is still significant room for improvement in the overall performance of the devices.

[0004] To further improve breakdown voltage, existing technologies have introduced LDMOS devices employing a Shallow Trench Isolation (STI) field plate structure. This structure places the polysilicon gate portion on top of the STI structure, using the STI dielectric layer as the field plate dielectric. This extends the lateral coverage distance of the gate field plate, reducing the electric field concentration effect at the gate edge and thus improving the device's breakdown voltage. However, to achieve a higher breakdown voltage, the thickness of the STI structure needs to be increased to provide stronger electric field shielding. But increasing the STI thickness narrows the effective current path above the drift region and increases the current flow path in the lateral drift region, significantly increasing the device's on-resistance and raising power consumption in the on-state. Therefore, this traditional STI field plate structure LDMOS device always faces the contradiction of not being able to simultaneously optimize breakdown voltage and on-resistance, especially in medium- and high-voltage applications where the trade-off is more pronounced, severely limiting the device's performance in high-voltage, low-loss applications. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] In view of the technical problems in the prior art, the increase in LDMOS on-resistance due to the increase in STI thickness and the inability to balance breakdown voltage and on-resistance, the present invention provides an LDMOS device and its manufacturing method, which can improve the breakdown voltage of the device while reducing the on-resistance and optimize the performance of medium and high voltage LDMOS.

[0007] The technical problem to be solved by the present invention is to provide an LDMOS device, comprising: An ultra-shallow trench isolation 102 is formed above and inside the first type substrate / first type epitaxial layer 101; The second type drift region 106 is located in the first type substrate / first type epitaxial layer 101 below the ultra-shallow trench isolation 102; The first type body region implantation region 107 is located in the first type substrate / first type epitaxial layer 101 next to the second type drift region 106; The gate insulating dielectric layer 103 covers the first body region implantation region 107, and the gate polysilicon 104 is located above the gate insulating dielectric layer 103; Sidewall dielectric layers 108 are formed on both sides of the gate polysilicon 104; The second type heavily doped implantation region 109 and the first type heavily doped implantation region 110 are formed within the first type bulk implantation region 107; A metallization reaction-blocking silicon oxide layer 201 covers the type II drift region 106 and the ultra-shallow trench isolation 102; The ILD etch stop layer 112 covers the entire upper surface of the device, and the interlayer dielectric layer 114 covers the ILD etch stop layer 112. Contact via 115 passes through ILD etch stop layer 112 and interlayer dielectric layer 114 and is connected to gate polysilicon 104 and type-2 heavily doped implantation region 109; Multiple floating contact vias 115-n located between the gate and drain ends pass through the ILD etch stop layer 112 and the interlayer dielectric layer 114 and are connected to the metal silicide reaction barrier silicon oxide layer 201. The first metal layer 116 is located above the interlayer dielectric layer 114 and is connected to the top of each contact via 115 and the floating contact via 115-n. Each floating contact via 115-n and the first metal layer 116 connected to it form a floating metal block. The floating metal block is surrounded by the dielectric layer and is not connected to an external electrode. The second metal layer 118 is shorted to the gate end or shorted to the source end, and the second metal layer 118 extends above a portion of the floating metal block. An intermetallic dielectric layer 119 is formed above the interlayer dielectric layer 114; The metal-to-metal through hole 117 is only connected to the contact through hole 115; Type I and Type II are inverted semiconductor materials.

[0008] Preferably, the LDMOS device is further improved such that the thickness of the ultra-shallow trench isolation 102 ranges from 100 Å to 3000 Å.

[0009] Preferably, in a further improvement of the LDMOS device, the overlap region between the gate polysilicon 104 and the ultra-shallow trench isolation 102 is less than 2 μm.

[0010] Preferably, in a further improvement of the LDMOS device, the dielectric layer below the floating metal block is a stack of an ultra-shallow trench isolation 102 and a metal silicide reaction barrier silicon oxide layer 201.

[0011] This invention provides a method for manufacturing an LDMOS device, comprising the following steps: 1) An ultra-shallow trench isolation 102, a gate insulating dielectric layer 103, a gate polysilicon 104, a second type drift region 106 are formed in the first type substrate / first type epitaxial layer 101. A sidewall dielectric layer 108, a second type heavily doped implantation region 109 and a first type heavily doped implantation region 110 are formed on both sides of the gate polysilicon 104. 2) A metal silicide reaction barrier silicon oxide layer 201 is deposited and selectively etched on the upper surface of the second type drift region 106 and the ultra-shallow trench isolation 102; a metal silicide reaction is performed on the polysilicon and silicon surface not covered by the metal silicide reaction barrier silicon oxide layer 201. 3) Deposit ILD etch stop layer 112, then deposit interlayer dielectric layer 114 and planarize by chemical mechanical polishing; 4) Etching forms and fills contact vias 115 that pass through the ILD etch stop layer 112 and the interlayer dielectric layer 114 to connect to the gate polysilicon 104 and the second type heavily doped implantation region 109. Multiple floating contact vias 115-n are etched between the gate and drain ends, passing through the ILD etch stop layer 112 and the interlayer dielectric layer 114, and connected to the metal silicide reaction barrier silicon oxide layer 201 and filled. 5) Deposit the first metal layer 116, and use photolithography to etch the first metal layer 116 to form contact vias 115 and floating contact vias 115-n. The first metal layer 116 is connected to the floating contact vias 115-n to form a floating metal block; the floating metal block is... 6) Deposit and planarize the intermetallic dielectric layer 119, etch to form intermetallic vias 117 and fill them; no first via 117 is formed above the floating metal block; 7) Deposit the second metal layer 118, and use photolithography to extend the second metal layer 118, which is shorted to the gate end or shorted to the source end, to the top of part of the floating metal block; Type I and Type II are inverted semiconductor materials.

[0012] Preferably, in a further improved LDMOS device manufacturing method, the thickness of the ultra-shallow trench isolation 102 ranges from 100 Å to 3000 Å.

[0013] Preferably, in a further improved LDMOS device manufacturing method, the overlap region between the gate polysilicon 104 and the ultra-shallow trench isolation 102 is less than 2 μm.

[0014] Preferably, in a further improvement to the LDMOS device manufacturing method, the dielectric layer below the floating metal block is a stack of ultra-shallow trench isolation (102) and metal silicide reaction barrier silicon oxide layer (201).

[0015] This invention addresses the technical problem of "difficulty in simultaneously achieving breakdown voltage and on-resistance" in traditional STI field-plate LDMOS devices, and solves this problem through three improvements: Low-resistance conduction mechanism of ultra-thin and ultra-shallow trench isolation dielectric layer 1) Traditional STI field plate structures thicken the dielectric layer to increase breakdown voltage, which compresses the effective conductive cross-section above the drift region. Simultaneously, the overlap area between the gate field plate and the drift region increases, introducing additional parasitic resistance, ultimately resulting in a significant increase in the device's on-resistance. This invention employs an ultra-shallow trench isolation dielectric layer with a thickness of only 100Å~3000Å, significantly reducing the overall thickness of the STI dielectric layer. At the same time, the overlap area between the gate polysilicon and the STI structure is controlled within 2μm, reducing the scattering effect of the gate edge electric field on carrier transport in the drift region. The combination of the ultra-thin STI structure and the small gate overlap significantly widens the effective current path in the drift region and reduces the intrinsic on-resistance of the device.

[0016] 2) To reduce on-resistance without sacrificing breakdown voltage, this invention incorporates floating metal blocks formed by a combination of floating contact vias and a first metal layer above the STI dielectric layer between the gate polysilicon and the drain. These floating metal blocks are completely surrounded by the dielectric layer and are not directly connected to external electrodes. Potential modulation is achieved through the upper second metal layer, forming a distributed field plate structure above the drift region. The potential of the floating metal blocks dynamically changes with the drain voltage, creating multiple electric field peaks on the surface of the drift region. This disperses the high electric field concentrated at the gate edge in traditional LDMOS devices, effectively suppressing breakdown caused by excessive local electric field. Therefore, without increasing the STI thickness, the breakdown voltage of the device is significantly improved.

[0017] 3) To prevent the surface of the drift region from being silicided in subsequent metal silicide processes, which would lead to increased leakage current and decreased device reliability, this invention provides a metal silicide reaction barrier layer, a silicon oxide layer, on the upper surface of the second type drift region and the STI dielectric layer. This silicon oxide layer can protect the silicon material on the surface of the drift region from reacting with the metal during the silicide process, maintain the stability of the doping characteristics and surface state of the drift region, avoid the increase in leakage current and degradation of breakdown voltage caused by silicide, and ensure the compatibility of the device process with standard CMOS processes without the need for additional special process steps. Attached Figure Description

[0018] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0019] Figure 1 This is a schematic diagram of the existing technology structure; Figure 2 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 1 ; Figure 3 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 2 ; Figure 4 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 3 ; Figure 5 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 4 ; Figure 6 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 5 ; Figure 7 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 6 ; Figure 8 This is a schematic diagram of the intermediate structure in an embodiment of the present invention. Figure 7 .

[0020] Explanation of reference numerals in the attached figures: P-type substrate / P-type epitaxial layer 101; Ultra-shallow trench isolation 102; Gate insulating dielectric layer 103; Gate polysilicon 104; N-type drift zone 106 P-type body region injection area 107; Sidewall medium layer 108; N-type heavily doped implantation region 109; P-type heavily doped implantation region 110; ILD etch stop layer 112; Interlayer dielectric layer 114; Contact hole 115; Different floating contact through holes are identified as 115-1, 115-2, 115-3…115-n; First metal layer 116; Metal-to-metal through-hole 117; Second metal layer 118; Metal silicide reaction blocks silicon oxide layer 201. Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0022] First embodiment; This invention provides an LDMOS device, taking the N-type as an example, characterized in that it includes: An ultra-shallow trench isolation 102 is formed above and inside the P-type substrate / P-type epitaxial layer 101; The N-type drift region 106 is located in the P-type substrate / P-type epitaxial layer 101 below the ultra-shallow trench isolation 102; The P-type body region implantation region 107 is located in the P-type substrate / P-type epitaxial layer 101 next to the N-type drift region 106; The gate insulating dielectric layer 103 covers the P-type body region implantation region 107, and the gate polysilicon 104 is located above the gate insulating dielectric layer 103; Sidewall dielectric layers 108 are formed on both sides of the gate polysilicon 104; The N-type heavily doped implantation region 109 and the P-type heavily doped implantation region 110 are formed within the P-type bulk implantation region 107; A metallization reaction-blocking silicon oxide layer 201 covers the N-type drift region 106 and the ultra-shallow trench isolation 102; The ILD etch stop layer 112 covers the entire upper surface of the device, and the interlayer dielectric layer 114 covers the ILD etch stop layer 112. Contact via 115 passes through ILD etch stop layer 112 and interlayer dielectric layer 114 and connects to gate polysilicon 104 and N-type heavily doped implantation region 109; Multiple floating contact vias 115-n located between the gate and drain ends pass through the ILD etch stop layer 112 and the interlayer dielectric layer 114 and are connected to the metal silicide reaction barrier silicon oxide layer 201. The first metal layer 116 is located above the interlayer dielectric layer 114 and is connected to the top of each contact via 115 and the floating contact via 115-n. Each floating contact via 115-n and the first metal layer 116 connected to it form a floating metal block. The floating metal block is surrounded by the dielectric layer and is not connected to an external electrode. The second metal layer 118 is shorted to the gate end or shorted to the source end, and the second metal layer 118 extends above a portion of the floating metal block. An intermetallic dielectric layer 119 is formed above the interlayer dielectric layer 114; The metal-to-metal through hole 117 is only connected to the contact through hole 115; The thickness of the ultra-shallow trench isolation 102 ranges from 100 Å to 3000 Å, and the overlap area between the gate polysilicon 104 and the ultra-shallow trench isolation 102 is less than 2 μm.

[0023] Second embodiment;

[0024] This invention provides a method for manufacturing an LDMOS device, taking the N-type as an example, including the following steps: 1) An ultra-shallow trench isolation 102 is formed in a P-type substrate / P-type epitaxial layer 101 using a shallow trench process; an N-type drift region 106 is implanted below the ultra-shallow trench isolation 102; A gate insulating dielectric layer 103 is grown above the P-type body region implantation region 107, and a gate polysilicon 104 is formed above the gate insulating dielectric layer 103; sidewall dielectric layers 108 are formed on both sides of the gate polysilicon 104; N-type heavily doped implantation regions 109 and P-type heavily doped implantation regions 110 are formed within the P-type body region implantation region 107 by heavy doping implantation, as referenced. Figure 2 As shown; 2) A metal silicide reaction barrier silicon oxide layer 201 is deposited and selectively etched on the upper surface of the N-type drift region 106 and the ultra-shallow trench isolation 102; a metal silicide reaction is then performed on the polysilicon and silicon surface not covered by the metal silicide reaction barrier silicon oxide layer 201, as described above. Figure 3 As shown; 3) Deposit the ILD etch stop layer 112, then deposit the interlayer dielectric layer 114 and planarize it using chemical mechanical polishing, as shown in the reference. Figure 4 As shown; 4) Etching forms and fills contact vias 115 that pass through the ILD etch stop layer 112 and the interlayer dielectric layer 114 to connect the gate polysilicon 104 and the N-type heavily doped implantation region 109; Multiple floating contact vias 115-n are etched between the gate and drain ends, passing through the ILD etch stop layer 112 and the interlayer dielectric layer 114, and connected to the metal silicide reaction barrier silicon oxide layer 201, and then filled. (Reference) Figure 5 As shown; 5) Deposit the first metal layer 116, and use photolithography to etch the first metal layer 116 onto the contact vias 115 and floating contact vias 115-n. The first metal layer 116 is connected to the floating contact vias 115-n to form a floating metal block. (Refer to...) Figure 6 As shown; 6) Deposit and planarize the intermetallic dielectric layer 119, etch to form intermetallic vias 117 and fill them; no first via 117 is formed above the floating metal block, see reference. Figure 7 As shown; 7) Deposit the second metal layer 118, and use photolithography to extend the second metal layer 118, which is shorted to the gate or source, above a portion of the floating metal block. (Refer to...) Figure 8 As shown; Preferably, the thickness of the ultra-shallow trench isolation 102 ranges from 100 Å to 3000 Å.

[0025] Preferably, the overlap area between the gate polysilicon 104 and the ultra-shallow trench isolation 102 is less than 2 μm.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0027] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An LDMOS device, characterized in that, include: An ultra-shallow trench isolation (102) is formed above the interior of the first type substrate / first type epitaxial layer (101); The second type drift region (106) is located in the first type substrate / first type epitaxial layer (101) below the ultra-shallow trench isolation (102); The first type body region implantation region (107) is located in the first type substrate / first type epitaxial layer (101) next to the second type drift region (106); A gate insulating dielectric layer (103) covers the first body region implantation region (107), and a gate polysilicon (104) is located above the gate insulating dielectric layer (103); Sidewall dielectric layers (108) are formed on both sides of the gate polysilicon (104); The second type heavily doped implantation region (109) and the first type heavily doped implantation region (110) are formed within the first type bulk implantation region (107); A metallization reaction barrier silicon oxide layer (201) covers the type II drift region (106) and the ultra-shallow trench isolation (102); The ILD etch stop layer (112) covers the entire upper surface of the device, and the interlayer dielectric layer (114) covers the ILD etch stop layer (112); The contact via (115) passes through the ILD etch stop layer (112) and the interlayer dielectric layer (114) and is connected to the gate polysilicon (104) and the second-type heavily doped implantation region (109); Multiple floating contact vias (115-n) located between the gate and drain ends pass through the ILD etch stop layer (112) and the interlayer dielectric layer (114) and are connected to the metal silicide reaction barrier silicon oxide layer (201); The first metal layer (116) is located above the interlayer dielectric layer (114) and is connected to the top of each contact via (115) and the floating contact via (115-n). Each floating contact via (115-n) and the first metal layer (116) connected to it form a floating metal block. The floating metal block is surrounded by the dielectric layer and is not connected to an external electrode. The second metal layer (118) is shorted to the gate end or shorted to the source end, and the second metal layer (118) extends above part of the floating metal block; An intermetallic dielectric layer (119) is formed above the interlayer dielectric layer (114); The metal-to-metal through hole (117) is only connected to the contact through hole (115); Type I and Type II are inverted semiconductor materials.

2. The LDMOS device according to claim 1, characterized in that: The thickness of the ultra-shallow trench isolation (102) ranges from 100 Å to 3000 Å.

3. The LDMOS device according to claim 1, characterized in that: The overlap region between the gate polysilicon (104) and the ultra-shallow trench isolation (102) is less than 2 μm.

4. The LDMOS device according to claim 1, characterized in that: The dielectric layer beneath the floating metal block is a stack of ultra-shallow trench isolation (102) and metal silicide reaction barrier silicon oxide layer (201).

5. A method for manufacturing an LDMOS device, characterized in that, Includes the following steps: 1) An ultra-shallow trench isolation (102), a gate insulating dielectric layer (103), a gate polysilicon (104), a second type drift region (106) are formed in the first type substrate / first type epitaxial layer (101). A sidewall dielectric layer (108), a second type heavily doped implantation region (109), and a first type heavily doped implantation region (110) are formed on both sides of the gate polysilicon (104). 2) A metal silicide reaction barrier silicon oxide layer (201) is deposited and selectively etched on the upper surface of the second type drift region (106) and the ultra-shallow trench isolation (102); a metal silicide reaction is performed on the polycrystalline silicon and silicon surface that are not covered by the metal silicide reaction barrier silicon oxide layer (201); 3) Deposit an ILD etch stop layer (112), then deposit an interlayer dielectric layer (114) and planarize it by chemical mechanical polishing; 4) Etching forms and fills contact vias (115) that pass through the ILD etch stop layer (112) and interlayer dielectric layer (114) to connect to the gate polysilicon (104) and the second-type heavily doped implantation region (109); Multiple floating contact vias (115-n) are etched between the gate and drain ends, passing through the ILD etch stop layer (112) and the interlayer dielectric layer (114) and connected to the metal silicide reaction barrier silicon oxide layer (201), and then filled. 5) Deposit the first metal layer (116), and use photolithography to form contact vias (115) and floating contact vias (115-n) on the first metal layer (116). The first metal layer (116) is connected to the floating contact vias (115-n) to form a floating metal block. 6) Deposit an intermetallic dielectric layer (119) and planarize it, etch to form an intermetallic via (117) and fill it; the first via (117) is not formed above the floating metal block. 7) Deposit a second metal layer (118), and use photolithography to extend the second metal layer (118) shorted to the gate end or shorted to the source end to the top of part of the floating metal block; Type I and Type II are inverted semiconductor materials.

6. The LDMOS device manufacturing method according to claim 5, characterized in that: The thickness of the ultra-shallow trench isolation (102) ranges from 100 Å to 3000 Å.

7. The LDMOS device manufacturing method according to claim 5, characterized in that: The overlap region between the gate polysilicon (104) and the ultra-shallow trench isolation (102) is less than 2 μm.

8. The LDMOS device manufacturing method according to claim 5, characterized in that: The dielectric layer beneath the floating metal block is a stack of ultra-shallow trench isolation (102) and metal silicide reaction barrier silicon oxide layer (201).

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