Switching assembly of a solid state circuit breaker, solid state circuit breaker and control method thereof

Abstract

This invention relates to the field of solid-state circuit breaker technology, and provides a switching assembly, a solid-state circuit breaker, and a control method thereof, comprising: an N-type drift layer disposed on a silicon carbide substrate; first and second JFET / CSL layers symmetrically disposed on both sides of the drift layer; first and second P-type body regions symmetrically disposed on both sides of the drift layer, the first P-type body region being connected to the first JFET / CSL layer, and the second P-type body region being connected to the second JFET / CSL layer, each of the first and second P-type body regions having an N-type contact region and a P-type contact region; first and second gates symmetrically disposed on both sides of the drift layer, both of the first and second gates being covered by an insulating layer; and first and second emitters symmetrically disposed on both sides of the drift layer, the first emitter being connected to the first JFET / CSL layer and the first P-type body region, and the second emitter being connected to the second JFET / CSL layer and the second P-type body region. This addresses the problems of high losses, large size, and low power in solid-state circuit breakers.

Description

Technical Field

[0001] This invention relates to the field of solid-state circuit breaker technology, and in particular to a switching assembly for a solid-state circuit breaker, a solid-state circuit breaker, and a control method thereof. Background Technology

[0002] In the field of power electronic circuit protection and wide bandgap semiconductor devices, solid-state circuit breakers are widely used in high-voltage power systems such as AC microgrids and bidirectional charging and discharging of electric vehicles, undertaking the functions of current switching, rapid fault interruption, and circuit safety protection.

[0003] Because silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have advantages such as high voltage resistance, fast switching speed, and low conduction loss, related technologies use SiC MOSFETs as the switching devices in solid-state circuit breakers. Bidirectional current switching is achieved by connecting two unidirectional SiC MOSFETs back-to-back (in series with their sources connected). However, the following technical drawbacks exist: First, the current must flow through two independent drift layers and a body diode, resulting in high on-resistance Ron and large losses; second, it requires two independent power packages, two heat dissipation systems, and complex drive isolation circuits, leading to a large size; third, heat is concentrated on the two discrete devices, affecting the overall power density of the system and resulting in low efficiency.

[0004] There is currently no effective solution to the problems of high conduction loss, large size and low power of solid-state circuit breakers in related technologies. Summary of the Invention

[0005] The present invention provides a switching assembly for a solid-state circuit breaker, a solid-state circuit breaker and a control method thereof, which at least solves the problems of high conduction loss, large size and low power of solid-state circuit breakers in the related art.

[0006] An embodiment of the present invention provides a switching assembly for a solid-state circuit breaker, comprising: a silicon carbide substrate; an N-type drift layer disposed on the silicon carbide substrate; a first JFET / CSL layer and a second JFET / CSL layer symmetrically disposed on both sides of the N-type drift layer; a first P-type body region and a second P-type body region symmetrically disposed on both sides of the N-type drift layer, wherein the first P-type body region is connected to the first JFET / CSL layer, and the second P-type body region is connected to the second JFET / CSL layer; both the first P-type body region and the second P-type body region are provided with an N-type contact region and a P-type contact region. The contact area includes a first gate and a second gate, symmetrically disposed on both sides of the N-type drift layer. Both the first gate and the second gate are covered by an insulating layer to isolate the first gate from the first P-type body region and the first emitter, and to isolate the second gate from the second P-type body region and the second emitter. The first emitter and the second emitter are symmetrically disposed on both sides of the N-type drift layer. The first emitter is connected to the first JFET / CSL layer and the first P-type body region, and the second emitter is connected to the second JFET / CSL layer and the second P-type body region.

[0007] As an optional embodiment, the first JFET / CSL layer includes a first-first JFET / CSL layer and a first-second JFET / CSL layer, and the second JFET / CSL layer includes a second-first JFET / CSL layer and a second-second JFET / CSL layer; the first-first JFET / CSL layer and the second-first JFET / CSL layer are symmetrically disposed on both sides of the N-type drift layer; the first-second JFET / CSL layer and the second-second-second JFET / CSL layer are symmetrically disposed on both sides of the N-type drift layer; the first P-type body region is disposed between the first-first JFET / CSL layer and the first-second JFET / CSL layer; and the second P-type body region is disposed between the second-first JFET / CSL layer and the second-second-second JFET / CSL layer.

[0008] As an optional solution, the first P-type body region includes a first one P-type body region and a first two P-type body region, and the second P-type body region includes a second one P-type body region and a second two P-type body region; the first one P-type body region and the second one P-type body region are symmetrically arranged on both sides of the N-type drift layer; the first two P-type body regions and the second two P-type body regions are symmetrically arranged on both sides of the N-type drift layer.

[0009] As an optional solution, the first JFET / CSL layer includes a junction field-effect transistor (JFET) and a current spreading layer (CSL); the current spreading layer (CSL) is connected to the N-type drift layer; and the junction field-effect transistor (JFET) is connected to the current spreading layer (CSL).

[0010] As an alternative, the first emitter and the second emitter are stepped in shape, and the stepped shape includes a connected protrusion and a base; the base of the first emitter is connected to the first JFET / CSL layer and the first P-type body region; the base of the second emitter is connected to the second JFET / CSL layer and the second P-type body region.

[0011] An embodiment of the present invention provides a solid-state circuit breaker, comprising: any of the aforementioned switching components; a power input terminal connected to the first emitter via a voltage sensor; a load terminal connected to the second emitter via a current sensor; and a processor connected to the first gate via a first isolated gate driver and connected to the second gate via a second isolated gate driver; wherein the voltage sensor feeds back a voltage signal to the processor in real time, and the current sensor feeds back a current signal to the processor in real time.

[0012] As an alternative, the processor mentioned above is a microcontroller (MCU) or a digital signal processor (DSP), and the current sensor mentioned above is a shunt or a Hall sensor.

[0013] As an optional solution, an electrical isolation barrier is provided between the processor and the power input terminal, the switching assembly, and the load terminal.

[0014] As an optional solution, it also includes: an auxiliary power supply module connected to the processor; and a human-machine interface or communication interface connected to the processor.

[0015] An embodiment of the present invention provides a control method for the aforementioned solid-state circuit breaker, comprising: when the processor receives the voltage signal and the current signal does not exceed a preset safety threshold, the processor outputs a high level to keep the first gate and the second gate open through the first isolated gate driver and the second isolated gate driver, thereby keeping the solid-state circuit breaker in a conducting state; when the current signal exceeds the preset safety threshold, the processor outputs a low level to disconnect the first gate and the second gate through the first isolated gate driver and the second isolated gate driver, thereby putting the solid-state circuit breaker in a protected state.

[0016] The switching assembly of the solid-state circuit breaker provided in this invention comprises an N-type drift layer disposed on a silicon carbide substrate; first and second JFET / CSL layers symmetrically disposed on both sides of the drift layer; first and second P-type body regions symmetrically disposed on both sides of the drift layer, the first P-type body region being connected to the first JFET / CSL layer and the second P-type body region being connected to the second JFET / CSL layer, both the first and second P-type body regions having N-type contact regions and P-type contact regions; first and second gates symmetrically disposed on both sides of the drift layer, both the first and second gates being covered by an insulating layer to isolate the first gate from the first P-type body region and the first emitter, and to isolate the second gate from the second P-type body region and the second emitter; first and second emitters symmetrically disposed on both sides of the drift layer, the first emitter being connected to the first JFET / CSL layer and the first P-type body region, and the second emitter being connected to the second JFET / CSL layer and the second P-type body region. Because current flows through only a single drift layer, the on-resistance is reduced by approximately 50% compared to back-to-back solutions in related technologies. Bidirectional functionality can be achieved with a single chip, significantly reducing the size and weight of the solid-state circuit breaker and offering the advantage of high integration. The symmetrical structure allows for double-sided cooling packaging, providing advantages in thermal management and reliability, thus contributing to improved overall system power density. This addresses the problems of high conduction losses, large size, and low power in solid-state circuit breakers in related technologies. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a switching assembly of a solid-state circuit breaker according to an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of a solid-state circuit breaker module in an embodiment of the present invention.

[0020] Figure 3 This is a flowchart illustrating the steps of a control method for a solid-state circuit breaker according to an embodiment of the present invention.

[0021] The above figures include the following reference numerals: 001, N-type drift layer; 101, First JFET / CSL layer; 102, Second JFET / CSL layer; 201, First P-type body region; 202, Second P-type body region; N+, N-type contact region; P+, P-type contact region; 301, First gate; 302, Second gate; 401, First emitter; 402, Second emitter; 1011, First JFET / CSL layer; 1012, First second JFET / CSL layer; 1021, Second first JFET / CSL layer; 1022, Second second second JFET / CSL layer; 2011, First first P-type body region; 2012, First second P-type body region; 2021, Second first P-type body region; 2022, Second second P-type body region; 3011, First insulating layer; 3021, Second insulating layer; 10. Switch assembly; 20. Power input terminal; 30. Voltage sensor; 40. Load terminal; 50. Current sensor; 60. Processor; 701. First isolated gate driver; 702. Second isolated gate driver; 80. Auxiliary power supply module; 90. Human-machine interface or communication interface. Detailed Implementation

[0022] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0023] Because silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have advantages such as high voltage resistance, fast switching speed, and low conduction loss, related technologies use SiC MOSFETs as the switching devices in solid-state circuit breakers. Bidirectional current switching is achieved by connecting two unidirectional SiC MOSFETs back-to-back (in series with their sources connected). However, the following technical drawbacks exist: First, the current must flow through two independent drift layers and a body diode, resulting in high on-resistance Ron and large losses; second, it requires two independent power packages, two heat dissipation systems, and complex drive isolation circuits, leading to a large size; third, heat is concentrated on the two discrete devices, affecting the overall power density of the system and resulting in low efficiency.

[0024] Therefore, such as Figure 1 As shown, an embodiment of the present invention provides a switching assembly for a solid-state circuit breaker, comprising a silicon carbide (SiC) substrate (… Figure 1(Not shown), N-type drift layer 001, first JFET / CSL layer 101, second JFET / CSL layer 102, first P-type body region 201, second P-type body region 202, N-type contact region N+, P-type contact region P+, first gate 301, second gate 302, first emitter 401 and second emitter 402.

[0025] An N-type drift layer 001 is disposed on the aforementioned silicon carbide substrate. A first JFET / CSL layer 101 and a second JFET / CSL layer 102 are symmetrically disposed on both sides of the N-type drift layer 001. A first P-type body region 201 and a second P-type body region 202 are symmetrically disposed on both sides of the N-type drift layer 001, wherein the first P-type body region 201 is connected to the first JFET / CSL layer 101, and the second P-type body region 202 is connected to the second JFET / CSL layer 102. Both the first P-type body region 201 and the second P-type body region 202 are provided with an N-type contact region N+ and a P-type contact region P+. The first gate 301 and the second gate 302 are symmetrically disposed on both sides of the N-type drift layer 001. The first gate 301 and the second gate 302 are both covered by an insulating layer to isolate the first gate 301 from the first P-type body region 201 and the first emitter 401, and to isolate the second gate 302 from the second P-type body region 202 and the second emitter 402. The first emitter 401 and the second emitter 402 are symmetrically disposed on both sides of the N-type drift layer 001. The first emitter 401 is connected to the first JFET / CSL layer 101 and the first P-type body region 201, and the second emitter 402 is connected to the second JFET / CSL layer 102 and the second P-type body region 202.

[0026] Figure 1 The diagram illustrates a first insulating layer 3011 covering the first gate 301 and a second insulating layer 3021 covering the second gate 302. Figure 1 From the shown perspective, the silicon carbide substrate is obscured by the N-type drift layer 001 and the symmetrically distributed structures on both sides of the N-type drift layer 001. Therefore, the silicon carbide substrate is not obscured. Figure 1 As shown in the image.

[0027] The single-layer N-type drift layer set on the silicon carbide substrate is the only conduction channel for bidirectional current and is also the core structure for the device to withstand high voltage.

[0028] The first JFET / CSL layer 101 and the second JFET / CSL layer 102 are both composite layers of junction field-effect transistors (JFETs) and current spreading layers (CSLs), which will be further explained later in this embodiment.

[0029] The N-type contact region N+ is a highly doped N-type region within the P-type body region, providing a low-resistance electron conduction path for current, achieving ohmic contact between the emitter and the internal components of the device. The P-type contact region P+ is a highly doped P-type region within the P-type body region, used to stabilize the P-type body potential, suppress parasitic diode conduction, and improve device reliability. It is important to note that the N-type contact regions N+ on both sides of the N-type drift layer 001 are symmetrically distributed with respect to the N-type drift layer 001, and the P-type contact regions P+ on both sides of the N-type drift layer 001 are also symmetrically distributed with respect to the N-type drift layer 001.

[0030] The first and second gates, symmetrically distributed on both sides of the N-type drift layer 001, are control electrodes used to receive drive signals to control the device to turn on / off; the dual gates are driven synchronously to achieve bidirectional current switching.

[0031] The insulating layer covering the gate is used to electrically isolate the gate from the P-type body region and the emitter, prevent leakage and short circuit, ensure the stability of the gate control signal, and adapt to the high and low voltage isolation requirements of the circuit breaker.

[0032] The first and second emitters, symmetrically distributed on both sides of the N-type drift layer 001, are the main current electrodes, which are connected to the JFET / CSL layer and the P-type body region on the same side, respectively, and are bidirectional current input / output ports.

[0033] When the first gate 301 and the second gate 302 are turned on, the current can pass directly through the N-type drift layer 001; while when the first gate 301 and the second gate 302 are turned off, bidirectional high voltage blocking is achieved by utilizing the PN junctions formed by the first P-type body region 201 and the second P-type body region 202 with the N-type drift layer 001.

[0034] The solution provided in this embodiment, because the current flows through only a single drift layer, reduces the on-resistance by approximately 50% compared to the back-to-back solutions in related technologies, resulting in low losses. It achieves bidirectional functionality with a single chip, significantly reducing the size and weight of the solid-state circuit breaker and offering high integration. The symmetrical structure allows for double-sided cooling packaging, providing superior thermal management and reliability, thus contributing to increased overall system power density. Therefore, based on the switching device provided in this embodiment, a solid-state circuit breaker with high integration, low on-resistance, and bidirectional voltage blocking and current conducting capabilities can be fabricated, solving the problems of high on-resistance, bulk redundancy, and low efficiency in back-to-back structures in related technologies.

[0035] Taking AC microgrid protection as an example, in a 220V / 50Hz AC system, the solid-state circuit breaker using the switching components provided in this embodiment can achieve low voltage drop conduction in both positive and negative half-cycles using a symmetrical structure, and can be forcibly turned off within 1-2us after a short circuit occurs, without generating an electric arc.

[0036] Taking bidirectional charging and discharging of electric vehicles as an example, in the scenario of vehicle reverse charging (vehicle to grid), the solid-state circuit breaker using the switching component provided in this embodiment can support current flowing from the vehicle battery to the grid for reverse charging, and bidirectional overcurrent protection can be achieved through the corresponding driving algorithm. The aforementioned driving algorithm can be determined by those skilled in the art based on existing control algorithms and a limited number of experiments; this embodiment will not elaborate on it further.

[0037] In addition, the fabrication process of the switching component provided in this embodiment may be, but is not limited to: using a highly doped N-type silicon carbide substrate, growing a drift layer by chemical vapor deposition; forming a P-type body region by ion implantation, activating doping by high-temperature annealing; and finally depositing polysilicon gates (first gate 301 and second gate 302) and metal electrodes (first emitter 401 and second emitter 402) on both sides of the drift layer.

[0038] As an optional embodiment, the first JFET / CSL layer 101 includes a first JFET / CSL layer 1011 and a first second JFET / CSL layer 1012, and the second JFET / CSL layer 102 includes a second first JFET / CSL layer 1021 and a second second JFET / CSL layer 1022. The first first JFET / CSL layer 1011 and the second first JFET / CSL layer 1021 are symmetrically disposed on both sides of the N-type drift layer 001. The first second second JFET / CSL layer 1012 and the second second second JFET / CSL layer 1022 are symmetrically disposed on both sides of the N-type drift layer 001. A first P-type body region 201 is disposed between the first first JFET / CSL layer 1011 and the first second second JFET / CSL layer 1012. A second P-type body region 202 is disposed between the second first JFET / CSL layer 1021 and the second second second JFET / CSL layer 1022.

[0039] The JFET / CSL layers on both sides of the N-type drift layer 001 are symmetrically distributed and arranged in a layered layout with the P-type body region centrally sandwiched, forming a uniform electric field confinement structure. This helps avoid local electric field concentration in the N-type drift layer 001, significantly reducing the risk of high-voltage breakdown, improving the device's high-voltage withstand capability, and making it suitable for high-voltage solid-state circuit breaker applications. Simultaneously, the symmetrical layered structure of the JFET / CSL layers ensures that the device's operating heat is evenly dissipated on both sides of the N-type drift layer, eliminating local hot spots, and facilitating double-sided cooling packaging, further enhancing thermal management capabilities and long-term device reliability.

[0040] As an optional configuration, the first P-type body region 201 includes a first P-type body region 2011 and a first second P-type body region 2012, and the second P-type body region 202 includes a second first P-type body region 2021 and a second second P-type body region 2022. The first first P-type body region 2011 and the second first P-type body region 2021 are symmetrically arranged on both sides of the N-type drift layer 001. The first second P-type body region 2012 and the second second P-type body region 2022 are symmetrically arranged on both sides of the N-type drift layer 001.

[0041] The P-type body regions on both sides of the N-type drift layer 001 are arranged in a layered layout under the premise of symmetrical distribution, which helps to accurately construct symmetrical channels, allowing current to spread evenly and flow smoothly in the drift layer, reducing current congestion and local heat generation. Based on the low loss of a single drift layer, the on-resistance is further reduced, and the overall conduction efficiency of the device is improved.

[0042] As an optional solution, the first JFET / CSL layer includes a junction field-effect transistor (JFET) and a current spreading layer (CSL); the current spreading layer (CSL) is connected to the N-type drift layer; and the junction field-effect transistor (JFET) is connected to the current spreading layer (CSL).

[0043] The current spread layer is directly connected to the aforementioned N-type drift layer, which can quickly widen the current path and uniformly distribute the charge carriers, avoiding current congestion in local areas. Combined with the stable conduction channel of the junction field-effect transistor (JFET), it allows current to pass more smoothly through the N-type drift layer, further reducing losses and improving device conduction efficiency on top of the already low on-resistance. Simultaneously, the current spread layer and the JFET form a progressive electric field buffer structure, which can uniformly modulate the electric field inside the N-type drift layer, eliminating electric field spikes and local concentrations, significantly improving the device's high-voltage blocking capability, reducing the risk of high-voltage breakdown, and adapting to the operating scenarios of high-voltage solid-state circuit breakers. Furthermore, the cascaded structure of the JFET and the current spread layer is compatible with SiC MOSFET fabrication processes such as chemical vapor deposition, ion implantation, and high-temperature annealing, resulting in a regular structure and uniform doping, which can improve chip fabrication yield.

[0044] Understandably, to maintain a symmetrical distribution, the second JFET / CSL layer adopts the same structure as the first JFET / CSL layer. Furthermore, when both the first and second JFET / CSL layers employ a layered layout, in order to... Figure 1 For example, the first JFET / CSL layer 1011, the first second JFET / CSL layer 1012, the second first JFET / CSL layer 1021, and the second second second JFET / CSL layer 1022 are all layer structures in which the current spread layer is connected to the N-type drift layer 001 and the junction field-effect transistor is connected to the current spread layer.

[0045] As an alternative, the first emitter 401 and the second emitter 402 are stepped, with the stepped shape including connected protrusions and a base. The base of the first emitter 401 is connected to the first JFET / CSL layer 101 and the first P-type body region 201. The base of the second emitter 402 is connected to the second JFET / CSL layer 102 and the second P-type body region 202.

[0046] The base is used for electrical connections, while the protrusions are used for external leads or bonding. This functional separation facilitates chip packaging and system integration. Simultaneously, the base forms a large-area ohmic contact with the JFET / CSL layer and the P-type body region, significantly reducing electrode contact resistance and allowing for smoother current injection and extraction. This further reduces conduction losses and improves device efficiency on top of the low resistance of the single drift layer.

[0047] like Figure 2 As shown, this invention also provides a solid-state circuit breaker, including any of the aforementioned switching components 10, a power input terminal 20, a load terminal 40, and a processor 60. Wherein, Figure 2 The red arrows in the diagram represent high-voltage power paths, the blue arrows represent low-voltage signal / control paths, and the yellow areas represent electrical isolation barriers.

[0048] The power input terminal 20 is connected to the first emitter 401 through the voltage sensor 30, the load terminal 40 is connected to the second emitter 402 through the current sensor 50, and the processor 60 is connected to the first gate 301 through the first isolated gate driver 701 and to the second gate 302 through the second isolated gate driver 702; wherein, the voltage sensor 30 feeds back the voltage signal to the processor 60 in real time, and the current sensor 50 feeds back the current signal to the processor 60 in real time.

[0049] The processor 60 controls the first isolated gate driver 701 and the second isolated gate driver 702 based on pulse width modulation (PWM) to control the gate voltage at both ends of the aforementioned switching components to be turned on or off.

[0050] The processor 60 controls the first gate 301 and the second gate 302 through two independent and isolated gate drivers to ensure that the turn-on / turn-off timing of the dual gates is completely synchronized, maintain the bidirectional electrical symmetry of the switching components, and ensure that the positive and negative current switching and voltage blocking performance are without deviation.

[0051] Since the solid-state circuit breaker provided in this embodiment uses the aforementioned switching components, it can solve the problems of high conduction loss, large size, and low power of solid-state circuit breakers in related technologies.

[0052] It should be noted that since the switching assembly 10 has a bidirectional symmetrical structure, the power input terminal 20 is connected to the second emitter 402 through the voltage sensor 30, the load terminal 40 is connected to the first emitter 401 through the current sensor 50, and the processor 60 is connected to the first gate 301 through the first isolated gate driver 701 and to the second gate 302 through the second isolated gate driver 702. The solid-state circuit breaker obtained in this way is essentially the same as the solid-state circuit breaker obtained by the connection method described above in this embodiment.

[0053] As an alternative, processor 60 can be a microcontroller (MCU) or a digital signal processor (DSP). Current sensor 50 can be a shunt or a Hall sensor.

[0054] A microcontroller (MCU) is a single-chip microcomputer that integrates a central processing unit, program memory, data memory, general-purpose input / output interface, analog-to-digital converter, timer, pulse width modulation controller, and other functional modules onto a single chip.

[0055] Digital signal processors (DSPs) are dedicated processors optimized for high-speed digital signal processing, filtering, vector transformation, and high-precision algorithm processing. They feature high-speed computing units and parallel processing architectures.

[0056] The shunt is a four-terminal power resistor device made of high-precision, low-resistance alloy material. It operates based on Ohm's law and achieves accurate measurement of the loop current by detecting the voltage drop across its own terminals.

[0057] Hall sensors are sensor devices that achieve magnetoelectric conversion based on the Hall effect. They can detect the magnetic field strength generated by conductor current in a non-contact manner to calculate the current magnitude and can achieve electrical isolation between the power circuit being measured and the detection circuit.

[0058] As an optional solution, an electrical isolation barrier is provided between the processor 60 and the power input terminal 20, the switching assembly 10, and the load terminal 40, such as... Figure 2 The yellow area is shown in part.

[0059] Electrical isolation barriers can be, but are not limited to, creepage distances, clearances, isolation grooves, and insulating substrates designed according to safety regulations on circuit boards. Using electrical isolation barriers to separate high-voltage power paths from low-voltage control paths can reduce high-voltage crosstalk and breakdown risks, protect low-voltage control circuits, and prevent control signals from being interfered with by high voltage, thus ensuring long-term stable system operation.

[0060] As an optional solution, it also includes an auxiliary power supply module 80, as well as a human-machine interface or communication interface.

[0061] An auxiliary power supply module 80, connected to the processor 60, is used to supply power to the processor 60. A human-machine interface or communication interface is also connected to the processor 60. Figure 2 In the attached diagram, reference numeral 90 indicates the human-machine interface or communication interface. The processor 60 has built-in control logic and protection algorithms, which can be written and modified through the human-machine interface or communication interface.

[0062] like Figure 3 As shown in the figure, the present invention also provides a control method for the above-mentioned solid-state circuit breaker, including steps S1 and S2.

[0063] Step S1: When the processor receives the voltage signal and the current signal does not exceed the preset safety threshold, the processor outputs a high level and keeps the first gate and the second gate open through the first isolated gate driver and the second isolated gate driver, so that the solid-state circuit breaker remains in the conducting state.

[0064] In step S2, when the current signal exceeds the preset safety threshold, the processor outputs a low level and cuts off the first gate and the second gate through the first isolated gate driver and the second isolated gate driver, so that the solid-state circuit breaker is in a protected state.

[0065] The control method provided in this embodiment, under normal operating conditions, allows the processor to synchronously output a high level, enabling the dual gates to turn on synchronously and stably. Current can directly pass through the single N-type drift layer for conduction, without additional device on-state voltage drop. The control logic only maintains the level, eliminating complex switching losses and ensuring the device operates at its lowest on-resistance state, further reducing losses. By synchronously controlling two isolated drives with a single processor, coordinated switching of the dual gates is achieved, eliminating the need for two independent control units. This reduces the size of the control board and wiring complexity, and lowers the redundancy of the solid-state circuit breaker. In case of a fault, the processor instantly outputs a low level, enabling rapid synchronous turn-off of the dual gates. Fault isolation can be completed within microseconds, preventing overheating damage and ensuring stable operation under high power conditions. Combined with low-loss conduction characteristics, this effectively improves the overall power density of the system.

[0066] The present invention also provides a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the control method of the present invention.

[0067] The present invention also provides a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the control method of the present invention.

[0068] Computer programs for implementing the control methods of embodiments of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0069] In the context of embodiments of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, or infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0070] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more". The descriptions of terms such as "first", "second", etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features.

[0071] The data involved in the embodiments of this invention (including but not limited to data used for analysis, stored data, displayed data, etc.) are collected, stored, used, processed, transmitted, provided, and disclosed in strict accordance with relevant laws, regulations, and regulatory requirements, and follow the principles of legality, legitimacy, necessity, and good faith.

[0072] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0073] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0074] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A switching assembly for a solid-state circuit breaker, characterized in that, include: silicon carbide substrate, An N-type drift layer is disposed on the silicon carbide substrate; The first JFET / CSL layer and the second JFET / CSL layer are symmetrically disposed on both sides of the N-type drift layer; The first P-type body region and the second P-type body region are symmetrically disposed on both sides of the N-type drift layer. The first P-type body region is connected to the first JFET / CSL layer, and the second P-type body region is connected to the second JFET / CSL layer. Both the first P-type body region and the second P-type body region are provided with N-type contact regions and P-type contact regions. The first gate and the second gate are symmetrically disposed on both sides of the N-type drift layer. Both the first gate and the second gate are covered by an insulating layer to isolate the first gate from the first P-type body region and the first emitter, and to isolate the second gate from the second P-type body region and the second emitter. The first emitter and the second emitter are symmetrically disposed on both sides of the N-type drift layer, wherein the first emitter is connected to the first JFET / CSL layer and the first P-type body region, and the second emitter is connected to the second JFET / CSL layer and the second P-type body region.

2. The switching assembly according to claim 1, characterized in that, The first JFET / CSL layer includes a first JFET / CSL layer and a first second JFET / CSL layer, and the second JFET / CSL layer includes a second first JFET / CSL layer and a second second JFET / CSL layer; The first JFET / CSL layer and the second JFET / CSL layer are symmetrically disposed on both sides of the N-type drift layer; The first dual JFET / CSL layer and the second dual JFET / CSL layer are symmetrically disposed on both sides of the N-type drift layer; The first P-type body region is disposed between the first JFET / CSL layer and the first second JFET / CSL layer; The second P-type body region is disposed between the second first JFET / CSL layer and the second second JFET / CSL layer.

3. The switching assembly according to claim 2, characterized in that, The first P-type body region includes a first one P-type body region and a first two P-type body region, and the second P-type body region includes a second one P-type body region and a second two P-type body region; The first P-type body region and the second P-type body region are symmetrically arranged on both sides of the N-type drift layer; The first two P-type body region and the second two P-type body region are symmetrically arranged on both sides of the N-type drift layer.

4. The switching assembly according to claim 1, characterized in that, The first JFET / CSL layer includes a junction field-effect transistor (JFET) and a current spreading layer (CSL); The current spreading layer CSL is connected to the N-type drift layer; The junction field-effect transistor (JFET) is connected to the current spreading layer (CSL).

5. The switching assembly according to claim 1, characterized in that, The first emitter and the second emitter are stepped in shape, and the stepped shape includes a connected protrusion and a base; The base of the first emitter is connected to the first JFET / CSL layer and the first P-type body region; The base of the second emitter is connected to the second JFET / CSL layer and the second P-type body region.

6. A solid-state circuit breaker, characterized in that, include: The switching assembly according to any one of claims 1 to 5; The power input terminal is connected to the first emitter via a voltage sensor; The load end is connected to the second emitter via a current sensor; The processor is connected to the first gate via a first isolated gate driver and to the second gate via a second isolated gate driver; The voltage sensor feeds back the voltage signal to the processor in real time, and the current sensor feeds back the current signal to the processor in real time.

7. The solid-state circuit breaker according to claim 6, characterized in that, The processor is a microcontroller (MCU) or a digital signal processor (DSP), and the current sensor is a shunt or a Hall sensor.

8. The solid-state circuit breaker according to claim 6, characterized in that, An electrical isolation barrier is provided between the processor and the power input terminal, the switching assembly, and the load terminal.

9. The solid-state circuit breaker according to claim 6, characterized in that, Also includes: An auxiliary power module is connected to the processor; A human-computer interaction terminal or communication interface is connected to the processor.

10. A control method for a solid-state circuit breaker, characterized in that, The solid-state circuit breaker is the solid-state circuit breaker according to any one of claims 6 to 9, and the method includes: When the processor receives the voltage signal and the current signal does not exceed a preset safety threshold, the processor outputs a high level, and keeps the first gate and the second gate open through the first isolated gate driver and the second isolated gate driver, so that the solid-state circuit breaker remains in the conducting state; When the current signal exceeds the preset safety threshold, the processor outputs a low level, and the first gate and the second gate are disconnected through the first isolated gate driver and the second isolated gate driver, so that the solid-state circuit breaker is in a protected state.

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