Trench gate silicon carbide mosfet device and method of manufacturing the same

Abstract

The application discloses a trench gate silicon carbide MOSFET device and a manufacturing method thereof, and relates to the technical field of power semiconductor devices. The device has a substrate, an epitaxial layer on the substrate, and a drain below. A gate trench is above the epitaxial layer, and both sides of the gate trench are multi-stage gate trench integration areas, and an interlayer dielectric and a source are on the multi-stage gate trench integration areas. The gate trench has polycrystalline silicon and a gate dielectric, the multi-stage gate trench integration area includes a connection area, multi-stage gate trenches and a current expansion layer, the bottom has a shielding layer, and the shielding layer has polycrystalline silicon and a gate dielectric. The source is connected with the drain through the connection area, and is isolated from the multi-stage gate trenches through the interlayer dielectric, the shielding layer is of a second conductive type, and the rest is of a first conductive type. In the application, when the device is blocked, the electric field at the gate dielectric is reduced by applying zero or negative gate voltage, when the device is turned on, positive gate voltage is applied to inhibit JFET effect, improve turn-on capacity and reduce loss. When avalanche occurs, the multi-stage trench structure moves down the breakdown point, prolongs the heat transfer path, delays the melting of the metal, and enhances the avalanche robustness.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and particularly relates to a trench gate silicon carbide MOSFET device and its manufacturing method. Background Technology

[0002] MOSFETs are the most widely used gate-controlled devices among silicon carbide power devices. Based on their structure, they can be divided into trench-gate and planar-gate types. Planar-gate MOSFETs have higher on-resistance and lower integration density due to limitations in manufacturing process precision. Trench-gate silicon carbide MOSFETs effectively increase channel density by utilizing the trench gate, representing an important development direction for next-generation silicon carbide MOSFETs. When a trench-gate silicon carbide MOSFET is blocked, the gate oxide layer's dielectric constant is lower than that of silicon carbide, and the curvature effect exists at the trench chamfer, resulting in a very high electric field at the bottom and corners of the gate. Prolonged operation under this high electric field leads to gate oxide degradation and decreased robustness. Furthermore, while introducing a grounded P+ shield can alleviate the electric field accumulation effect near the gate trench chamfer and improve the device's blocking capability, it also introduces an additional junction field-effect transistor (JFET) region, significantly increasing on-resistance and reducing the device's turn-on capability. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defect that trench gate silicon carbide MOSFET devices in the prior art cannot simultaneously guarantee low on-resistance and high robustness, and to provide a trench gate silicon carbide MOSFET device and its manufacturing method.

[0004] The present invention solves the above-mentioned technical problems through the following technical solution:

[0005] This invention provides a trench-gate silicon carbide MOSFET device, which includes: a substrate, an epitaxial layer, a drain, a gate trench, a multi-level gate trench integration region, an interlayer dielectric, and a source.

[0006] The epitaxial layer is disposed above the substrate, and the drain is disposed below the substrate, with the drain in ohmic contact with the substrate; the gate trench is disposed above the epitaxial layer, and a multi-level gate trench integration region is disposed on each side of the gate trench; the interlayer dielectric and the source are both disposed above the gate trench and the multi-level gate trench integration region.

[0007] The gate trench includes a first polysilicon and a first gate dielectric surrounding the periphery of the first polysilicon, with the bottom of the first gate dielectric embedded in the epitaxial layer;

[0008] Each of the multi-level gate trench integration regions is provided with a connection area and multi-level gate trenches in sequence from the center to both sides. A current spreading layer is provided between the gate trenches and the multi-level gate trenches, and the connection area is located above the current spreading layer. A shielding layer is provided at the bottom of each multi-level gate trench. The shielding layer is used to reduce the electric field of the first gate dielectric, and the connection area is used to connect the drain and the source.

[0009] Each of the multi-level gate trenches is provided with a second polysilicon and a second gate dielectric surrounding the outside of the second polysilicon;

[0010] The source electrode forms an ohmic contact with each of the two connection regions, and the source electrode is separated from the two multi-level gate trenches by the interlayer dielectric.

[0011] The substrate, the epitaxial layer, and the current spreading layer are all semiconductors of the first conductivity type;

[0012] The shielding layer is a semiconductor of the second conductivity type.

[0013] In this scheme, by changing the source trench potential to the gate potential, a depletion-type MOS is integrated on the sidewalls of a multi-level trench. Depending on the device's operating mode, hole inversion and accumulation occur in the epitaxial layer on the surface of the multi-level trench sidewalls. Specifically, when the device is blocked, a zero or negative gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned on, and the shielding layer is grounded, which can effectively reduce the electric field of the first gate dielectric and improve robustness. When the device is turned on, a positive gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned off, the shielding layer is floating, and the junction field-effect transistor (JFET) effect is suppressed, which can effectively improve the device's conduction capability. When the device experiences avalanche, the multi-level gate trench shifts the avalanche breakdown point downward, increases the internal heat transfer distance, delays the burn-out caused by the melting of the surface aluminum metal, and improves the device's avalanche robustness.

[0014] Preferably, the connection region includes a first contact region, a second contact region, and a well region;

[0015] The first contact area is disposed above the well area, and the second contact area is disposed on the same side of the well area and the first contact area and is in contact with the second gate medium;

[0016] The bottom of the well region and the bottom of the second contact region are both in contact with the current spreading layer;

[0017] The first contact area is a semiconductor of a first conductivity type, and both the well region and the second contact area are semiconductors of a second conductivity type.

[0018] In this scheme, the region formed by the first contact region, the second contact region, and the well region is the source and drain region of the MOSFET. This region is a key part of the MOSFET structure. The first contact region and the second contact region are N-type and P-type highly doped regions, respectively. They form good ohmic contacts with the metal electrode and are used to connect the source and drain of the transistor.

[0019] Preferably, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor, or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.

[0020] Preferably, the number of stages in each of the multi-stage gate trenches is greater than or equal to 2.

[0021] In this design, by creating multi-level stepped trenches at the metal / semiconductor interface, P-type ions can be implanted deeper along the trench direction, resulting in better electric field shielding. Compared to single-level trench devices of the same depth, this reduces the fabrication complexity. The multi-level trench structure also significantly reduces the surface electric field. Because the bottom width of the multi-level trenches is smaller, the resulting junction field-effect transistor (JFET) region is smaller, reducing the impact on the diode's forward voltage drop.

[0022] Preferably, the first gate dielectric and the second gate dielectric are silicon dioxide or high-k dielectric.

[0023] In this solution, the gate capacitance can be increased by using a high-k dielectric or silicon dioxide in the semiconductor device, thereby reducing leakage current and improving the switching speed and power consumption performance of the transistor while maintaining the same insulating layer thickness.

[0024] Preferably, the interlayer medium is silicon dioxide.

[0025] Preferably, the region comprised of the multi-level gate trench integration region, the current spreading layer, the shielding layer, and the epitaxial layer is used to form a threshold voltage greater than the Miller voltage of the trench gate silicon carbide MOSFET device.

[0026] In this design, the threshold voltage of the region comprised of a multi-level gate trench integration region, a current spreading layer, a shielding layer, and an epitaxial layer is set to be greater than the Miller voltage of the trench-gate silicon carbide MOSFET. This means that even when the trench-gate silicon carbide MOSFET is turned on, the depletion-type MOSFET can remain off until a sufficient voltage is applied to overcome the Miller voltage. Before the depletion-type MOSFET turns on, holes are replenished to ensure continuous operation.

[0027] The present invention also provides a method for manufacturing a trench-gate silicon carbide MOSFET device, the method comprising:

[0028] Fabrication to form a substrate;

[0029] An epitaxial layer is formed on the substrate, and first-type ions are implanted into the epitaxial layer to form a current spreading layer;

[0030] The first type of ions and the second type of ions are injected sequentially to form a connection region;

[0031] Etching is performed at the middle position of the epitaxial layer to form a gate trench, and multiple etching is performed on both sides of the gate trench to form a multi-level gate trench.

[0032] A shielding layer is formed by injecting the second type of ions into the bottom and sidewalls of the multi-level grid trench;

[0033] The first and second gate dielectrics are formed by dry oxygen oxidation and then annealed in a nitric oxide atmosphere.

[0034] Depositing polysilicon flattens the device surface;

[0035] Deposit interlayer dielectric and etch the interlayer dielectric;

[0036] The source electrode is obtained by etching the contact holes between the source and the gate and depositing metal to form an ohmic contact.

[0037] Metal is deposited on the back side to form an ohmic contact, thus creating the drain electrode;

[0038] The substrate, the epitaxial layer, and the current spreading layer are all semiconductors of the first conductivity type;

[0039] The shielding layer is a semiconductor of the second conductivity type.

[0040] Preferably, the first type of ion is a nitrogen ion and the second type of ion is an aluminum ion, or the first type of ion is an aluminum ion and the second type of ion is a nitrogen ion.

[0041] Preferably, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor, or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.

[0042] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0043] The positive advancements of this application are as follows: By changing the source trench potential to the gate potential and integrating a depletion-type MOS on the sidewalls of the multi-level trenches, depending on the device's operating mode, hole inversion and accumulation occur in the epitaxial layer on the surface of the multi-level trench sidewalls. Specifically, when the device is blocked, a zero or negative gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned on, and the shielding layer is grounded, effectively reducing the electric field of the first gate dielectric and improving robustness. When the device is turned on, a positive gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned off, the shielding layer floats, and the JFET effect is suppressed, effectively improving the device's conduction capability. When avalanche occurs, the multi-level gate trenches shift the avalanche breakdown point downwards, increasing the internal heat transfer distance and delaying burn-out caused by the melting of surface aluminum metal, thus improving the device's avalanche robustness. Attached Figure Description

[0044] Figure 1 This is a schematic cross-sectional view of a trench gate silicon carbide MOSFET device provided in an embodiment of the present invention.

[0045] Figure 2 This is a schematic flowchart of a method for manufacturing a trench gate silicon carbide MOSFET device according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of nitrogen ion implantation to form a current spreading layer on an N-epitaxial wafer in Embodiment 2 of the present invention;

[0047] Figure 4 This is a schematic diagram of the formation of the P-well region by implanting aluminum ions in Embodiment 2 of the present invention;

[0048] Figure 5 This is a schematic diagram of the formation of the P+ contact region by implanting aluminum ions in Embodiment 2 of the present invention;

[0049] Figure 6 This is a schematic diagram of the formation of an N+ contact region by injecting nitrogen ions in Embodiment 2 of the present invention;

[0050] Figure 7 This is a schematic diagram of etching to form gate trenches in Embodiment 2 of the present invention, and multiple etching processes to form multi-level gate trenches;

[0051] Figure 8 This is a schematic diagram of the formation of a P+ shielding layer by injecting aluminum ions into the sidewalls and bottom of the multi-level grid trench in Embodiment 2 of the present invention;

[0052] Figure 9 This is a schematic diagram of the formation of a gate oxide layer by dry oxygen oxidation in Embodiment 2 of the present invention, followed by annealing in a nitric oxide atmosphere;

[0053] Figure 10 This is a schematic diagram of the planarization of the surface by depositing polycrystalline silicon in Embodiment 2 of the present invention;

[0054] Figure 11 This is a schematic diagram of the deposition and etching of the interlayer medium in Embodiment 2 of the present invention;

[0055] Figure 12 This is a schematic diagram of etching the source and gate contact holes, depositing metal to form an ohmic contact, and depositing metal on the back side to form an ohmic contact in Embodiment 2 of the present invention.

[0056] Explanation of reference numerals in the attached figures:

[0057] Substrate 1

[0058] Epitaxial layer 2

[0059] Drain 3

[0060] Interlayer medium 4

[0061] Source 5

[0062] First polycrystalline silicon 6

[0063] First gate dielectric 7

[0064] Current spreading layer 8

[0065] Shielding layer 9

[0066] Second polysilicon 10

[0067] Second gate dielectric 11

[0068] First contact zone 12

[0069] Second contact area 13

[0070] Tunnel 14 Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0072] It should be noted that if this embodiment involves directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0073] Furthermore, if this embodiment involves descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0074] Example 1

[0075] Please see Figure 1 This embodiment provides a trench-gate silicon carbide MOSFET device. Figure 1 This is a cross-sectional view of a trench-gate silicon carbide MOSFET device provided in an embodiment of the present invention. The trench-gate silicon carbide MOSFET device includes: a substrate 1, an epitaxial layer 2, a drain 3, a gate trench, a multi-level gate trench integration region, an interlayer dielectric 4, and a source 5. The epitaxial layer 2 is disposed above the substrate 1, and the drain 3 is disposed below the substrate 1, with the drain 3 in ohmic contact with the substrate 1. A gate trench is disposed above the epitaxial layer 2, and a multi-level gate trench integration region is disposed on each side of the gate trench. The interlayer dielectric 4 and the source 5 are both disposed above the gate trench and the multi-level gate trench integration region. The gate trench includes a first polysilicon 6 and a first gate dielectric 7 surrounding the first polysilicon 6. The bottom of the first gate dielectric 7 is embedded in the epitaxial layer 2. Each multi-level gate trench integration region... The region is provided with source 5 and drain 3 connection area and multi-level gate trench in sequence from the center to both sides. A current spreading layer 8 is provided between the gate trench and the multi-level gate trench. The source 5 and drain 3 connection area is located above the current spreading layer 8. A shielding layer 9 is provided at the bottom of each multi-level gate trench. The shielding layer 9 is used to reduce the electric field of the first gate dielectric 7. The connection area is used to connect the drain 3 and the source 5. A second polysilicon 10 and a second gate dielectric 11 surrounding the second polysilicon 10 are provided in each multi-level gate trench. The source 5 forms an ohmic contact with the two source 5 and drain 3 connection areas respectively. The source 5 is separated from the two multi-level gate trenches by the interlayer dielectric 4. The substrate 1, epitaxial layer 2 and current spreading layer 8 are all first conductivity type semiconductors. The shielding layer 9 is a second conductivity type semiconductor.

[0076] In this embodiment, by changing the source trench potential of 5 to the gate potential, a depletion-type MOS is integrated on the sidewall of the multi-level trench. Depending on the device's operating mode, hole inversion and accumulation occur in the epitaxial layer 2 on the surface of the multi-level trench sidewall. That is, when the device is blocked, a zero or negative gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned on, and the shielding layer 9 is grounded, which can effectively reduce the electric field of the first gate dielectric 7 and improve robustness. When the device is turned on, a positive gate voltage is applied to the multi-level trench gate, the depletion-type MOS is turned off, the shielding layer 9 is floating, the JFET effect is suppressed, and the device's conduction capability can be effectively improved. When the device experiences avalanche, the multi-level gate trench shifts the avalanche breakdown point downward, increases the internal heat transfer distance, delays the burn-out caused by the melting of the surface aluminum metal, and improves the device's avalanche robustness.

[0077] Specifically, the source 5 and drain 3 connection region includes a first contact region 12, a second contact region 13, and a well region 14. The first contact region 12 is disposed above the well region 14, and the second contact region 13 is disposed on the same side of the well region 14 and the first contact region 12 and contacts the second gate dielectric 11. The bottom of the well region 14 and the bottom of the second contact region 13 are both in contact with the current spreading layer 8. The first contact region 12 is a semiconductor of a first conductivity type, and the well region 14 and the second contact region 13 are both semiconductors of a second conductivity type. In this application, the region formed by the first contact region 12, the second contact region 13, and the well region 14 is the source 5 and drain 3 region of the MOSFET. This region is a key part of the MOSFET structure. The first contact region 12 and the second contact region 13 are respectively N-type and P-type highly doped regions, which form good ohmic contacts with the metal electrode to connect the source 5 and drain 3 of the transistor.

[0078] In this application, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor. Specifically, taking an N-type semiconductor as the first conductivity type and a P-type semiconductor as the second conductivity type as an example, the specific MOSFET device structure is described in detail below:

[0079] The device includes an N-type substrate 1 and an N-type epitaxial layer 2 above the N-type substrate 1; a gate trench above the N-type epitaxial layer 2, a first polysilicon 6 disposed within the gate trench, and a first gate dielectric 7 surrounding the outer periphery of the first polysilicon 6. Multi-level gate trenches are respectively provided on the upper left and upper right of the N-type epitaxial layer 2, and a second polysilicon 10 is disposed within the multi-level gate trenches. A second gate dielectric 11 is disposed on the side and bottom edge of the second polysilicon 10 near the gate trench. An N-type current spreading layer 8 is disposed between the gate trench and the multi-level gate trenches (i.e., an N-type current spreading layer 8 is disposed between the first gate dielectric 7 and the second gate dielectric 11). A P-type well (P-well region) is disposed above the N-type current spreading layer 8, and an N+ contact region is disposed above the P-well region. A P+ contact region is disposed on the side of the N+ contact region and the P-well region away from the gate trench. The bottom of the P+ contact region and the bottom of the P-well region are in contact with the N-type current spreading layer 8. A P+ shielding layer 9 is disposed at the bottom of the multi-level gate trench. The P+ shielding layer 9 is embedded in the N-type epitaxial layer 2, and the P+ shielding layer 9 does not contact the N-type current spreading layer 8 or the first gate dielectric 7. A drain 3 is disposed below the device, forming an ohmic contact with the N-type substrate 1, and a source 5 is disposed above the device, forming an ohmic contact with the P+ contact region and the N+ contact region. The second polysilicon 10, the first gate dielectric 7, and the second gate dielectric 11 are separated from the source 5 by an interlayer dielectric 4 and do not contact the source 5.

[0080] In this design, source 5 and drain 3 are made of metal, such as aluminum, while the first gate dielectric 7 and the second gate dielectric 11 are made of silicon dioxide or high-k dielectrics. High-k dielectrics are materials with a high dielectric constant (k-value), used in semiconductor devices as insulating materials between the transistor gate and the insulating layer. The dielectric constant is a physical quantity that measures a material's ability to store charge; the dielectric constant of high-k dielectrics is typically greater than that of silicates (such as silicon dioxide). In semiconductor devices, using high-k dielectrics can increase gate capacitance, thereby reducing leakage current and improving transistor switching speed and power consumption performance while maintaining the same insulating layer thickness. Commonly used high-k dielectric materials include alumina (Al₂O₃), barium titanate (BaTiO₃), aluminum nitride (AlN), and lead cerium titanate (Pb(Zr,Ti)O₃, abbreviated as PZT). The interlayer dielectric 4 is silicon dioxide (SiO₂).

[0081] In this embodiment, each multi-level gate trench has two or more levels, and the depth of the multi-level gate trench is greater than 3 μm. By designing multi-level stepped trenches at the metal / semiconductor contact interface, P-type ions can be implanted deeper along the trench direction, constructing better electric field shielding and reducing the fabrication difficulty compared to single-level trench devices of the same depth. The multi-level trench structure can also significantly reduce the surface electric field. Because the bottom width of the multi-level trench is smaller, the area of ​​the resulting junction field-effect transistor (JFET) region is smaller, reducing the impact on the forward voltage drop of the diode.

[0082] In this embodiment, by changing the trench potential of the source 5 to the gate potential, i.e., the first polysilicon 6 and the second polysilicon 10 are connected to the gate potential, and the second polysilicon 10 is not directly connected to the source 5, a depletion-type PMOS (i.e., the P+ contact region, the N-type current extension layer 8, and the P+ shielding layer 9 are connected through the N-type epitaxial layer 2) is integrated on the sidewall of the multi-level trench. Depending on the device's operating mode, holes inversion and accumulation occur on the N-type epitaxial layer 2 on the surface of the multi-level trench sidewall. When the device is blocked, zero gate voltage or negative gate voltage is applied to the multi-level trench gate (i.e., zero gate voltage or negative gate voltage is applied to the second polysilicon 10), the depletion-type PMOS is turned on, and the potential of the P+ shielding layer 9 is the same as the potential of the P+ contact region. At this time, since the P+ contact region is connected to the source 5, the P+ contact region, the N-type current extension layer 8, and the P+ shielding layer 9 are connected through the N-type epitaxial layer 2, and the P+ shielding layer 9 is grounded, thereby effectively reducing the electric field of the first gate dielectric 7 and improving robustness.

[0083] When the device is turned on, a positive gate voltage is applied to the multi-level trench gate (i.e., a positive gate voltage is applied to the second polysilicon 10), the depletion-type PMOS is turned off, and the P+ shielding layer 9 is floating (i.e., the P+ shielding layer 9 is not grounded and is disconnected). The JFET effect is suppressed, which can effectively improve the device's conduction capability.

[0084] When a device experiences avalanche, the multi-level gate trenches shift the avalanche breakdown point downwards, increasing the internal heat transfer distance and thus delaying the burn-out caused by the melting of the surface aluminum metal, thereby improving the device's avalanche robustness.

[0085] Compared with conventional MOSFET devices, the trench-gate silicon carbide MOSFET device of this application can reduce the conduction loss by 15% in the on state, reduce the gate oxide electric field strength by 30% in the off state, and increase the avalanche tolerance by 10% in the avalanche state.

[0086] In this embodiment, the region comprised of the multi-level gate trench integration region, the current spreading layer 8, the shielding layer 9, and the epitaxial layer 2 is used to form a threshold voltage greater than the Miller voltage of the trench-gate silicon carbide MOSFET device. Specifically, the PMOS is made of a P-type semiconductor material, whose majority carriers are holes (i.e., electrons are missing). When the PMOS is turned on, the holes in its channels recombine with electrons, resulting in a decrease in the number of holes. If the PMOS is frequently switched on and off, this recombination process will cause the number of holes to continuously decrease, thereby weakening the effect of the PMOS. By setting the depletion-type PMOS threshold voltage greater than the Miller voltage of the trench-gate silicon carbide MOSFET, it means that when the trench-gate silicon carbide MOSFET is initially turned on, the PMOS can also remain in the off state until a sufficient voltage is applied to overcome the Miller voltage. Before the PMOS is turned on, there is a replenishment of holes to ensure that the PMOS can continue to operate. This replenishment may be achieved through the turn-on process.

[0087] In other embodiments, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor. The operating principle of this trench-gate silicon carbide MOSFET device is the same as that of the trench-gate silicon carbide MOSFET devices described above, and will not be repeated here.

[0088] Example 2

[0089] Please see Figures 2 to 12 This application also provides a method for manufacturing a trench-gate silicon carbide MOSFET device, which is used to manufacture the trench-gate silicon carbide MOSFET device as described above. Figure 2 This is a schematic flowchart illustrating a method for manufacturing a trench-gate silicon carbide MOSFET device according to an embodiment of the present invention. Figure 2 As shown, the method includes:

[0090] S101: Fabrication of a substrate;

[0091] S102: An epitaxial layer is formed on top of the substrate, and first-type ions are implanted into the epitaxial layer to form a current spreading layer;

[0092] S103: First type ions and second type ions are sequentially injected to form a connection region;

[0093] S104: Etching is performed in the middle of the epitaxial layer to form a gate trench, and multiple etching is performed on both sides of the gate trench to form a multi-level gate trench.

[0094] S105: Type II ions are injected into the bottom and sidewalls of the multi-level grid trench to form a shielding layer;

[0095] S106: The first and second gate dielectrics are formed by dry oxygen oxidation and then annealed in a nitric oxide atmosphere;

[0096] S107: Depositing polysilicon to planarize the device surface;

[0097] S108: Deposit interlayer dielectric and etch the interlayer dielectric;

[0098] S109: Etch the source and gate contact holes and deposit metal to form an ohmic contact to obtain the source;

[0099] S1010: Metal is deposited on the back side to form an ohmic contact and obtain the drain electrode;

[0100] The substrate, epitaxial layer, and current spreading layer are all semiconductors of the first conductivity type, and the shielding layer is a semiconductor of the second conductivity type.

[0101] In this embodiment, the first conductivity type semiconductor is an N-type semiconductor, the second conductivity type semiconductor is a P-type semiconductor, the first type ion is a nitrogen ion, and the second type ion is an aluminum ion. The manufacturing process of this type of trench-gate silicon carbide MOSFET device will be described in detail below, in conjunction with... Figures 3 to 12 The explanation includes the following steps:

[0102] Step 1: Clean the silicon carbide epitaxial wafer (N-), and implant nitrogen ions (N ions) into the N- epitaxial wafer to form an N-type current spreading layer. See details below. Figure 3 ;

[0103] Step 2: Implant aluminum ions (Al ions) to form the P-well region, see details below. Figure 4 ;

[0104] Step 3: Inject aluminum ions (Al ions) to form P+ contact regions, and inject nitrogen ions (N ions) to form N+ contact regions. See details below. Figure 5 and Figure 6 ;

[0105] Step 4: Etching to form gate trenches. Multiple etching operations form multi-level gate trenches. See details. Figure 7 ;

[0106] Step 5: Inject aluminum ions (Al ions) into the sidewalls and bottom of the multi-level gate trench to form a P+ shielding layer. See details below. Figure 8 ;

[0107] Step 6: Dry oxygen oxidation forms the gate oxide layer (i.e., the first and second gate dielectrics mentioned above), followed by annealing in a nitric oxide atmosphere. See details below. Figure 9 ;

[0108] Step 7: Deposit polycrystalline silicon to planarize the surface. See details below. Figure 10 ;

[0109] Step 8: Deposit and etch the interlayer dielectric. See details below. Figure 11 ;

[0110] Step 9: Etch the source and gate contact holes, deposit metal to form an ohmic contact to obtain the source. See details below. Figure 12 ;

[0111] Step 10: Deposit metal on the back side to form an ohmic contact and obtain the drain electrode. See details below. Figure 12 .

[0112] In other embodiments, the first conductivity type semiconductor is a P-type semiconductor, the second conductivity type semiconductor is an N-type semiconductor, the first type ion is aluminum ions, and the second type ion is nitrogen ions. The manufacturing process of this type of trench-gate silicon carbide MOSFET device corresponds to the process described above and will not be elaborated here.

[0113] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A trench-gate silicon carbide MOSFET device, characterized in that, The trench gate silicon carbide MOSFET device includes: a substrate, an epitaxial layer, a drain, a gate trench, a multi-level gate trench integration region, an interlayer dielectric, and a source. The epitaxial layer is disposed above the substrate, and the drain is disposed below the substrate, with the drain in ohmic contact with the substrate; the gate trench is disposed above the epitaxial layer, and a multi-level gate trench integration region is disposed on each side of the gate trench; the interlayer dielectric and the source are both disposed above the gate trench and the multi-level gate trench integration region. The gate trench includes a first polysilicon and a first gate dielectric surrounding the periphery of the first polysilicon, with the bottom of the first gate dielectric embedded in the epitaxial layer; Each of the multi-level gate trench integration regions is provided with a connection area and multi-level gate trenches in sequence from the center to both sides. A current spreading layer is provided between the gate trenches and the multi-level gate trenches, and the connection area is located above the current spreading layer. A shielding layer is provided at the bottom of each multi-level gate trench. The shielding layer is used to reduce the electric field of the first gate dielectric, and the connection area is used to connect the drain and the source. Each of the multi-level gate trenches is provided with a second polysilicon and a second gate dielectric surrounding the outside of the second polysilicon; The source electrode forms an ohmic contact with each of the two connection regions, and the source electrode is separated from the two multi-level gate trenches by the interlayer dielectric. The substrate, the epitaxial layer, and the current spreading layer are all semiconductors of the first conductivity type; The shielding layer is a semiconductor of the second conductivity type; The connection region includes a first contact region, a second contact region, and a well region; the first contact region is disposed above the well region, and the second contact region is disposed on the same side of the well region and the first contact region and is in contact with the second gate dielectric; the bottom of the well region and the bottom of the second contact region are both in contact with the current spreading layer; the first contact region is a semiconductor of a first conductivity type, and the well region and the second contact region are both semiconductors of a second conductivity type.

2. The trench-gate silicon carbide MOSFET device as described in claim 1, characterized in that, The first type of semiconductor is an N-type semiconductor and the second type of semiconductor is a P-type semiconductor, or the first type of semiconductor is a P-type semiconductor and the second type of semiconductor is an N-type semiconductor.

3. The trench-gate silicon carbide MOSFET device as described in claim 1, characterized in that, Each of the multi-level gate trenches has a number of levels greater than or equal to 2.

4. The trench-gate silicon carbide MOSFET device as described in claim 1, characterized in that, The first gate dielectric and the second gate dielectric are silicon dioxide or high-k dielectric.

5. The trench-gate silicon carbide MOSFET device as described in claim 1, characterized in that, The interlayer medium is silicon dioxide.

6. The trench-gate silicon carbide MOSFET device as described in claim 1, characterized in that, The region composed of the multi-level gate trench integration region, the current spreading layer, the shielding layer, and the epitaxial layer is used to form a threshold voltage greater than the Miller voltage of the trench gate silicon carbide MOSFET device.

7. A method for manufacturing a trench-gate silicon carbide MOSFET device as described in any one of claims 1-6, characterized in that, The method for manufacturing the trench-gate silicon carbide MOSFET device includes: Fabrication to form a substrate; An epitaxial layer is formed on the substrate, and first-type ions are implanted into the epitaxial layer to form a current spreading layer; The first type of ions and the second type of ions are sequentially implanted to form a connection region; the connection region includes a first contact region, a second contact region, and a well region; the first contact region is disposed above the well region, and the second contact region is disposed on the same side of the well region and the first contact region and is in contact with the second gate dielectric; the bottom of the well region and the bottom of the second contact region are both in contact with the current spreading layer; the first contact region is a semiconductor of a first conductivity type, and the well region and the second contact region are both semiconductors of a second conductivity type; Etching is performed at the middle position of the epitaxial layer to form a gate trench, and multiple etching is performed on both sides of the gate trench to form a multi-level gate trench. A shielding layer is formed by injecting the second type of ions into the bottom and sidewalls of the multi-level grid trench; The first and second gate dielectrics are formed by dry oxygen oxidation and then annealed in a nitric oxide atmosphere. Depositing polysilicon flattens the device surface; Deposit interlayer dielectric and etch the interlayer dielectric; The source electrode is obtained by etching the contact holes between the source and the gate and depositing metal to form an ohmic contact. Metal is deposited on the back side to form an ohmic contact, thus creating the drain electrode; The substrate, the epitaxial layer, and the current spreading layer are all semiconductors of the first conductivity type; The shielding layer is a semiconductor of the second conductivity type.

8. The method for manufacturing a trench-gate silicon carbide MOSFET device as described in claim 7, characterized in that, The first type of ion is nitrogen ion and the second type of ion is aluminum ion, or the first type of ion is aluminum ion and the second type of ion is nitrogen ion.

9. The method for manufacturing a trench-gate silicon carbide MOSFET device as described in claim 8, characterized in that, The first type of semiconductor is an N-type semiconductor and the second type of semiconductor is a P-type semiconductor, or the first type of semiconductor is a P-type semiconductor and the second type of semiconductor is an N-type semiconductor.

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