Array substrate and display panel thereof

Abstract

The application discloses an array substrate and a display panel thereof. The array substrate comprises a substrate, a plurality of pixel units are arranged on one side of the substrate, a thin film transistor, a flat part and a pixel electrode are sequentially arranged in the pixel unit in a direction away from the substrate, the pixel electrode is electrically connected with the thin film transistor, and the flat parts in the plurality of pixel units form a flat layer. The array substrate further comprises a solar cell, the solar cell is at least partially arranged in the flat layer, a projection of the solar cell on a direction perpendicular to the substrate does not overlap with a projection of the pixel electrode layer, the solar cell is used for converting part of light irradiated on the solar cell into electric energy, the solar cell comprises a plurality of solar cell units, and the solar cell units are arranged at intervals from the pixel electrode. The array substrate and the display panel thereof disclosed by the application can improve the endurance of display products and realize an extremely narrow frame or a frameless display.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and its display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays have become the mainstream display technology for smartphones, tablets, televisions, and wearable devices due to their superior performance, including low power consumption, high color saturation, wide viewing angle, and flexibility. As consumers' aesthetic demands for end-products continue to rise, the bezel width of display panels needs to be further reduced to achieve a better visual experience.

[0003] Furthermore, while meeting user needs, OLED display technology should also consider the issue of mobile phone battery life. As the functional integration of display devices continues to increase, simultaneously achieving display driving and energy harvesting functions within a limited panel space has become an important development direction. In existing technologies, solar cells are usually fabricated separately and then attached to the surface of the display device or embedded in the bezel area. This not only increases the module thickness and assembly complexity but also makes it difficult to be compatible with the narrow bezel design of the display panel.

[0004] Therefore, how to integrate solar cell functionality while achieving ultra-narrow or borderless bezels on display panels, and how to simplify manufacturing processes and reduce production costs, are technical problems that urgently need to be solved in this field. Summary of the Invention

[0005] This application provides an array substrate and its display panel, which are designed to improve the performance of display products.

[0006] An embodiment of the first aspect of this application provides an array substrate, comprising: a substrate, wherein a plurality of pixel units are disposed on one side of the substrate, and thin-film transistors, planarization portions, and pixel electrodes are sequentially stacked within each pixel unit along a direction away from the substrate, the pixel electrodes being electrically connected to the thin-film transistors, the thin-film transistors within the plurality of pixel units forming a thin-film transistor layer, the planarization portions within the plurality of pixel units forming a planarization layer, and the pixel electrodes within the plurality of pixel units forming a pixel electrode layer; further comprising: a solar cell, wherein the solar cell is at least partially disposed within the planarization layer, and in a direction perpendicular to the substrate, the orthographic projection of the solar cell does not overlap with the orthographic projection of the pixel electrode layer; the solar cell is used to convert a portion of the light irradiated on the solar cell into electrical energy; the solar cell includes a plurality of solar cell units, the solar cell units being spaced apart from the pixel electrodes.

[0007] In some embodiments of this application, at least one bonding region is provided on the side of the substrate away from the thin-film transistor layer; the thin-film transistor includes a gate, an active layer, a first electrode, and a second electrode; the solar cell unit includes a first electrode and a second electrode, and a photoelectric conversion thin film is formed between the first electrode and the second electrode; the array substrate further includes: a first conductive layer disposed between the substrate and the thin-film transistor layer, the first conductive layer including a plurality of conductive portions, the conductive portions including a first conductive portion, a second conductive portion, and a third conductive portion, the first electrode being electrically connected to the first conductive portion, the first electrode being electrically connected to the second conductive portion, and the second electrode being electrically connected to the third conductive portion; a second conductive layer disposed within the bonding region of the substrate, the second conductive layer including a plurality of bonding terminals, the bonding terminals including a first bonding terminal, a second bonding terminal, and a third bonding terminal, the first conductive portion being electrically connected to at least one first bonding terminal, the second conductive portion being electrically connected to at least one second bonding terminal, and the third conductive portion being electrically connected to at least one third bonding terminal.

[0008] In some embodiments of this application, the first electrode is disposed in the same layer as both the first electrode and the second electrode, and the surface of the second electrode near the substrate is flush with the surface of the pixel electrode near the substrate.

[0009] In some embodiments of this application, the first electrode is made of the same material as the first electrode and the second electrode, and the second electrode is made of the same material as the pixel electrode.

[0010] In some embodiments of this application, a plurality of solar cell units are arranged along a second direction to form a first solar cell unit column, and at least one pixel electrode is disposed between two adjacent solar cell units in the first solar cell unit column; at least one solar cell unit is arranged along the second direction to form a second solar cell unit column; the first solar cell unit column and the second solar cell unit column are arranged alternately in a first direction perpendicular to the second direction.

[0011] In some embodiments of this application, the second conductive layer includes a first bonding terminal group, a second bonding terminal group, and a third bonding terminal group. The first bonding terminal group includes a plurality of first bonding terminals, the second bonding terminal group includes a plurality of second bonding terminals, and the third bonding terminal group includes a plurality of third bonding terminals. The first bonding terminal group is located between the second bonding terminal group and the third bonding terminal group.

[0012] In some embodiments of this application, the array substrate further includes a third conductive layer, the third conductive layer including a plurality of fourth conductive portions, the fourth conductive portions being disposed on the same layer as the first electrode of the thin film transistor, the first electrode of the thin film transistor being electrically connected to the fourth conductive portions, and the fourth conductive portions being electrically connected to the first conductive portions through at least one via.

[0013] In some embodiments of this application, the width of the first conductive portion is greater than the width of the fourth conductive portion.

[0014] In some embodiments of this application, the solar cell further includes a conductive structure in which the first electrode of a portion of the solar cell unit is electrically connected to the second electrode layer of at least one adjacent solar cell unit.

[0015] In some embodiments of this application, a barrier layer is provided on the sidewall of the solar cell unit and at least a portion of the surface of the second electrode away from the substrate.

[0016] In some embodiments of this application, the substrate further includes a support layer disposed on the side of the second conductive layer away from the first conductive layer, the support layer including at least one first opening that exposes at least a portion of the second conductive layer.

[0017] Based on the above-described array substrate technical solution, a second aspect of this application further provides a display panel, the display panel including the array substrate of any embodiment of the first aspect, and further including: a pixel defining layer disposed on one side of the array substrate, the pixel defining layer including a pixel defining portion and a pixel opening formed by the pixel defining portion, the pixel opening exposing a portion of the pixel electrode; a light-emitting layer disposed on the side of the pixel defining layer away from the array substrate, the light-emitting layer including a plurality of light-emitting devices, the light-emitting devices being electrically connected to the second electrode of the thin-film transistor; an encapsulation layer disposed on the side of the light-emitting layer away from the array substrate; and a flexible circuit board disposed on the backlight side of the light-emitting layer, the flexible circuit board including a fourth conductive layer, the fourth conductive layer being electrically connected to the second conductive layer.

[0018] The beneficial effects of the embodiments of this application are as follows: The array substrate and its display panel provided in this application, by correspondingly connecting the first conductive part, the second conductive part, and the third conductive part in the first conductive layer with the first bonding terminal, the second bonding terminal, and the third bonding terminal in the second conductive layer, lead the display driving signal and the power signal generated by the solar cell to the bonding area on the back of the substrate through the first conductive layer and the second conductive layer. This, combined with the first opening on the support layer, enables direct connection of external circuits such as flexible circuit boards or flip-chip films from the back. Compared to the prior art, which bends the bonding area to the back of the display panel, this application effectively reduces the width of the bottom bezel of the display panel while integrating display and light energy collection functions, achieving the beneficial effects of extremely narrow bezels or even bezel-less designs. Furthermore, it avoids damage or even breakage of the wiring due to bending stress during bending, thus improving the reliability of the display product. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the schematic diagrams of a planar structure of an array substrate provided in an embodiment of this application;

[0021] Figure 2 Provided for the embodiments of this application Figure 1 One of the schematic diagrams of the cross-sectional structure of the array substrate at point AA; Figure 3 Provided for the embodiments of this application Figure 1 Schematic diagram of the cross-sectional structure of the array substrate at point AA (Part 2); Figure 4 This is a second schematic diagram of a planar structure of an array substrate provided in an embodiment of this application; Figure 5 Provided for the embodiments of this application Figure 3 A schematic diagram of the planar structure at point B; Figure 6 Provided for the embodiments of this application Figure 1 The third schematic diagram of the cross-sectional structure of the array substrate at point AA; Figure 7 Provided for the embodiments of this application Figure 1 Fourth schematic diagram of the cross-sectional structure of the array substrate at point AA; Figure 8 A cross-sectional schematic diagram of a solar cell provided in an embodiment of this application; Figure 9 Provided for the embodiments of this application Figure 1 Fifth schematic diagram of the cross-sectional structure of the array substrate at point AA; Figure 10 An embodiment provided in this application Figure 1 A cross-sectional view of the display panel at point AA.

[0022] Explanation of reference numerals in the attached figures: 10, substrate; 11, data line; 12, scan line; 13, thin-film transistor layer; 131, thin-film transistor; 1311, first electrode; 1312, second electrode; 1313, gate; 1314, active layer; 14, pixel electrode layer; 141, pixel electrode; 15, planarization layer; 151, planarization portion; 16, solar cell; 161, solar cell unit; 1611, first electrode; 1612, photoelectric conversion thin film; 1613, second electrode; 1614, barrier layer; 17, interlayer insulating layer; 171, first interlayer insulating layer; 172, second interlayer insulating layer; 173, third interlayer insulating layer; 18, buffer layer; 19, first conductive layer; 1 91. First conductive part; 192. Second conductive part; 193. Third conductive part; 20. Second conductive layer; 201. First bonding terminal; 201'. First bonding terminal group; 202. Second bonding terminal; 202'. Second bonding terminal group; 203. Third bonding terminal; 203'. Third bonding terminal group; 21. Third conductive layer; 211. Fourth conductive part; 212. Via; 22. Support layer; 221. First opening; 23. Conductive structure; 24. Pixel limiting layer; 241. Pixel limiting part; 242. Pixel opening; 25. Light emitting layer; 26. Encapsulation layer; 27. Flexible circuit board; 271. Fourth conductive layer; B. Bonding area; X. First direction; Y. Second direction. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0028] Please refer to the reference. Figure 1 and Figure 2 As shown, this application embodiment provides an array substrate, including a substrate 10. The substrate 10 serves as a supporting base for the array substrate, supporting subsequent film layer structures. On one side of the substrate 10, cross-arranged scan lines 12 and data lines 11 are provided, along with a plurality of pixel units arranged in an array, divided by the scan lines 12 and data lines 11. Along a direction away from the substrate 10, thin-film transistors 131, planarization portions 151, and pixel electrodes 141 are sequentially stacked within each pixel unit, with the pixel electrodes 141 electrically connected to the thin-film transistors 131. The thin-film transistors 131 within the plurality of pixel units form a thin-film transistor layer 13, the planarization portions 151 within the plurality of pixel units form a planarization layer 15, and the pixel electrodes 141 within the plurality of pixel units form a pixel electrode layer 14.

[0029] Those skilled in the art will understand that the specific structure of the thin-film transistor 131 may include a gate 1313, an active layer 1314, a first electrode 1311 and a second electrode 1312, and one or more interlayer insulating layers 17 (e.g., a first interlayer insulating layer 171 and a second interlayer insulating layer 172) are provided between each film layer to ensure electrical isolation and mechanical support between each functional layer. This embodiment does not impose specific limitations on this.

[0030] Please continue to refer to this. Figure 2 As shown, the array substrate provided in this embodiment also includes a solar cell 16. The solar cell 16 is at least partially disposed within the planarization layer 15, and as... Figure 2As shown, in the direction perpendicular to the substrate 10, the orthographic projection of the solar cell 16 does not overlap with the orthographic projection of the pixel electrode layer 14. The solar cell 16 is used to convert a portion of the light shining on it into electrical energy, thereby realizing the collection and utilization of light energy. The solar cell 16 includes multiple solar cell units 161, which are spaced apart from the pixel electrode 141 to prevent electrical signal interference between them. In this embodiment, by at least partially placing the solar cell 16 within the planarization layer 15, on the one hand, there is no need to increase the overall thickness of the array substrate, which is beneficial for the thin design of the display product; on the other hand, the spaced arrangement of the solar cell units 161 and the pixel electrode 141 can effectively avoid electrical crosstalk between the solar cell 16 and the pixel electrode 141, ensuring the normal operation of the display function. Through the above structural design, the display function and the photoelectric conversion function are integrated inside the array substrate, improving the battery life of the display product without affecting the display effect.

[0031] Please refer to the reference. Figure 3 As shown, based on the above embodiment, at least one bonding region B is provided on the side of the substrate 10 away from the thin-film transistor layer 13. The thin-film transistor 131 includes a gate 1313, an active layer 1314, a first electrode 1311, and a second electrode 1312. The solar cell unit 161 includes a first electrode 1611 and a second electrode 1613, and a photoelectric conversion thin film 1612 is formed between the first electrode 1611 and the second electrode 1613. The array substrate also includes a first conductive layer 19 and a second conductive layer 20.

[0032] In this embodiment, a buffer layer 18 is further provided between the substrate 10 and the first conductive layer 19. On the one hand, the buffer layer 18 helps to enhance the adhesion between the substrate 10 and the first conductive layer 19, thereby reducing the risk of the first conductive layer 19 detaching from the substrate 10. On the other hand, the buffer layer 18 can effectively block the high temperature during the formation of the first conductive layer 19, providing better protection for the substrate 10. The material used to form the buffer layer 18 can be various, such as one or more of silicon oxide and silicon nitride, or other materials. However, this embodiment does not impose specific limitations on this, as long as the buffer layer 18 can achieve the aforementioned functions.

[0033] In this embodiment, a third interlayer insulating layer 173 is further provided between the first conductive layer 19 and the thin-film transistor layer 13. On the one hand, the third interlayer insulating layer 173 facilitates electrical isolation between the first conductive layer 19 and the thin-film transistor layer 13, preventing unexpected short circuits between the first conductive layer 19 and the electrodes of the thin-film transistor 131. On the other hand, the third interlayer insulating layer 173 can effectively planarize the surface morphology above the first conductive layer 19, providing a flat substrate for the subsequent fabrication of the thin-film transistor layer 13, which is beneficial to improving the performance uniformity of the thin-film transistor 131. Various materials can be used to form the third interlayer insulating layer 173, such as one or more of silicon oxide and silicon nitride, or other organic or inorganic insulating materials. However, this embodiment does not impose specific limitations, as long as the third interlayer insulating layer 173 can achieve the aforementioned insulating isolation and surface planarization effects.

[0034] A first conductive layer 19 is disposed between a buffer layer 18 and a third interlayer insulating layer 173. The first conductive layer 19 includes multiple conductive portions, including a first conductive portion 191, a second conductive portion 192, and a third conductive portion 193. The first conductive portion 191 is electrically connected to the first electrode 1311 of the thin-film transistor 131, the second conductive portion 192 is electrically connected to the first electrode 1611 of the solar cell 16, and the third conductive portion 193 is electrically connected to the second electrode 1613 of the solar cell 16. A second conductive layer 20 is disposed within the bonding region B of the substrate 10. The second conductive layer 20 includes multiple bonding terminals, including a first bonding terminal 201, a second bonding terminal 202, and a third bonding terminal 203. The first conductive portion 191 is electrically connected to at least one first bonding terminal 201, the second conductive portion 192 is electrically connected to at least one second bonding terminal 202, and the third conductive portion 193 is electrically connected to at least one third bonding terminal 203. With the above structure, the power signal or data signal required by the thin film transistor 131 can be transmitted to the first electrode 1311 through the first bonding terminal 201 and the first conductive part 191. The electrical energy generated by the solar cell 16 can be output to the outside through the second electrode 1613, the third conductive part 193 and the third bonding terminal 203, or through the first electrode 1611, the second conductive part 192 and the second bonding terminal 202, thereby realizing the independent transmission of the display driving signal and the power acquisition signal in the bonding area B.

[0035] Through the above structure, the signal terminals originally located in the lower bezel area of ​​the display panel and connected to the first conductive part 191, and the electrode leads connected to the second conductive part 192 and the third conductive part 203, are all led to the bonding area B on the back of the substrate 10 through the first conductive layer 19 and the second conductive layer 20. Therefore, in subsequent module processes, the flip-chip film or flexible circuit board can directly achieve electrical connection with each bonding terminal in the bonding area B from the back of the array substrate, eliminating the need for the connection terminal bending process. As a result, there is no bending area for the connection terminals around the display panel, eliminating the lower bezel limitation caused by the bending radius of the connection terminals, thereby achieving the technical effect of extremely narrow bezels or even bezel-less. In addition, the electrical connection between the first conductive layer 19 and the second conductive layer 20 adopts a via connection method. Compared with existing array substrates, this avoids the damage or even breakage of the traces due to bending stress when the traces are bent, thus improving the reliability of the display product.

[0036] This embodiment achieves independent aggregation of display driving signals and solar cell output signals within the bonding area B by setting a first conductive layer 19 between the substrate 10 and the thin-film transistor layer 13, and leading the display signal lines and solar cell signal lines to corresponding bonding terminals in the bonding area B through the first conductive part 191, the second conductive part 192, and the third conductive part 193, respectively. Simultaneously, by setting the bonding area B on the side of the substrate 10 away from the thin-film transistor layer 13 (i.e., the back side), external circuits can be directly connected to the bonding terminals from the back side, eliminating the need for any wiring or bonding operations in the front bezel area of ​​the display panel. This significantly reduces the width of the bottom bezel, providing a structural basis for achieving near-bezel-less display products. Furthermore, this design eliminates the need for traditional bending processes, simplifies module assembly, and improves production efficiency and product yield.

[0037] Further, please refer to Figure 2 and Figure 3As shown, the first electrode 1611 of the solar cell 16 is co-layered with the first electrode 1311 and the second electrode 1312 of the thin-film transistor 131. That is, the first electrode 1611, the first electrode 1311, and the second electrode 1312 can be formed in the same film layer using the same patterning process, thus eliminating the need for additional masks and photolithography processes. Simultaneously, the surface of the second electrode 1613 near the substrate 10 is flush with the surface of the pixel electrode 141 near the substrate 10, which helps ensure the flatness and density of the film layer in subsequent encapsulation processes. Furthermore, both can be completed simultaneously in the same photolithography or evaporation process, simplifying the manufacturing process. This embodiment significantly simplifies the manufacturing process by co-layering the first electrode 1611 with the first electrode 1311 and the second electrode 1312 of the thin-film transistor 131, reducing the number of masks and lowering manufacturing costs. At the same time, the second electrode 1613 and the pixel electrode 141 are fabricated in the same process and are flush with each other, which helps improve the uniformity of the subsequent encapsulation layer coverage and enhances the long-term reliability of the device.

[0038] Preferably, the first electrode 1611 is made of the same material as the first electrode 1311 and the second electrode 1312 of the thin-film transistor 131. For example, the first electrode 1311 and the second electrode 1312 can be formed using a single-layer or stacked structure (e.g., Ti / Al / Ti stack) of one or more of molybdenum, aluminum, and titanium, and the first electrode 1611 also uses this stacked structure. The second electrode 1613 is made of the same material as the pixel electrode 141, for example, it can be made of a transparent conductive stacked structure of ITO / Ag. The Ag layer located on the side of the ITO electrode (second electrode) away from the substrate 10 can serve not only as the top electrode of the solar cell 16, but also as a metal trace on the second electrode 1613 of the solar cell 16. Specifically, in the solar cell 16, the second electrode 1613, as the top electrode, needs to balance light transmittance and conductivity, and the conductivity of the ITO thin film alone is limited. This application significantly enhances the overall conductivity of the top electrode of the solar cell 16 by reusing the Ag layer in the second electrode 1613 as an additional metal trace, thus superimposing a low-resistance metal mesh or continuous thin film on top of the ITO layer. When the solar cell 16 generates photogenerated carriers under illumination, the Ag layer can quickly collect and transport the current from the generation location to the second conductive part 192 and the third conductive part 193 with lower resistance, and then lead it out to the bonding region B via the second conductive layer 20. This design effectively reduces the series resistance of the solar cell 16, reduces Joule heat loss during current transmission, improves the collection efficiency of photogenerated carriers, and ultimately achieves a significant improvement in the photoelectric conversion efficiency of the solar cell 16.

[0039] This embodiment uses the same material for the first electrode 1611 as the first electrode 1311 and the second electrode 1312, and the same material for the second electrode 1613 as the pixel electrode 141. This ensures electrical matching between the electrode layers and reduces contact resistance. Furthermore, it achieves material reuse, reducing the types of vapor deposition or sputtering targets and lowering material costs. Simultaneously, the second electrode 1613 reuses the Ag layer in the ITO / Ag stacked structure as a metal trace, stacking a low-resistance Ag conductive layer on top of the ITO transparent electrode. This effectively improves the conductivity of the top electrode of the solar cell 16, reduces resistance loss in the current transmission path, and increases the collection efficiency of photogenerated carriers, thereby significantly enhancing the photoelectric conversion performance of the solar cell 16. Moreover, this reuse design eliminates the need for additional masks and photolithography processes, further reducing manufacturing costs while improving performance.

[0040] Please refer to Figure 4As shown, in this embodiment, multiple solar cell units 161 are arranged along the second direction Y to form a first solar cell unit column. In the first solar cell unit column, at least one pixel electrode 141 is disposed between two adjacent solar cell units 161. At least one solar cell unit 161 is arranged along the second direction Y to form a second solar cell unit column. The first solar cell unit column and the second solar cell unit column are arranged alternately in a first direction X perpendicular to the second direction Y. Specifically, multiple solar cell units 161 are arranged along the second direction Y to form the first solar cell unit column. Along the second direction Y, at least one pixel electrode 141 is disposed between two adjacent solar cell units 161. That is, in the same column, the solar cell units 161 are not arranged continuously, but are alternately and intermittently disposed with the pixel electrodes 141, and at least one pixel electrode 141 is inserted between every two solar cell units 161. Exemplarily, two, three or more pixel electrodes 141 can be disposed between two adjacent solar cell units 161, and the specific number can be designed according to the resolution requirements of the display panel and the power requirements of the solar cells 16. By adjusting the number of pixel electrodes 141 between solar cell units 161, different balance points can be achieved between display performance and light harvesting capability. When a higher display resolution or aperture ratio is required, the number of pixel electrodes 141 between adjacent solar cell units 161 can be increased to reduce the occupation of the display area by the solar cells 16; when a stronger light harvesting capability is required, the number of pixel electrodes 141 between adjacent solar cell units 161 can be reduced to increase the distribution density of the solar cells 16. Simultaneously, at least one solar cell unit 161 is arranged along the second direction Y to form a second solar cell unit column. The first solar cell unit column and the second solar cell unit column are arranged alternately in the first direction X, which is perpendicular to the second direction Y. In other words, in the planar layout of the array substrate, the solar cell units 161 are distributed in a discrete and spaced pattern throughout the display area. Through this arrangement, the solar cell units 161 are neither overly concentrated, affecting the pixel aperture ratio, nor too sparse, resulting in insufficient light harvesting capability. The pixel electrode 141 disposed between two adjacent solar cell units 161 can ensure that the pixel density of the display area does not decrease due to the introduction of solar cells 16. At the same time, the alternating arrangement of the first solar cell unit column and the second solar cell unit column in the first direction X enables the solar cells 16 to achieve uniform coverage throughout the entire display area, which is beneficial to obtain a relatively stable photoelectric conversion output under different illumination angles.

[0041] By arranging multiple solar cell units 161 along the second direction Y to form a first solar cell unit column, and setting at least one pixel electrode 141 between two adjacent solar cell units 161, the adverse effects of the continuous dense arrangement of solar cell units 161 on the display aperture ratio are effectively avoided, ensuring the luminous brightness and display quality of the display product. At the same time, the first solar cell unit column and the second solar cell unit column are arranged alternately in the first direction X, so that the solar cells 16 are uniformly distributed in the display area, which is conducive to improving the spatial uniformity of light energy collection and avoiding excessive fluctuations in charging current due to local illumination differences.

[0042] Please see Figure 3 and Figure 5 In this embodiment, the first conductive layer 19 includes a first bonding terminal group 201', a second bonding terminal group 202', and a third bonding terminal group 203'. The first bonding terminal group 201' includes a plurality of first bonding terminals 201, the second bonding terminal group 202' includes a plurality of second bonding terminals 202, and the third bonding terminal group 203' includes a plurality of third bonding terminals 203. Along the first direction X (the width direction of the bonding region B), the first bonding terminal group 201' is located between the second bonding terminal group 202' and the third bonding terminal group 203'. That is, the plurality of first bonding terminals 201 used for transmitting display drive signals are concentrated in the central region of the bonding region B, while the plurality of second bonding terminals 202 used for transmitting positive electrode signals of the solar cell 16 and the plurality of third bonding terminals 203 used for transmitting negative electrode signals are respectively arranged on both sides of the first bonding terminal group 201'.

[0043] By arranging the display signal terminal group in the center of the bonding area B and the solar cell signal terminal group on both sides, it is beneficial to achieve partition alignment during subsequent bonding of flip-chip films or flexible circuit boards, reducing the risk of signal crosstalk in the bonding process. At the same time, placing the solar cell terminals on both sides also makes it easier to bring out the positive and negative electrodes separately in the subsequent module process, simplifying the design of the external circuit.

[0044] In one specific embodiment, the total number of second bonding terminals 202 and third bonding terminals 203 is set to 10, wherein there are 5 second bonding terminals 202, which are used to transmit the positive electrode signal of the solar cell 16, and 5 third bonding terminals 203, which are used to transmit the negative electrode signal of the solar cell 16. Along the first direction X, the second bonding terminal group 202' consisting of 5 second bonding terminals 202 and the third bonding terminal group 203' consisting of 5 third bonding terminals 203 are respectively arranged at the leftmost and rightmost positions in the bonding area B, that is, the second bonding terminals 202 are concentrated in one edge area of ​​the bonding area B, and the third bonding terminals 203 are concentrated in the other edge area of ​​the bonding area B, while the first bonding terminal group 201' is located between the second bonding terminal group 202' and the third bonding terminal group 203'. The width of each bonding terminal can be designed according to the maximum output power achievable by the solar cell 16. In this embodiment, the width of the second bonding terminal 202 and the third bonding terminal 203 ranges from 10 µm to 300 µm. For example, it can be 50 µm, 100 µm, 150 µm, 200 µm, or 250 µm, but this embodiment does not impose specific limitations on this. The specific values ​​depend on the power requirements of the solar cell 16. For example, when a large photocurrent needs to be transmitted, a larger terminal width can be selected to reduce contact resistance and transmission loss.

[0045] Please refer to Figure 6 The array substrate further includes a third conductive layer 21, which includes a plurality of fourth conductive portions 211. The fourth conductive portions 211 are disposed on the same layer as the first electrode 1311 of the thin-film transistor 131. The first electrode 1311 of the thin-film transistor 131 and the fourth conductive portions 211 are electrically connected. The fourth conductive portions 211 are electrically connected to the first conductive portion 191 through at least one via 212. In this embodiment, the fourth conductive portions 211 and the first electrode 1311 of the thin-film transistor 131 are disposed on the same layer, that is, the fourth conductive portions 211 can be patterned using the same material as the first electrode 1311, which helps to reduce the difficulty of the manufacturing process and improve the production efficiency of the display panel. Of course, in order to reduce the impedance of the fourth conductive portions 211, a material with lower impedance than the material used for the first electrode 1311 can also be used for patterning, but this embodiment does not impose specific limitations on this.

[0046] The fourth conductive part 211 is electrically connected to the first conductive part 191, so that the voltage signal on the first conductive part 191 can be transmitted to the fourth conductive part 211 through the via 212. The impedance relationship between the materials used in the first conductive part 191 and the fourth conductive part 211 and the number of vias 212 can be set according to actual needs, as long as the voltage difference between the thin film transistors 131 can be reduced. This embodiment does not impose specific restrictions on this, so that the display panel has better uniformity when displaying images.

[0047] Optional, please continue to refer to Figure 6 As shown, the width of the first conductive portion 191 is greater than the width of the fourth conductive portion 211. Since the circuit arrangement of the film layer containing the fourth conductive portion 211 is relatively dense, to prevent coupling effects between the circuits, the fourth conductive portion 211 must be made thinner, i.e., narrower in width. However, this results in a higher impedance for the fourth conductive portion 211. By electrically connecting the fourth conductive portion 211 to the wider first conductive portion 191, it is beneficial to reduce the voltage difference transmitted to each thin-film transistor 131. To further reduce this voltage difference, the number of vias 212 can be increased, thereby further improving the uniformity of the display panel image. The material used for the first conductive portion 191 can be the same as or different from the material used for the fourth conductive portion 211; this embodiment does not impose specific limitations on this.

[0048] Please refer to Figure 8 , Figure 8 This is a cross-sectional schematic diagram of a solar cell provided in an embodiment of this application. Specifically, the solar cell 16 further includes a conductive structure 23. In the solar cell unit 161, the first electrode 1611 of one solar cell unit 161 is electrically connected to the second electrode 1613 of at least one adjacent solar cell unit 161 via the conductive structure 23. This connection method allows multiple solar cell units 161 to be connected in series. Series connection can increase the overall output voltage, making it suitable for display products that require higher driving voltages.

[0049] Understandably, multiple solar cell units 161 can also be connected in parallel (i.e., all first electrodes 1611 are connected together, and all second electrodes 1613 are connected together). Parallel connection can increase the overall output current. Designers can choose series, parallel, or a combination of series and parallel connection methods based on the power consumption characteristics of the display product and the lighting conditions of the operating environment.

[0050] The conductive structure 23 can be specifically one of a conductive via, a conductive metal line, or a conductive metal layer. Specifically, the conductive structure 23 can be formed using the same material as the first electrode 1611 or the second electrode 1613, or it can be a separate metal overlap structure.

[0051] In some embodiments of this application, the solar cell 16 further includes a barrier layer 1614. For example... Figure 9 As shown, a barrier layer 1614 is provided on at least a portion of the surface of the solar cell unit 161 and the second electrode 1613 away from the substrate 10. The barrier layer 1614 can be formed using inorganic insulating materials (such as silicon oxide or silicon nitride) or organic insulating materials (such as photoresist or polyimide). This barrier layer 1614 covers the sidewall of the solar cell unit 161, effectively preventing the photoelectric conversion film 1612 from being eroded by water and oxygen or laterally penetrated by etching solutions in subsequent processes. Simultaneously, the barrier layer 1614 covers at least a portion of the surface of the second electrode 1613, protecting the second electrode 1613 from process damage during subsequent processes.

[0052] This embodiment provides a barrier layer 1614 on the sidewall of the solar cell unit 161 and at least part of the surface of the second electrode 1613, which can effectively prevent moisture intrusion from damaging the solar cell 16 and provide physical protection for the solar cell 16 in subsequent processes.

[0053] Please see Figure 7 In this embodiment, the substrate 10 further includes a support layer 22 disposed on the side of the second conductive layer 20 away from the first conductive layer 19. The support layer 22 includes at least one first opening 221, which exposes at least a portion of the second conductive layer 20.

[0054] Specifically, the support layer 22 can be formed of flexible organic materials such as polyimide, serving as a back protective layer for the array substrate and providing support for subsequent laser aperture opening processes. The support layer 22 includes at least one first opening 221, which exposes at least a portion of the second conductive layer 20. This first opening 221 can be formed by a laser etching process and is used to electrically connect external circuits (such as flexible circuit boards or flip-chip films) to the second conductive layer 20 in subsequent bonding processes. With the first opening 221, external circuits can be directly electrically connected from the back of the array substrate to the bonding terminals located in the bonding area B, without needing to bend any flexible circuit boards or flip-chip films to the back, or reserving any bonding space at the front edge of the display panel. Furthermore, by appropriately setting the size of the first opening 221, the support layer 22 also provides good protection for the electrical connection structure between the external circuitry and the second conductive layer 20, which helps improve the effectiveness of the electrical connection structure between the second conductive layer 20 and the external circuitry.

[0055] Based on the same inventive concept, this application also provides a display panel, including the array substrate in any of the above embodiments, and further including a pixel defining layer 24, a light emitting layer 25, an encapsulation layer 26 and a flexible circuit board.

[0056] like Figure 10 As shown, a pixel defining layer 24 is disposed on one side of the array substrate, specifically on the side of the planarization layer 15 and pixel electrode layer 14 away from the substrate 10. The pixel defining layer 24 includes a pixel defining portion 241 and a pixel opening 242 formed by the pixel defining portion 241, the pixel opening 242 exposing a portion of the pixel electrode 141. A light-emitting layer 25 is disposed on the side of the pixel defining layer 24 away from the array substrate. The light-emitting layer 25 includes multiple light-emitting devices, each of which is electrically connected to the second electrode 1312 of the thin-film transistor 131, specifically through the pixel electrode 141. An encapsulation layer 26 is disposed on the side of the light-emitting layer 25 away from the array substrate, used to block water and oxygen corrosion, protecting the light-emitting layer 25 and internal components such as the solar cell 16. A flexible circuit board 27 is disposed on the backlight side of the light-emitting layer 25. The flexible circuit board 27 includes a fourth conductive layer 271, which is electrically connected to the second conductive layer 20, thereby enabling the input of external driving signals and power supplies, and the output of electrical energy from the solar cell 16. After the fourth conductive layer 271 and the second conductive layer 20 are electrically connected, an appropriate amount of insulating adhesive, such as UV adhesive, can be filled into the first opening 221 to provide insulation protection for the electrical connection structure. At the same time, the fourth conductive layer 271 can be better confined within the first opening 221.

[0057] This embodiment integrates the array substrate with the pixel limiting layer 24, the light-emitting layer 25, and the encapsulation layer 26 to form a complete display panel structure, achieving high-resolution display while integrating solar charging functionality. The encapsulation layer 26 simultaneously covers the light-emitting layer 25 and the solar cell 16, providing common water and oxygen protection for both types of functional devices and simplifying the encapsulation process. The flexible circuit board 27 is directly connected to the bonding terminal from the back of the array substrate through the first opening 221, thus eliminating the need for the bending process of the bonding terminal. Consequently, there is no bending area for the bonding terminal around the display panel, eliminating the bottom bezel limitation caused by the bending radius of the bonding terminal. Compared to display panels that bend the bonding area to the back of the display module, the display panel provided in this embodiment saves the width of the bending radius, further reducing the width of the bottom bezel, thereby achieving an extremely narrow bezel or even a bezel-less technical effect. In addition, the electrical connection between the first conductive layer 19 and the second conductive layer 20 adopts a via connection method. Compared with existing display panels, this avoids the damage or even breakage of the wiring due to bending stress when the wiring is bent, improving the reliability of the display product.

[0058] In summary, the array substrate and its display panel provided in this application electrically connect the first conductive portion 191, the second conductive portion 192, and the third conductive portion 193 in the first conductive layer 19 to the first bonding terminal 201, the second bonding terminal 202, and the third bonding terminal 203 in the second conductive layer 20. This allows the display drive signal and the electrical energy signal generated by the solar cell 16 to be led to the bonding area B on the back of the substrate 10 via the first conductive layer 19 and the second conductive layer 20. This, combined with the first opening 221 on the support layer 22, enables direct connection of external circuits such as the flexible circuit board 27 or the flip-chip film from the back. Compared to the prior art where the bonding area is bent to the back of the display panel, this application effectively reduces the width of the bottom bezel of the display panel while integrating display and light energy collection functions, achieving the beneficial effects of an extremely narrow bezel or even a bezel-less design. Furthermore, it avoids damage or even breakage of the wiring due to bending stress during bending, thus improving the reliability of the display product.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: A substrate has a plurality of pixel units disposed on one side of the substrate. In the direction away from the substrate, a thin film transistor, a planarization portion and a pixel electrode are sequentially stacked in the pixel unit. The pixel electrode is electrically connected to the thin film transistor. The thin film transistors in the plurality of pixel units form a thin film transistor layer, the planarization portions in the plurality of pixel units form a planarization layer, and the pixel electrodes in the plurality of pixel units form a pixel electrode layer. The array substrate further includes: a solar cell, which is at least partially disposed within the planarization layer, wherein the orthographic projection of the solar cell does not overlap with the orthographic projection of the pixel electrode layer in a direction perpendicular to the substrate; the solar cell is used to convert a portion of the light illuminating the solar cell into electrical energy; the solar cell includes a plurality of solar cell units, which are spaced apart from the pixel electrode.

2. The array substrate according to claim 1, characterized in that, The substrate has at least one bonding region on the side away from the thin-film transistor layer; the thin-film transistor includes a gate, an active layer, a first electrode, and a second electrode; the solar cell unit includes a first electrode and a second electrode, and a photoelectric conversion thin film is formed between the first electrode and the second electrode; the array substrate further includes: A first conductive layer is disposed between the substrate and the thin film transistor layer. The first conductive layer includes a plurality of conductive portions, including a first conductive portion, a second conductive portion and a third conductive portion. A first electrode is electrically connected to the first conductive portion, the first electrode is electrically connected to the second conductive portion, and the second electrode is electrically connected to the third conductive portion. A second conductive layer is disposed within the bonding area of ​​the substrate. The second conductive layer includes a plurality of bonding terminals, including a first bonding terminal, a second bonding terminal, and a third bonding terminal. The first conductive portion is electrically connected to at least one first bonding terminal, the second conductive portion is electrically connected to at least one second bonding terminal, and the third conductive portion is electrically connected to at least one third bonding terminal.

3. The array substrate according to claim 2, characterized in that, The first electrode is disposed in the same layer as both the first electrode and the second electrode, and the surface of the second electrode near the substrate is flush with the surface of the pixel electrode near the substrate. Preferably, the first electrode is made of the same material as the first electrode and the second electrode, and the second electrode is made of the same material as the pixel electrode.

4. The array substrate according to claim 1, characterized in that, Multiple solar cell units are arranged along a second direction to form a first solar cell unit column, and at least one pixel electrode is provided between two adjacent solar cell units in the first solar cell unit column; At least one of the solar cell units is arranged along the second direction to form a second solar cell unit column; the first solar cell unit column and the second solar cell unit column are arranged alternately in a first direction perpendicular to the second direction.

5. The array substrate according to claim 2, characterized in that, The second conductive layer includes a first bonding terminal group, a second bonding terminal group, and a third bonding terminal group. The first bonding terminal group includes a plurality of first bonding terminals, the second bonding terminal group includes a plurality of second bonding terminals, and the third bonding terminal group includes a plurality of third bonding terminals. The first bonding terminal group is located between the second bonding terminal group and the third bonding terminal group.

6. The array substrate according to claim 2, characterized in that, The array substrate further includes a third conductive layer, which includes a plurality of fourth conductive portions. The fourth conductive portions are disposed on the same layer as the first electrode of the thin film transistor. The first electrode of the thin film transistor and the fourth conductive portions are electrically connected. The fourth conductive portions are electrically connected to the first conductive portions through at least one via. Preferably, the width of the first conductive part is greater than the width of the fourth conductive part.

7. The array substrate according to claim 2, characterized in that, The solar cell further includes a conductive structure in which the first electrode of a portion of the solar cell unit is electrically connected to the second electrode layer of at least one adjacent solar cell unit.

8. The array substrate according to claim 3, characterized in that, A barrier layer is provided on at least a portion of the surface of the solar cell unit and the second electrode away from the substrate.

9. The array substrate according to claim 2, characterized in that, The substrate further includes a support layer disposed on the side of the second conductive layer away from the first conductive layer, the support layer including at least one first opening, the first opening exposing at least a portion of the second conductive layer.

10. A display panel, characterized in that, The array substrate as described in any one of claims 1-9 further comprises: A pixel defining layer is disposed on one side of the array substrate. The pixel defining layer includes a pixel defining portion and a pixel opening formed by the pixel defining portion. The pixel opening exposes a portion of the pixel electrode. A light-emitting layer is disposed on the side of the pixel limiting layer away from the array substrate. The light-emitting layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the second electrode of the thin-film transistor. An encapsulation layer is disposed on the side of the light-emitting layer away from the array substrate; A flexible circuit board is disposed on the backlight side of the light-emitting layer. The flexible circuit board includes a fourth conductive layer, which is electrically connected to the second conductive layer.

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