Package substrate, method of manufacturing the same, and semiconductor package device

Abstract

The application relates to a packaging substrate and a manufacturing method thereof and a semiconductor packaging device. The packaging substrate comprises a plurality of glass core plates which are stacked, two adjacent glass core plates are connected through a conductive column, and an insulating filling layer is arranged between the two adjacent glass core plates; the glass core plate has a first surface and a second surface which are opposite in the stacking direction, and the first surface and / or the second surface of at least one glass core plate is provided with a circuit structure; the glass core plate further comprises a through hole which penetrates the first surface and the second surface and contains a conductive medium. In the packaging substrate, the circuit structure is uniformly distributed on the surface of the glass core plate by adopting the stacked arrangement of the multilayer glass core plate, so that the glass core plate can maintain good dimensional stability at a lower thickness, and the packaging substrate with high wiring density and excellent electrical performance can be obtained.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to packaging substrates and their manufacturing methods, and semiconductor packaging devices. Background Technology

[0002] As the computing power requirements of artificial intelligence chips continue to grow, packaging substrates need to provide higher interconnect density, better thermomechanical stability, and lower high-frequency signal loss.

[0003] Traditional packaging substrate manufacturing processes involve forming circuit structures on organic substrates (such as ABF) and stacking multiple organic substrates on a glass core, using the glass core to mitigate warpage of the organic substrate. To further increase wiring density, the circuit structure area of ​​the organic substrate continues to increase, as does the number of stacked layers. However, this also requires the glass core to have a greater thickness to suppress warpage, and the aspect ratio of the through-glass via (TGV) also increases accordingly, which is detrimental to maintaining good electrical performance of the packaging structure. Summary of the Invention

[0004] Therefore, it is necessary to provide a packaging substrate with high wiring density and excellent electrical performance, a method for manufacturing the same, and a semiconductor packaging device.

[0005] In a first aspect, this application provides a packaging substrate.

[0006] An encapsulation substrate includes a plurality of glass core plates stacked together, with adjacent glass core plates connected by conductive pillars and an insulating filler layer between adjacent glass core plates;

[0007] The glass core plate has a first surface and a second surface opposite each other in the stacking direction, and at least one of the first surface and / or the second surface of the glass core plate has a circuit structure; the glass core plate also includes a through hole penetrating the first surface and the second surface, and the through hole contains a conductive medium.

[0008] In some embodiments, the aspect ratio of the glass core plate is (0.5~10):1; the thickness of the glass core plate is 20µm~500µm.

[0009] In some embodiments, the insulating filler layer is made of a resin material;

[0010] And / or, the material of the conductive pillar includes copper;

[0011] And / or the material of the conductive medium includes copper.

[0012] In some embodiments, the upper and lower surfaces of the packaging substrate are solder resisted and surface treated in the stacking direction.

[0013] In a second aspect, this application provides a method for manufacturing the aforementioned packaging substrate.

[0014] A method for manufacturing the above-mentioned packaging substrate includes the following steps:

[0015] Multiple glass substrates are obtained, through holes are made on the surface of the glass substrates, and circuit structures are formed on the first surface and / or the second surface of the glass substrates to form multiple glass core boards;

[0016] The conductive medium is filled into the through holes, and metal pillars for interconnection are formed at preset positions of each glass core plate. Multiple glass core plates are stacked up and down, so that two metal pillars at corresponding positions on adjacent glass core plates are connected to each other. The two connected metal pillars are bonded to a connected conductive pillar by chemical deposition to obtain the matrix structure.

[0017] An insulating filler layer is prepared between the two glass core plates connected to the substrate structure to form the encapsulation substrate.

[0018] In some embodiments, the metal pillar comprises a convex metal pillar, at least a portion of the surface of which is deposited with an activation layer, the activation layer comprising one or more of palladium, nickel, silver, and platinum.

[0019] In some embodiments, after multiple glass core plates are stacked one on top of the other, the distance between the top ends of two adjacent convex metal pillars is less than or equal to 10 μm.

[0020] In some embodiments, the chemical deposition step includes:

[0021] The stacked glass core plates are immersed in copper molten liquid and reacted at 25°C to 50°C for 10 to 120 minutes.

[0022] In some embodiments, the chemical deposition step includes:

[0023] The stacked glass core plates are immersed in nickel melt and reacted at 75°C to 90°C for 10 to 50 minutes.

[0024] In a third aspect, this application provides a semiconductor packaging device.

[0025] A semiconductor packaging device includes the packaging substrate described above or the packaging substrate manufactured by the method described above.

[0026] This application provides a packaging substrate that employs a multilayer glass core plate stack and routes the circuit structure onto the surface of the glass core plate. This allows the glass core plate to maintain good dimensional stability at a relatively low thickness, resulting in a packaging substrate with high wiring density and excellent electrical performance. The multilayer glass core plate stack provides high-density wiring space, conductive pillars enable interlayer electrical connectivity, and vias in the glass core plate, filled with conductive dielectric, provide vertical conductive paths within the substrate. The insulating filler layer provides support and stress buffering for the stacked structure. Through this structural design, the packaging substrate can form an all-glass substrate structure. This not only leverages the low thermal expansion coefficient and low dielectric constant of the glass core plate to achieve excellent structural stability and electrical performance, but also helps reduce the difficulty of processing vias on single-layer glass core plates and improves the filling quality of the conductive dielectric, further enhancing the electrical transmission performance of the packaging substrate. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart of a method for preparing a packaging substrate according to one embodiment of this application.

[0029] Figure 2 This is a flowchart of a method for preparing a packaging substrate according to another embodiment of this application.

[0030] Figure 3 This is a schematic diagram of the packaging substrate in one embodiment of this application.

[0031] Figure 4 This is a partial schematic diagram of the stacked glass core boards according to one embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100. Glass core board; 101. Convex metal pillar; 102. Through hole; 103. Circuit structure; 104. Insulating filling layer; 105. Conductive pillar. Detailed Implementation

[0034] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0035] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In this application, "at least one" means one or more, such as one, two, or more than two. "Multiple" or "several" means at least two, such as two, three, etc.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.

[0038] Unless otherwise specified, all steps in this application may be performed sequentially or randomly. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the method may also include step (c), indicating that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0039] In this application, "above" or "below" includes the number itself. For example, "below 1" includes 1.

[0040] Unless otherwise specified, the temperature parameters in this application are permitted to be either constant-temperature treatment or variations within a certain temperature range. It should be understood that the constant-temperature treatment allows temperature fluctuations within the precision range of the instrument control, such as ±5℃, ±4℃, ±3℃, ±2℃, or ±1℃.

[0041] The first aspect of this application provides a packaging substrate capable of having high wiring density and excellent electrical performance.

[0042] For example, please see Figure 1 and 2 , Figure 1 and 2 This is a schematic diagram of the structure of the encapsulation substrate according to one embodiment of this application. The encapsulation substrate includes a plurality of glass core plates 100 stacked together, adjacent glass core plates 100 are connected by conductive pillars 105, and an insulating filler layer 104 is provided between adjacent glass core plates 100.

[0043] The glass core board 100 has a first surface and a second surface opposite each other in the stacking direction. The first surface and / or the second surface of the glass core board 100 have a circuit structure 103. It is understood that at least one circuit structure 103 exists in the glass core board 100.

[0044] The glass core plate 100 also includes a through hole 102 penetrating the first and second surfaces, the through hole 102 containing a conductive medium. It is understood that the stacked glass core plates 100 can achieve vertical electrical conduction through the direct or indirect connection between the conductive post 105 and the through hole 102.

[0045] In this embodiment, by employing a multilayer glass core board 100 stacked and wiring the circuit structure 103 onto the surface of the glass core board 100, the glass core board 100 can maintain good dimensional stability at a relatively low thickness, resulting in a packaging substrate with high wiring density and excellent electrical performance. The multilayer glass core board 100 stacking provides high-density wiring space, the conductive pillars 105 achieve interlayer electrical connectivity, the through-holes 102 in the glass core board 100, filled with conductive dielectric, provide vertical conductive paths within the substrate, and the insulating filler layer 104 provides support and stress buffering for the stacked structure. Through this structural design, the packaging substrate can form an all-glass substrate structure. This not only leverages the low thermal expansion coefficient and low dielectric constant of the glass core board 100 to achieve excellent structural stability and electrical performance, but also helps reduce the processing difficulty of the through-holes 102 on a single-layer glass core board 100 and improves the filling quality of the conductive dielectric, further enhancing the electrical transmission performance of the packaging substrate.

[0046] In some embodiments, both the first and second surfaces of the glass core board 100 have circuit structures 103. Designing circuit structures 103 on both the first and second surfaces of the glass core board 100 helps achieve higher wiring density on a limited substrate area. Furthermore, it allows for a more symmetrical packaging structure, thereby alleviating unilateral stress and reducing warpage.

[0047] In some embodiments, the first and second surfaces of the glass core plate 100 in the encapsulation substrate both have circuit structures 103.

[0048] In some embodiments, the thickness of the glass core plate 100 is 20µm to 500µm. Optionally, the thickness of the glass core plate 100 can be, but is not limited to, 20µm, 50µm, 100µm, 150µm, 200µm, 300µm, 400µm, 500µm, or other values ​​within the range of 20µm to 500µm.

[0049] In some embodiments, the thickness-to-diameter ratio of the glass core plate 100 is (0.5~10):1. Optionally, the thickness-to-diameter ratio of the glass core plate 100 can be, but is not limited to, 0.5:1, 1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, or other values ​​within the range of (0.5~10):1. Maintaining a lower thickness-to-diameter ratio of the through holes 102 in the glass core plate 100 is more conducive to improving the filling quality of the conductive medium. This application can use the thin-layer glass core plate 100 as a support structure, and with comparable hole diameters, a smaller thickness-to-diameter ratio can be maintained, thereby obtaining a high-quality filling effect.

[0050] In some embodiments, the via 102 is completely filled with a conductive medium, and the conductive post 105 is connected to the conductive medium. The conductive post 105 and the conductive medium form a continuous conductive path in the vertical direction, providing a more stable and reliable conductive cross-section, which helps reduce the resistance of vertical interconnects and plays an important role in maintaining efficient signal transmission in multilayer stacked package structures.

[0051] In some embodiments, the insulating filler layer 104 is made of a resin material. The resin material can provide stress buffering for the glass core 100, helping to improve the reliability of the encapsulation structure. Optionally, the resin material is selected from epoxy molding compound, polyimide resin, and epoxy / polyimide-based resin. The epoxy molding compound is an EMC plastic resin, and the epoxy / polyimide-based resin is ABF resin.

[0052] In some embodiments, the material of the conductive post 105 includes copper.

[0053] In some of these embodiments, the conductive medium is made of copper.

[0054] In some embodiments, the upper and lower surfaces of the packaging substrate are treated with solder resist and surface finish in the stacking direction. The upper and lower surfaces of the packaging substrate are the surfaces of the two outermost glass cores 100 in the stacking direction that are furthest from the other glass cores 100. Solder resist and surface finish treatment on the upper and lower surfaces of the outermost glass cores 100 of the packaging substrate helps protect the circuit structure 103 and improves solderability. The solder resist layer can selectively cover the copper traces on the substrate surface, preventing bridging and short circuits in subsequent soldering processes. Surface finish treatments, such as OSP, electroless nickel-palladium-gold (ENEPIG), electroless silver, and electroless tin treatments, are performed on the exposed pad areas. Electroless nickel-palladium-gold (ENEPIG) treatment is preferred, as the nickel layer acts as a barrier layer to prevent copper migration, the palladium layer effectively avoids the black nickel defect common in conventional immersion gold processes, and the gold layer provides good solderability and oxidation protection, further contributing to high-density packaging of the packaging substrate.

[0055] In a second aspect, this application provides a method for manufacturing the aforementioned packaging substrate.

[0056] For example, please see Figure 3 , Figure 3 This is a flowchart illustrating a method for fabricating a packaging substrate according to an embodiment of this application. The method for fabricating the packaging substrate includes the following steps:

[0057] S1. Obtain multiple glass substrates, make through holes 102 on the surface of the glass substrates, and form circuit structures 103 on the first and / or second surfaces of the glass substrates to form multiple glass core boards 100.

[0058] S2. Fill the through hole 102 with a conductive medium, form metal pillars for interconnection at preset positions of each glass core plate 100, stack multiple glass core plates 100 one on top of the other, so that two metal pillars at corresponding positions on adjacent glass core plates 100 are connected to each other, and the two connected metal pillars are bonded to a connected conductive pillar 105 by chemical deposition to obtain the substrate structure.

[0059] S3. An insulating filling layer 104 is prepared between two glass core plates 100 connected in the substrate structure to form an encapsulation substrate.

[0060] In some embodiments, through holes 102 are formed on the surface of the glass substrate, and circuit structures 103 are formed on the first and second surfaces of the glass substrate to form a glass core board 100.

[0061] A conductive medium is filled into the through holes 102 of the glass core plate 100, and metal pillars for interconnection are formed at preset positions of each glass core plate 100. Multiple glass core plates 100 are stacked one on top of the other, so that two metal pillars at corresponding positions on adjacent glass core plates 100 are connected to each other. The two connected metal pillars are bonded to a connected conductive pillar 105 by chemical deposition to obtain the matrix structure.

[0062] An insulating filling layer 104 is prepared between two adjacent glass core plates 100 in the substrate structure to form an encapsulation substrate.

[0063] Please see Figure 4 , Figure 4 This is a partial schematic diagram of the stacked glass core plates 100 according to one embodiment of this application. In some embodiments, the metal pillars include convex metal pillars 101, the cylindrical surfaces of which are connected to the glass core plates 100. The convex metal pillar 101 has a metal column and a convex structure located at the end of the metal column, wherein the convex metal pillar 101 is connected to the glass core plates 100 through the metal column.

[0064] In this embodiment, the convex structure of the convex metal pillar 101 has a non-planar extended curved surface structure. On the one hand, the convex structure of the convex metal pillar 101 can provide alignment guidance, and the convex bevel can compensate for horizontal offset within a certain range, reducing the accuracy requirements for interconnect alignment. On the other hand, research has found that when the conductive pillar 105 is formed based on chemical deposition, during the reaction process, the curved surface of the convex metal pillar 101 helps guide the gas generated by the reaction to be discharged outward, which can effectively prevent bubbles from clogging between the two metal pillars. The resulting conductive pillar 105 has low porosity and high connection strength, and superior electrical performance.

[0065] In some embodiments, the convex metal pillar 101 has a convex structure.

[0066] In some embodiments, the cross-sectional area of ​​the convex structure of the convex metal column 101 gradually decreases.

[0067] In some embodiments, the convex structure of the convex metal column 101 is conical.

[0068] In some embodiments, the glass substrate comprises borosilicate glass.

[0069] In some embodiments, at least a portion of the surface of the metal pillar is deposited with an activation layer, which includes one or more of palladium, nickel, silver, and platinum. Pre-depositing catalytically active metal particles such as palladium, nickel, silver, or platinum on the surface of the metal pillar allows metal ions in the plating bath to be preferentially reduced and deposited in the activation region, ensuring that the conductive pillar 105 grows only in the predetermined metal pillar alignment region. This avoids unwanted metal deposition on the surface of the glass core plate 100, thereby improving the forming accuracy of the substrate structure.

[0070] During chemical deposition, the spacing between the metal pillars of adjacent glass core plates 100 significantly impacts the performance of the formed conductive pillars 105. Excessive spacing increases the time required for complete bridging during chemical deposition, potentially leading to irregular morphologies or even voids during lateral metal growth. Conversely, insufficient spacing places higher demands on substrate flatness and stacking alignment accuracy, reducing process yield. Please refer to [link to relevant documentation]. Figure 2 After stacking the glass core plates 100, the distance between the top ends of the two adjacent convex metal pillars 101 is d. In some embodiments, the distance between the top ends of the two adjacent convex metal pillars 101 after stacking the glass core plates 100 is less than or equal to 10 μm. Studies have shown that, thanks to the presence of the convex structure, a higher fault tolerance space can be obtained when forming the conductive pillars 105 using the above scheme. Even when the top end distance is about 10 μm, a good chemical deposition effect can still be achieved. Furthermore, the resulting conductive pillars 105 have fewer internal voids, higher structural strength, and excellent electrical properties, and are less prone to problems such as detachment and delamination.

[0071] In some embodiments, the steps of the chemical deposition method include:

[0072] The stacked glass core plate 100 is immersed in copper melting solution and reacted at 25℃~50℃ for 10min~120min.

[0073] In other embodiments, the stacked glass core plate 100 is immersed in molten nickel and reacted at 75°C to 90°C for 10 to 50 minutes. Maintaining the above reaction conditions provides mild growth conditions, which helps to improve the density of the conductive pillar 105.

[0074] In some embodiments, the insulating filler layer 104 is prepared using a resin material in a non-cured state.

[0075] In some embodiments, the preparation of the insulating filler layer 104 includes the following steps:

[0076] Resin slurry is injected under vacuum to fill the gap between two adjacent glass core plates 100, and cross-linked and cured at 130℃~280℃ to form an insulating filling layer 104.

[0077] In a third aspect, this application provides a semiconductor packaging device.

[0078] A semiconductor packaging device includes the packaging substrate described above or the packaging substrate manufactured by the method described above.

[0079] The present application will be further described in detail below with reference to specific embodiments.

[0080] Unless otherwise specified, the raw materials used in the following specific embodiments and comparative examples are all commercially available products; the instruments used are all commercially available products; and the processes used are all conventionally selected by those skilled in the art unless otherwise specified.

[0081] Example 1

[0082] This embodiment provides a packaging substrate, the structure of which is shown below. Figure 1 .

[0083] The method for preparing the packaging substrate is as follows:

[0084] S1. Select two glass substrates of the same size with a thickness of 0.46 mm. Use laser-induced etching to create through holes 102 with a diameter of 80 µm on the surface of the glass substrates. Fill the through holes 102 by vacuum sputtering and electroplating to make the two sides electrically conductive. Form circuit patterns A and B on the first and second surfaces of one glass substrate, respectively, and form circuit patterns C and D on the first and second surfaces of the other glass substrate, respectively, thereby forming two glass core boards 100. The surfaces where circuit patterns A and D are located are the outermost surfaces and the pads are kept flat and coplanar.

[0085] S2. Convex metal pillars 101 are formed at the preset connection points on the B and C surfaces of the circuit pattern to be bonded. A palladium activation layer is plated on the convex metal pillars 101. The B and C surfaces of the circuit patterns of two glass core boards 100 are stacked opposite each other, so that the two convex metal pillars 101 to be bonded at corresponding positions are connected. The top spacing is controlled to be within 10μm. Copper is deposited for 120min at 36℃ using Dongshuo Technology EC-2 plating solution, so that the convex metal pillars 101 at corresponding positions grow into connected conductive pillars 105, forming a substrate structure.

[0086] S3. In the substrate structure, epoxy molding compound is filled between two adjacent glass core plates 100 (between layers B and C) and cured to obtain an insulating filling layer 104. The circuit patterns on the outermost A and D sides are subjected to solder resist treatment and organic solderable protective film surface treatment (OSP) to obtain the encapsulation substrate.

[0087] Example 2

[0088] This embodiment provides a packaging substrate, the structure of which is shown below. Figure 2 .

[0089] The method for preparing the packaging substrate is as follows:

[0090] S1. Select three glass substrates of the same size with a thickness of 0.3 mm. Use laser-induced etching to create through holes 102 with a diameter of 60 µm on the surface of the glass substrates. Fill the through holes 102 by vacuum sputtering and electroplating to make the two sides electrically conductive. Form circuit patterns A, B, C, D, E and F sequentially on the first and second surfaces of the three glass substrates to form three glass core boards 100. The surfaces where circuit patterns A and F are located are the outermost surfaces and the pads are kept flat and coplanar.

[0091] S2. Convex metal pillars 101 are formed at the preset connection points on the B and C surfaces and the D and E surfaces of the circuit pattern. A nickel activation layer is plated on the convex metal pillars 101. Three glass core boards 100 are stacked so that the B and C surfaces of the circuit pattern are opposite each other and the D and E surfaces of the circuit pattern are opposite each other. The two convex metal pillars 101 to be bonded at corresponding positions are connected. The top spacing is controlled to be within 4μm. Nickel is deposited for 20 minutes at 80℃ using Dongshuo Technology 5183 nickel bath, so that the convex metal pillars 101 at corresponding positions grow into connected conductive pillars 105, forming a substrate structure.

[0092] S3. Polyimide paste is filled and cured between two adjacent glass core plates 100 in the substrate structure (between layers B and C and between layers D and E) to obtain an insulating filling layer 104. The circuit patterns on the outermost A and F surfaces are subjected to solder resist treatment and electroless nickel-palladium-gold surface treatment (ENEPIG) to obtain the encapsulation substrate.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this invention patent should be determined by the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A packaging substrate, characterized in that, It includes multiple glass core plates stacked together, with adjacent glass core plates connected by conductive pillars and an insulating filler layer between adjacent glass core plates; The glass core plate has opposing first and second surfaces in the stacking direction, and at least one of the first and / or second surfaces of the glass core plate has a circuit structure; the glass core plate further includes a through hole penetrating the first and second surfaces, and the through hole contains a conductive medium.

2. The packaging substrate according to claim 1, characterized in that, The thickness-to-diameter ratio of the glass core plate is (0.5~10):1; the thickness of the glass core plate is 20µm~500µm.

3. The packaging substrate according to claim 1, characterized in that, The insulating filler layer is made of resin material; and / or The material of the conductive pillar includes copper; and / or The material of the conductive medium includes copper.

4. The packaging substrate according to any one of claims 1 to 3, characterized in that, In the stacking direction, the upper and lower surfaces of the packaging substrate are treated with solder resist and surface treatment.

5. A method for manufacturing a packaging substrate according to any one of claims 1 to 4, characterized in that, Includes the following steps: Multiple glass substrates are obtained, through holes are made on the surface of the glass substrates, and circuit structures are formed on the first surface and / or the second surface of the glass substrates to form multiple glass core boards. The conductive medium is filled into the through holes, and metal pillars for interconnection are formed at preset positions of each glass core plate. Multiple glass core plates are stacked up and down, so that two metal pillars at corresponding positions on adjacent glass core plates are connected to each other. The two connected metal pillars are bonded to a connected conductive pillar by chemical deposition to obtain the matrix structure. An insulating filler layer is prepared between the two glass core plates connected to the substrate structure to form the encapsulation substrate.

6. The method for manufacturing a packaging substrate according to claim 5, characterized in that, The metal pillar includes a convex metal pillar, and at least a portion of the surface of the convex metal pillar is deposited with an activation layer, the activation layer including one or more of palladium, nickel, silver and platinum.

7. The method for manufacturing a packaging substrate according to claim 6, characterized in that, After multiple glass core plates are stacked one on top of the other, the distance between the top ends of two convex metal pillars that are in contact with each other is less than or equal to 10 μm.

8. The method for manufacturing a packaging substrate according to any one of claims 5 to 7, characterized in that, The chemical deposition steps include: The stacked glass core plates are immersed in copper molten liquid and reacted at 25°C to 50°C for 10 to 120 minutes.

9. The method for manufacturing a packaging substrate according to any one of claims 5 to 7, characterized in that, The chemical deposition steps include: The stacked glass core plates are immersed in nickel melt and reacted at 75°C to 90°C for 10 to 50 minutes.

10. A semiconductor packaged device, characterized in that, The packaging substrate includes the packaging substrate as described in any one of claims 1 to 4 or the packaging substrate as described in any one of claims 5 to 9, and is manufactured by the same method.

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