Semiconductor package

Abstract

A semiconductor package is provided, comprising: a package substrate; a plurality of chip modules stacked in a stepped structure on the package substrate in a first direction substantially perpendicular to the front surface of the package substrate; a capping layer surrounding the plurality of chip modules; and a plurality of interconnect modules extending in the first direction on the rear surface of the plurality of chip modules by penetrating the capping layer and configured to electrically connect the package substrate to at least one of the plurality of chip modules, wherein each of the plurality of interconnect modules includes an interconnect molding film surrounded by the capping layer and a plurality of interconnect pillars penetrating the interconnect molding film, and wherein the plurality of chip modules includes a plurality of chips stacked in a stepped structure.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0023012, filed with the Korean Intellectual Property Office on February 21, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiment relates to a semiconductor package. Background Technology

[0003] Due to advancements in the electronics industry, the demand for high functionality, high speed, and miniaturization of electronic components is increasing. To respond to this trend, methods can be employed such as stacking multiple semiconductor chips and mounting them within a single package wiring structure, or stacking packages on top of each other. For example, layered package (PIP) or pile-up package (POP) semiconductor packages can be used.

[0004] Meanwhile, with the increasing integration of semiconductor packaging, a vertical wiring structure has been adopted in which semiconductor chips are stacked vertically and electrically connected. Summary of the Invention

[0005] Various aspects of this disclosure provide a semiconductor package capable of stacking semiconductor chips in a high-level hierarchy.

[0006] Various aspects of this disclosure provide a semiconductor package comprising pillars modularized according to various stacking numbers.

[0007] The technical objectives of this disclosure are not limited to those described above, and other undescribed technical objectives can be clearly understood by those skilled in the art from the following description.

[0008] According to various aspects of this disclosure, a semiconductor package is provided, comprising: a package substrate; a plurality of chip modules stacked in a stepped structure on the package substrate in a first direction substantially perpendicular to a front surface of the package substrate; a capping layer surrounding the plurality of chip modules; and a plurality of interconnect modules extending along the first direction through penetration of the capping layer on a rear surface of the plurality of chip modules and configured to electrically connect at least one of the plurality of chip modules to the package substrate, wherein each of the plurality of interconnect modules includes: an interconnect molding film surrounded by the capping layer; and a plurality of interconnect pillars penetrating the interconnect molding film, and wherein the plurality of chip modules includes a plurality of chips stacked in a stepped structure.

[0009] According to various aspects of this disclosure, a semiconductor package is provided, comprising: a package substrate; a first chip module, a second chip module, a third chip module, and a fourth chip module stacked in a stepped structure on the package substrate in a first direction substantially perpendicular to the front surface of the package substrate; a capping layer surrounding the first chip module, the second chip module, the third chip module, and the fourth chip module; and a plurality of interconnect modules extending along the first direction by penetrating the capping layer and configured to electrically connect the package substrate to each of the first chip module, the second chip module, the third chip module, and the fourth chip module, wherein the first chip module includes at least one first chip, a first chip molding film, and a first wiring post, the at least one first chip being positioned spaced apart from the package substrate in the first direction, the first chip molding film surrounding the first chip, and the first wiring post penetrating the first chip molding film in the first direction and being connected to the first chip, wherein the second chip module includes at least one second chip, a second chip molding film, and a second wiring post, the... At least one second chip is placed on the rear surface of the first chip module and located between the packaging substrate and the first chip module. A second chip molding film surrounds the second chip. A second wiring post penetrates the second chip molding film in the first direction and is connected to the second chip. The third chip module includes at least one third chip, a third chip molding film, and a third wiring post. The at least one third chip is placed on the rear surface of the second chip module and located between the packaging substrate and the second chip module. The third chip molding film surrounds the third chip. The third wiring post penetrates the third chip molding film in the first direction and is connected to the third chip. The fourth chip module includes at least one fourth chip, a fourth chip molding film, and a fourth wiring post. The at least one fourth chip is placed on the rear surface of the third chip module and located between the packaging substrate and the third chip module. The fourth chip molding film surrounds the fourth chip. The fourth wiring post penetrates the fourth chip molding film in the first direction and is connected to the fourth chip.

[0010] According to various aspects of this disclosure, a semiconductor package is provided, comprising: a package substrate; a first chip module, a second chip module, a third chip module, and a fourth chip module stacked in a stepped structure on the package substrate in a first direction substantially perpendicular to the front surface of the package substrate; a capping layer surrounding the first chip module, the second chip module, the third chip module, and the fourth chip module; and a plurality of interconnect modules extending along the first direction on the rear surface of each of the first chip module, the second chip module, and the third chip module by penetrating the capping layer, and configured to electrically connect the package substrate to the first chip module, the second chip module, and the third chip module, wherein at least one of the plurality of interconnect modules has a length in the first direction that differs from the length of each of a portion of the plurality of interconnect modules, and wherein the lowest surface of the plurality of interconnect modules has the same height.

[0011] According to various aspects of this disclosure, a method for manufacturing a semiconductor package is provided, comprising: stacking a plurality of chips in a stepped structure on the substrate in a first direction substantially perpendicular to the front surface of the substrate; forming a plurality of wiring posts corresponding to each of the plurality of chips at a stepped region on one side of the plurality of chips; forming a chip molding film surrounding the plurality of wiring posts and the plurality of chips; cutting a plurality of chip modules including the plurality of chips, the plurality of wiring posts and the chip molding film from the substrate; stacking the plurality of chip modules in a stepped structure on a carrier substrate; placing each of a plurality of interconnect modules to overlap at least a portion of the plurality of wiring posts on the plurality of chip modules in the first direction; forming a capping layer surrounding each of the plurality of chip modules and the plurality of interconnect modules; forming a package substrate on the plurality of chip modules, the plurality of interconnect modules and the capping layer; and removing the carrier substrate.

[0012] According to various aspects of this disclosure, a method for manufacturing the semiconductor package is provided, further comprising: forming the plurality of interconnect modules prior to placing each of the plurality of interconnect modules, including: forming an interconnect molding layer, forming a recessed region penetrating at least a portion of the interconnect molding layer in a first direction, and forming an interconnect pillar in the recessed region.

[0013] Specific details of other example embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0014] These and / or other aspects, features, and advantages will become clearer and more readily understood from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0017] Figure 3 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0019] Figure 5 By magnification Figure 4 An exemplary diagram of an example embodiment of region B;

[0020] Figure 6 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0021] Figure 7 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0022] Figure 8 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0023] Figure 9 This is a diagram illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

[0024] Figures 10 to 18 This is a diagram illustrating, in process order, an example of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0025] Before describing the exemplary embodiments in detail, the words and terms used in the specification and claims should not be construed as limited to their ordinary or dictionary meanings, but rather as meanings and concepts consistent with the technical concept of this disclosure, provided that the inventor can appropriately define the concepts of the terms to best interpret his or her own invention. Therefore, the exemplary embodiments described herein and the configurations shown in the accompanying drawings are merely the most ideal exemplary embodiments of this disclosure and do not fully cover the technical concept of this disclosure. Consequently, it should be understood that various equivalents and modifications may exist as alternatives at the time of filing this application.

[0026] In the following description, unless the context clearly specifies otherwise, singular expressions include plural expressions. It should be understood that terms such as “including or comprising” and “forming” are intended to indicate the presence of features, quantities, steps, operations, elements, components or combinations thereof described in the specification, and are not intended to preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components or combinations thereof.

[0027] Furthermore, it should be clarified beforehand that expressions such as upper side, upper part, lower side, lower part, side surface, front surface, and rear surface are used in the following text to indicate directions relative to those shown in the accompanying drawings, and may be used in other ways when the orientation of the corresponding object changes. For clarity, the shape, size, etc., of elements in the accompanying drawings may be exaggerated.

[0028] In the following description, exemplary embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0029] Figure 1 This is a diagram used to illustrate a semiconductor package according to an example embodiment.

[0030] Reference Figure 1 The semiconductor package 1000 according to the example embodiment includes a package substrate 50, a first chip module CM1, a second chip module CM2, a third chip module CM3, a fourth chip module CM4, a capping layer 600, and a plurality of interconnect modules IM.

[0031] According to an example embodiment, the packaging substrate 50 can be a wiring structure for packaging. For example, the packaging substrate 50 can be a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, obviously, the packaging substrate 50 can also be a wiring structure for wafer-level packaging (WLP) manufactured at the wafer level. The packaging substrate 50 can be a semiconductor chip including semiconductor devices. The packaging substrate 50 can be used as a support substrate for semiconductor packaging.

[0032] In the example embodiment, the encapsulation substrate 50 may be a glass substrate, a ceramic substrate, or a plastic substrate, but the encapsulation substrate 50 is not limited thereto. As an example, the encapsulation substrate 50 may include a resin (e.g., prepreg, Ajinomoto laminate (ABF), FR-4, or bismaleimide triazine (BT)) impregnated together with an inorganic filler in a core material such as glass fiber (e.g., glass cloth or glass fiber cloth).

[0033] According to an example embodiment, the package substrate 50 may include, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the package substrate 50 may be a silicon substrate. As yet another example, the package substrate 50 may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the package substrate 50 is not limited thereto.

[0034] According to an example embodiment, the package substrate 50 may include conductive regions, such as impurity-doped traps or impurity-doped structures. The package substrate 50 may have various element isolation structures, such as shallow trench isolation (STI) structures.

[0035] According to an example embodiment, the packaging substrate 50 may include a substrate body portion 51 and a substrate wiring structure 52.

[0036] According to an example embodiment, when the encapsulation substrate 50 is a PCB, the substrate body portion 51 may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. The encapsulation substrate 50 may include at least one material selected from tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene ether, BT, Thermount, cyanate ester, and liquid crystal polymer.

[0037] According to an example embodiment, the substrate body portion 51 may include a photoimageable dielectric. As an example, the substrate body portion 51 may include a photoimageable polymer. The photoimageable polymer may be composed of at least one of, for example, photoimageable polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene-based polymer. As another example, the substrate body portion 51 may be composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0038] According to an example embodiment, although not shown, the surface of the substrate body portion 51 may be covered with a solder resist. For example, a passivation film may be formed on the surface of the substrate body portion 51. The passivation film formed on the surface of the substrate body portion 51 can protect the substrate wiring structure 52 and other structures from external impacts or moisture. The passivation film may include a solder resist. However, the technical concept of this disclosure is not limited thereto.

[0039] According to an example embodiment, a substrate wiring structure 52 may be placed in a substrate body portion 51. The substrate wiring structure 52 may include wiring patterns and wiring vias connecting each wiring pattern. For example, the substrate wiring structure 52 may be a multilayer structure in which two or more wiring patterns or two or more wiring vias are alternately stacked. For example, the wiring patterns may extend along a second direction D2. Wiring vias may connect wiring patterns spaced apart in a first direction D1. Here, the first direction D1 may refer to a direction perpendicular to the surface of the package substrate 50. For example, the first direction D1 may indicate a direction perpendicular to the front surface or the rear surface of the package substrate.

[0040] In the example embodiment, the substrate wiring structure 52 may include a conductive material. For example, the substrate wiring structure 52 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but is not limited thereto.

[0041] According to an example embodiment, a plurality of chip modules CM include a first chip module CM1, a second chip module CM2, a third chip module CM3, and a fourth chip module CM4 stacked in a stepped structure on the front surface of the packaging substrate 50 in a first direction D1 perpendicular to the front surface of the packaging substrate 50. The first chip module CM1, the second chip module CM2, the third chip module CM3, and the fourth chip module CM4 stacked in a stepped structure can be positioned by offsetting them at predetermined intervals in a second direction D2.

[0042] According to an example embodiment, each of the first chip module CM1, the second chip module CM2, the third chip module CM3, and the fourth chip module CM4 may include at least one chip (e.g., the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400), a chip molding film 500 surrounding the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400, and wiring posts 120 extending along a first direction D1 through the chip molding film 500 and electrically connected to the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400.

[0043] According to an example embodiment, the first chip module CM1 may include at least one first chip 100 placed at a distance from the packaging substrate 50 in a first direction D1 perpendicular to the front surface of the packaging substrate 50, a first chip molding film 510 surrounding the first chip 100, and a first wiring post 121 penetrating the first chip molding film 510 in the first direction D1 and connected to the first chip 100.

[0044] According to an example embodiment, the second chip module CM2 may include at least one second chip 200 placed on the rear surface of the first chip module CM1 and located between the packaging substrate 50 and the first chip module CM1, a second chip molding film 520 surrounding the second chip 200, and a second wiring post 122 penetrating the second chip molding film 520 in a first direction D1 and connected to the second chip 200.

[0045] According to an example embodiment, the third chip module CM3 may include at least one third chip 300 placed on the rear surface of the second chip module CM2 and located between the packaging substrate 50 and the second chip module CM2, a third chip molding film 530 surrounding the third chip 300, and a third wiring post 123 penetrating the third chip molding film 530 in a first direction and connected to the third chip 300.

[0046] According to an example embodiment, the fourth chip module CM4 may include at least one fourth chip 400 placed on the rear surface of the third chip module CM3 and located between the packaging substrate 50 and the third chip module CM3, a fourth chip molding film 540 surrounding the fourth chip 400, and a fourth wiring post 124 penetrating the fourth chip molding film 540 in a first direction D1 and connected to the fourth chip 400.

[0047] According to an example embodiment, a first chip module CM1 can be placed on a packaging substrate 50 in a first direction D1. The first chip module CM1 can also be placed on a second chip module CM2 in the first direction D1. Compared to the second chip module CM2, the first chip module CM1 can be placed further away from the packaging substrate 50 in the first direction D1.

[0048] According to an example embodiment, the first chip module CM1 may include at least one first chip 100. For example, the first chip module CM1 may include multiple first chips 100. For example, the first chip module CM1 may include four first chips 100. The first chips 100 may be placed on the packaging substrate 50 in the first direction D1. Figure 1 The illustration shows a first chip module CM1 comprising four first chips 100, but the example embodiment is not limited thereto. For example, it is apparent that the first chip module CM1 may include only one first chip 100, or it may include five or more first chips 100.

[0049] For example, multiple first chips 100 to fourth chips 400 may be offset from each other in stepped regions (e.g., first stepped region ST1, second stepped region ST2, third stepped region ST3, and fourth stepped region ST4) in the second direction D2. Offset placement may refer to staggered placement at predetermined intervals. For example, instead of placing the multiple first chips 100 to fourth chips 400 to completely overlap each other in the first direction D1, a portion of them may overlap in the first direction D1, and the remaining portions may be staggered in the second direction D2 so as not to overlap in the first direction D1. The sidewalls of the multiple first chips 100 may be placed at uniform intervals, rather than being placed on the same plane as each other. Because the multiple first chips 100 to fourth chips 400 may be offset in the second direction D2, the connection pads 110 placed at each of the portions of the multiple first chips 100 to fourth chips 400 may not overlap with another portion of the multiple first chips 100 to fourth chips 400 in the first direction D1. Therefore, the connection pad 110 can be connected to the first wiring post 121, the second wiring post 122, the third wiring post 123 and the fourth wiring post 124 respectively.

[0050] According to an example embodiment, the chip molding film 500 may surround the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400. The chip molding film 500 may surround the wiring posts 120. The chip molding film 500 may form an interface with the capping layer 600. The chip molding film 500 may include an insulating material. For example, the chip molding film 500 may include an insulating polymer material such as epoxy molding compound (EMC). As another example, the chip molding film 500 may include a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The chip molding film 500 may include fillers. The filler content included in the chip molding films 500 of the first chip module CM1, the second chip module CM2, the third chip module CM3, and the fourth chip module CM4 may differ.

[0051] For example, the chip molding film 500 may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or prepregs, ABF, FR-4, BT, and EMC containing inorganic fillers and / or glass fibers.

[0052] According to an example embodiment, wiring posts 120 can be placed between the first chip 100 to the fourth chip 400 and the first interconnect module IM1 to the third interconnect module IM3. Wiring posts 120 can extend along a first direction D1 between the first chip 100 to the fourth chip 400 and the first interconnect module IM1 to the third interconnect module IM3. Wiring posts 120 can penetrate the chip molding film 500. Wiring posts 120 can be configured to electrically connect interconnect posts IP to the first chip 100 to the fourth chip 400. Wiring posts 120 can include metallic materials such as titanium (Ti), copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof. Figure 1 The wiring post 120 is shown to be a single-layer film, but the example embodiment is not limited thereto. For example, the wiring post 120 may include a multilayer film structure.

[0053] According to an example embodiment, each of the plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may include an insulating film 101, an adhesive layer 105, and bonding pads 110. Each of the plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may be offset from each other at stepped regions (first stepped region ST1, second stepped region ST2, third stepped region ST3, and fourth stepped region ST4).

[0054] According to an example embodiment, the insulating film 101 may include, for example, a photoimageable dielectric. For instance, the insulating film 101 may include a photoimageable polymer. The photoimageable polymer may be composed of at least one of, for example, photoimageable polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer. As another example, the insulating film 101 may be composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0055] According to an example embodiment, adhesive layer 105 may include a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. However, the technical concept of this disclosure is not limited thereto. For example, adhesive layer 105 may be a tape configured to secure the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400 to each other. For example, adhesive layer 105 may be a tape comprising an epoxy component.

[0056] According to an example embodiment, the connection pad 110 may be placed on the lower surface of each of the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400. Here, the lower surface of each of the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400 may refer to a surface of each of the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400 facing the package substrate 50. The connection pad 110 may be exposed on the surface of each of the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400. The connection pad 110 may contact the first wiring post 121, the second wiring post 122, the third wiring post 123, and the fourth wiring post 124. The connection pad 110 may be configured to be electrically connected to the interconnect module IM via the wiring post 120, which will be described below, and may receive electrical signals input from the external connection terminal 55, but is not limited thereto.

[0057] According to an example embodiment, each of a plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may include an integrated circuit (IC). Each of the plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may have an active surface on which the IC is formed and a passive surface located on the opposite side of the active surface. The active surface may be referred to as a front surface, and the passive surface may be referred to as a rear surface. For example, the front surface may refer to the surface facing the package substrate 50. The passive surface may refer to the surface located on the opposite side of the front surface.

[0058] According to an example embodiment, each of the plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may be a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM). Alternatively, the memory semiconductor chip may also be a non-volatile memory such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). However, the example embodiment is not limited thereto.

[0059] For example, at least a portion of a plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) may be logic semiconductor chips. Logic semiconductor chips may be application processors (APs) such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), digital signal processors, cryptographic processors, microprocessors, microcontrollers, and application-specific integrated circuits (ASICs).

[0060] According to an example embodiment, each of the plurality of chip modules CM may include a passivation layer 700 on the front surface of the top chip among the plurality of chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400). The front surface of the chip may refer to the surface located on the opposite side of the rear surface of the chip facing the package substrate 50.

[0061] According to an example embodiment, the capping layer 600 may include an insulating material. As an example, the capping layer 600 may include an insulating polymer material such as EMC. As another example, the capping layer 600 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg, ABF, FR-4, BT, and EMC containing inorganic fillers and / or glass fibers. The capping layer 600 may include fillers. Even if the capping layer 600 and the plurality of interconnect modules IM described below comprise the same material, an interface SF may be formed between the capping layer 600 and the plurality of interconnect modules IM due to the process sequence. Even if the capping layer 600 and the chip molding film 500 comprise the same substance, an interface may be formed between the capping layer 600 and the chip molding film 500 due to the process sequence.

[0062] According to an example embodiment, a plurality of interconnect modules IM may include a first interconnect module IM1 placed in a first stepped region ST1 of a first chip module CM1 overlapping with a first wiring post 121 in a first direction D1, a second interconnect module IM2 placed in a second stepped region ST2 of a second chip module CM2 overlapping with a second wiring post 122 in a first direction D1, and a third interconnect module IM3 placed in a third stepped region ST3 of a third chip module CM3 overlapping with a third wiring post 123 in a first direction D1.

[0063] According to an example embodiment, a plurality of interconnect modules IM can extend through the capping layer 600 in a first direction D1 and can be configured to electrically connect the package substrate 50 to a first chip module CM1, a second chip module CM2, a third chip module CM3, and a fourth chip module CM4. Each of the plurality of interconnect modules IM may include an interconnect molding film 800 and at least one interconnect post IP, which extends along the first direction D1 through the interconnect molding film 800 and is connected to any one of the first wiring post 121, the second wiring post 122, the third wiring post 123, and the fourth wiring post 124.

[0064] According to an example embodiment, the interconnect molding film 800 may be surrounded by a capping layer 600. The interconnect molding film 800 may form an interface SF with the capping layer 600. The interconnect molding film 800 may surround an interconnect pillar IP. The interconnect molding film 800 may be spaced apart from the chip molding film 500. The interconnect molding film 800 may be spaced apart from the chip molding film 500, with a connector 900 disposed therebetween. The interconnect molding film 800 may include an insulating material. As an example, the interconnect molding film 800 may include an insulating polymer material such as EMC. As another example, the interconnect molding film 800 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg, ABF, FR-4, BT, and EMC containing inorganic fillers and / or glass fibers. The interconnect molding film 800 may include fillers.

[0065] According to an example embodiment, the interconnect pillar IP may be surrounded by an interconnect molding film 800. The interconnect pillar IP may extend between the package substrate 50 and the first chip module CM1 to the third chip module CM3. The interconnect pillar IP may be configured to electrically connect the wiring pillar 120 and the package substrate 50. The interconnect pillar IP may include metallic materials such as titanium (Ti), copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof. Figure 1 The interconnect pillar IP is shown to be a single-layer film, but the example embodiment is not limited to this. For example, the interconnect pillar IP may have a multilayer film structure.

[0066] According to the example embodiment, the first interconnect module IM1, the second interconnect module IM2, and the third interconnect module IM3 can be placed corresponding to the first stepped region ST1, the second stepped region ST2, and the third stepped region ST3, respectively. More specifically, the first interconnect module IM1 can be placed to overlap with the first wiring post 121 of the first stepped region ST1 in the first direction, the second interconnect module IM2 can be placed to overlap with the second wiring post 122 of the second stepped region ST2 in the first direction D1, and the third interconnect module IM3 can be placed to overlap with the third wiring post 123 of the third stepped region ST3 in the first direction D1. According to the example embodiment, the number of interconnect post IPs can be the same as the number of multiple wiring posts 120 included in the chip module CM that overlaps with the corresponding interconnect post IPs in the first direction D1. This can establish a one-to-one correspondence between wiring posts 120 and interconnect post IPs to improve the reliability of electrical connections. Furthermore, because the interconnect module IM is formed separately from the wiring posts 120 in each chip module CM, the aspect ratio (AR) of the wiring posts 120 or interconnect module IM can be reduced compared to the case where a single long wiring post 120 is formed. This can reduce the manufacturing risks caused by the high AR that may occur in a structure where multiple chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) are stacked in a high-level hierarchy.

[0067] According to the example embodiment, the length of at least one of the plurality of interconnect modules IM in the first direction D1 may be different from the lengths of the other interconnect modules. Here, the height of the lowest surface of the plurality of interconnect modules IM may be the same as each other.

[0068] According to an example embodiment, the lengths of the multiple interconnect modules IM in the first direction D1 can be different from each other. More specifically, the first length of the first interconnect module IM1 in the first direction D1 can be greater than the second length of the second interconnect module IM2 in the first direction D1, and the second length of the second interconnect module IM2 in the first direction D1 can be greater than the third length of the third interconnect module IM3 in the first direction D1. This may be because the interconnect modules are formed to correspond to each step region of a chip module stacked in a stepped structure. For example, the AR of the first interconnect module IM1 can be 15:1 to 20:1, the AR of the second interconnect module IM2 can be 10:1 to 15:1, and the AR of the third interconnect module IM3 can be 5:1 to 10:1, but is not limited thereto. When the AR of the interconnect module IM is large, by combining multiple interconnect modules IM, the manufacturing risk caused by the high AR that may occur in a structure in which multiple chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) are stacked in a high-level structure can be reduced.

[0069] According to an example embodiment, the lowest surfaces of the plurality of interconnect modules IM have the same height, while the heights of their top surfaces may differ. More specifically, the height of the top surface of a portion of the plurality of interconnect modules IM may be higher than the height of the top surface of another portion. This structure can be configured to correspond to the height of each step in a chip module stacked in a stepped shape.

[0070] According to an example embodiment, the connector 900 can be placed between the interconnect module IM and the chip module CM. According to an example embodiment, the connector 900 can be placed between the bottom of a plurality of wiring posts 120 and the top of a plurality of interconnect modules IM. Specifically, the connector 900 can electrically connect the lower surface of the wiring posts 120 to the upper surface of the interconnect posts IP. The connector 900 may include bumps 910 or connection pads 920. Bumps 910 may include solder balls or solder bumps. As another example, bumps 910 may include microbumps. Bumps 910 may be spherical or ellipsoidal, but are not limited thereto. The number, spacing, arrangement, and shape of bumps 910 are not limited to those shown in the figures, and obviously, their number, spacing, arrangement, and shape can vary according to the design. Bumps 910 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but are not limited thereto. Regarding the example embodiments described below, for ease of explanation, they will be primarily described and referenced. Figure 1 The differences in the content described.

[0071] Figure 2 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0072] Reference Figure 2 The semiconductor package 1000A may also include external connection terminals 55 on the rear surface of the package substrate 50. The external connection terminals 55 may be placed on external connection pads 54. The external connection terminals 55 may contact the external connection pads 54. As an example, the external connection terminals 55 may include solder balls or solder bumps. As another example, the external connection terminals 55 may include microbumps. The external connection terminals 55 may be spherical or ellipsoidal, but are not limited thereto. The number, spacing, arrangement, and shape of the external connection terminals 55 are not limited to those shown in the figures, and it is obvious that their number, spacing, arrangement, and shape may vary depending on the design. The external connection terminals 55 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but are not limited thereto.

[0073] According to the example embodiment, the external connection terminal 55 can electrically connect the substrate wiring structure 52 to an external device. Therefore, the external connection terminal 55 can provide electrical signals to the substrate wiring structure 52, or provide electrical signals provided from the substrate wiring structure 52 to an external device.

[0074] For example, external connection terminal 55 can provide electrical signals to the first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4 by providing electrical signals relative to them. External connection terminal 55 can receive signals input to the first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4. External connection terminal 55 can also receive signals output from the first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4.

[0075] Figure 3 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0076] Reference Figure 3 The semiconductor package 1000B may further include alignment pads 710 in each of the first chip module CM1, the second chip module CM2, the third chip module CM3, and the fourth chip module CM4. According to an example embodiment, the alignment pads 710 may be placed in the chip molding film 500 of each of the first chip module CM1, the second chip module CM2, the third chip module CM3, and the fourth chip module CM4. The alignment pads 710 may be covered by the chip molding film 500. Specifically, in the first direction D1, the alignment pads 710 may be placed on the rear surface of the passivation layer 700 facing the package substrate 50. For example, the alignment pads 710 may be used to align each chip (e.g., the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400). Alignment may refer to setting a position around a reference point for placement in a predetermined location. Alignment pads 710 may be placed on passivation layer 700 or somewhere in semiconductor package 1000B, but may not be present in semiconductor package 1000B during chip dicing (e.g., first chip 100, second chip 200, third chip 300 and fourth chip 400).

[0077] Figure 4 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0078] Reference Figure 4 Region B, for semiconductor package 1000C, and Figure 1Unlike the semiconductor package 1000, the width L1 of the top of the interconnect pillar IP in the second direction D2 can be smaller than the width L2 of the bottom of the interconnect pillar IP in the second direction D2. In other words, for the interconnect pillar IP, its width in the second direction D2 may increase in the direction toward the front surface of the package substrate 50. This may be because, as will be described below... Figures 15A-15D In the process, it is formed to vary according to the height of the interconnect molding film 800. Figures 15A-15D When the recessed region RC is formed in the process, with the bottom width narrowed, the bump 910 can be attached to the narrowed portion of the interconnect pillar IP, which will be described below, before being connected to the first chip module CM1.

[0079] Figure 5 By magnification Figure 4 An exemplary diagram of an example embodiment of region B.

[0080] Figure 5 The image is shown by magnification. Figure 4 Region B. (Refer to...) Figure 5 The semiconductor package 1000D can have the same characteristics as... Figure 4 The interconnect pillar IPs of the semiconductor package 1000C have different structures. According to an example embodiment, the width L1 of the top of the interconnect pillar IP in the second direction D2 can be greater than the width L2 of the bottom of the interconnect pillar IP in the second direction D2. In other words, for the interconnect pillar IP, its width in the second direction D2 may gradually decrease in the direction toward the front surface of the package substrate 50. This may be because, as will be described below... Figures 15A-15D In the process, it is formed to vary according to the height of the interconnect molding film 800. Figures 15A-15D When the recessed region RC is formed in the process, with the bottom width narrowed, the bump 910 can be attached to the part opposite to the narrowed part of the interconnect pillar IP (the part with the increased width of the interconnect pillar IP) before being connected to the first chip module CM1.

[0081] Figure 6 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0082] Reference Figure 6The first interconnect module IM1 of the semiconductor package 1000E may include a first module portion IM1_1 and a second module portion IM1_2 that overlap each other in a first direction D1 within a first stepped region ST1. Here, a bump 910 of a connecting portion 900 may be placed between the first module portion IM1_1 and the second module portion IM1_2. According to an example embodiment, the length of the first module portion IM1_1 in the first direction D1 may be substantially the same as the length of the third interconnect module IM3 in the first direction D1. This may be because the third interconnect module IM3 and the first module portion IM1_1 are manufactured using substantially the same process, but are not limited thereto. Similarly, the length of the second module portion IM1_2 in the first direction D1 may be substantially the same as the length of the second interconnect module IM2 in the first direction D1. This may be because the second interconnect module IM2 and the second module portion IM1_2 are manufactured using substantially the same process, but are not limited thereto. Therefore, with Figure 1 The semiconductor package 1000 (in which the first interconnect module IM1, the second interconnect module IM2, and the third interconnect module IM1, which have different lengths on the first direction D1, are manufactured differently from each other) is different. Figure 6 The semiconductor package 1000E can simultaneously manufacture the first module portion IM1_1 and the second module portion IM1_2 of the first interconnect module IM1 while performing the manufacturing processes for the second interconnect module IM2 and the third interconnect module IM3, thereby reducing process complexity. Furthermore, the arc resistance (AR) of the interconnect modules IM can be reduced, and therefore, the manufacturing risks caused by high AR that may arise in a high-level stacked structure of multiple chips (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400) can be reduced.

[0083] Figure 7 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0084] Reference Figure 7In the second stepped region ST2 of the second chip module CM2, the semiconductor package 1000F may also include a fourth interconnect module IM4 between the second interconnect module IM2 and the front surface of the package substrate 50. A bump 910 of a connecting portion 900 may be placed between the second interconnect module IM2 and the fourth interconnect module IM4. According to an example embodiment, the length of the second interconnect module IM2 in the first direction D1 may be substantially the same as the length of each of the third interconnect module IM3 and the fourth interconnect module IM4 in the first direction D1. This may be because the second interconnect module IM2 and the fourth interconnect module IM4 are manufactured together using a process substantially the same as that used to manufacture the third interconnect module IM3. The length of the first module portion IM1_1 of the first interconnect module IM1 in the first direction D1 may be substantially the same as the length of the third interconnect module IM3 in the first direction D1.

[0085] Figure 8 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0086] Reference Figure 8 The semiconductor package 1000G may also include an underfill resin UF, which is used for... Figure 7 The semiconductor package 1000F is used to fill the space between the first chip module CM1 and the first interconnect module IM1, the space between the second chip module CM2 and the second interconnect module IM2, and the space between the third chip module CM3 and the third interconnect module IM3. According to an example embodiment, an underfill resin UF can be placed around the connector 900. The underfill resin UF can improve the mechanical stability of the connector 900 and protect it from external environmental influences. The underfill resin can be a molding underfill material (MUF) or a capillary underfill material (CUF).

[0087] Figure 9 This is a diagram illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0088] For ease of explanation, for Figure 9 The example embodiments will be mainly described and referenced. Figure 1 The differences in the content described.

[0089] Reference Figure 9 The semiconductor package 1000H may also include an underfill resin UF, which is used for... Figure 1The semiconductor package 1000 is filled with the space between the first chip module CM1 and the first interconnect module IM1, the space between the second chip module CM2 and the second interconnect module IM2, and the space between the third chip module CM3 and the third interconnect module IM3. According to an example embodiment, the underfill resin UF can be placed around the connector 900. The underfill resin UF can improve the mechanical stability of the connector 900 and protect it from external environmental influences. The underfill resin can be MUF or CUF.

[0090] Figures 10 to 18 This is a diagram illustrating, in process order, an example of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0091] Reference Figure 10 First chip 100, second chip 200, third chip 300, and fourth chip 400 can be stacked in a stepped structure on substrate 210. Substrate 210 is used to support the chips in subsequent processes and can be made of various materials such as silicon, glass, and ceramic. When stacking first chip 100, second chip 200, third chip 300, and fourth chip 400, precise alignment of each chip is crucial, and for this purpose, [the following methods can be used]. Figure 2 Alignment pads 710. Alignment pads 710 can be formed on passivation layer 700 or placed in other areas of the semiconductor package to precisely control chip positioning. Because the first chip 100, second chip 200, third chip 300, and fourth chip 400 are offset from each other in stepped regions (e.g., first stepped region ST1, second stepped region ST2, third stepped region ST3, and fourth stepped region ST4) in the second direction D2, the connection pads 110 of each chip do not overlap with other chips. By using adhesive layer 105, each chip can be securely fixed to chips on or below the substrate 210.

[0092] Reference Figure 11A chip molding film 500 can be formed around a plurality of wiring posts 120 and a plurality of chips (e.g., a first chip 100, a second chip 200, a third chip 300, and a fourth chip 400). For example, after forming the chip molding film 500 around the plurality of chips (e.g., a first chip 100, a second chip 200, a third chip 300, and a fourth chip 400), a plurality of wiring posts (e.g., a first step region ST1, a second step region ST2, a third step region ST3, and a fourth step region ST4) corresponding to each of the plurality of chips (e.g., a first wiring post 121, a second wiring post 122, a third wiring post 123, and a fourth wiring post 124) can be formed at a stepped region (e.g., a first step region ST1, a second step region ST2, a third step region ST3, and a fourth step region ST4) on one side of the plurality of chips (e.g., a first chip 100, a second chip 200, a third chip 300, and a fourth chip 400). Wiring posts 120 can be formed on the connection pads 110 of each chip using methods such as sputtering, electroplating, and chemical vapor deposition (CVD). Specifically, after forming a recessed space for the wiring posts 120 by etching the chip molding film 500, the recessed space is filled with material to form the wiring posts 120. The wiring posts 120 can be electrically connected to the connection pads 110 of each of the first chip 100, the second chip 200, the third chip 300, and the fourth chip 400, and can be formed by penetrating the chip molding film 500 in a first direction D1, but are not limited thereto.

[0093] Reference Figure 12 and Figure 13 Connection pads 920 can be formed on multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4), and then multiple chip modules (e.g., first chip 100, second chip 200, third chip 300, and fourth chip 400), multiple wiring pillars 120, and chip molding films 500 can be diced from the substrate 210, but not limited to this. Multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4) can be formed by dicing along the dicing line CL.

[0094] Reference Figure 14Multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4) can be stacked on the carrier substrate 10 in a stepped structure. First, a pre-adhesive layer 701 can be applied to the carrier substrate 10, and then the multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3, and fourth chip module CM4) can be stacked. The pre-adhesive layer 701 can facilitate the stacking of the chip modules CM in subsequent processes. Alignment pads 750 may be included in the pre-adhesive layer 701, but are not limited to.

[0095] Figures 15A to 15D The process for forming the interconnect module IM is shown, which can be configured through the following detailed operations.

[0096] Reference Figure 15A First, an interconnect molding film 800 can be formed. The interconnect molding film 800 can be formed using methods such as sputtering or CVD. The interconnect molding film 800 serves to support and protect the interconnect pillars IP that will be formed in subsequent processes.

[0097] Reference Figure 15B A recessed region RC that penetrates the interconnect molding film 800 can be formed. This recessed region RC can be formed by removing a portion of the interconnect molding film 800 using an etching process or the like.

[0098] Reference Figure 15C Interconnect pillar IPs can be formed on the recessed region RC. The interconnect pillar IPs can be formed using methods such as electroplating or sputtering, and can be electrically connected to the wiring pillars 120 in subsequent processes. Typically, a metallic material such as copper (Cu) can be used for the interconnect pillar IPs.

[0099] Reference Figure 15D Bumps 910 can be selectively attached to the upper or lower surface of the interconnect pillar IP. Solder bumps, micro-bumps, etc., can be used for bumps 910, and in subsequent processes, bumps 910 can facilitate electrical connections between the chip module and the package substrate 50. The lengths of the first interconnect module IM1 to the fourth interconnect module IM4 in the first direction can be adjusted by polishing the interconnect module IM or by setting the length of the interconnect molding film 800 in the first direction.

[0100] Reference Figure 16After forming the interconnect module IM, the interconnect module IM can be positioned in the first direction D1 to overlap at least a portion of the wiring posts 120 in the first stepped region ST1, the second stepped region ST2, and the third stepped region ST3 of the multiple chip modules (e.g., the first chip module CM1, the second chip module CM2, and the third chip module CM3). To connect the interconnect module IM and the multiple chip modules (e.g., the first chip module CM1, the second chip module CM2, and the third chip module CM3) via the connection portion 900, heat can be applied to achieve the connection.

[0101] Reference Figure 17 It can form a capping layer 600 around each of multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3 and fourth chip module CM4) and multiple interconnect modules IM, and can perform a planarization process.

[0102] Reference Figure 18 The packaging substrate and external connection pads 54 can be formed on multiple chip modules (e.g., first chip module CM1, second chip module CM2, third chip module CM3 and fourth chip module CM4), multiple interconnect modules IM, and cover layer 600.

[0103] Next, the carrier substrate 10 and the pre-adhesive layer 701 can be removed to form Figure 1 Semiconductor package 1000.

[0104] According to an example embodiment, semiconductor packages can be manufactured by modularizing them so that processes are performed by each module unit, thereby minimizing manufacturing risks even when semiconductor chips are stacked in high-level layers of 16 or more.

[0105] According to the example embodiment, interconnect pillars can be formed for each module to reduce the aspect ratio (AR) of the interconnect pillars required for semiconductor packaging, thereby facilitating manufacturing.

[0106] Although various exemplary embodiments of the present disclosure have been described in detail above, the scope of the disclosure is not limited thereto, and it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the technical concept of the present disclosure as defined in the appended claims. Furthermore, the above exemplary embodiments can be implemented by removing some elements, and the various exemplary embodiments can be implemented in combination with each other.

Claims

1. A semiconductor package, comprising: Packaging substrate; Multiple chip modules are stacked in a stepped structure on the packaging substrate in a first direction perpendicular to the front surface of the packaging substrate; A capping layer surrounds the plurality of chip modules; as well as Multiple interconnect modules extend along the first direction on the rear surface of the multiple chip modules by penetrating the capping layer, and are configured to electrically connect the package substrate to at least one of the multiple chip modules. Each of the plurality of interconnect modules includes: An interconnected molded film surrounded by the capping layer; and Multiple interconnect pillars penetrating the interconnect molding film, and Each of the plurality of chip modules comprises a plurality of chips stacked in a stepped structure.

2. The semiconductor package according to claim 1, wherein, An interface is formed between the interconnected molded film and the capping layer.

3. The semiconductor package according to claim 1 further includes a connection portion between the plurality of chip modules and the interconnect module. in, The connecting part is a bump or a pad.

4. The semiconductor package of claim 3 further includes an underfill resin, the underfill resin surrounding the connection portion and used to fill the space between the plurality of chip modules and the plurality of interconnect modules.

5. The semiconductor package according to claim 1, wherein, Each of the plurality of chip modules further includes: A chip molding film surrounds the plurality of chips; and Multiple wiring posts extend along the first direction by penetrating the chip molding film and are electrically connected to the multiple chips.

6. The semiconductor package according to claim 1, wherein, Each of the plurality of chip modules further includes a passivation layer located on the front surface of the top-mounted chip among the plurality of chips. At least one of the plurality of chip modules further includes alignment pads, which are placed on the rear surface of the passivation layer facing the package substrate on one side of the plurality of chips.

7. The semiconductor package according to claim 5, wherein, The number of interconnect pillars is equal to the number of the plurality of wiring pillars included in the chip module that overlap with the interconnect pillars in the first direction.

8. The semiconductor package according to claim 1, wherein, At least one of the plurality of interconnect modules has a different length than the other interconnect module.

9. A semiconductor package, comprising: Packaging substrate; The first chip module, the second chip module, the third chip module, and the fourth chip module are stacked on the packaging substrate in a stepped structure in a first direction perpendicular to the front surface of the packaging substrate. A capping layer surrounds the first chip module, the second chip module, the third chip module, and the fourth chip module; as well as Multiple interconnect modules extend along the first direction by penetrating the capping layer and are configured to electrically connect the packaging substrate to each of the first chip module, the second chip module, the third chip module, and the fourth chip module. The first chip module includes at least one first chip, a first chip molding film, and a first wiring post. The at least one first chip is positioned spaced apart from the packaging substrate in the first direction. The first chip molding film surrounds the first chip, and the first wiring post penetrates the first chip molding film in the first direction and is connected to the first chip. The second chip module includes at least one second chip, a second chip molding film, and a second wiring post. The at least one second chip is placed on the rear surface of the first chip module and located between the packaging substrate and the first chip module. The second chip molding film surrounds the second chip, and the second wiring post penetrates the second chip molding film in the first direction and is connected to the second chip. The third chip module includes at least one third chip, a third chip molding film, and a third wiring post. The at least one third chip is placed on the rear surface of the second chip module and located between the packaging substrate and the second chip module. The third chip molding film surrounds the third chip. The third wiring post penetrates the third chip molding film in the first direction and is connected to the third chip. The fourth chip module includes at least one fourth chip, a fourth chip molding film, and a fourth wiring post. The at least one fourth chip is placed on the rear surface of the third chip module and is located between the packaging substrate and the third chip module. The fourth chip molding film surrounds the fourth chip, and the fourth wiring post penetrates the fourth chip molding film in the first direction and is connected to the fourth chip.

10. The semiconductor package according to claim 9, wherein, An interface is formed between the plurality of interconnect modules and the capping layer.

11. The semiconductor package according to claim 9, wherein, The first wiring post, the second wiring post, the third wiring post, and the fourth wiring post are electrically connected to the corresponding chips of the first chip, the second chip, the third chip, and the fourth chip in the first step area, the second step area, the third step area, and the fourth step area, respectively. The first step area, the second step area, the third step area, and the fourth step area are located on one side of the first chip module, the second chip module, the third chip module, and the fourth chip module, respectively.

12. The semiconductor package of claim 11, wherein, Each of the plurality of interconnect modules includes: Interconnected molded film, in contact with the capping layer; and At least one interconnect post extends along the first direction by penetrating the interconnect molding film and is connected to any one of the first wiring post, the second wiring post, the third wiring post, and the fourth wiring post.

13. The semiconductor package according to claim 12, wherein, The plurality of interconnect modules include: A first interconnect module is placed in the first stepped region of the first chip module, overlapping the first wiring post in the first direction; A second interconnect module is positioned in the second stepped region of the second chip module, overlapping the second wiring post in the first direction; and The third interconnect module is positioned to overlap the third wiring post in the first direction in the third step region of the third chip module.

14. The semiconductor package of claim 13, wherein, The first interconnect module has a first length in the first direction that is greater than the second interconnect module in the first direction, and Wherein, the second length of the second interconnect module is greater than the third length of the third interconnect module in the first direction.

15. The semiconductor package according to claim 13, wherein, The first interconnect module includes a first module portion and a second module portion, which overlap each other in the first step region in the first direction.

16. The semiconductor package of claim 15, further comprising a connection portion located between the first module portion and the second module portion in the first stepped region.

17. The semiconductor package of claim 15, wherein, The plurality of interconnect modules further includes a fourth interconnect module, which is located in the second stepped region of the second chip module between the second interconnect module and the front surface of the packaging substrate.

18. The semiconductor package according to claim 9, further comprising: The connection portion is located between the bottom of the plurality of wiring posts and the top of the plurality of interconnect modules; as well as The bottom is filled with resin, surrounding the connecting portion, and used to fill the space between the first chip module, the second chip module, the third chip module, and the fourth chip module and the corresponding interconnect modules among the plurality of interconnect modules.

19. A semiconductor package, comprising: Packaging substrate; The first chip module, the second chip module, the third chip module, and the fourth chip module are stacked on the packaging substrate in a stepped structure in a first direction perpendicular to the front surface of the packaging substrate. A capping layer surrounds the first chip module, the second chip module, the third chip module, and the fourth chip module; as well as Multiple interconnect modules extend along the first direction on the rear surface of each of the first, second, and third chip modules by penetrating the capping layer, and are configured to electrically connect the package substrate to the first, second, and third chip modules. Wherein, at least one of the plurality of interconnect modules has a length in the first direction that differs from the length of each of the plurality of interconnect modules in a subset of the plurality of interconnect modules, and The lowest surface of the plurality of interconnect modules has the same height.

20. The semiconductor package of claim 19, wherein, The height of the top surface of a portion of the plurality of interconnect modules is higher than the height of the top surface of another portion of the plurality of interconnect modules.

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