A multi-chip interrupt scheduling method based on RISC-V architecture

Abstract

The application discloses a kind of multicore interrupt scheduling methods based on RISC-V architecture, it is related to chip scheduling technical field, including, chip interrupt pressure table is compared with preset hot area threshold value, and according to the link delay of inter-chip interrupt link, target RISC-V chip is selected from migratable chip set, according to edge interrupt autonomous table, corresponding lockstep time window is matched for target RISC-V chip, and interrupt execution window mapping table is formed, according to interrupt execution window mapping table, the predicted wake-up moment is calculated, and target RISC-V chip is woken up in advance, and the interrupt service program is executed to target RISC-V chip after wake-up, and edge autonomous interrupt scheduling result is obtained;The application realizes load balancing by generating interrupt scheduling result, and enhances the scheduling flexibility and response capability of multicore architecture.

Description

Technical Field

[0001] This invention relates to the field of chip scheduling technology, and in particular to a multi-chip interrupt scheduling method, electronic device and storage medium based on RISC-V architecture. Background Technology

[0002] With the development of edge computing, industrial internet, and real-time control technologies, interrupt handling mechanisms based on heterogeneous multi-core and multi-chip collaboration have gradually become an important research direction for high real-time embedded devices. Especially in scenarios such as industrial control, intelligent manufacturing, autonomous driving edge nodes, and low-latency sensing terminals, a large number of peripheral interrupt requests need to be responded to and processed in a very short time, which puts forward higher requirements for chip-level real-time scheduling capabilities. Due to its open instruction set, strong customizability, and ease of building dedicated acceleration logic, the RISC-V architecture has been widely used in edge computing devices, multi-processor collaborative control platforms, and real-time control chip design in recent years. At the same time, in order to meet the needs of real-time task processing, some studies have also combined low-power wake-up, interrupt load balancing, and task migration technologies to optimize the execution process of interrupt service routines, so as to improve the real-time response capability of edge computing nodes under complex working conditions.

[0003] Nevertheless, existing chip scheduling methods still have room for improvement. First, they lack a joint stress assessment mechanism for the number of interrupts, interrupt service routine execution time, and waiting queue length. When local chips enter a high-load state, problems such as interrupt request backlog, increased response latency, and deadline failure can easily occur. Second, they lack collaborative constraint analysis for inter-chip link latency, lockstep time window, and interrupt deadline, which may lead to time window conflicts or real-time response failures after interrupt migration. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] To solve one or more of the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides a multi-chip interrupt scheduling method based on a RISC-V architecture, comprising,

[0007] Collect the serial numbers of each RISC-V chip, the inter-chip interrupt links, and the peripheral interrupt source numbers;

[0008] Based on the RISC-V chip number and peripheral interrupt source number, the default service chip and the set of migrateable chips are selected to form an edge interrupt autonomous table;

[0009] After calculating the number of interrupts, interrupt service routine execution time and wait queue length of each RISC-V chip based on the edge interrupt autonomy table, the chip interrupt pressure is calculated to form a chip interrupt pressure table.

[0010] The chip interrupt pressure gauge is compared with the preset hot zone threshold, and the target RISC-V chip is selected from the set of transferable chips based on the link delay of the inter-chip interrupt link.

[0011] Based on the edge interrupt autonomy table, a corresponding lockstep time window is matched for the target RISC-V chip to form an interrupt execution window mapping table;

[0012] Based on the interrupt execution window mapping table, calculate the predicted wake-up time and wake up the target RISC-V chip in advance;

[0013] The interrupt service routine is executed on the target RISC-V chip after it is woken up, and the edge autonomous interrupt scheduling result is obtained.

[0014] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the filtering of the default service chip and the set of migrateable chips specifically includes:

[0015] Based on the RISC-V chip number, read the core occupancy status, wake-up time and current queuing time of each RISC-V chip one by one, and collect the corresponding interrupt level, interrupt cutoff time and interrupt service routine entry address one by one according to the peripheral interrupt source number.

[0016] RISC-V chips that meet the interrupt deadline and whose core occupancy status is idle are marked as default service chips. RISC-V chips that meet the interrupt deadline, have reachable inter-chip interrupt links, and whose current queuing time is lower than a preset queuing time threshold, other than the default service chips, are grouped into a set of migrateable chips.

[0017] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the step of forming an edge interrupt autonomous table refers to arranging the correspondence between peripheral interrupt source numbers, default service chips, set of transferable chips, interrupt levels, interrupt deadlines, and interrupt service routine entry addresses to form an edge interrupt autonomous table.

[0018] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the calculation of chip interrupt pressure specifically involves:

[0019] Based on the edge interrupt autonomy table, peripheral interrupt source numbers are collected according to RISC-V chip numbers, and the number of interrupts received by each RISC-V chip within a preset statistical period is counted.

[0020] Based on the entry address of the interrupt service routine corresponding to each peripheral interrupt source number, the execution time of the corresponding interrupt service routine from the start to the completion of execution is recorded to obtain the execution time of the interrupt service routine.

[0021] Collect the number of peripheral interrupt source numbers that have not yet been executed in each RISC-V chip to obtain the length of the waiting queue;

[0022] The chip interrupt pressure of each RISC-V chip is calculated based on the number of interrupts, the execution time of the interrupt service routine, and the length of the waiting queue.

[0023] As a preferred embodiment of the multi-chip interrupt scheduling method based on RISC-V architecture described in this invention, the step of forming a chip interrupt pressure table refers to establishing a chip interrupt pressure record based on the RISC-V chip number, writing the number of interrupts, interrupt service routine execution time, waiting queue length, and chip interrupt pressure corresponding to each RISC-V chip into the same chip interrupt pressure record, and then arranging the chip interrupt pressure records in ascending order of RISC-V chip number.

[0024] As a preferred embodiment of the multi-chip interrupt scheduling method based on RISC-V architecture described in this invention, the selection of the target RISC-V chip specifically includes:

[0025] Read the chip interrupt pressure corresponding to the default service chip in the chip interrupt pressure table, and compare the chip interrupt pressure with the preset hot zone threshold.

[0026] When the interrupt pressure of the default service chip is less than or equal to the preset hot zone threshold, the default service chip will be selected as the target RISC-V chip.

[0027] When the chip interrupt pressure corresponding to the default service chip is greater than the preset hot zone threshold, the set of migrated chips corresponding to the peripheral interrupt source number is read from the edge interrupt autonomous table.

[0028] Remove RISC-V chips from the set of migrated chips whose interrupt pressure exceeds the preset hot zone threshold. Then, read the link delay from the default service chip to the remaining RISC-V chips in the set of migrated chips according to the inter-chip interrupt link. Sort the link delays in ascending order of value and select the RISC-V chip with the smallest link delay as the target RISC-V chip.

[0029] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the step of forming the interrupt execution window mapping table specifically involves:

[0030] Extract the interrupt level, interrupt cutoff time, and interrupt service routine entry address corresponding to the peripheral interrupt source number in the edge interrupt autonomous table. Based on the interrupt reception record and interrupt execution record corresponding to the target RISC-V chip, determine the interrupt requests that have been received in the target RISC-V chip but have not yet formed a processing completion flag.

[0031] The already occupied lockstep time window is identified based on the execution time of the interrupt service routine corresponding to the interrupt request that has been received but has not yet generated a processing completion flag;

[0032] Candidate lockstep time windows that allow the execution of interrupt service routines are extracted from the preset lockstep time window rules according to the interrupt level;

[0033] Remove candidate lockstep time windows that overlap with already occupied lockstep time windows, and then filter from the remaining candidate lockstep time windows that have an end time no later than the interruption deadline.

[0034] The selected lockstep time windows are sorted from earliest to latest according to their start time, and the lockstep time window with the earliest start time is matched to the target RISC-V chip.

[0035] The peripheral interrupt source number, target RISC-V chip, interrupt level, interrupt deadline, interrupt service routine entry address, and the start and end times of the lockstep time window are written into the same record table to form an interrupt execution window mapping table.

[0036] As a preferred embodiment of the multi-chip interrupt scheduling method based on RISC-V architecture described in this invention, the calculation and prediction of the wake-up time specifically involves:

[0037] Read the target RISC-V chip, lockstep time window, and interrupt cutoff time corresponding to the peripheral interrupt source number in the interrupt execution window mapping table, and read the wake-up time required for the target RISC-V chip to switch from the current low-power state to the running state;

[0038] The predicted wake-up time is obtained by calculating the difference between the start time of the lockstep time window and the wake-up time.

[0039] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the step of waking up the target RISC-V chip in advance specifically includes:

[0040] When the predicted wake-up time is reached, read the corresponding peripheral interrupt source number, target RISC-V chip, lockstep time window and interrupt service routine entry address from the interrupt execution window mapping table.

[0041] The peripheral interrupt source number, lockstep time window, and interrupt service routine entry address are merged according to the field order to form a wake-up instruction;

[0042] When the target RISC-V chip is the default service chip, the wake-up command is written to the target RISC-V chip. When the target RISC-V chip is not the default service chip, the wake-up command is sent to the target RISC-V chip according to the inter-chip interrupt link, thus completing the early wake-up.

[0043] As a preferred embodiment of the multi-chip interrupt scheduling method based on the RISC-V architecture described in this invention, the step of obtaining the edge autonomous interrupt scheduling result specifically involves:

[0044] Based on the target RISC-V chip, interrupt service routine entry address, and lockstep time window in the interrupt execution window mapping table, at the start of the lockstep time window, the target RISC-V chip is controlled to execute the interrupt service routine according to the interrupt service routine entry address, and the current execution position and unfinished processing content of the interrupt service routine are recorded.

[0045] When the target RISC-V chip is waiting for inter-chip resources to return during the execution of the interrupt service routine, the target RISC-V chip is removed from the set of migrated chips in the edge interrupt autonomous table, and then the RISC-V chip with the smallest link latency is selected as the successor RISC-V chip.

[0046] The peripheral interrupt source number, interrupt service routine entry address, current execution position, and unfinished processing content are sent to the relay RISC-V chip via the inter-chip interrupt link, and the relay RISC-V chip continues to process the unfinished processing content from the current execution position;

[0047] After the unfinished processing is completed, the peripheral interrupt source number, target RISC-V chip, relay RISC-V chip, interrupt service routine completion time, and processing completion identifier are associated and recorded to obtain the edge autonomous interrupt scheduling result.

[0048] In a second aspect, this application provides an electronic device, including: a processor; and a memory storing program instructions that, when executed by the processor, cause the electronic device to implement one or more embodiments of the first aspect described above.

[0049] Thirdly, this application provides a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by one or more processors, implement one or more embodiments of the first aspect described above.

[0050] The beneficial effects of this invention are as follows: By constructing a multi-dimensional chip interrupt pressure table and combining it with hot zone threshold judgment, accurate quantification and dynamic perception of the load of RISC-V multi-chip system are achieved, providing a decision-making basis for intelligent scheduling. Utilizing a lockstep time window mechanism, this invention pre-allocates conflict-free deterministic execution slots for interrupt services of different priorities, eliminating time competition at the source and effectively ensuring hard real-time performance. It can effectively avoid problems such as interrupt request backlog, increased response latency, and deadline failure when local chips enter a high-load state. By utilizing the inter-chip collaborative processing flow, interrupt services are allowed to seamlessly migrate to other chips to continue execution while waiting for resources, breaking the physical limitations of single-chip processing capabilities, improving throughput, and achieving load balancing while ensuring low power consumption and high real-time performance. This enhances the scheduling flexibility and responsiveness of the multi-chip architecture and can effectively avoid the problem of time window conflicts or real-time response failures that may still occur after interrupt migration. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart of a multi-chip interrupt scheduling method based on RISC-V architecture provided in an embodiment of the present invention.

[0053] Figure 2 This is a flowchart illustrating the formation of an interrupt execution window mapping table in a multi-chip interrupt scheduling method based on RISC-V architecture provided in an embodiment of the present invention.

[0054] Figure 3 This is a flowchart illustrating the formation of a chip interrupt pressure table in a multi-chip interrupt scheduling method based on RISC-V architecture provided in an embodiment of the present invention.

[0055] Figure 4 This is a flowchart illustrating the formation of an edge interrupt autonomous table in a multi-chip interrupt scheduling method based on RISC-V architecture provided in an embodiment of the present invention. Detailed Implementation

[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0057] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0058] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0059] Reference Figures 1-4 This is one embodiment of the present invention, which provides a multi-chip interrupt scheduling method based on a RISC-V architecture, comprising the following steps:

[0060] S1: Collect the serial number of each RISC-V chip, the inter-chip interrupt link, and the peripheral interrupt source number.

[0061] It should be noted that the edge computing device initiates a configuration record to read each RISC-V chip involved in interrupt handling, assigns a unique number to each RISC-V chip, and records it as the RISC-V chip number; it reads the inter-chip connection ports used to transmit interrupt requests between each RISC-V chip, the source RISC-V chip number, the destination RISC-V chip number, and the link transmission delay, and records the source RISC-V chip number, destination RISC-V chip number, and link transmission delay according to their correspondence as inter-chip interrupt links; it configures a PLIC extended interrupt control structure with target route configuration capability in the edge computing device. The PLIC extended interrupt control structure includes an interrupt source number register, an interrupt pending status register, an interrupt enable register, an interrupt priority register, and a target route configuration register. Each peripheral interrupt source corresponds to one interrupt source number register entry, one pending bit in the interrupt pending status register, one priority bit in the interrupt priority register, and one target route configuration register entry. Each RISC-V chip has an enable bit configured in its interrupt receive context corresponding to the peripheral interrupt source number. When a peripheral interrupt source issues an interrupt request, the pending bit corresponding to the peripheral interrupt source number is in a valid state. When the peripheral interrupt source number corresponds to the RISC-V chip number recorded in the target routing configuration register, and the enable bit in the interrupt receive context corresponding to the RISC-V chip is in an enabled state, the corresponding interrupt request is routed to the RISC-V chip recorded in the target routing configuration register. When multiple pending bits are in a valid state at the same time, the interrupt request forwarding order is selected according to the hardware interrupt arbitration priority represented by the corresponding priority bit. The interrupt source identifier value corresponding to each peripheral interrupt source is read from the interrupt source number register, and the interrupt source identifier value is used as the peripheral interrupt source number. The RISC-V chip number corresponding to the peripheral interrupt source number is read from the target routing configuration register, and the peripheral interrupt source number is associated with the RISC-V chip number receiving the corresponding interrupt request.

[0062] S2: Based on the serial numbers of each RISC-V chip and the peripheral interrupt source serial numbers, filter the default service chip and the set of migrateable chips to form an edge interrupt autonomous table.

[0063] S2.1: It should be noted that, based on the RISC-V chip number, the corresponding operating status record of each RISC-V chip is accessed. The processing cores in each RISC-V chip used for handling interrupt service routines are read one by one to determine whether they are currently executing interrupt service routines. Processing cores currently executing interrupt service routines are recorded as occupied, and those not executing interrupt service routines are recorded as idle, thus obtaining the core occupancy status. The duration required for the corresponding RISC-V chip to switch from the current low-power state to the running state is read, and this duration is recorded as the wake-up time. Interrupt requests received but not yet executed by each RISC-V chip are read, and the execution time of the interrupt service routine corresponding to each interrupt request is accumulated. The accumulated result is recorded as the current queuing time. Interrupt attribute records are accessed one by one according to the peripheral interrupt source number, and the interrupt level, interrupt deadline, and interrupt service routine entry address corresponding to the peripheral interrupt source number are read.

[0064] Furthermore, the interrupt attribute record construction process is as follows: When a peripheral interrupt source is connected to the RISC-V chip, the interrupt request type, the allowed interrupt response deadline constraint, and the interrupt service routine storage address corresponding to the peripheral interrupt source number are read according to the peripheral interrupt source number. The interrupt deadline refers to the maximum duration allowed to complete the interrupt response from the moment the interrupt request corresponding to the peripheral interrupt source number is received. According to the preset interrupt level range to which the deadline constraint belongs, the corresponding interrupt level is written for the peripheral interrupt source number, and the deadline constraint is written as the corresponding interrupt deadline. For example, when the deadline constraint corresponding to the actuator over-limit feedback signal is 40μs, since 40μs belongs to the first-level interrupt level range of no more than 50μs, the interrupt level corresponding to the actuator over-limit feedback signal is written as the first-level interrupt level, and 40μs is written as the corresponding interrupt deadline. Time; When the cutoff time constraint for the industrial sensor sampling completion signal is 120μs, since 120μs falls within the range corresponding to the second-level interrupt level (greater than 50μs and not greater than 200μs), the interrupt level corresponding to the industrial sensor sampling completion signal is written as the second-level interrupt level, and 120μs is written as the corresponding interrupt cutoff time; When the cutoff time constraint for the status reporting signal is 800μs, since 800μs falls within the range corresponding to the third-level interrupt level (greater than 200μs and not greater than 1000μs), the interrupt level corresponding to the status reporting signal is written as the third-level interrupt level, and 800μs is written as the corresponding interrupt cutoff time; The interrupt service routine storage address is used as the interrupt service routine entry address; The same record is written according to the correspondence between the peripheral interrupt source number, interrupt level, interrupt cutoff time, and interrupt service routine entry address to form an interrupt attribute record.

[0065] The correspondence between interrupt request types and preset interrupt levels is configured as follows: extract the deadline constraints for completing the interrupt response according to the interrupt request type corresponding to the peripheral interrupt source, configure interrupt request types with a deadline constraint of no more than 50μs as Level 1 interrupt, configure interrupt request types with a deadline constraint of more than 50μs but no more than 200μs as Level 2 interrupt, and configure interrupt request types with a deadline constraint of more than 200μs but no more than 1000μs as Level 3 interrupt, so as to form a preset interrupt level correspondence for writing interrupt attribute records.

[0066] S2.2: It should be noted that, for each peripheral interrupt source number, the interrupt deadline corresponding to the peripheral interrupt source number is compared with the wake-up time and current queuing time of each RISC-V chip; for RISC-V chips whose core occupancy is idle and whose sum of wake-up time and current queuing time is less than or equal to the interrupt deadline, they are sorted in ascending order of the sum of wake-up time and current queuing time, and the RISC-V chip at the top of the sort is marked as the default service chip corresponding to the peripheral interrupt source number; for each RISC-V chip other than the default service chip, it is verified whether there is an inter-chip interrupt link that can transmit interrupt requests between the RISC-V chip associated with the peripheral interrupt source number and each RISC-V chip, and the corresponding link transmission delay is read from the inter-chip interrupt link that can transmit interrupt requests; RISC-V chips whose sum of wake-up time, current queuing time and link transmission delay is less than or equal to the interrupt deadline and whose current queuing time is lower than the preset queuing time threshold are grouped according to RISC-V chip number to form a set of transferable chips. The correspondences between peripheral interrupt source numbers, default service chips, set of transferable chips, interrupt levels, interrupt cutoff times, and interrupt service routine entry addresses are arranged to form an autonomous edge interrupt table.

[0067] Furthermore, the queuing time threshold is set based on the remaining waiting time after deducting the maximum wake-up time of the RISC-V chip and the maximum link delay of the inter-chip interrupt link from the interrupt cutoff time corresponding to the peripheral interrupt source number.

[0068] S3: Based on the edge interrupt autonomous table, the number of interrupts, interrupt service routine execution time and wait queue length of each RISC-V chip are counted, and the interrupt pressure of each RISC-V chip is calculated to form a chip interrupt pressure table.

[0069] S3.1: It should be noted that, based on the default service chip and the set of transferable chips in the edge interrupt autonomous table, peripheral interrupt source numbers corresponding to each RISC-V chip are collected according to the RISC-V chip number; within a preset statistical period, interrupt requests issued by peripheral interrupt source numbers are received sequentially, and based on the RISC-V chip number to which the interrupt request actually enters, the peripheral interrupt source number and the interrupt request reception time are written into the interrupt reception record of the corresponding RISC-V chip; at the end of the preset statistical period, the number of records in the interrupt reception record whose interrupt request reception time is within the preset statistical period is counted according to the RISC-V chip number, and the number of records is taken as the number of interrupts received by the corresponding RISC-V chip within the preset statistical period.

[0070] Furthermore, the statistical period is set based on the longest interrupt cutoff time corresponding to the peripheral interrupt source number, the pressure change of the RISC-V chip under continuous interrupt requests to reflect demand, and the response frequency of edge computing nodes to hot zone migration, for example, 20μs.

[0071] S3.2: It should be noted that, based on the peripheral interrupt source number, the corresponding interrupt service routine entry address is located in the edge interrupt autonomous table. When the RISC-V chip starts executing the interrupt service routine according to the interrupt service routine entry address, the peripheral interrupt source number, RISC-V chip number, and start execution time are written into the interrupt execution record. When the RISC-V chip completes the interrupt service routine and writes the processing completion flag, the execution completion time is written into the corresponding interrupt execution record. The difference between the execution completion time and the start execution time corresponding to the same peripheral interrupt source number is calculated to obtain the single interrupt service routine execution time. At the end of the preset statistical period, the single interrupt service routine execution times formed within the preset statistical period are collected according to the RISC-V chip number, and the collected single interrupt service routine execution times are summed to obtain the corresponding RISC-V chip's interrupt service routine execution time within the preset statistical period.

[0072] S3.3: It should be noted that, according to the RISC-V chip number, the interrupt requests received by the corresponding RISC-V chip are verified one by one. Interrupt requests that have been written into the interrupt reception record but not yet into the interrupt execution record are identified as interrupt requests that have not yet been executed. The peripheral interrupt source numbers corresponding to the interrupt requests that have not yet been executed are extracted, and the peripheral interrupt source numbers are arranged in ascending order of interrupt deadline time to form the waiting queue record for the corresponding RISC-V chip. The number of peripheral interrupt source numbers in the waiting queue record is counted, and the counted number is recorded as the waiting queue length for the corresponding RISC-V chip.

[0073] S3.4: It should be noted that the chip interrupt pressure of each RISC-V chip is calculated based on the number of interrupts, the execution time of the interrupt service routine, and the length of the wait queue. The formula is as follows:

[0074] ;

[0075] in, This indicates the interrupt load corresponding to the RISC-V chip number. This indicates the number of interrupts corresponding to the RISC-V chip number. This indicates the execution time of the interrupt service routine corresponding to the RISC-V chip number. This indicates the length of the wait queue corresponding to the RISC-V chip number. This indicates the maximum number of interrupts for each RISC-V chip within a preset statistical period. This indicates the maximum interrupt service routine execution time for each RISC-V chip within a preset statistical period. This indicates the maximum waiting queue length for each RISC-V chip within a preset statistical period. , and These represent the weights for the number of interrupts, the execution time of the interrupt service routine, and the length of the waiting queue, respectively.

[0076] A chip interrupt pressure record is established based on the RISC-V chip number. The number of interrupts, interrupt service routine execution time, wait queue length and chip interrupt pressure for each RISC-V chip are written into the same chip interrupt pressure record. Then, the chip interrupt pressure records are arranged in ascending order of RISC-V chip number to obtain the chip interrupt pressure table.

[0077] Furthermore, since the waiting queue length directly reflects the backlog of interrupt requests that have been received but not yet executed, increasing the waiting queue length will directly prolong the response time of newly arriving interrupt requests, and therefore has the highest weight. For example... The value is 0.45; the interrupt service routine execution time reflects the degree to which the RISC-V chip is continuously occupied by interrupt processing within a preset statistical period. The longer the interrupt service routine execution time, the less time is available to process subsequent interrupt requests, and therefore the corresponding weight is secondary. For example, The value is set to 0.35; the interrupt count only reflects the frequency of interrupt request arrivals. Multiple interrupt requests with short execution times may not necessarily cause significant blocking, therefore the corresponding weight is the smallest, for example... Take 0.20.

[0078] S4: Compare the chip interrupt pressure gauge with the preset hot zone threshold, and select the target RISC-V chip from the set of transferable chips based on the link delay of the inter-chip interrupt link.

[0079] It should be noted that, based on the peripheral interrupt source number in the edge interrupt autonomous table, the corresponding default service chip is located, and based on the RISC-V chip number of the default service chip, the corresponding chip interrupt pressure record is located in the chip interrupt pressure table. The chip interrupt pressure corresponding to the default service chip is extracted from the chip interrupt pressure record. The chip interrupt pressure corresponding to the default service chip is compared with a preset hot zone threshold. When the chip interrupt pressure is less than or equal to the preset hot zone threshold, it indicates that the default service chip can continue to accept the interrupt request corresponding to the peripheral interrupt source number, and the default service chip is selected as the target RISC-V chip. When the chip interrupt pressure is greater than the preset hot zone threshold, it indicates that the interrupt processing load of the default service chip exceeds the preset hot zone threshold, and the corresponding set of migrated chips is located in the edge interrupt autonomous table based on the peripheral interrupt source number. Based on the RISC-V chip numbers in the migrated chip set, locate the corresponding chip interrupt pressure in the chip interrupt pressure table, and delete RISC-V chip numbers whose chip interrupt pressure is greater than the preset hot zone threshold to obtain a candidate target RISC-V chip set. Based on the RISC-V chip number corresponding to the default service chip and the RISC-V chip numbers in the candidate target RISC-V chip set, locate the corresponding link transmission delay in the inter-chip interrupt link. Arrange the RISC-V chip numbers in the candidate target RISC-V chip set in ascending order of link transmission delay, and when the link transmission delay is the same, arrange them in ascending order of chip interrupt pressure, and select the RISC-V chip at the top of the list as the target RISC-V chip.

[0080] Furthermore, the hot zone threshold is set based on whether the default service chip can meet the interrupt cutoff time corresponding to the peripheral interrupt source number when it continues to accept interrupt requests within a preset statistical period, for example, 0.7.

[0081] S5: Based on the edge interrupt autonomous table, match the corresponding lockstep time window for the target RISC-V chip to form an interrupt execution window mapping table.

[0082] S5.1: It should be noted that, based on the peripheral interrupt source number, the corresponding record is located in the edge interrupt autonomous table, and the interrupt level, interrupt deadline, and interrupt service routine entry address corresponding to the peripheral interrupt source number are extracted; based on the interrupt reception record corresponding to the target RISC-V chip, the peripheral interrupt source numbers already received by the target RISC-V chip are collected, and then, based on the interrupt execution record, each received peripheral interrupt source number is verified to see if it corresponds to a processing completion flag. Interrupt requests corresponding to peripheral interrupt source numbers without a processing completion flag are determined as incomplete interrupt requests; for interrupt requests that have started executing the interrupt service routine but have not yet formed a processing completion flag... The following steps are required: First, the start time of the interrupt execution record is used as the window start time, and the sum of the start time and the corresponding single interrupt service routine execution time is used as the window end time. Second, for interrupt requests that have been received but have not yet started executing their interrupt service routines, they are arranged in ascending order of interrupt deadline time. The window end time corresponding to the previous incomplete interrupt request is used as the window start time, and the sum of the window start time and the corresponding estimated execution time is used as the window end time. Third, the time range between the window start time and the window end time corresponding to each incomplete interrupt request is recorded as the occupied lockstep time window corresponding to the target RISC-V chip.

[0083] Furthermore, the process of obtaining the execution time is as follows: Based on the peripheral interrupt source number corresponding to the interrupt request that has been received but has not yet started executing the interrupt service routine, search the existing interrupt execution records for interrupt execution records that correspond to the same peripheral interrupt source number and have already formed a processing completion mark; extract the start execution time and execution completion time from each interrupt execution record, calculate the difference between the execution completion time and the start execution time to obtain the execution time of each single interrupt service routine; calculate the average of the execution times of each single interrupt service routine corresponding to the same peripheral interrupt source number, and record the calculation result as the expected execution time of the corresponding interrupt request; when there is no interrupt execution record corresponding to the same peripheral interrupt source number and has already formed a processing completion mark in the existing interrupt execution records, record the initial execution time corresponding to the peripheral interrupt source number in the interrupt attribute record as the expected execution time of the corresponding interrupt request.

[0084] S5.2: It should be noted that, based on the interrupt level corresponding to the peripheral interrupt source number in the edge interrupt autonomous table, the window configuration record corresponding to the interrupt level is located in the preset lockstep time window rules; wherein, the preset lockstep time window rules configure lockstep time windows in a continuous arrangement according to the interrupt level, with a lockstep time window of length of 50μs corresponding to the first-level interrupt level, a lockstep time window of length of 200μs corresponding to the second-level interrupt level, and a lockstep time window of length of 1000μs corresponding to the third-level interrupt level; starting from the current time, lockstep time windows are sequentially divided within the subsequent executable time range of the target RISC-V chip according to the corresponding window length, and the window start time, window end time, and interrupt level corresponding to each lockstep time window are associated and recorded; lockstep time windows whose interrupt level is consistent with the interrupt level corresponding to the peripheral interrupt source number are grouped into candidate lockstep time windows that allow the execution of interrupt service routines.

[0085] Furthermore, the current moment refers to the real-time timing of the edge computing device during the interrupt scheduling process, which is used to uniformly mark the time position corresponding to interrupt request reception, interrupt service routine execution, lockstep time window matching, and early wake-up trigger; it is collected in real time by the unified timer configured when the edge computing device starts up.

[0086] S5.3: It should be noted that, based on the occupied lockstep time window corresponding to the target RISC-V chip, the start time and end time of each candidate lockstep time window are compared one by one. When the start time of a candidate lockstep time window is earlier than the end time of an occupied lockstep time window, and the end time of a candidate lockstep time window is later than the start time of an occupied lockstep time window, the corresponding candidate lockstep time window is determined as a candidate lockstep time window with time overlap and is deleted from the candidate lockstep time window. For the candidate lockstep time windows retained after deletion, based on the interrupt request reception time corresponding to the peripheral interrupt source number, the difference between the end time of the candidate lockstep time window and the interrupt request reception time is calculated, and the difference is compared with the interrupt cutoff time corresponding to the peripheral interrupt source number in the edge interrupt autonomous table. The candidate lockstep time windows with a difference less than or equal to the interrupt cutoff time are determined as lockstep time windows that meet the interrupt cutoff time. Arrange the lockstep time windows that meet the interrupt deadline in ascending order of their start times. If lockstep time windows have the same start time, arrange them in ascending order of their end times. Extract the start and end times of the first lockstep time window in the order and assign it to the target RISC-V chip. Record the peripheral interrupt source number, target RISC-V chip, interrupt level, interrupt deadline, interrupt service routine entry address, and the lockstep time window assigned to the target RISC-V chip.

[0087] Based on the lockstep time window already matched to the target RISC-V chip, extract the window start time and window end time of the lockstep time window; locate the corresponding interrupt level, interrupt deadline time, and interrupt service routine entry address in the edge interrupt autonomous table based on the peripheral interrupt source number; write the peripheral interrupt source number, target RISC-V chip, interrupt level, interrupt deadline time, interrupt service routine entry address, and the window start time and window end time of the lockstep time window into the same record table according to the field order to form an interrupt execution window mapping record; for each subsequent lockstep time window matched to the target RISC-V chip, write the corresponding interrupt execution window mapping record according to the same field order, and arrange the interrupt execution window mapping records in order of window start time from earliest to latest to form an interrupt execution window mapping table.

[0088] S6: Calculate the predicted wake-up time based on the interrupt execution window mapping table, and wake up the target RISC-V chip in advance.

[0089] S6.1: It should be noted that, based on the peripheral interrupt source number, the corresponding interrupt execution window mapping record is located in the interrupt execution window mapping table. From the interrupt execution window mapping record, the target RISC-V chip, the start time of the lockstep time window, the end time of the lockstep time window, and the interrupt cutoff time are extracted. Based on the RISC-V chip number corresponding to the target RISC-V chip, the running status record is accessed to verify whether the target RISC-V chip is currently in a low-power state. The duration required for the target RISC-V chip to switch from the current low-power state to the running state is extracted and recorded as the wake-up time corresponding to the target RISC-V chip. The difference between the lockstep time window start time and the wake-up time is calculated to obtain the predicted wake-up time.

[0090] The current time is compared with the predicted wake-up time corresponding to the peripheral interrupt source number. When the current time equals the predicted wake-up time, the corresponding interrupt execution window mapping record is located in the interrupt execution window mapping table according to the peripheral interrupt source number. The peripheral interrupt source number, target RISC-V chip, window start time of the lockstep time window, window end time of the lockstep time window, and interrupt service routine entry address are extracted from the interrupt execution window mapping record. The peripheral interrupt source number, window start time of the lockstep time window, window end time of the lockstep time window, and interrupt service routine entry address are merged according to the field order to form a wake-up instruction.

[0091] S6.2: It should be noted that, based on the peripheral interrupt source number, the corresponding default service chip is located in the edge interrupt autonomous table, and the RISC-V chip number corresponding to the default service chip is compared with the RISC-V chip number corresponding to the target RISC-V chip in the interrupt execution window mapping table; when the RISC-V chip number corresponding to the target RISC-V chip matches the RISC-V chip number corresponding to the default service chip, the wake-up command is sent to the target RISC-V chip through the chip power management unit or the CLINT / PLIC wake-up source, so that the target RISC-V chip switches from the current low-power state according to the peripheral interrupt source number, interrupt service routine entry address and lockstep time window in the wake-up command. Switch to running state; when the RISC-V chip number corresponding to the target RISC-V chip is inconsistent with the RISC-V chip number corresponding to the default service chip, determine the interrupt request transmission starting point based on the association record between the peripheral interrupt source number and the RISC-V chip number receiving the corresponding interrupt request, and send the wake-up command from the interrupt request transmission starting point to the target RISC-V chip according to the inter-chip interrupt link, so that the target RISC-V chip switches from the current low-power state to the running state according to the wake-up command; record the running state in the running state record corresponding to the target RISC-V chip, and verify that the time when the target RISC-V chip enters the running state is earlier than the window start time of the lockstep time window, thus completing the early wake-up.

[0092] S7: Execute the interrupt service routine on the target RISC-V chip after wake-up to obtain the edge autonomous interrupt scheduling result.

[0093] S7.1: It should be noted that, based on the peripheral interrupt source number, the corresponding interrupt execution window mapping record is located in the interrupt execution window mapping table, and the target RISC-V chip, interrupt service routine entry address, lockstep time window start time, and lockstep time window end time are extracted; the current time is compared with the lockstep time window start time, and when the current time is equal to the lockstep time window start time, the interrupt service routine entry address is written into the corresponding program execution entry register of the target RISC-V chip, so that the target RISC-V chip starts executing the interrupt service routine corresponding to the peripheral interrupt source number from the interrupt service routine entry address; during the execution of the interrupt service routine by the target RISC-V chip, the end address corresponding to the program segment that has been processed is recorded as the current execution position of the interrupt service routine, and the program segments that have not been completed and need to wait for inter-chip resource return after the current execution position and their corresponding processing data are recorded as unprocessed content. Record the peripheral interrupt source number, target RISC-V chip, interrupt service routine entry address, lockstep time window, current execution position, and unfinished processing content accordingly. This will provide a basis for selecting the successor RISC-V chip and migrating the remaining interrupt service routines when the target RISC-V chip is waiting for inter-chip resources to return.

[0094] S7.2: It should be noted that when the target RISC-V chip needs to access shared resources or data structures occupied by other chips during the execution of an interrupt service routine, the target RISC-V chip issues an inter-chip resource request through the inter-chip interrupt link or shared resource arbitration logic; if no resource availability result is received from the receiving chip through the inter-chip interrupt link or resource return signal within the preset resource return waiting time, the corresponding interrupt service routine is determined to be in an inter-chip resource waiting state; the corresponding set of transferable chips is located in the edge interrupt autonomous table according to the peripheral interrupt source number, and the target RISC-V chip is removed from the set of transferable chips. The RISC-V chip number corresponding to the V chip is used to obtain the relay candidate chip set. Based on the RISC-V chip number corresponding to the target RISC-V chip and the RISC-V chip numbers in the relay candidate chip set, the link transmission delay from the target RISC-V chip to each relay candidate chip is located in the inter-chip interrupt link. The RISC-V chips in the relay candidate chip set are arranged in ascending order of link transmission delay, and when the link transmission delay is the same, they are arranged in ascending order of chip interrupt pressure. The RISC-V chip ranked first is selected as the relay RISC-V chip.

[0095] S7.3: It should be noted that, based on the peripheral interrupt source number, interrupt service routine entry address, current execution position, and unfinished processing content recorded by the target RISC-V chip, the peripheral interrupt source number, interrupt service routine entry address, current execution position, and unfinished processing content are merged according to the field order to form the remaining interrupt service routine stage; according to the RISC-V chip number corresponding to the target RISC-V chip and the RISC-V chip number corresponding to the relay RISC-V chip, the transmission path from the target RISC-V chip to the relay RISC-V chip is located in the inter-chip interrupt link, and the remaining interrupt service routine stage is sent to the relay RISC-V chip along the transmission path; after receiving the remaining interrupt service routine stage, the relay RISC-V chip verifies the corresponding interrupt service routine entry address according to the peripheral interrupt source number, locates the starting position of the unfinished execution in the interrupt service routine according to the current execution position, and uses the unfinished processing content as the processing input required for continued execution; the relay RISC-V chip starts executing the unfinished processing process in the interrupt service routine from the current execution position until the unfinished processing content is completed.

[0096] When the relay RISC-V chip completes the unfinished processing, the interrupt service routine completion time recorded by the relay RISC-V chip is extracted, and the flag value indicating that the unfinished processing has been completed is recorded as the processing completion flag. Based on the peripheral interrupt source number, the target RISC-V chip and the interrupt service routine entry address in the interrupt execution window mapping table are associated, and the relay RISC-V chip selected during the inter-chip interrupt link transmission is also associated. The peripheral interrupt source number, target RISC-V chip, relay RISC-V chip, interrupt service routine completion time, and processing completion flag are written into the same interrupt scheduling result record in the order of the fields. The interrupt scheduling result records are arranged according to the peripheral interrupt source number and the interrupt service routine completion time to obtain the edge autonomous interrupt scheduling result.

[0097] In summary, this invention achieves accurate quantification and dynamic perception of the load on a RISC-V multi-chip system by constructing a multi-dimensional chip interrupt pressure table and combining it with hot zone threshold judgment, providing a decision-making basis for intelligent scheduling. Utilizing a lockstep time window mechanism, this invention pre-allocates conflict-free deterministic execution slots for interrupt services of different priorities, eliminating time races at the source and effectively ensuring hard real-time performance. By leveraging inter-chip failover processing, interrupt services are allowed to seamlessly migrate to other chips to continue execution while waiting for resources, breaking the physical limitations of single-chip processing power and improving throughput. While ensuring low power consumption and high real-time performance, it achieves load balancing and enhances the scheduling flexibility and responsiveness of the multi-chip architecture.

[0098] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

[0099] Based on the foregoing description in conjunction with the accompanying drawings, those skilled in the art will understand that the embodiments of this application can also be implemented by software programs. Therefore, this application also provides a computer-readable storage medium. This computer-readable storage medium stores computer-readable instructions thereon, which, when executed by one or more processors, implement the method described above in conjunction with the accompanying drawings.

[0100] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computing device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0101] It should be noted that although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0102] It should be understood that when the terms "first," "second," "third," and "fourth," etc., are used in the claims, specification, and drawings of this application, they are used only to distinguish different objects and not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0103] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0104] Although the embodiments of this application are described above, the content is merely an example adopted for the purpose of facilitating understanding of this application and is not intended to limit the scope and application scenarios of this application. Any person skilled in the art described in this application may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A multi-chip interrupt scheduling method based on RISC-V architecture, characterized in that: include, Collect the serial number, inter-chip interrupt link, and peripheral interrupt source number of each RISC-V chip; Based on the serial numbers of each RISC-V chip and the peripheral interrupt source numbers, the default service chip and the set of migrateable chips are selected to form an edge interrupt autonomous table; After calculating the number of interrupts, interrupt service routine execution time and wait queue length of each RISC-V chip based on the edge interrupt autonomy table, the interrupt pressure of each RISC-V chip is calculated to form a chip interrupt pressure table. The chip interrupt pressure gauge is compared with the preset hot zone threshold, and the target RISC-V chip is selected from the set of transferable chips based on the link delay of the inter-chip interrupt link. Based on the edge interrupt autonomy table, a corresponding lockstep time window is matched for the target RISC-V chip to form an interrupt execution window mapping table; Based on the interrupt execution window mapping table, calculate the predicted wake-up time and wake up the target RISC-V chip in advance; The interrupt service routine is executed on the target RISC-V chip after it is woken up, and the edge autonomous interrupt scheduling result is obtained.

2. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 1, characterized in that: The selection of the default service chip and the set of transferable chips specifically includes: Based on the RISC-V chip number, read the core occupancy status, wake-up time and current queuing time of each RISC-V chip one by one, and collect the corresponding interrupt level, interrupt cutoff time and interrupt service routine entry address one by one according to the peripheral interrupt source number. RISC-V chips that meet the interrupt deadline and whose core occupancy status is idle are marked as default service chips. RISC-V chips that meet the interrupt deadline, have reachable inter-chip interrupt links, and whose current queuing time is lower than a preset queuing time threshold, other than the default service chips, are grouped into a set of migrateable chips.

3. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 2, characterized in that: The formation of the edge interrupt autonomous table refers to arranging the correspondence between peripheral interrupt source number, default service chip, set of transferable chips, interrupt level, interrupt cutoff time and interrupt service routine entry address to form the edge interrupt autonomous table.

4. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 3, characterized in that: The interrupt pressure of the computing chip is specifically: Based on the edge interrupt autonomy table, peripheral interrupt source numbers are collected according to RISC-V chip numbers, and the number of interrupts received by each RISC-V chip within a preset statistical period is counted. Based on the entry address of the interrupt service routine corresponding to each peripheral interrupt source number, the execution time of the corresponding interrupt service routine from the start to the completion of execution is recorded to obtain the execution time of the interrupt service routine. Collect the number of peripheral interrupt source numbers that have not yet been executed in each RISC-V chip to obtain the length of the waiting queue; The chip interrupt pressure of each RISC-V chip is calculated based on the number of interrupts, the execution time of the interrupt service routine, and the length of the waiting queue.

5. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 4, characterized in that: The process of creating a chip interrupt pressure table refers to establishing a chip interrupt pressure record based on the RISC-V chip number. The number of interrupts, interrupt service routine execution time, wait queue length, and chip interrupt pressure corresponding to each RISC-V chip are written into the same chip interrupt pressure record. Then, the chip interrupt pressure records are arranged in ascending order of the RISC-V chip number.

6. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 1, characterized in that: The selection of the target RISC-V chip specifically involves: Read the chip interrupt pressure corresponding to the default service chip in the chip interrupt pressure table, and compare the chip interrupt pressure with the preset hot zone threshold. When the interrupt pressure of the default service chip is less than or equal to the preset hot zone threshold, the default service chip will be selected as the target RISC-V chip. When the chip interrupt pressure corresponding to the default service chip is greater than the preset hot zone threshold, the set of migrated chips corresponding to the peripheral interrupt source number is read from the edge interrupt autonomous table. Remove RISC-V chips from the set of migrated chips whose interrupt pressure exceeds the preset hot zone threshold. Then, read the link delay from the default service chip to the remaining RISC-V chips in the set of migrated chips according to the inter-chip interrupt link. Sort the link delays in ascending order of value and select the RISC-V chip with the smallest link delay as the target RISC-V chip.

7. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 1, characterized in that: The formation of the interrupt execution window mapping table is specifically as follows: Extract the interrupt level, interrupt cutoff time, and interrupt service routine entry address corresponding to the peripheral interrupt source number in the edge interrupt autonomous table. Based on the interrupt reception record and interrupt execution record corresponding to the target RISC-V chip, determine the interrupt requests that have been received in the target RISC-V chip but have not yet formed a processing completion flag. The already occupied lockstep time window is identified based on the execution time of the interrupt service routine corresponding to the interrupt request that has been received but has not yet generated a processing completion flag; Candidate lockstep time windows that allow the execution of interrupt service routines are extracted from the preset lockstep time window rules according to the interrupt level; Remove candidate lockstep time windows that overlap with already occupied lockstep time windows, and then filter from the remaining candidate lockstep time windows that have an end time no later than the interruption deadline. The selected lockstep time windows are sorted from earliest to latest according to their start time, and the lockstep time window with the earliest start time is matched to the target RISC-V chip. The peripheral interrupt source number, target RISC-V chip, interrupt level, interrupt deadline, interrupt service routine entry address, and the start and end times of the lockstep time window are written into the same record table to form an interrupt execution window mapping table.

8. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 7, characterized in that: The calculation and prediction of the wake-up time specifically involves: Read the target RISC-V chip, lockstep time window, and interrupt cutoff time corresponding to the peripheral interrupt source number in the interrupt execution window mapping table, and read the wake-up time required for the target RISC-V chip to switch from the current low-power state to the running state; The predicted wake-up time is obtained by calculating the difference between the start time of the lockstep time window and the wake-up time.

9. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 8, characterized in that: The aforementioned early wake-up of the target RISC-V chip specifically refers to: When the predicted wake-up time is reached, read the corresponding peripheral interrupt source number, target RISC-V chip, lockstep time window and interrupt service routine entry address from the interrupt execution window mapping table. The peripheral interrupt source number, lockstep time window, and interrupt service routine entry address are merged according to the field order to form a wake-up instruction; When the target RISC-V chip is the default service chip, the wake-up command is written to the target RISC-V chip. When the target RISC-V chip is not the default service chip, the wake-up command is sent to the target RISC-V chip according to the inter-chip interrupt link, thus completing the early wake-up.

10. The multi-chip interrupt scheduling method based on RISC-V architecture as described in claim 9, characterized in that: The specific details of obtaining the edge autonomous interrupt scheduling result are as follows: Based on the target RISC-V chip, interrupt service routine entry address, and lockstep time window in the interrupt execution window mapping table, at the start of the lockstep time window, the target RISC-V chip is controlled to execute the interrupt service routine according to the interrupt service routine entry address, and the current execution position and unfinished processing content of the interrupt service routine are recorded. When the target RISC-V chip is waiting for inter-chip resources to return during the execution of the interrupt service routine, the target RISC-V chip is removed from the set of migrated chips in the edge interrupt autonomous table, and then the RISC-V chip with the smallest link latency is selected as the successor RISC-V chip. The peripheral interrupt source number, interrupt service routine entry address, current execution position, and unfinished processing content are sent to the relay RISC-V chip via the inter-chip interrupt link, and the relay RISC-V chip continues to process the unfinished processing content from the current execution position; After the unfinished processing is completed, the peripheral interrupt source number, target RISC-V chip, relay RISC-V chip, interrupt service routine completion time, and processing completion identifier are associated and recorded to obtain the edge autonomous interrupt scheduling result.

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