Instruction stream generation method, apparatus, device, and storage medium

Abstract

The application provides an instruction stream generation method and device, equipment and storage medium, and relates to the technical field of computers. The application flexibly configures the initial state of an instruction generator and a virtual predictor according to a configuration file, ensures that the generated instruction stream meets specific constraint conditions, the instruction generator determines a current generation mode according to a generation mode probability distribution, introduces randomness to cover more scenarios, generates a current instruction under the current generation mode, and guarantees the correctness and standardization of the instruction through legality detection, inputs the legal instruction into the virtual predictor, predicts the influence of the instruction on a branch prediction unit, evaluates the potential effect of the instruction on the behavior of the BPU in advance, and adds the instruction to the instruction stream when the prediction result meets preset expected conditions, so that the generated instruction stream can effectively verify the key behavior of the BPU, is especially suitable for the verification of a complex multi-level branch prediction algorithm, improves the verification efficiency and coverage, and reduces the difficulty of manually writing test cases.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device and storage medium for generating instruction streams. Background Technology

[0002] With the continuous development of processor architecture, the Branch Prediction Unit (BPU) has become an indispensable module in modern high-performance processors. The main function of the BPU is to predict the program's execution path in advance when encountering branch instructions, thereby reducing pipeline stalls and improving instruction execution efficiency. The accuracy of the BPU directly affects the processor's performance; therefore, verifying its functionality and performance is particularly important.

[0003] With the advancement of prediction algorithms, the verification of BPU currently mainly includes the following methods: (1) Manually writing instruction streams, which can construct targeted test cases for specific corner (extreme / special) scenarios. However, the workload is large and it is difficult to cover complex random scenarios, so it can only be used as a supplement to verification; (2) Random instruction stream generators, which use automated tools such as RISCV-DV to generate large-scale random instruction streams, which contain a certain proportion of branch instructions. These can cover most scenarios, but the instruction streams are mostly randomly distributed and it is difficult to cover the extreme or special behaviors of BPU; (3) System-level simulation platforms, which use virtual platforms such as RISCV-OVPsim to run operating systems or applications and verify branch prediction behavior through actual program execution. This can verify the performance of BPU in a real software environment, but it is mainly used for functional verification of multi-core systems, system integration testing, and software compatibility testing, and it is also difficult to cover corner scenarios.

[0004] However, the existing technology has the following shortcomings: (1) Most of the existing automation tools generate general random instruction streams, which cannot be specifically generated for the key behaviors of BPU, resulting in incomplete BPU function verification; (2) It is difficult to accurately control dynamic parameters such as branch instruction type, branch loop depth, and branch history, which makes it difficult to fully verify some corner scenarios; (3) For the verification of complex multi-level branch prediction algorithms, it is extremely difficult and inefficient to manually write test cases.

[0005] Therefore, the low efficiency of functional verification of branch prediction units in existing technologies has become a pressing technical problem that needs to be solved. Summary of the Invention

[0006] This application provides an instruction stream generation method, apparatus, device, and storage medium, aiming to solve the technical problem of low accuracy of instruction stream generation parameters in the prior art, which leads to incomplete functional verification of the branch prediction unit, so as to improve the functional verification efficiency of the branch prediction unit.

[0007] Firstly, this application provides a method for generating an instruction stream, the method comprising the following steps: Configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file; In the initial state, the instruction generator determines the current generation mode of the instruction generator according to the probability distribution of the generation mode; Based on the instruction generation constraints, the instruction generator generates the current instruction in the current generation mode; Perform a validity check on the current instruction and obtain the detection result of the current instruction; When the detection result of the current instruction is that the instruction is valid, the current instruction is input into the virtual predictor so as to predict the impact of the current instruction on the branch prediction unit and obtain the impact prediction result corresponding to the current instruction. When the predicted impact result corresponding to the current instruction meets the preset expected conditions, the current instruction is added to the instruction stream.

[0008] Secondly, this application also provides an instruction stream generation apparatus, the instruction stream generation apparatus comprising: An initial state configuration module is used to configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file. A generation mode determination module is used to determine the current generation mode of the instruction generator based on the generation mode probability distribution in the initial state. The instruction generation module is used to generate instructions based on the instruction generation constraints, and the instruction generator generates the current instruction in the current generation mode. A legality detection module is used to perform legality detection on the current instruction and obtain the detection result of the current instruction; The instruction prediction module is used to input the current instruction into the virtual predictor when the detection result of the current instruction is that the instruction is legal, so as to predict the impact of the current instruction on the branch prediction unit through the virtual predictor and obtain the impact prediction result corresponding to the current instruction. The instruction stream construction module is used to add the current instruction to the instruction stream when the influence prediction result corresponding to the current instruction meets the preset expected conditions.

[0009] Thirdly, this application also provides a computer device, the computer device including a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the instruction stream generation method described above.

[0010] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the instruction stream generation method described above.

[0011] This application provides an instruction stream generation method, apparatus, computer device, and storage medium. The method flexibly configures the initial states of the instruction generator and virtual predictor according to a configuration file, ensuring that the generated instruction stream meets specific constraints. The instruction generator determines the current generation mode based on the probability distribution of the generation mode, introducing randomness to cover more scenarios. The current instruction is generated under the current generation mode, and its correctness and standardization are ensured through legality checks. The legal instruction is input into the virtual predictor to predict its impact on the branch prediction unit, thus assessing the potential effect of the instruction on the BPU's behavior in advance. When the prediction result meets the preset expected conditions, the instruction is added to the instruction stream, ensuring that the generated instruction stream can effectively verify the key behaviors of the BPU. This is particularly suitable for verifying complex multi-level branch prediction algorithms, improving verification efficiency and coverage, and reducing the difficulty of manually writing test cases. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This application provides an instruction stream generation platform structure. Figure 2 This is a flowchart illustrating an embodiment of an instruction stream generation method provided in this application. Figure 3 A schematic diagram of configurable items for an instruction stream generation platform provided in an embodiment of this application; Figure 4 This is a schematic diagram of the instruction stream generation process provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an embodiment of an instruction stream generation device provided in this application; Figure 6 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.

[0014] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the described order. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0017] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] In one embodiment, the instruction stream generation method provided in this application is applied to, for example, Figure 1 The instruction stream generation platform shown is designed to generate instruction streams that conform to the behavior characteristics of the branch prediction unit (BPU) while satisfying various constraints to support the testing and verification of hardware predictors.

[0019] like Figure 1 As shown, the instruction stream generation platform consists of a virtual predictor 11, an instruction generator 12, a predictor behavior analyzer 13, constraints 14 for different types of instructions, and constraints 15 corresponding to different generation modes.

[0020] The instruction generator is responsible for performing constrained randomization of instructions and checking instruction validity; the virtual predictor is responsible for providing the prediction results and internal update information of the BPU for the currently randomly generated instructions under ideal conditions; the coverage instruction generator is responsible for providing the coverage of the current instruction flow under ideal conditions for the behavior of BPU internal entries; the constraints of the instruction and the constraints of the generation mode jointly restrict the program counter (PC) value, type, whether to jump, and jump target address of the current instruction.

[0021] Specifically, the instruction generator is responsible for generating the instruction stream and ensuring that the generated instructions conform to the constraints. Based on the probability distribution of the generation pattern and the instruction constraints, the instruction generator randomly generates instructions and performs a validity check on the generated instructions to ensure that the PC value, instruction type, jump target address, etc., meet the constraints. Simultaneously, during the instruction generation process, the generation strategy is dynamically adjusted to best meet the expectations of the constraints on the BPU's behavior.

[0022] The virtual predictor is the core module in the platform used to simulate the behavior of the branch prediction unit (BPU). Based on the characteristics of the instruction flow, it provides the BPU prediction results under ideal conditions, including: the prediction result of the current instruction (such as whether to jump), the update information of the internal state of the BPU (such as entry allocation, historical information update, etc.), and the coverage statistics of the predictor behavior, which are used to analyze the coverage of the instruction flow on the internal entries of the BPU.

[0023] The predictor behavior analyzer is used to analyze the impact of instruction flow on BPU behavior, to statistically analyze the coverage of BPU internal entries, to evaluate the degree of coverage of the instruction flow on predictor behavior, and to provide detailed analysis results of predictor behavior for optimizing instruction flow generation strategies.

[0024] The generation pattern constraint defines the mode and probability distribution of instruction generation, which is used to specify the generation mode of instruction stream (such as random generation of single instructions, random generation of block instructions, etc.) and restrict the characteristics of instruction stream (such as instruction block size, instruction probability distribution, etc.).

[0025] Instruction constraints are specific restrictions on instruction generation, including limiting the range of PC values, instruction type, whether to jump and the jump target address, and ensuring that the generated instructions conform to hardware behavior and configuration file requirements.

[0026] In one specific embodiment, in this instruction stream generation platform, the instruction generator randomly generates instructions based on generation mode constraints and instruction constraints. The instruction generator performs a legality check on the instructions to ensure they meet the constraints. The virtual predictor predicts the legal instructions and returns the prediction results and BPU internal state update information. The predictor behavior analyzer calculates the coverage of BPU internal entries based on the prediction results and internal state update information provided by the virtual predictor. The analyzer feeds back the coverage statistics to the instruction generator to optimize the instruction stream generation strategy. The instruction generator saves the generated instruction stream as an instruction stream file and an instruction table file, and the predictor behavior analyzer saves the coverage statistics of BPU behavior as a predictor behavior statistics file.

[0027] The instruction stream generation platform provided in this application has a predictor corresponding to the branch prediction algorithm. It can continuously feed back prediction results, table updates, historical jumps, and other information to the instruction generator as the instruction stream is generated, dynamically adjusting the generation direction of the instruction stream. It has rich configurable options, allowing users to set parameters such as branch instruction type, branch instruction density, loop depth, and branch instruction target, controlling the core mechanism and special scenarios (such as prediction table conflict, extreme jump mode, high-intensity prediction failure, and nested loops) of the instruction stream to hit the BPU, enabling high-efficiency coverage of corner scenarios. It has strong interface versatility, can quickly support different instruction set extensions (such as C extensions) and different BPU prediction algorithms (such as RAS, BTB, Bimodal, TAGE, etc.), and is easy to integrate into the verification platform. It can perform predictor behavior analysis on the generated instruction stream, comprehensively statistically analyze the performance of multi-level predictors, and provide targeted statistical data.

[0028] This instruction stream generation platform, through the collaborative work of multiple modules including a virtual predictor, instruction generator, and predictor behavior analyzer, can generate instruction streams that conform to the behavioral characteristics of a branch prediction unit (BPU) while satisfying various constraints. During instruction generation, the platform dynamically adjusts the generation strategy, optimizes coverage, and ensures the correctness and validity of the instruction stream through validity checks, providing robust support for the testing and verification of hardware predictors.

[0029] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of an instruction stream generation method provided in this application.

[0030] like Figure 2 As shown, the instruction stream generation method includes steps S101 to S106.

[0031] S101. Configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file; In one embodiment, in the instruction stream generation platform, the initial states of the instruction generator and the virtual predictor are set according to configuration files. These configuration items define the behavioral characteristics of the instruction generator and the virtual predictor and impose constraints on the instruction stream generation process.

[0032] In one embodiment, Figure 3 The configurable items for the instruction stream generation platform are given. The predictor parameter structure includes internal algorithm enable, history length, table length, and table entry bit width. The instruction generator parameter structure includes the PC value range, total number of instructions, and jump function length. At the same time, instruction constraints (distribution of different types of instructions, compressed / uncompressed distribution) and generation mode constraints (expected BPU behavior) are also part of the instruction generator parameter structure.

[0033] Specifically, the instruction stream generation platform reads the predictor parameter structure, generator parameter structure, instruction constraints, and generation mode constraints from the configuration file. Based on the predictor parameter structure, it sets the initial state of the virtual predictor, including internal algorithm enablement, history length, table length, and table entry bit width. Based on the generator parameter structure, it sets the initial state of the instruction generator, including the PC value range, total number of instructions, and jump function length. The instruction constraints and generation mode constraints are then loaded into the generator to guide the instruction generation process.

[0034] For example, the instruction stream generation platform configures the initial state of the instruction generator (starting PC, instruction probability distribution, generation mode probability distribution, etc.) and the initial state of the virtual predictor (depth of RAS (Return Address Stack), size of internal table entries / banks, length of global history, length of auxiliary history, relevant parameters of hash algorithm, etc.) according to the configuration file.

[0035] In the initial configuration of the instruction generator, the starting PC sets the starting address of the instruction stream. This is the starting point for instruction execution, and the addresses of subsequent instructions will be calculated and generated based on this. The instruction probability distribution defines the probability of different instruction types appearing in the instruction stream. For example, some instructions (such as branch instructions, arithmetic instructions, etc.) may have different frequencies of occurrence, which will affect the characteristics and behavior of the instruction stream. The generation mode probability distribution specifies the probability of selecting different generation modes. The generation mode determines how the instruction stream is generated, such as sequential generation, random generation, or generation based on specific rules.

[0036] In the initial configuration of the virtual predictor, the depth of the Return Address Stack (RAS) sets the depth of the return address stack. The RAS is mainly used to store the return addresses of function call instructions; the greater the depth, the more return addresses can be stored. The size of the internal table entries / banks defines the size of the predictor's internal table entries. Entries store prediction-related information; an entry represents the size of each entry, and a bank may represent the number of entries or the grouping method. The length of the global history sets the length of the global history register. The global history records the results of a series of recently executed branch instructions; a longer history length provides more contextual information, helping to improve prediction accuracy. The length of the auxiliary history sets the length of the auxiliary history, which may be used in specific prediction algorithms as supplementary or auxiliary information to the global history. The parameters related to the hash algorithm define the parameters required for the hash algorithm, which maps historical information or other relevant data to the predictor's table entries for prediction. These parameters may include the type of hash function, the size of the hash table, etc.

[0037] During the initial state configuration of the instruction generator and the virtual predictor, it is necessary to check whether the parameters in the configuration file are consistent and valid. For example, whether the range of PC values ​​matches the jump target address constraint, and whether the instruction type constraint is compatible with the generation mode constraint.

[0038] The instruction stream generation platform can configure the initial states of the instruction generator and the virtual predictor according to different testing needs and scenarios. This allows the instruction generator and the virtual predictor to work collaboratively during the instruction stream generation process, generating instruction streams that conform to hardware behavior and testing objectives. These configuration items not only define the initial states of the instruction generator and the virtual predictor but also impose constraints on the characteristics of the instruction stream, ensuring that the generated instruction streams are diverse and targeted, and can comprehensively cover the behavioral characteristics of the branch prediction unit (BPU).

[0039] S102. In the initial state, the instruction generator determines the current generation mode of the instruction generator according to the generation mode probability distribution; In one embodiment, in the initial state, the instruction generator determines the current generation mode based on the probability distribution of the generation mode. The generation mode determines the generation method and characteristics of the instruction stream, such as sequential generation, random generation, or generation based on specific rules.

[0040] Different generation modes correspond to different instruction generation strategies. For example, in single-instruction random generation mode, the generation of each instruction is independent and based entirely on randomness; while in block instruction random generation mode, the correlation within the instruction block is considered, generating instruction sequences with a certain degree of locality. Different generation modes affect the characteristics of the instruction stream, such as instruction correlation and locality, thereby meeting different testing requirements.

[0041] Generally, single-instruction random generation mode refers to generating one instruction at a time, with instruction type, operands, etc., selected entirely randomly. Block instruction random generation mode refers to generating instructions on a block-by-block basis, with a high degree of correlation between instructions within each block. Rule-based generation mode refers to generating instruction sequences according to specific rules or templates to simulate specific program behaviors.

[0042] Each generation mode can be assigned a probability value, and the sum of these probabilities is 1. For example, the configuration file can define the probability of a single-instruction random generation mode as 40%, the probability of a block instruction random generation mode as 30%, and the probability of a rule-based generation mode as 30%. During the generation process, the probability distribution of the generation modes can be dynamically adjusted according to actual needs. For example, if it is found that the instruction stream generated by a certain generation mode is more in line with the test objective, the probability of that mode can be appropriately increased.

[0043] The instruction generator can generate a random number between 0 and 1 using a random number generator. Based on the probability distribution of the generation pattern, the interval [0,1] is divided into multiple sub-intervals, each corresponding to a generation pattern. For example, suppose the configuration file defines three generation patterns: single-instruction random generation pattern (pattern A), block instruction random generation pattern (pattern B), and rule-based generation pattern (pattern C), with probability distributions of 40%, 30%, and 30%, respectively. During initialization, the instruction generator reads the generation pattern probability distribution from the configuration file. Before generating the first instruction, the instruction generator calls the random number generation function to obtain a random number, such as 0.5. According to the probability interval mapping, 0.5 falls within the second sub-interval [0.4,0.7), thus determining the current generation pattern as Pattern B, i.e., the block instruction random generation pattern. Then, the instruction generator begins generating instructions according to the strategy of the block instruction random generation pattern.

[0044] This embodiment, by setting different generation modes and their probability distributions, can meet various testing needs and generate instruction streams with different characteristics. For example, it can increase the randomness of the instruction stream through a single-instruction random generation mode, simulate the locality of reference behavior of a program using a block instruction random generation mode, and reproduce specific program scenarios based on specific rules, thereby effectively improving the flexibility and adaptability of instruction stream generation. Simultaneously, it supports dynamically adjusting the probability distribution of the generation mode during the generation process, further enhancing the controllability and specificity of instruction stream generation, and better meeting the needs of different testing objectives and scenarios.

[0045] S103. Based on the instruction generation constraints, the instruction generator generates the current instruction in the current generation mode; In one embodiment, after the instruction generator determines the current generation mode, it generates instructions based on that mode and related constraints. The instruction generation strategy is selected according to the generation mode. For example, in single-instruction random generation mode, one instruction is generated each time, with the instruction type, operands, etc., selected randomly. For instance, the instruction type is randomly selected based on the instruction probability distribution, and then the operands are randomly generated. In block instruction random generation mode, instructions are generated in units of instruction blocks. Within a block, the instructions are highly correlated, and instruction sequences may be generated according to certain rules or templates. In rule-based generation mode, instruction sequences are generated according to predefined rules or templates to simulate specific program behaviors.

[0046] The single-instruction random generation mode can generate highly random instruction sequences, effectively simulating complex and ever-changing program execution situations; the block instruction random generation mode generates instruction flows that are closer to the actual program structure by maintaining the correlation of instructions within the block; and the rule-based generation mode can simulate specific scenarios or behaviors to meet specific testing needs.

[0047] The current instruction is generated based on the constraints starting from the initial PC value. The PC value of the current instruction is calculated based on the initial PC value and the instruction format. The specific content of the current instruction is generated based on the instruction type and operands.

[0048] S104. Perform a legality check on the current instruction and obtain the detection result of the current instruction; During the instruction stream generation process, the instruction generator needs to perform strict legality checks on the generated instructions to ensure that they comply with configuration file constraints and hardware behavior requirements.

[0049] For example, the validity checks include start program counter (PC) validity checks, instruction type validity checks, and constraint conflict checks. The generated current instruction will first pass the PC check to prevent the generation of invalid PC values ​​and invalid jump PC values, and then pass the instruction type validity check to ensure that the generated instruction stream conforms to the pattern of the configuration file constraints.

[0050] In one embodiment, a PC validity check is performed on the current instruction to obtain a first detection result of the current instruction; if the first detection result is valid, an instruction type validity check is performed on the current instruction to obtain a second detection result of the current instruction; if the second detection result is valid, a constraint conflict check is performed on the current instruction to obtain a third detection result of the current instruction; if the third detection result indicates that the current instruction satisfies the constraint conditions, the detection result of the current instruction is determined to be valid.

[0051] For example, the current PC value corresponding to the current instruction is obtained, and it is checked whether the current PC value is within the legal range defined in the configuration file. For jump instructions, it is also necessary to check whether the jump target PC value is valid, that is, to check whether the jump target PC value is within the allowed address range. If the PC value is invalid, the error message is recorded, and the instruction is regenerated or the generation parameters are adjusted according to the error handling policy; if the PC value is valid, the next step of instruction type validity check is performed.

[0052] In the instruction type validity check, it examines whether the generated instruction type is within the instruction set allowed by the configuration file, and verifies whether the instruction type conforms to a specific pattern or distribution according to the requirements of the current generation mode. If the instruction type is invalid, an error message is recorded, and the instruction is regenerated; if the instruction type is valid, the process proceeds to the next step of constraint conflict detection.

[0053] In constraint conflict detection, the generated instructions are checked to see if they conform to the instruction constraints, such as the distribution of different instruction types and compressed / uncompressed distribution. It is also verified whether the instruction generation conforms to the generation mode constraints, such as whether it satisfies the expected BPU behavior. If a constraint conflict exists, error information is recorded, and the generation strategy is adjusted or the instruction is regenerated based on the conflict. If the instruction satisfies all constraints, it is determined to be valid and can be added to the instruction stream.

[0054] In one specific embodiment, assume the current generation mode is a single-instruction random generation mode, with a starting PC of 0x0000. The instruction generator selects a branch instruction based on the instruction probability distribution and randomly generates a jump target address of 0x0005. Then, a PC check is performed to verify that 0x0005 is within the PC value range and conforms to the increasing pattern of the instruction flow. Assuming the PC value range is from 0x0000 to 0xffff, then 0x0005 is valid. Next, an instruction type validity check is performed to confirm that the branch instruction is an allowed instruction type. Finally, it is checked whether the instruction conforms to other constraints, such as compressed / uncompressed distribution.

[0055] Based on the results of PC validity checks, instruction type validity checks, and constraint conflict checks, a comprehensive judgment is made as to whether an instruction is valid. If all check results are valid and the constraints are met, the instruction is determined to be valid, added to the instruction stream, and the current PC value is updated to the PC value of the next instruction. If any check result is invalid or a constraint conflict exists, the instruction is adjusted or regenerated according to the error handling strategy.

[0056] By conducting multi-level validity checks, the generated instruction stream is ensured to comply with configuration file constraints and hardware behavior requirements. This effectively prevents the generation of illegal PC values ​​and jump PC values, while ensuring that the instruction type and distribution characteristics meet expectations.

[0057] If one or more of the first, second, and third detection results are illegal, the detection result of the current instruction is determined to be an illegal instruction.

[0058] After performing a validity check on the current instruction, it is necessary to determine whether the instruction is illegal based on the check results, and adjust the generation strategy of the instruction stream generation platform accordingly. A complete illegality check can be performed on the current instruction to obtain a complete check result. If any one or more of the first check result (PC validity), the second check result (instruction type validity), and the third check result (constraint conflict detection) are illegal, then the current instruction is determined to be illegal.

[0059] For example, the PC value of the current instruction or the PC value of the jump target exceeds the legal range or does not conform to the increasing rule; the current instruction type is not within the range allowed by the configuration file, or does not conform to the instruction probability distribution of the generation mode; the current instruction does not meet the instruction constraints or generation mode constraints, such as failing to trigger the expected BPU behavior or violating the distribution characteristics; and so on.

[0060] For illegal current instructions, the instruction generation adjustment strategy of the instruction stream generation platform is determined based on the detected illegal type of the current instruction, so as to adjust the instruction stream generation strategy.

[0061] In one embodiment, when the detection result of the current instruction is that the instruction is illegal, an error message is generated according to the type of illegality of the current instruction; when the detection result of the current instruction is that the instruction is legal, but the impact prediction result corresponding to the current instruction does not meet the preset expected conditions, the instruction generation constraints of the current generation mode are adjusted, and the instruction generation continues to be executed with the adjusted instruction generation constraints.

[0062] In one embodiment, the types of illegal instructions can include illegal PC values, illegal instruction types, and constraint conflicts, corresponding to the illegal results of the first, second, and third detection results mentioned above. Specifically, an illegal PC means that the PC value of the current instruction or the PC value of the jump target exceeds the legal range or does not conform to the increasing rule; an illegal instruction type means that the current instruction type is not within the range allowed by the configuration file or does not conform to the instruction probability distribution of the generation mode; a constraint conflict means that the current instruction does not meet the instruction constraints or generation mode constraints, such as failing to trigger the expected BPU behavior or violating the distribution characteristics.

[0063] Different instruction generation and adjustment strategies can be adopted for different types of illegal instructions.

[0064] The current instruction detection result can have three possible outcomes: First, if the current instruction's PC is invalid, the instruction type is invalid, or there is a constraint conflict, the instruction generator will report an error, requiring the user to check the configuration file for any unresolved conflicts. Second, if the current instruction's PC and jump PC are valid, the instruction type is valid, and it meets the current constraint mode's expectations for the BPU (e.g., the constraint mode expects the instruction to allocate an entry in the tage's long history table), then the instruction will be added to the instruction stream. Third, if the current instruction's PC and jump PC are valid, and the instruction type is valid, but it does not meet the constraint mode's expectations for the BPU, the instruction generator can take a step back. For example, due to the special nature of the tage algorithm, it may be impossible for tage to allocate an entry in the long history table at the beginning of the instruction stream. In this case, the instruction generator will tend to allocate an entry in tage's short history table first and continue generating the instruction stream.

[0065] Specifically, for invalid PCs, an adjustment strategy can be adopted, such as adjusting the PC value or adjusting the jump target address. That is, regenerate a PC value within the legal range to ensure that the PC follows an increasing pattern. For jump instructions, recalculate the jump target address to make it legal.

[0066] For invalid command types, strategies such as reselecting the command type or adjusting the command probability distribution can be employed. Specifically, reselecting the command type means randomly selecting a new command type based on the command probability distribution to ensure it is within the allowed range; adjusting the command probability distribution means that if invalid command types occur multiple times, the user is prompted to check whether the command probability distribution in the configuration file is reasonable, and adjustments are made as needed.

[0067] For constraint conflicts, adjustment strategies such as adjusting instruction generation parameters or regenerating instructions can be used. Specifically, the parameters of the instruction generator (such as instruction distribution and jump probability) are modified to meet the constraints. After adjusting the parameters, the instructions are regenerated to ensure that the constraints are satisfied.

[0068] By dynamically adjusting the generation strategy, the efficiency and quality of instruction stream generation can be improved, ensuring that the generated instruction stream can fully cover the behavioral characteristics of the branch prediction unit (BPU), thereby providing reliable data support for the testing and verification of hardware predictors.

[0069] S105. When the detection result of the current instruction is that the instruction is legal, the current instruction is input into the virtual predictor so as to predict the impact of the current instruction on the branch prediction unit through the virtual predictor and obtain the impact prediction result corresponding to the current instruction. In one embodiment, the current instruction is passed from the instruction generator to the virtual predictor. The passed instruction information may include the instruction's opcode, operands, PC value, etc. The virtual predictor prepares to make a prediction based on its current internal state (such as historical information, table entries, etc.). For example, updating the global history register and local history registers.

[0070] The virtual predictor outputs a prediction of the current instruction's impact on the BPU, including the predicted branch direction, entry update information, and historical update information. Specifically, the virtual predictor analyzes the type and characteristics of the current instruction, such as whether it is a branch instruction or a jump instruction. Based on the instruction type and historical information, it generates a prediction result, predicting whether a branch will be taken or not for branch instructions. It determines whether the current instruction will cause updates to internal BPU entries; for example, for branch instructions, new entries may be allocated in the BTB (Branch Target Buffer) or the history table. It predicts updates to the global and local histories, such as updating the global history register to reflect recent branch results.

[0071] In one specific embodiment, assuming the current instruction is a branch instruction, the virtual predictor predicts that the instruction will take a branch based on historical information and allocates a new entry in the BTB. If this prediction meets the expectations of the constraint mode, the instruction is added to the instruction stream. For a jump instruction, the virtual predictor predicts that it will update the global history register. If this update meets the expectations of the constraint mode for historical updates, subsequent instructions are generated. If the virtual predictor's prediction shows that the current instruction cannot meet the expected behavior of the constraint mode for the BPU, the instruction generator adjusts its generation strategy based on the predictor's feedback, selecting a suboptimal solution to continue generating instructions. If the prediction result indicates that the instruction may cause abnormal behavior of the BPU, the instruction generator reports an ERROR and prompts the user to check for conflicts in the configuration file.

[0072] The system records the impact prediction results generated by the virtual predictor and feeds these results back to the instruction generator. The instruction generator can adjust its generation mode based on the prediction results to better meet the testing requirements of the BPU behavior.

[0073] By inputting legitimate instructions into the virtual predictor, the impact of instructions on the Branch Prediction Unit (BPU) can be predicted in advance. This allows the instruction generator to dynamically adjust its generation strategy based on the prediction results, ensuring that the generated instruction stream not only meets the syntactic and semantic legality requirements but also satisfies the testing needs for specific BPU behavior patterns. Simultaneously, timely feedback and adjustments prevent the generation of unexpected instructions, improving the efficiency and relevance of instruction stream generation and ensuring effective verification and testing of BPU behavior.

[0074] S106. When the impact prediction result corresponding to the current instruction meets the preset expected conditions, the current instruction is added to the instruction stream.

[0075] In one embodiment, the preset expected conditions are defined by a configuration file and may include expected branch prediction results (such as branching or not branching), expected table entry updates (such as allocating new table entries in the BTB or history table), expected history updates (such as the update method of global history or local history), etc.

[0076] Specifically, the predicted branch direction can be compared with the expected branch direction. For example, if a branch instruction is expected to be predicted as a branch, and the actual prediction result is also a branch, then the condition is met.

[0077] You can check whether the table entry update meets the expected conditions. For example, if you expect a certain instruction to allocate an entry in the long history table, and the actual prediction result also shows that an entry will be allocated in the long history table, then the condition is met.

[0078] It can be verified whether the historical update method meets the expected conditions. For example, if it is expected that a certain instruction will update the global history register, and the actual prediction result also shows that a global history update will be performed, then the conditions are met.

[0079] If the predicted impact of the current instruction matches all preset expected conditions, the instruction is added to the instruction stream. Simultaneously, the internal state of the instruction generator, such as the current PC value, is updated to prepare for the generation of subsequent instructions. If the predicted impact of the current instruction does not match the preset expected conditions, an adjustment strategy is adopted based on the specific situation. For example, if it is expected that an entry will be allocated in the long history table but the actual prediction results show that this cannot be met, the entry will be allocated in the short history table instead, and the generation of subsequent instructions will continue.

[0080] During instruction stream generation, preset expectation conditions can be dynamically adjusted based on actual conditions. For example, if the current preset expectation conditions are found to be too strict, resulting in few instructions being able to meet the conditions, the preset expectation conditions can be appropriately adjusted to improve the efficiency of instruction stream generation.

[0081] The current instruction is added to the instruction stream to ensure the continuity and integrity of the instruction stream. The internal state of the instruction generator is updated, such as the current PC value and the number of instructions generated, to reflect the addition of new instructions.

[0082] This embodiment compares the predicted impact of the current instruction with preset expected conditions and determines whether to add the instruction to the instruction stream accordingly. This allows for precise control over the characteristics of the generated instruction stream, ensuring it meets the testing requirements for the Branch Prediction Unit (BPU) behavior. Simultaneously, dynamically adjusting the preset expected conditions and instruction generation strategy guarantees the legality and validity of the instruction stream while improving its generation efficiency and flexibility. This ensures the generated instruction stream comprehensively covers various BPU behavior patterns, thereby providing high-quality test data for the testing and verification of the hardware predictor.

[0083] In one embodiment, after the current generation mode is completed, the total number of instructions in the instruction stream is detected; when the total number of instructions is greater than or equal to a preset instruction number threshold, instruction stream data is output, wherein the instruction stream data includes an instruction stream file, an overall instruction table file, and a predictor behavior file.

[0084] like Figure 4 As shown, after the instruction generation task in the current generation mode is completed (for example, if the specific constraints of the mode are met, such as successfully occupying an entry in L0BTB and training it to be a strong jump), the generator counts the total number of instructions that have been generated. This counting process is continuous and accumulates from the start of instruction stream generation until the current generation mode is completed.

[0085] The system retrieves a preset instruction count threshold from the configuration file, which defines the total target for instruction stream generation. It compares the current total number of instructions with the preset threshold; if the total number of instructions has reached or exceeded the threshold, the instruction generator terminates. The instruction generator then organizes and outputs the generated instruction stream data, including the instruction stream file, the overall instruction table file, and the predictor behavior file.

[0086] The instruction stream file contains all generated instructions recorded in the order of instruction execution. The overall instruction table file records detailed information for each instruction, such as opcode, operands, and PC value. The predictor behavior file records the behavior data of the virtual predictor during the instruction stream generation process, such as prediction results, table updates, and historical updates.

[0087] In another embodiment, when the number of instructions is less than a preset instruction number threshold, a random number generator is used to randomly select another generation mode according to the probability distribution of the generation mode; the instruction generator is switched to the other generation mode to continue generating instructions according to the constraints of the other generation mode.

[0088] In one embodiment, the generation modes and their corresponding selection probabilities are read from a configuration file. The generation mode probability distribution defines the probability of each generation mode being selected. A random number generator is invoked to generate a random number between 0 and 1. Based on the generation mode probability distribution, the random number is mapped to the corresponding generation mode. The other generation mode is determined based on the sub-interval where the generated random number falls.

[0089] Switching the instruction generator's current generation mode to another involves updating the generator's internal state parameters, such as instruction probability distribution and jump function length, to meet the constraints of the new generation mode. Based on the requirements of the new generation mode, relevant parameters are initialized; for example, if the new generation mode is a block instruction random generation mode, the instruction block size and related parameters need to be initialized.

[0090] After switching to the new generation mode, the instruction generator continues to generate instructions according to the constraints of the new mode, including generating instructions starting from the current PC value and performing PC checks, instruction type validity checks, and constraint conflict checks. In another generation mode, the instruction generation and detection process is repeated until the termination condition is met (such as the total number of instructions reaching a preset threshold).

[0091] Continue generating instructions in another generation mode, repeating the instruction count detection and comparison operation at the end of each generation mode, and comparing the total number of instructions counted with the preset instruction count threshold in the configuration file. If the total number of instructions is less than the threshold, instruction generation needs to continue.

[0092] In this embodiment, the instruction generator can ensure the total amount and quality of instruction stream generation by counting and comparing the number of instructions in real time during the generation process after the generation mode is completed. When the total number of instructions reaches a preset threshold, the complete instruction stream data can be output in a timely manner. When the number of instructions has not reached the threshold, a new generation mode is randomly selected and switched, ensuring the diversity of instruction streams and the continuity of the generation process. This effectively avoids the problem of monotonous instruction stream characteristics caused by a single generation mode, thereby improving the adaptability and coverage of instruction stream generation and better meeting the requirements for comprehensiveness and accuracy of hardware predictor behavior testing.

[0093] The method provided in this application can dynamically program instruction streams under the guidance of a built-in predictor, supports mainstream prediction algorithms (TAGE, BTB, Bimodal, etc.), can quickly extend existing arbitrary branch prediction algorithms, and has high configurability; moreover, the predictor can predict the results of instruction execution, serving as a reference model for the behavior of RTL.

[0094] This embodiment provides an instruction stream generation method. This method flexibly configures the initial states of the instruction generator and the virtual predictor according to a configuration file, ensuring that the generated instruction stream meets specific constraints. The instruction generator determines the current generation mode based on the probability distribution of the generation mode, introducing randomness to cover more scenarios. The current instruction is generated under the current generation mode, and its correctness and standardization are ensured through legality checks. The legal instruction is input into the virtual predictor to predict its impact on the branch prediction unit, thus assessing the potential effect of the instruction on the BPU's behavior in advance. When the prediction result meets the preset expected conditions, the instruction is added to the instruction stream, ensuring that the generated instruction stream can effectively verify the key behaviors of the BPU. This method is particularly suitable for verifying complex multi-level branch prediction algorithms, improving verification efficiency and coverage, and reducing the difficulty of manually writing test cases.

[0095] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a current embodiment of an instruction stream generation device provided in this application. The instruction stream generation device is used to execute the aforementioned instruction stream generation method.

[0096] like Figure 5 As shown, the instruction stream generation device 200 includes: an initial state configuration module 201, a generation mode determination module 202, an instruction generation module 203, a legality detection module 204, an instruction prediction module 205, and an instruction stream construction module 206.

[0097] The initial state configuration module 201 is used to configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file. The generation mode determination module 202 is used to determine the current generation mode of the instruction generator according to the generation mode probability distribution in the initial state. Instruction generation module 203 is used to generate the current instruction according to the instruction generation constraints, wherein the instruction generator generates the current instruction in the current generation mode; The legality detection module 204 is used to perform legality detection on the current instruction and obtain the detection result of the current instruction; The instruction prediction module 205 is used to input the current instruction into the virtual predictor when the detection result of the current instruction is that the instruction is legal, so as to predict the impact of the current instruction on the branch prediction unit through the virtual predictor and obtain the impact prediction result corresponding to the current instruction. The instruction stream construction module 206 is used to add the current instruction to the instruction stream when the influence prediction result corresponding to the current instruction meets the preset expected conditions.

[0098] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the above-described apparatus and modules can be referred to the corresponding processes in the aforementioned instruction stream generation method embodiments, and will not be repeated here.

[0099] The apparatus provided in the above embodiments can be implemented as a computer program, which can be used in, for example... Figure 6 It runs on the computer device shown.

[0100] Please see Figure 6 , Figure 6 This is a schematic block diagram illustrating the structure of a computer device according to an embodiment of this application. The computer device may be a server.

[0101] See Figure 6 The computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.

[0102] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any instruction stream generation method.

[0103] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0104] Internal memory provides an environment for the execution of computer programs stored in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to execute any instruction stream generation method.

[0105] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0106] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0107] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: Configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file; In the initial state, the instruction generator determines the current generation mode of the instruction generator according to the probability distribution of the generation mode; Based on the instruction generation constraints, the instruction generator generates the current instruction in the current generation mode; Perform a validity check on the current instruction and obtain the detection result of the current instruction; When the detection result of the current instruction is that the instruction is valid, the current instruction is input into the virtual predictor so as to predict the impact of the current instruction on the branch prediction unit and obtain the impact prediction result corresponding to the current instruction. When the predicted impact result corresponding to the current instruction meets the preset expected conditions, the current instruction is added to the instruction stream.

[0108] The embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and the processor executing the program instructions to implement any of the instruction stream generation methods provided in the embodiments of this application.

[0109] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0110] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for generating an instruction stream, characterized in that, Applied to an instruction stream generation platform, the instruction stream generation platform including an instruction generator and a virtual predictor, the method includes: Configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file; In the initial state, the instruction generator determines the current generation mode of the instruction generator according to the probability distribution of the generation mode; Based on the instruction generation constraints, the instruction generator generates the current instruction in the current generation mode; Perform a validity check on the current instruction and obtain the detection result of the current instruction; When the detection result of the current instruction is that the instruction is valid, the current instruction is input into the virtual predictor so as to predict the impact of the current instruction on the branch prediction unit and obtain the impact prediction result corresponding to the current instruction. When the predicted impact result corresponding to the current instruction meets the preset expected conditions, the current instruction is added to the instruction stream.

2. The instruction stream generation method according to claim 1, characterized in that, The validity checks include the validity checks of the start program counter (PC), the validity checks of the instruction type, and the checks for constraint conflicts. The step of performing a legality check on the current instruction and obtaining the detection result of the current instruction includes: Perform a PC validity check on the current instruction to obtain the first check result of the current instruction; If the first detection result is valid, perform an instruction type validity check on the current instruction to obtain a second detection result for the current instruction; If the second detection result is valid, constraint conflict detection is performed on the current instruction to obtain the third detection result of the current instruction; When the third detection result indicates that the current instruction meets the constraints, the detection result of the current instruction is determined to be a valid instruction.

3. The instruction stream generation method according to claim 2, characterized in that, The step of performing a legality check on the current instruction and obtaining the detection result of the current instruction includes: If one or more of the first, second, and third detection results are illegal, the detection result of the current instruction is determined to be an illegal instruction.

4. The instruction stream generation method according to claim 1, characterized in that, After inputting the current instruction into the virtual predictor to predict the impact of the current instruction on the branch prediction unit and obtaining the impact prediction result corresponding to the current instruction, the method further includes: When the detection result of the current instruction is that the instruction is illegal, an error message is generated according to the type of illegality of the current instruction; When the detection result of the current instruction is that the instruction is valid, but the prediction result of the impact corresponding to the current instruction does not meet the preset expected conditions, the instruction generation constraints of the current generation mode are adjusted, and the instruction generation continues to be executed with the adjusted instruction generation constraints.

5. The instruction stream generation method according to claim 1, characterized in that, The impact prediction results include the predicted branch direction, table update information, and historical update information.

6. The instruction stream generation method according to claim 1, characterized in that, After adding the current instruction to the instruction stream, the method further includes: After the current generation mode is completed, the total number of instructions in the instruction stream is detected. When the total number of instructions is greater than or equal to a preset instruction number threshold, instruction stream data is output, wherein the instruction stream data includes an instruction stream file, an overall instruction table file, and a predictor behavior file.

7. The instruction stream generation method according to claim 6, characterized in that, After detecting the current total number of instructions in the instruction stream, the method further includes: When the number of instructions is less than a preset instruction number threshold, a random number generator is used to randomly select another generation mode according to the probability distribution of the generation mode. The instruction generator is switched to the other generation mode to continue generating instructions based on the instruction generation constraints of the other generation mode.

8. An instruction stream generation apparatus, characterized in that, The instruction stream generation device includes: An initial state configuration module is used to configure the initial state of the instruction generator and the initial state of the virtual predictor according to the configuration file. A generation mode determination module is used to determine the current generation mode of the instruction generator based on the generation mode probability distribution in the initial state. The instruction generation module is used to generate the current instruction based on the instruction generation constraints, and the instruction generator generates the current instruction in the current generation mode. A legality detection module is used to perform legality detection on the current instruction and obtain the detection result of the current instruction; The instruction prediction module is used to input the current instruction into the virtual predictor when the detection result of the current instruction is that the instruction is legal, so as to predict the impact of the current instruction on the branch prediction unit through the virtual predictor and obtain the impact prediction result corresponding to the current instruction. The instruction stream construction module is used to add the current instruction to the instruction stream when the influence prediction result corresponding to the current instruction meets the preset expected conditions.

9. A computer device, characterized in that, The computer device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the instruction stream generation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the instruction stream generation method as described in any one of claims 1 to 7.

Images