A flash memory garbage collection method, device, equipment and readable storage medium

Abstract

The application discloses a flash memory garbage collection method, device and equipment and a readable storage medium, and is applied to the storage field and comprises the following steps: when garbage collection is triggered, a candidate sub-block is determined, and a sub-page validity bitmap and wear information are obtained; a target collection sub-block is determined according to the number of valid sub-pages, the number of invalid sub-pages and the wear information; valid sub-page data and a logical address of the target collection sub-block are obtained and aggregated to obtain to-be-migrated data; a target storage position with the minimum interference quantity is determined according to a programming interference relationship between sub-page positions in a physical page; the to-be-migrated data is written, a mapping relationship and a sub-page validity state are updated, the target collection sub-block is erased, and the wear information is updated. Through the cooperation between sub-page state sensing and sub-block collection execution, the application takes into account collection benefits, migration overhead, wear and programming interference, reduces write amplification and data interference risk, improves flash memory reliability and prolongs the service life.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a flash memory garbage collection method, apparatus, device, and readable storage medium. Background Technology

[0002] With the rapid development of computer storage technology, NAND Flash memory has become the core storage medium for solid-state drives (SSDs) due to its advantages such as non-volatility, high performance, low power consumption, and high storage density. However, NAND Flash memory has inherent physical limitations: its storage cells have a limited number of program / erase (PE) cycles. After exceeding the rated PE cycles, the reliability of the storage cells will significantly decrease, eventually leading to SSD failure. Therefore, how to improve the lifespan of NAND Flash memory is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a flash memory garbage collection method, apparatus, device, and readable storage medium that can solve the problem of low lifespan of NAND flash memory.

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a flash memory garbage collection method, comprising: When garbage collection is triggered, at least one candidate sub-block is identified, and the subpage validity bitmap and wear information of each candidate sub-block are obtained; The number of valid and invalid subpages is determined based on the subpage validity bitmap, and the lifetime of each candidate subblock is determined in conjunction with the wear information. The target reclaimed subblock is then determined based on the lifetime information. Obtain the valid subpage data and corresponding logical addresses in the target recycling subblock, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; Based on the programming interference relationship between different subpage locations within a physical page, the target storage location with the minimum interference is determined from multiple candidate storage locations; Write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock.

[0005] On the one hand, before obtaining the subpage validity bitmap and wear information of each candidate sub-block, the following steps are also included: The sub-block partitioning parameters and sub-page partitioning parameters are determined based on the physical specifications of the flash memory; Based on the subpage partitioning parameters, a subpage validity bit chart is established for each physical page, so that each bit in the subpage validity bit chart corresponds to each subpage in the physical page, and the validity status of the corresponding subpage is recorded with a valid or invalid identifier. A sub-block wear count table is established for each sub-block based on the sub-block division parameters, and the number of programming / erasing times for each sub-block is recorded in the sub-block wear count table; Perform a programming interference test on the flash memory, and establish a physical page interference model table based on the programming interference test results; The subpage validity bitmap, the subblock wear count table, and the physical page interference model table are stored in the controller storage space. In response to a subpage data write or data migration operation, the bit corresponding to the data write position is set to a valid flag, and the bit corresponding to the atomic page position is set to an invalid flag according to the original mapping relationship of the overwritten or migrated data. In response to a sub-block erase operation, the programming / erasing count for the corresponding sub-block in the sub-block wear count table is incremented by one.

[0006] On the one hand, a programming interference test is performed on the flash memory, and a physical page interference model table is established based on the programming interference test results, including: Perform a programming operation on the first subpage location within a physical page, and detect the original bit error rate increments at each second subpage location within the same physical page caused by the programming operation; The raw bit error rate increments corresponding to multiple programming operations are statistically analyzed to determine the average raw bit error rate increments corresponding to each second subpage position and the maximum value among the raw bit error rate increments. Calculate the ratio of the average value of each original bit error rate increment to the maximum value to obtain the programming interference weight of the first subpage position to each second subpage position; By changing the position of the first subpage and repeatedly determining the programming interference weights, a physical page interference model table is obtained, which characterizes the programming interference relationship between different subpage positions within a physical page.

[0007] On the one hand, obtain the subpage validity bitmap for each candidate sub-block, including: Based on the sub-block identifier of each candidate sub-block, determine the physical pages in each candidate sub-block; Based on the correspondence between the physical page and the subpage validity bitmap, read the subpage validity bitmap corresponding to each physical page; The subpage validity bitmaps corresponding to each physical page belonging to the same candidate sub-block are summarized to obtain the subpage validity bitmaps for each candidate sub-block.

[0008] On the one hand, determining the number of valid subpages and the number of invalid subpages based on the subpage validity bitmap includes: Obtain the subpage validity bitmap corresponding to each physical page in each candidate subblock; The number of valid subpages corresponding to the valid identifiers in the subpage validity bitmap is counted to obtain the number of valid subpages for the corresponding candidate subblock. The number of invalid subpages corresponding to the invalid identifiers in the subpage validity bitmap is counted to obtain the number of invalid subpages for the corresponding candidate sub-block.

[0009] On one hand, the number of valid and invalid subpages is determined based on the subpage validity bitmap, and the lifetime of each candidate subblock is determined in conjunction with the wear information. Based on the lifetime information, the target reclaimed subblock is determined, including: Obtain the number of programming / erase operations for each candidate sub-block, and determine the average number of programming / erase operations based on the number of programming / erase operations for each sub-block in the flash memory; Based on the difference between the number of invalid subpages and the number of valid subpages in each candidate subblock, determine the value result between the space reclamation benefit and data migration overhead of each candidate subblock; The wear result of each candidate sub-block is determined based on the difference between the number of programming / erasing operations for each candidate sub-block and the average number of programming / erasing operations. Based on the value results and the wear results, the lifetime status of each candidate sub-block is determined, and the candidate sub-block with the best lifetime status is determined as the target recycling sub-block.

[0010] On the one hand, the lifetime of each candidate sub-block is determined based on the value result and the wear result, including: The value result is obtained by subtracting the product of the first weighting coefficient and the number of valid pages from the number of invalid pages. The wear result is obtained by subtracting the programming / erase count of the corresponding candidate sub-block from the average programming / erase count and multiplying the difference by the second weighting coefficient. The value result is added to the wear result to obtain the lifetime status of the corresponding candidate sub-block.

[0011] On the one hand, based on the programming interference relationship between different subpage locations within a physical page, the target storage location with the least interference is determined from multiple candidate storage locations, including: Based on the number of subpages occupied by the data to be migrated, multiple candidate storage locations are determined from the writable subpage locations of multiple candidate physical pages; Based on the programming interference relationship, determine the amount of programming interference generated by writing the data to be migrated to each candidate storage location; Compare the programming interference amounts corresponding to each candidate storage location, and determine the candidate storage location with the smallest programming interference amount as the target storage location.

[0012] On the one hand, based on the programming interference relationship, the amount of programming interference generated by writing the data to be migrated to each candidate storage location is determined, including: Determine the number of valid subpages contained in the data to be migrated, and identify multiple candidate physical pages from physical pages that have writable subpage locations that are no less than the number of valid subpages. For each candidate physical page, based on the writable subpage locations in the candidate physical page, select the same number of subpage locations as the number of valid subpage data to form multiple candidate subpage location combinations, and determine each candidate subpage location combination as a candidate storage location; Determine the location of the subpage with stored valid data in each candidate physical page, and for each subpage location to be programmed in each combination of candidate subpage locations, query the physical page interference model table for the first interference weight of the subpage location to be programmed on the subpage location with stored valid data; For a candidate subpage location combination containing at least two subpage locations to be programmed, a second interference weight generated between each subpage location to be programmed in the candidate subpage location combination is queried from the physical page interference model table; The programming interference amount corresponding to the candidate subpage position combination is obtained by summing the first interference weight and the second interference weight corresponding to the same candidate subpage position combination.

[0013] On one hand, the valid subpage data is aggregated according to the relationship between the logical addresses to obtain the data to be migrated, including: Read the valid subpage data and its corresponding logical address into the controller cache. The valid subpage data is sorted according to the logical address, and the logical address interval between adjacent valid subpage data is determined. Valid subpage data with consecutive logical addresses or with logical address intervals less than a preset interval threshold are grouped into the same data set; The valid subpage data in each data set are grouped according to the number of subpages contained in a single physical page, so that the number of valid subpage data in each group does not exceed the number of subpages contained in a single physical page, and the valid subpage data in each group is determined as the data to be migrated.

[0014] On the one hand, when garbage collection is triggered, at least one candidate sub-block is identified, including: Monitor the number of free sub-blocks in flash memory; The garbage collection trigger threshold is determined based on the write load and remaining lifetime, and the garbage collection trigger threshold is adjusted according to changes in the write load or the remaining lifetime. When the number of free sub-blocks is lower than the garbage collection trigger threshold, the proportion of invalid sub-pages in each non-free sub-block is determined; At least one candidate sub-block is selected from the non-idle sub-blocks based on the invalid sub-page ratio.

[0015] On the one hand, obtaining the valid subpage data and corresponding logical addresses in the target reclaimed subblock includes: Read the subpage validity bitmap corresponding to each physical page in the target reclaimed subblock; Based on the subpage validity bitmap, determine each subpage marked as valid and generate a list of valid subpages; The original data stored in each valid subpage is read from the list of valid subpages to obtain the valid subpage data; Based on the mapping relationship corresponding to each valid subpage, obtain the logical address corresponding to the original data.

[0016] The present invention also provides a flash memory garbage collection device, comprising: The information acquisition module is used to identify at least one candidate sub-block when garbage collection is triggered, and to acquire the sub-page validity bitmap and wear information of each candidate sub-block; The recycling sub-block determination module is used to determine the number of valid sub-pages and invalid sub-pages based on the sub-page validity bitmap, and to determine the lifetime of each candidate sub-block in combination with the wear information, and to determine the target recycling sub-block based on the lifetime. The data aggregation module is used to obtain the valid subpage data and corresponding logical addresses in the target recycling sub-block, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; The storage location determination module is used to determine the target storage location with the least interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within a physical page. The erase and update module is used to write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock.

[0017] The present invention also provides a flash memory waste recycling device, comprising: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the flash memory garbage collection method described above.

[0018] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the flash memory garbage collection method described above.

[0019] The present invention also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the flash memory garbage collection method described above.

[0020] As can be seen from the above technical solution, the present invention, when triggering garbage collection, determines at least one candidate sub-block and obtains the subpage validity bitmap and wear information of each candidate sub-block; determines the number of valid subpages and invalid subpages based on the subpage validity bitmap, and determines the lifetime of each candidate sub-block in combination with the wear information; determines the target reclaimed sub-block based on the lifetime; obtains the valid subpage data and corresponding logical addresses in the target reclaimed sub-block, and aggregates the valid subpage data according to the relationship between logical addresses to obtain the data to be migrated; determines the target storage location with the least interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within the physical page; writes the data to be migrated to the target storage location, updates the mapping relationship between logical addresses and physical locations and the subpage validity status, erases the target reclaimed sub-block, and updates the wear information of the target reclaimed sub-block.

[0021] The beneficial effects of this invention are as follows: By deeply coordinating subpage state awareness and subblock operation execution, the invention accurately reflects the data validity status within candidate subblocks using a subpage validity bitmap, and determines target reclaimed subblocks by combining subblock wear information. This ensures that the selection of reclaimed objects balances space release benefits, valid data migration overhead, and wear level. Simultaneously, by aggregating valid subpage data based on logical address relationships, the invention reduces the dispersion of migrated data and additional writes. Furthermore, by selecting the storage location with the least interference based on the programming interference relationship between subpage locations, the invention reduces the impact of migration writes on other data within the same physical page. Therefore, it can reduce write amplification and programming interference caused by garbage collection, improve uneven subblock wear, enhance data storage reliability, and extend flash memory lifespan.

[0022] In addition, the present invention also provides a flash memory garbage collection device, apparatus and readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description

[0023] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart of a flash memory garbage collection method provided in an embodiment of the present invention; Figure 2 A schematic diagram of a flash memory waste recycling system provided in an embodiment of the present invention; Figure 3 A schematic diagram of collaborative lifetime decision-making provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a data restructuring and migration process provided in an embodiment of the present invention; Figure 5 This is a schematic flowchart of a flash memory garbage collection method provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a flash memory waste recycling device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a flash memory waste recycling device provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0026] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0027] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] First, the English vocabulary used in this invention will be explained: SSD: Solid State Drive.

[0029] NAND Flash: A type of non-volatile flash memory, often simply called NAND flash memory.

[0030] FTL: Flash Translation Layer.

[0031] P / E: Program / Erase.

[0032] RBER (Raw Bit Error Rate) is the raw bit error rate.

[0033] LBA: Logical Block Address.

[0034] DRAM: Dynamic Random Access Memory.

[0035] With the development of computer storage technology, NAND flash memory has become the main storage medium for solid-state drives (SSDs) due to its non-volatility, low power consumption, and high storage density. NAND flash memory cells can only withstand a limited number of programming / erase cycles. Effective data migration and repeated erasures during garbage collection can cause write amplification and potentially exacerbate wear differences between different storage areas. Existing solutions typically employ sub-block level erasure or sub-page level writing for fine-grained management, but sub-block reclamation and sub-page state management are disconnected, making it difficult to simultaneously and accurately assess migration overhead, wear levels, and intra-page programming interference. Therefore, reducing write amplification and uneven wear caused by garbage collection, and minimizing programming interference, are urgent technical problems that need to be solved.

[0036] Next, a flash memory garbage collection method provided by an embodiment of the present invention will be described in detail. Figure 1 A flowchart of a flash memory garbage collection method provided in an embodiment of the present invention may include: S101: When garbage collection is triggered, at least one candidate sub-block is identified, and the subpage validity bitmap and wear information of each candidate sub-block are obtained.

[0037] refer to Figure 2 , Figure 2 This is a schematic diagram of a flash memory garbage collection system provided in an embodiment of the present invention. The system includes a host, a flash translation layer (FTL) module, a flash memory controller, and NAND flash memory. The flash memory controller includes a lifetime extension management engine, a garbage collection scheduling module, and a data layout module; the lifetime extension management engine includes a subpage state manager, a subblock space optimizer, a subpage-subblock collaborative management module, and a metadata storage module. The subpage state manager is used to maintain the valid state of subpages, the subblock space optimizer is used to maintain the subblock space and wear state, the subpage-subblock collaborative management module is used to make recycling decisions based on relevant states, and the data layout module is used to organize the data to be migrated. The above module names and divisions are only used to illustrate the functional relationships and do not limit the specific software, firmware, or hardware implementation of each function. The flash memory controller is used as the execution subject of steps S101 to S105 in the following description, and will be referred to as the controller.

[0038] In S101, after the garbage collection process is triggered, the flash memory controller identifies one or more candidate sub-blocks that need to participate in the recycling evaluation and reads the status information of each candidate sub-block. A sub-block can be a region in a physical block that can be independently erased, and a subpage can be a data unit in a physical page divided according to write granularity. The subpage validity bitmap uses bits to represent whether the data stored in each subpage within the candidate sub-block is currently valid data, and the wear information represents the degree of use of the candidate sub-block after undergoing programming / erasing operations. By simultaneously acquiring the data validity status at the subpage granularity and the wear status at the sub-block granularity, a relevant evaluation basis can be provided for the subsequent determination of target recyclable sub-blocks.

[0039] Furthermore, the process of determining at least one candidate sub-block when triggering garbage collection may include: monitoring the number of free sub-blocks in the flash memory; determining a garbage collection trigger threshold based on write load and remaining lifetime, and adjusting the garbage collection trigger threshold based on changes in write load or remaining lifetime; determining the proportion of invalid subpages in each non-free sub-block when the number of free sub-blocks is lower than the garbage collection trigger threshold; and selecting at least one candidate sub-block from the non-free sub-blocks based on the proportion of invalid subpages.

[0040] In this implementation, the controller continuously obtains the number of free sub-blocks in the flash memory and sets a garbage collection trigger threshold based on write pressure and remaining flash memory lifetime. Write load can reflect the number of write requests, data volume, or bandwidth usage per unit time, while remaining lifetime can be estimated from the wear and tear of the entire flash memory or specific regions. The controller can adjust the garbage collection trigger threshold according to changes in operating status, appropriately advancing or delaying garbage collection during periods of high write pressure or lifetime changes. Once the number of free sub-blocks reaches the trigger condition, the controller then forms a candidate sub-block set based on the proportion of invalid sub-pages in the non-free sub-blocks. The initial value, adjustment period, and number of candidate sub-blocks for the garbage collection trigger threshold can be set according to device performance requirements. This method adapts the timing of garbage collection triggering to the current load and lifetime status, prioritizing sub-blocks with more free space for evaluation, reducing situations where garbage collection is too frequent or started too late.

[0041] Furthermore, the above-mentioned acquisition of the subpage validity bitmap of each candidate sub-block may include: determining the physical pages in each candidate sub-block based on the sub-block identifier of each candidate sub-block; reading the subpage validity bitmap corresponding to each physical page based on the correspondence between the physical page and the subpage validity bitmap; and summarizing the subpage validity bitmaps corresponding to each physical page belonging to the same candidate sub-block to obtain the subpage validity bitmap of each candidate sub-block.

[0042] In this implementation, a sub-block can include multiple physical pages, and each physical page can correspond to a sub-page validity bitmap. Therefore, after determining a candidate sub-block, the controller can first locate the physical pages it contains based on the sub-block identifier, then read the sub-page validity bitmaps of each physical page from the bitmap management area, and combine them according to the sub-block affiliation. This aggregation can be done by concatenating the physical pages in order, building an index set, or traversing each page during statistics, as long as a complete sub-page validity status within the candidate sub-block range can be formed. The correspondence between physical pages and sub-page validity bitmaps can be maintained by address indexes, table entry numbers, or other mapping methods. By aggregating the sub-page validity bitmaps of each physical page under the same candidate sub-block, it is possible to avoid missing status due to observing only a single physical page, ensuring that subsequent statistics cover all sub-pages of the candidate sub-block.

[0043] Furthermore, before obtaining the subpage validity bitmap and wear information of each candidate sub-block, the process may further include: determining sub-block partitioning parameters and subpage partitioning parameters based on the physical specifications of the flash memory; establishing a subpage validity bitmap for each physical page based on the subpage partitioning parameters, such that each bit in the subpage validity bitmap corresponds to each subpage within the physical page, and recording the validity status of the corresponding subpage with a valid or invalid identifier; establishing a sub-block wear count table for each sub-block based on the sub-block partitioning parameters, and recording the programming / erase count of each sub-block in the sub-block wear count table; performing a programming interference test on the flash memory, and establishing a physical page interference model table based on the programming interference test results; storing the subpage validity bitmap, sub-block wear count table, and physical page interference model table in the controller storage space; in response to subpage data write or data migration operations, setting the bit corresponding to the data write position as a valid identifier, and setting the bit corresponding to the atomic page position as an invalid identifier according to the original mapping relationship corresponding to the overwritten data or migrated data; in response to a sub-block erase operation, incrementing the programming / erase count of the corresponding sub-block in the sub-block wear count table by one.

[0044] In this implementation, before the garbage collection process begins, the controller can configure the sub-block and sub-page partitioning method based on the physical specifications of the NAND flash memory used, such as page size, partially erasable range, and programming granularity. A sub-page validity bitmap can be set for each physical page, with one bit corresponding to one sub-page; a valid identifier indicates that the data in the sub-page is still consistent with the current logical address mapping, while an invalid identifier indicates that the data has been overwritten, migrated, or is no longer needed. A sub-block wear count table records the number of programming / erasing operations for each sub-block, and a physical page interference model table records the interference relationships between different sub-page locations. This metadata can be stored in the controller's volatile or non-volatile storage space and loaded into the working storage space at startup. After each write or migration, the controller synchronously updates the validity status of the old and new sub-pages; after each sub-block erase, the corresponding wear count is synchronously updated. The storage format, identifier values, and persistence period of each table can be set according to the controller's resources. By establishing and updating this metadata as it is used in practice, the state used for subsequent recycling decisions can be kept consistent with the current state of the flash memory, providing a unified data foundation for subpage state awareness, subblock wear management, and interference assessment.

[0045] Furthermore, the aforementioned programming interference test on flash memory, and the establishment of a physical page interference model table based on the test results, can specifically include: performing a programming operation on the first subpage location within a physical page, and detecting the original bit error rate increments at each second subpage location within the same physical page caused by the programming operation; statistically analyzing the original bit error rate increments corresponding to multiple programming operations to determine the average original bit error rate increment at each second subpage location and the maximum value among the original bit error rate increments; calculating the ratio of the average to the maximum value of each original bit error rate increment to obtain the programming interference weight of the first subpage location on each second page location; changing the first subpage location and repeatedly determining the programming interference weight to obtain a physical page interference model table characterizing the programming interference relationship between different subpage locations within a physical page.

[0046] In this implementation, programming interference testing can be completed during the calibration phase of the flash memory product, and the test results are written to the firmware and loaded during controller initialization. When a model update is required, the test can also be retested during the preset maintenance phase. During testing, a programming operation is performed using a specific subpage location within a physical page as the first subpage location. The original bit error rate (BER) of other subpage locations within the same physical page before and after programming is read, and the difference between the two is taken as the original BER increment. By repeating the test on different data modes, different number of cycles, or multiple sample pages, the average BER increment of each second subpage location and the maximum value among all increments are determined. The average value is normalized relative to the maximum value to obtain the programming interference weight of the first subpage location for each second subpage location. By sequentially changing the first subpage location, a physical page interference model table covering different location combinations within a page can be established. A larger programming interference weight indicates a stronger potential interference for the corresponding location combination. The number of tests, normalization method, and weight accuracy can be adjusted according to the flash memory model. By pre-quantifying the interference differences between different subpage locations, the storage location can be selected based on comparable risk indicators during subsequent migration, reducing the data reliability risk caused by allocation according to fixed location rules.

[0047] S102: Determine the number of valid and invalid subpages based on the subpage validity bitmap, and determine the lifetime of each candidate subblock based on wear information, and determine the target reclaimed subblock based on the lifetime.

[0048] In S102, the flash memory controller uses the subpage validity bitmap obtained in S101 to determine the amount of data still to be retained and the space that can be released in each candidate sub-block, and uses wear information to determine the usage level of each candidate sub-block. The number of valid subpages reflects the scale of data to be migrated when reclaiming candidate sub-blocks, while the number of invalid pages reflects the storage space that can be released after erasure. Lifetime status is the result of a comprehensive evaluation of the above space and wear factors. Lifetime status can be represented by a score, ranking level, or comparison indicator; the evaluation direction can be pre-defined, for example, a larger value indicates greater suitability for reclamation. The target reclamation sub-block is the sub-block ultimately selected from the candidate sub-blocks for data migration and erasure. By jointly considering the data validity status and wear status, it is possible to avoid repeatedly erasing local sub-blocks by selecting only sub-blocks with a large amount of invalid data.

[0049] Furthermore, the above-mentioned determination of the number of valid and invalid subpages based on the subpage validity bitmap may include: obtaining the subpage validity bitmap corresponding to each physical page in each candidate subblock; counting the number of bits corresponding to the valid identifier in the subpage validity bitmap to obtain the number of valid subpages in the corresponding candidate subblock; and counting the number of bits corresponding to the invalid identifier in the subpage validity bitmap to obtain the number of invalid subpages in the corresponding candidate subblock.

[0050] In this implementation, during the statistical analysis, the controller reads the subpage validity bitmap of the physical pages contained in each candidate sub-block and identifies the bits in the bitmap used to represent valid and invalid states. The number of valid subpages is obtained by accumulating the number of bits corresponding to valid identifiers within the candidate sub-block range; similarly, the number of invalid subpages is obtained by accumulating the number of bits corresponding to invalid identifiers. If the subpage validity bitmap also contains unused, reserved, or abnormal states, these can be excluded or recorded separately according to preset rules before the statistical analysis to ensure that both types of quantities reflect the actual migrated data and reclaimable space. The specific binary values ​​of the valid and invalid identifiers are not limited to "1" and "0," as long as they can distinguish the subpage states. This statistical method directly quantifies migration overhead and space gains on a subpage basis, improving the granularity of candidate sub-block state evaluation.

[0051] Furthermore, the process of determining the number of valid and invalid subpages based on the subpage validity bitmap, and determining the lifetime of each candidate sub-block in conjunction with wear information, and determining the target reclaimed sub-block based on the lifetime, may include: obtaining the number of programming / erase cycles for each candidate sub-block, and determining the average number of programming / erase cycles based on the number of programming / erase cycles for each sub-block in the flash memory; determining the value result between the space reclamation benefit and data migration overhead of each candidate sub-block based on the difference between the number of invalid and valid subpages for each candidate sub-block; determining the wear result of each candidate sub-block based on the difference between the number of programming / erase cycles for each candidate sub-block and the average number of programming / erase cycles; determining the lifetime of each candidate sub-block based on the value result and the wear result, and identifying the candidate sub-block with the best lifetime as the target reclaimed sub-block.

[0052] In this implementation, the controller first obtains the number of program / erase operations for each candidate sub-block from the sub-block wear count table, and determines the average number of program / erase operations based on the sub-blocks participating in the statistics in the flash memory. A higher number of invalid subpages relative to the number of valid subpages generally indicates more free space and lower migration overhead after reclamation; a lower number of program / erase operations for a candidate sub-block relative to the average indicates less wear and a greater margin for subsequent erase operations. Therefore, the controller can generate a value result representing the trade-off between space reclamation benefits and data migration overhead, and a wear result representing the relative wear level of the candidate sub-blocks, and then combine these two results into a lifetime profile. The combination method can be weighted calculation, hierarchical comparison, or sequential sorting, as long as the evaluation direction of each candidate sub-block remains consistent. After evaluating all candidate sub-blocks, the candidate sub-block with the best lifetime profile is selected as the target reclamation sub-block. This process makes the reclamation decision constrained by both sub-page state and sub-block wear, which helps to suppress write amplification and alleviate wear concentration while releasing space.

[0053] Furthermore, determining the lifetime of each candidate sub-block based on the value result and the wear result may include: subtracting the product of the first weighting coefficient and the number of valid sub-pages from the number of invalid sub-pages to obtain the value result; subtracting the programming / erase count of the corresponding candidate sub-block from the average programming / erase count, and multiplying the difference by the second weighting coefficient to obtain the wear result; and adding the value result and the wear result to obtain the lifetime of the corresponding candidate sub-block.

[0054] In one specific calculation method, the value result can be expressed as the number of invalid subpages minus the product of the first weighting coefficient and the number of valid subpages. Here, the number of invalid subpages corresponds to the freeable space, the number of valid subpages corresponds to the data that needs to be moved, and the first weighting coefficient is used to adjust the controller's emphasis on migration overhead. The wear result can be expressed as the difference between the average number of programming / erase cycles and the number of programming / erase cycles of candidate subblocks, multiplied by the second weighting coefficient; the lower the number of programming / erase cycles of a candidate subblock is compared to the average, the greater the wear result. Adding the value result and the wear result yields the lifetime under a unified evaluation scale. The first and second weighting coefficients can be fixed values ​​greater than zero, or dynamically set according to write load, performance mode, or lifetime stage. Horizontal comparisons can be performed by applying the same calculation rules to each candidate subblock. This method transforms space gains, migration costs, and wear leveling into a calculable comprehensive result, facilitating the rapid selection of target reclaimable subblocks that balance current recycling efficiency and long-term lifetime.

[0055] For example, you can refer to Figure 3 , Figure 3 This is a schematic diagram of a collaborative lifetime decision-making method provided in an embodiment of the present invention. The page-sub-block collaborative management module of the controller first obtains the subpage validity bitmap of the candidate sub-block, the number of programming / erase cycles of the candidate sub-block, the average number of programming / erase cycles, and the weighting coefficient; the bitmaps of the three physical pages are "1001", "0101", and "0001" respectively, thus calculating 5 valid subpages and 7 invalid subpages. Subsequently, according to the preset scoring formula: When the first weighting coefficient m is 0.5, the value result is 7 - 0.5 × 5 = 4.5; when the average number of programming / erasing operations is 1500, the number of programming / erasing operations for the candidate sub-block is 1200, and the second weighting coefficient n is 0.3, the wear result is 0.3 × (1500 - 1200) = 90; adding the value result and the wear result, the comprehensive score of the candidate sub-block is obtained as 94.5. After completing the score calculation for each candidate sub-block, the comprehensive scores are compared, and the candidate sub-block with the highest comprehensive score is determined as the target recovery sub-block.

[0056] S103: Obtain the valid subpage data and corresponding logical addresses in the target reclaimed subblock, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated.

[0057] In S103, the controller only reads valid subpage data within the target reclaimed subblock, avoiding the migration of expired data. Logical addresses identify data addresses managed by the host side or flash translation layer; the controller can identify spatially local data based on the continuity or proximity of logical addresses. Aggregation refers to rearranging or grouping the scattered valid subpage data within the controller's available storage space, allowing multiple related subpages to be written as a single unit of data to be migrated. The data to be migrated can contain one or more valid subpages, the size of which can be determined based on the writable physical page capacity, cache size, and write strategy. Data extraction, logical relationship analysis, and data reorganization can be performed sequentially. By organizing valid data before migration, scattered small-granularity writes are reduced, and a unified data unit is provided for subsequent selection of appropriate subpage locations within physical pages.

[0058] Furthermore, the above-mentioned acquisition of valid subpage data and corresponding logical addresses in the target reclaimed subblock may include: reading the subpage validity bitmap corresponding to each physical page in the target reclaimed subblock; determining each subpage marked as valid based on the subpage validity bitmap and generating a list of valid subpages; reading the original data stored in each valid subpage based on the list of valid subpages to obtain the valid subpage data; and obtaining the logical address corresponding to the original data based on the mapping relationship corresponding to each valid subpage.

[0059] In this implementation, the controller first reads the subpage validity bitmap of each physical page in the target reclaimed sub-block and determines the location of the subpages to be retained based on the validity identifiers. After organizing these subpage locations, their respective physical pages, and intra-page offsets into a valid subpage list, the controller can initiate a read operation according to the valid subpage list to obtain the original data stored in the corresponding subpage. For each valid subpage, the controller can also query the mapping information maintained by the flash memory translation layer to determine the logical address corresponding to the original data. The valid subpage list can be arranged according to physical location, logical address, or read batch; this embodiment does not limit this. If a verification anomaly is found during the read process, it can also be handled according to the controller's existing error correction or reread mechanism. This method uses the subpage validity bitmap to directly locate the data to be migrated, reduces the reading of invalid subpages, and keeps the original data corresponding to the logical address, providing accurate input for subsequent sorting and aggregation.

[0060] Furthermore, the above-mentioned aggregation of valid subpage data based on the relationship between logical addresses to obtain the data to be migrated may include: reading the valid subpage data and its corresponding logical addresses into the controller cache; sorting the valid subpage data according to the logical addresses and determining the logical address interval between adjacent valid subpage data; dividing valid subpage data with consecutive logical addresses or logical address intervals less than a preset interval threshold into the same data set; grouping the valid subpage data in each data set according to the number of subpages contained in a single physical page, so that the number of valid subpage data in each group does not exceed the number of subpages contained in a single physical page, and determining each group of valid subpage data as the data to be migrated.

[0061] In this implementation, the controller can temporarily store the read valid subpage data and logical addresses in a cache, and sort them according to their logical addresses in ascending or descending order. For two adjacent valid subpages after sorting, the controller can calculate their logical address interval. If the logical addresses are consecutive, or the logical address interval is less than a preset interval threshold, the corresponding data is considered to have strong spatial locality and is grouped into the same data set. The preset interval threshold can be set according to the logical address granularity, cache capacity, and access characteristics. Subsequently, each data set is further grouped according to the number of subpages that a single physical page can accommodate, so that each group of data can be stored within a single physical page. When the size of the data set exceeds the capacity of a single page, it can be split into multiple groups. The sorted logical address order can be retained within each group, and it is treated as a set of data to be migrated. This method re-centralizes logically related but physically scattered data, which can improve the density and order of migration writes, reduce physical page space fragmentation, and reduce subsequent additional migrations caused by data dispersion.

[0062] For example, refer to Figure 4 , Figure 4This is a schematic diagram of a data reorganization and migration process provided in an embodiment of the present invention. After determining the target reclaimed sub-block, the system reads the data of each valid sub-page and its corresponding logical block address (LBA) from the NAND flash memory according to the list of valid sub-pages. The controller's data layout module sorts the valid sub-page data according to the logical block address, and sequentially determines the logical address interval between adjacent valid sub-page data. When the logical addresses are consecutive or the logical address interval is less than the interval threshold set by the system, the corresponding valid sub-page data is divided into the same data set, and the number of valid sub-pages in each data set does not exceed the total number of sub-pages contained in a single physical page. For valid sub-page data that does not meet the above conditions, it is regrouped and aggregated according to a preset threshold. Subsequently, the valid sub-page data in each data set is reorganized in the controller cache to form data to be migrated with higher data density. The system queries the physical page interference model table to evaluate the programming interference risk corresponding to the writable sub-page location in each candidate physical page, and selects the target storage location with a smaller programming interference to write the data to be migrated. After the writing is completed, the mapping relationship between logical address and physical location in the flash translation layer (FTL) is updated.

[0063] Furthermore, after obtaining the valid subpage data and corresponding logical addresses in the target reclaimed subblock, the process may further include: obtaining read count information and error verification information corresponding to the valid subpage data; determining the read disturbance risk corresponding to the valid subpage data based on the read count information, and determining the data reliability status corresponding to the valid subpage data based on the error verification information; when the read disturbance risk exceeds a preset risk threshold, or the data reliability status does not meet the preset reliability conditions, performing data recovery processing on the valid subpage data to obtain the recovered valid subpage data; performing data aggregation based on the recovered valid subpage data, and writing the aggregated data to the target storage location. This allows for timely identification and repair of valid data with low reliability during garbage collection, preventing data with error risks from being directly migrated to a new storage location, thereby improving the accuracy and reliability of migrated data and reducing repeated reads, repeated migrations, and additional programming operations caused by data errors.

[0064] S104: Based on the programming interference relationship between different subpage locations within a physical page, determine the target storage location with the least interference from multiple candidate storage locations.

[0065] In S104, a candidate storage location refers to a combination of one or more writable subpage locations capable of accommodating the data to be migrated. Since different subpage locations within the same physical page may have different impacts on other locations during programming, the controller can use pre-obtained or runtime-updated programming interference relationships to perform a risk assessment of each candidate storage location. The interference level characterizes the combined impact that writing the data to be migrated to a candidate storage location may have on the existing valid data within that physical page and the subpage to be written. The target storage location is the combination of candidate storage locations with the lowest interference level. The interference level can be obtained through weighted accumulation, ranking comparison, or other methods that reflect the relative strength of interference. By comparing multiple locations that meet the capacity requirements, rather than directly selecting the first free location, the impact of migration writes on the reliability of data within the page can be reduced.

[0066] Furthermore, the above-mentioned determination of the target storage location with the minimum interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within a physical page may include: determining multiple candidate storage locations from the writable subpage locations of multiple candidate physical pages based on the number of subpages occupied by the data to be migrated; determining the amount of programming interference generated by writing the data to be migrated to each candidate storage location based on the programming interference relationship; comparing the programming interference amounts corresponding to each candidate storage location, and determining the candidate storage location with the minimum programming interference amount as the target storage location.

[0067] In this implementation, the controller first filters candidate physical pages with a sufficient number of writable subpages based on the number of subpages contained in the data to be migrated. Then, multiple candidate storage locations are formed from the writable areas of these candidate physical pages. For each candidate storage location, the controller estimates the amount of programming interference generated after writing the corresponding number of subpages based on programming interference relationships. During estimation, the size of the data to be migrated and the capacity of the candidate storage location are kept at least matched to avoid further splitting due to insufficient capacity. After calculating the programming interference of each candidate storage location using the same rules, the controller compares them and selects the one with the smallest programming interference as the target storage location. If multiple minimum values ​​exist, the selection can be further based on the remaining writable space, physical page status, or preset priority. This method, while ensuring that the data to be migrated can be written completely, uses programming interference as a location allocation condition, which helps reduce the risk of additional bit errors during the garbage collection and migration process.

[0068] Furthermore, determining the amount of programming interference generated by writing the data to be migrated to each candidate storage location based on the aforementioned programming interference relationship may include: determining the number of valid subpage data contained in the data to be migrated, and determining multiple candidate physical pages from physical pages with writable subpage locations having no less than the number of valid subpage data; for each candidate physical page, selecting subpage locations with the same number of valid subpage data as the writable subpage locations in the candidate physical page, forming multiple candidate subpage location combinations, and determining each candidate subpage location combination as a candidate storage location; determining the subpage locations in each candidate physical page that have stored valid data, and for each subpage location to be programmed in each candidate subpage location combination, querying the physical page interference model table for the subpage location to be programmed that has stored valid data. The system calculates the first interference weight generated by the location; for candidate subpage location combinations containing at least two subpage locations to be programmed, it queries the physical page interference model table to find the second interference weight generated between the subpage locations to be programmed in the candidate subpage location combination; it sums the first interference weight and the second interference weight corresponding to the same candidate subpage location combination to obtain the programming interference amount corresponding to the candidate subpage location combination; it determines the programming interference amount corresponding to different candidate subpage location combinations in each candidate physical page, and compares each candidate subpage location combination based on the programming interference amount; it determines the candidate subpage location combination with the smallest programming interference amount as the target storage location, and establishes the correspondence between each valid subpage data and each subpage location to be programmed in the target storage location according to the arrangement order of each valid subpage data in the data to be migrated.

[0069] In a more specific implementation, the controller first determines the number of valid subpages contained in a set of data to be migrated, and then filters candidate physical pages with at least that number of writable subpages. For each candidate physical page, different combinations of locations with the same number of valid subpages can be selected from its writable subpage locations; each combination constitutes a candidate storage location. Subsequently, the controller determines the subpage locations in the candidate physical pages that already store valid data, and queries the physical page interference model table to find the first interference weight of each subpage location to be programmed on these subpage locations that already store valid data, to characterize the impact of new writes on the original data. When a candidate storage location contains more than two subpage locations to be programmed, the controller also queries the second interference weight between each subpage location to be programmed, to characterize the mutual influence between locations in the same batch of writes. The first interference weight and the second interference weight under the same candidate storage location are summed to obtain the programming interference amount of that candidate storage location. After completing the calculations for different candidate physical pages and different location combinations, the candidate storage location with the smallest programming interference amount is selected, and a one-to-one correspondence between valid subpages and subpage locations to be programmed is established according to the order of the data to be migrated. The first and second interference weights can come from different entries in the same model table, as long as their units or normalization scales remain consistent. This method can simultaneously consider the impact of new data on existing data and the mutual influence between newly written subpages, making the location selection results more comprehensive.

[0070] S105: Write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock.

[0071] In S105, the flash memory controller writes the data to be migrated to the target storage location according to the established data-to-subpage location correspondence. After confirming successful writing, it updates the mapping relationship between logical addresses and physical locations maintained by the flash memory translation layer, so that subsequent accesses to the corresponding logical addresses point to the new physical locations. Simultaneously, the valid status of the newly written subpage is updated to valid, and the valid status of the subpages corresponding to the original storage locations that have completed migration in the target reclaimed subblock is updated to invalid, to prevent both old and new locations from being simultaneously identified as currently valid data. Once all the data that needs to be retained in the target reclaimed subblock has been migrated, the controller can perform an erase operation. After successful erasure, it updates the wear information and free status of the subblock, allowing it to re-participate in subsequent space allocation. Logs, verification flags, or transaction mechanisms can be used to ensure anomaly recovery between mapping updates, status updates, and erasure; this embodiment does not limit the specific implementation. By synchronously updating the mapping, valid status, and wear status after write confirmation, the controller's metadata can be kept consistent with the actual flash memory status, completing a closed-loop subpage status awareness and subblock reclamation process.

[0072] Furthermore, after the data to be migrated is written to the target storage location, the process may further include: reading back the data to be migrated from the target storage location to obtain the readback data, and performing a consistency check on the readback data and the data to be migrated before writing; when the consistency check passes, updating the mapping relationship between the logical address and the physical location, and marking the atomic page location as invalid; when the consistency check fails, marking the target storage location as unavailable, determining the alternative storage location with the second smallest programming interference from the remaining candidate storage locations, writing the data to be migrated to the alternative storage location, and performing a consistency check again. In this implementation, after the data to be migrated is written to the target storage location, the mapping relationship is not immediately updated and the target reclaimed sub-block is not erased. Instead, the data is first read back from the target storage location, and the consistency between the readback data and the data before writing is verified by means of checksum, hash value, or bit-by-bit comparison; only after the verification passes is the logical address mapped to the target storage location and the atomic page marked as invalid. If the verification fails, the current target storage location is stopped from being used, and the candidate storage location with the second smallest programming interference is selected for rewriting. This avoids writing erroneous data into the mapping table due to programming failures, storage unit degradation, or programming interference, and prevents the original valid data from being prematurely invalidated or erased when migration fails, thereby improving the reliability and fault tolerance of data migration during garbage collection and reducing the risk of data loss.

[0073] The flash memory garbage collection method provided in this embodiment of the invention proceeds as follows: S101: When garbage collection is triggered, at least one candidate sub-block is determined, and the subpage validity bitmap and wear information of each candidate sub-block are obtained; S102: The number of valid subpages and invalid subpages are determined according to the subpage validity bitmap, and the lifetime of each candidate sub-block is determined in combination with the wear information, and the target reclaimed sub-block is determined according to the lifetime; S103: The valid subpage data and corresponding logical addresses in the target reclaimed sub-block are obtained, and the valid subpage data is aggregated according to the relationship between logical addresses to obtain the data to be migrated; S104: According to the programming interference relationship between different subpage locations within a physical page, the target storage location with the least interference is determined from multiple candidate storage locations; S105: The data to be migrated is written to the target storage location, the mapping relationship between logical addresses and physical locations and the subpage validity status are updated, the target reclaimed sub-block is erased, and the wear information of the target reclaimed sub-block is updated. This method achieves deep collaboration between subpage state awareness and subblock operation execution. It utilizes a subpage validity bitmap to accurately reflect the validity status of data within candidate subblocks and combines this with subblock wear information to determine target reclaimed subblocks. This ensures that the selection of reclaimed objects balances space release benefits, valid data migration overhead, and wear level. Simultaneously, it aggregates valid subpage data based on logical address relationships, reducing the dispersion of migrated data and additional writes. Furthermore, it selects the storage location with the least interference based on the programming interference relationship between subpage locations, minimizing the impact of migration writes on other data within the same physical page. Therefore, it can reduce write amplification and programming interference caused by garbage collection, improve uneven subblock wear, enhance data storage reliability, and extend flash memory lifespan.

[0074] For a clearer understanding of this invention, please refer to the following details. Figure 5 , Figure 5 This is a flowchart illustrating a flash memory garbage collection method provided in an embodiment of the present invention, which may specifically include: The system initializes and constructs metadata, establishing a subpage validity bitmap, a subpage mapping table, and a subblock wear count table. Upon receiving data written by the host, the system writes the data to the corresponding subpage and synchronously updates the subpage validity bitmap and subpage mapping table. When the number of free subblocks is detected to be below a preset threshold, the lifespan extension engine is triggered to execute the garbage collection process. The subpage-subblock collaborative management module combines the number of valid subpages, invalid subpages, and wear information of each candidate subblock to perform lifespan scoring, and determines the candidate subblock with the highest score as the target reclaimed subblock. Subsequently, the system reads the valid subpage data in the target reclaimed subblock, reorganizes and aggregates the valid subpage data according to the logical address relationship, writes the aggregated data to the target storage location, and updates the mapping relationship between logical address and physical location and the subpage validity status. Finally, after confirming that the valid data migration is complete, the target reclaimed subblock is erased, and the subblock wear count table is updated, thus completing one garbage collection process.

[0075] The flash memory garbage collection device provided in the embodiments of the present invention will be described below. The flash memory garbage collection device described below can be referred to in correspondence with the flash memory garbage collection method described above.

[0076] Please refer to the details. Figure 6 , Figure 6 A schematic diagram of a flash memory garbage collection device provided in an embodiment of the present invention may include: The information acquisition module 100 is used to determine at least one candidate sub-block when garbage collection is triggered, and to acquire the subpage validity bitmap and wear information of each candidate sub-block; The recycling sub-block determination module 200 is used to determine the number of valid sub-pages and the number of invalid sub-pages based on the sub-page validity bitmap, and to determine the lifetime of each candidate sub-block in combination with the wear information, and to determine the target recycling sub-block based on the lifetime. The data aggregation module 300 is used to obtain the valid subpage data and corresponding logical addresses in the target recycling subblock, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; The storage location determination module 400 is used to determine the target storage location with the least interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within a physical page. The erase and update module 500 is used to write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock.

[0077] Based on any of the above embodiments, the flash memory garbage collection device may further include: The partitioning module is used to determine the sub-block partitioning parameters and sub-page partitioning parameters based on the physical specifications of the flash memory; The subpage validity bit chart module is used to establish a subpage validity bit chart for each physical page according to the subpage division parameters, so that each bit in the subpage validity bit chart corresponds to each subpage in the physical page, and records the validity status of the corresponding subpage with a valid or invalid identifier. The sub-block wear counting table module is used to establish a sub-block wear counting table for each sub-block according to the sub-block division parameters, and to record the number of programming / erasing operations for each sub-block in the sub-block wear counting table; The physical page interference model table module is used to perform programming interference tests on the flash memory and establish a physical page interference model table based on the programming interference test results. The storage module is used to store the subpage validity bit chart, the subblock wear count table, and the physical page interference model table in the controller storage space; The identification module is used to respond to subpage data writing or data migration operations by setting the bit corresponding to the data writing position as a valid identifier and setting the bit corresponding to the atomic page position as an invalid identifier according to the original mapping relationship of the overwritten or migrated data. The update module is used to increment the programming / erase count of the corresponding sub-block in the sub-block wear count table by one in response to the sub-block erase operation.

[0078] Based on any of the above embodiments, the physical page interference model table module may include: The programming unit is used to perform a programming operation on the first subpage location within a physical page and to detect the original bit error rate increments at each second subpage location within the same physical page caused by the programming operation. The first statistical unit is used to statistically analyze the original bit error rate increments corresponding to multiple programming operations, and to determine the average value of the original bit error rate increments corresponding to each second subpage position and the maximum value among the original bit error rate increments. The calculation unit is used to calculate the ratio of the average value of the bit error rate increment of each original bit to the maximum value, so as to obtain the programming interference weight of the first subpage position to each second subpage position; A construction unit is used to change the position of the first subpage and repeatedly determine the programming interference weights to obtain a physical page interference model table that characterizes the programming interference relationship between different subpage positions within a physical page.

[0079] Based on any of the above embodiments, the information acquisition module 100 may include: The determining unit is used to determine the physical pages in each candidate sub-block based on the sub-block identifier of each candidate sub-block; The reading unit is used to read the subpage validity bitmap corresponding to each physical page according to the correspondence between the physical page and the subpage validity bitmap; The summarization unit is used to summarize the subpage validity bitmaps corresponding to each physical page belonging to the same candidate sub-block, and obtain the subpage validity bitmaps for each candidate sub-block.

[0080] Based on any of the above embodiments, the recycling sub-block determination module 200 may include: The acquisition unit is used to acquire the subpage validity bitmap corresponding to each physical page in each candidate subblock; The second statistical unit is used to count the number of bits corresponding to the valid identifier in the subpage validity bitmap to obtain the number of valid subpages of the corresponding candidate subblock. The third statistical unit is used to count the number of bits corresponding to the invalid identifier in the subpage validity bitmap, and to obtain the number of invalid subpages of the corresponding candidate subblock.

[0081] Based on any of the above embodiments, the recycling sub-block determination module 200 may include: The count acquisition unit is used to acquire the number of programming / erasing operations for each candidate sub-block and determine the average number of programming / erasing operations based on the number of programming / erasing operations for each sub-block in the flash memory; The result determination unit is used to determine the value result between the space reclamation benefit and data migration overhead of each candidate sub-block based on the difference between the number of invalid sub-pages and the number of valid sub-pages of each candidate sub-block. The wear result confirmation unit is used to determine the wear result of each candidate sub-block based on the difference between the number of programming / wiping times of each candidate sub-block and the average number of programming / wiping times. The recycling sub-block determination unit is used to determine the lifespan of each candidate sub-block based on the value result and the wear result, and to determine the candidate sub-block with the best lifespan as the target recycling sub-block.

[0082] Based on any of the above embodiments, the reclaimed sub-block determination unit may include: The spatial migration value calculation subunit is used to subtract the product of the first weighting coefficient and the number of valid pages from the number of invalid pages to obtain the value result; The wear value calculation subunit is used to subtract the programming / erasing count of the corresponding candidate sub-block from the average programming / erasing count, and multiply the resulting difference by the second weighting coefficient to obtain the wear result; The lifetime determination subunit is used to add the value result to the wear result to obtain the lifetime status of the corresponding candidate sub-block.

[0083] Based on any of the above embodiments, the storage location determination module 400 may include: The candidate location determination unit is used to determine multiple candidate storage locations from the writable subpage locations of multiple candidate physical pages based on the number of subpages occupied by the data to be migrated. The programming interference determination unit is used to determine the amount of programming interference generated by writing the data to be migrated to each candidate storage location based on the programming interference relationship. The comparison unit is used to compare the programming interference amount corresponding to each candidate storage location and determine the candidate storage location with the smallest programming interference amount as the target storage location.

[0084] Based on any of the above embodiments, the programming interference determination unit may include: The candidate physical page determination subunit is used to determine the number of valid subpage data contained in the data to be migrated, and to determine multiple candidate physical pages from physical pages with writable subpage locations that are not less than the number of valid subpage data. The candidate storage location determination subunit is used to select, for each candidate physical page, a number of subpage locations equal to the number of valid subpage data locations based on the writable subpage locations in the candidate physical page, forming multiple candidate subpage location combinations, and determining each candidate subpage location combination as a candidate storage location; The first interference weight determination subunit is used to determine the location of the subpage with stored valid data in each candidate physical page, and for each subpage location to be programmed in each candidate subpage location combination, query the physical page interference model table for the first interference weight generated by the subpage location to be programmed on the subpage location with stored valid data. The second interference weight determination subunit is used to query the physical page interference model table for the second interference weight generated between each subpage position to be programmed in the candidate subpage position combination containing at least two subpage positions to be programmed. The programming interference determination subunit is used to accumulate the first interference weights and the second interference weights corresponding to the same candidate subpage position combination to obtain the programming interference amount corresponding to the candidate subpage position combination.

[0085] Based on any of the above embodiments, the data aggregation module 300 may include: The reading unit is used to read the valid subpage data and its corresponding logical address into the controller cache. A sorting unit is used to sort the valid subpage data according to the logical address and determine the logical address interval between adjacent valid subpage data. A set partitioning unit is used to partition valid subpage data with consecutive logical addresses or with logical address intervals less than a preset interval threshold into the same data set; The data to be migrated determination unit is used to group the valid subpage data in each data set according to the number of subpages contained in a single physical page, so that the number of valid subpage data in each group does not exceed the number of subpages contained in a single physical page, and to determine the valid subpage data in each group as the data to be migrated.

[0086] Based on any of the above embodiments, the information acquisition module 100 may include: The monitoring unit is used to monitor the number of free sub-blocks in the flash memory; A threshold unit is used to determine a garbage collection trigger threshold based on write load and remaining lifetime, and to adjust the garbage collection trigger threshold according to changes in the write load or the remaining lifetime. The invalid subpage ratio determination unit is used to determine the invalid subpage ratio of each non-free sub-block when the number of free sub-blocks is lower than the garbage collection trigger threshold. A filtering unit is used to filter at least one candidate sub-block from the non-idle sub-blocks according to the proportion of invalid sub-pages.

[0087] Based on any of the above embodiments, the data aggregation module 300 may include: The subpage validity bitmap reading unit is used to read the subpage validity bitmap corresponding to each physical page in the target reclaimed subblock; The valid subpage list generation unit is used to determine each subpage marked as valid based on the subpage validity bitmap, and generate a valid subpage list; The valid subpage data acquisition unit is used to read the original data stored in each valid subpage according to the valid subpage list to obtain the valid subpage data; The logical address acquisition unit is used to acquire the logical address corresponding to the original data according to the mapping relationship corresponding to each valid subpage.

[0088] It should be noted that the order of the modules and units in the aforementioned flash memory garbage collection device can be changed without affecting the logic.

[0089] The flash memory garbage collection device provided in this embodiment of the invention includes an information acquisition module 100, which determines at least one candidate sub-block and acquires the subpage validity bitmap and wear information of each candidate sub-block when garbage collection is triggered; a sub-block determination module 200, which determines the number of valid subpages and invalid subpages based on the subpage validity bitmap, and determines the lifetime of each candidate sub-block in conjunction with the wear information, and determines the target reclaimed sub-block based on the lifetime; a data aggregation module 300, which acquires the valid subpage data and corresponding logical addresses in the target reclaimed sub-block, and aggregates the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; a storage location determination module 400, which determines the target storage location with the least interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within a physical page; and an erase and update module 500, which writes the data to be migrated to the target storage location, updates the mapping relationship between logical addresses and physical locations and the subpage validity status, erases the target reclaimed sub-block, and updates the wear information of the target reclaimed sub-block. This device achieves deep collaboration between subpage status awareness and subblock operation execution. It utilizes a subpage validity bitmap to accurately reflect the data validity status within candidate subblocks and combines this with subblock wear information to determine target reclaimed subblocks. This ensures that the selection of reclaimed objects balances space release benefits, valid data migration overhead, and wear level. Simultaneously, it aggregates valid subpage data based on logical address relationships, reducing the dispersion of migrated data and additional writes. Furthermore, it selects the storage location with the least interference based on the programming interference relationship between subpage locations, minimizing the impact of migration writes on other data within the same physical page. Therefore, it can reduce write amplification and programming interference caused by garbage collection, improve uneven subblock wear, enhance data storage reliability, and extend flash memory lifespan.

[0090] The flash memory garbage collection device provided in the embodiments of the present invention is described below. The flash memory garbage collection device described below can be referred to in correspondence with the flash memory garbage collection method described above. Please refer to... Figure 7 , Figure 7 A schematic diagram of a flash memory waste recycling device provided in an embodiment of the present invention may include: Memory 60 is used to store computer programs; The processor 61 is used to implement the steps of the flash memory garbage collection method as described in the above embodiments when executing a computer program.

[0091] The flash memory recycling device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0092] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0093] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the flash memory garbage collection method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data related to the flash memory garbage collection method.

[0094] In some embodiments, the flash memory recycling device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0095] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on flash memory garbage collection devices and may include more or fewer components than illustrated.

[0096] It is understood that if the flash memory garbage collection method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical disks, and other media capable of storing program code.

[0097] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the flash memory garbage collection method described above.

[0098] The foregoing has provided a detailed description of a flash memory garbage collection method, apparatus, device, and storage medium provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0099] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0100] The present invention has provided a detailed description of a flash memory garbage collection method, apparatus, device, and storage medium. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative of the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A flash memory garbage collection method, characterized in that, include: When garbage collection is triggered, at least one candidate sub-block is identified, and the subpage validity bitmap and wear information of each candidate sub-block are obtained; The number of valid and invalid subpages is determined based on the subpage validity bitmap, and the lifetime of each candidate subblock is determined in conjunction with the wear information. The target reclaimed subblock is then determined based on the lifetime information. Obtain the valid subpage data and corresponding logical addresses in the target recycling subblock, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; Based on the programming interference relationship between different subpage locations within a physical page, the target storage location with the least interference is determined from multiple candidate storage locations; Write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock; Before obtaining the subpage validity bitmap and wear information for each candidate sub-block, the following steps are also included: The sub-block partitioning parameters and sub-page partitioning parameters are determined based on the physical specifications of the flash memory; Based on the subpage partitioning parameters, a subpage validity bit chart is established for each physical page, so that each bit in the subpage validity bit chart corresponds to each subpage in the physical page, and the validity status of the corresponding subpage is recorded with a valid or invalid identifier. A sub-block wear count table is established for each sub-block based on the sub-block division parameters, and the number of programming / erasing times for each sub-block is recorded in the sub-block wear count table; Perform a programming interference test on the flash memory, and establish a physical page interference model table based on the programming interference test results; The subpage validity bitmap, the subblock wear count table, and the physical page interference model table are stored in the controller storage space. In response to a subpage data write or data migration operation, the bit corresponding to the data write position is set to a valid flag, and the bit corresponding to the atomic page position is set to an invalid flag according to the original mapping relationship of the overwritten or migrated data. In response to a sub-block erase operation, the programming / erasing count of the corresponding sub-block in the sub-block wear count table is incremented by one; Perform a programming interference test on the flash memory, and establish a physical page interference model table based on the test results, including: Perform a programming operation on the first subpage location within a physical page, and detect the original bit error rate increments at each second subpage location within the same physical page caused by the programming operation; The raw bit error rate increments corresponding to multiple programming operations are statistically analyzed to determine the average raw bit error rate increments corresponding to each second subpage position and the maximum value among the raw bit error rate increments. Calculate the ratio of the average value of each original bit error rate increment to the maximum value to obtain the programming interference weight of the first subpage position to each second subpage position; By changing the position of the first subpage and repeatedly determining the programming interference weight, a physical page interference model table representing the programming interference relationship between different subpage positions within a physical page is obtained. The number of valid and invalid subpages is determined based on the subpage validity bitmap, and the lifetime of each candidate subblock is determined in conjunction with the wear information. The target reclaimed subblock is then determined based on the lifetime information, including: Obtain the number of programming / erase operations for each candidate sub-block, and determine the average number of programming / erase operations based on the number of programming / erase operations for each sub-block in the flash memory; Based on the difference between the number of invalid subpages and the number of valid subpages in each candidate subblock, determine the value result between the space reclamation benefit and data migration overhead of each candidate subblock; The wear result of each candidate sub-block is determined based on the difference between the number of programming / erasing operations for each candidate sub-block and the average number of programming / erasing operations. Based on the value results and the wear results, the lifetime status of each candidate sub-block is determined, and the candidate sub-block with the best lifetime status is determined as the target recycling sub-block.

2. The flash memory garbage collection method according to claim 1, characterized in that, Obtain the subpage validity bitmap for each candidate sub-block, including: Based on the sub-block identifier of each candidate sub-block, determine the physical pages in each candidate sub-block; Based on the correspondence between the physical page and the subpage validity bitmap, read the subpage validity bitmap corresponding to each physical page; The subpage validity bitmaps corresponding to each physical page belonging to the same candidate sub-block are summarized to obtain the subpage validity bitmaps for each candidate sub-block.

3. The flash memory garbage collection method according to claim 1, characterized in that, Determining the number of valid and invalid subpages based on the subpage validity bitmap includes: Obtain the subpage validity bitmap corresponding to each physical page in each candidate subblock; The number of valid subpages corresponding to the valid identifiers in the subpage validity bitmap is counted to obtain the number of valid subpages for the corresponding candidate subblock. The number of invalid subpages corresponding to the invalid identifiers in the subpage validity bitmap is counted to obtain the number of invalid subpages for the corresponding candidate sub-block.

4. The flash memory garbage collection method according to claim 1, characterized in that, The lifetime of each candidate sub-block is determined based on the value results and the wear results, including: The value result is obtained by subtracting the product of the first weighting coefficient and the number of valid pages from the number of invalid pages. The wear result is obtained by subtracting the programming / erase count of the corresponding candidate sub-block from the average programming / erase count and multiplying the difference by the second weighting coefficient. The value result is added to the wear result to obtain the lifetime status of the corresponding candidate sub-block.

5. The flash memory garbage collection method according to any one of claims 1 to 4, characterized in that, Based on the programming interference relationships between different subpage locations within a physical page, the target storage location with the minimum interference is determined from multiple candidate storage locations, including: Based on the number of subpages occupied by the data to be migrated, multiple candidate storage locations are determined from the writable subpage locations of multiple candidate physical pages; Based on the programming interference relationship, determine the amount of programming interference generated by writing the data to be migrated to each candidate storage location; Compare the programming interference amounts corresponding to each candidate storage location, and determine the candidate storage location with the smallest programming interference amount as the target storage location.

6. The flash memory garbage collection method according to claim 5, characterized in that, Based on the programming interference relationship, the amount of programming interference generated by writing the data to be migrated to each candidate storage location is determined, including: Determine the number of valid subpages contained in the data to be migrated, and identify multiple candidate physical pages from physical pages that have writable subpage locations that are no less than the number of valid subpages. For each candidate physical page, based on the writable subpage locations in the candidate physical page, select the same number of subpage locations as the number of valid subpage data to form multiple candidate subpage location combinations, and determine each candidate subpage location combination as a candidate storage location; Determine the location of the subpage with stored valid data in each candidate physical page, and for each subpage location to be programmed in each combination of candidate subpage locations, query the physical page interference model table for the first interference weight of the subpage location to be programmed on the subpage location with stored valid data; For a candidate subpage location combination containing at least two subpage locations to be programmed, a second interference weight generated between each subpage location to be programmed in the candidate subpage location combination is queried from the physical page interference model table; The programming interference amount corresponding to the candidate subpage position combination is obtained by summing the first interference weight and the second interference weight corresponding to the same candidate subpage position combination.

7. The flash memory garbage collection method according to claim 1, characterized in that, The valid subpage data is aggregated based on the relationships between the logical addresses to obtain the data to be migrated, including: Read the valid subpage data and its corresponding logical address into the controller cache. The valid subpage data is sorted according to the logical address, and the logical address interval between adjacent valid subpage data is determined. Valid subpage data with consecutive logical addresses or with logical address intervals less than a preset interval threshold are grouped into the same data set; The valid subpage data in each data set are grouped according to the number of subpages contained in a single physical page, so that the number of valid subpage data in each group does not exceed the number of subpages contained in a single physical page, and the valid subpage data in each group is determined as the data to be migrated.

8. The flash memory garbage collection method according to claim 1, characterized in that, When garbage collection is triggered, at least one candidate sub-block is identified, including: Monitor the number of free sub-blocks in flash memory; The garbage collection trigger threshold is determined based on the write load and remaining lifetime, and the garbage collection trigger threshold is adjusted according to changes in the write load or the remaining lifetime. When the number of free sub-blocks is lower than the garbage collection trigger threshold, the proportion of invalid sub-pages in each non-free sub-block is determined; At least one candidate sub-block is selected from the non-idle sub-blocks based on the invalid sub-page ratio.

9. The flash memory garbage collection method according to claim 1, characterized in that, Obtaining the valid subpage data and corresponding logical addresses in the target reclaimed subblock includes: Read the subpage validity bitmap corresponding to each physical page in the target reclaimed subblock; Based on the subpage validity bitmap, determine each subpage marked as valid and generate a list of valid subpages; The original data stored in each valid subpage is read from the list of valid subpages to obtain the valid subpage data; Based on the mapping relationship corresponding to each valid subpage, obtain the logical address corresponding to the original data.

10. A flash memory waste recycling device, characterized in that, include: The information acquisition module is used to identify at least one candidate sub-block when garbage collection is triggered, and to acquire the sub-page validity bitmap and wear information of each candidate sub-block; The recycling sub-block determination module is used to determine the number of valid sub-pages and invalid sub-pages based on the sub-page validity bitmap, and to determine the lifetime of each candidate sub-block in combination with the wear information, and to determine the target recycling sub-block based on the lifetime. The data aggregation module is used to obtain the valid subpage data and corresponding logical addresses in the target recycling sub-block, and aggregate the valid subpage data according to the relationship between the logical addresses to obtain the data to be migrated; The storage location determination module is used to determine the target storage location with the least interference from multiple candidate storage locations based on the programming interference relationship between different subpage locations within a physical page. The erase and update module is used to write the data to be migrated to the target storage location, update the mapping relationship between logical address and physical location and the valid status of subpages, erase the target reclaimed subblock and update the wear information of the target reclaimed subblock; The partitioning module is used to determine the sub-block partitioning parameters and sub-page partitioning parameters based on the physical specifications of the flash memory; The subpage validity bit chart module is used to establish a subpage validity bit chart for each physical page according to the subpage division parameters, so that each bit in the subpage validity bit chart corresponds to each subpage in the physical page, and records the validity status of the corresponding subpage with a valid or invalid identifier. The sub-block wear counting table module is used to establish a sub-block wear counting table for each sub-block according to the sub-block division parameters, and to record the number of programming / erasing operations for each sub-block in the sub-block wear counting table; The physical page interference model table module is used to perform programming interference tests on the flash memory and establish a physical page interference model table based on the programming interference test results. The storage module is used to store the subpage validity bit chart, the subblock wear count table, and the physical page interference model table in the controller storage space; The identification module is used to respond to subpage data writing or data migration operations by setting the bit corresponding to the data writing position as a valid identifier and setting the bit corresponding to the atomic page position as an invalid identifier according to the original mapping relationship of the overwritten or migrated data. The update module is used to increment the programming / erase count of the corresponding sub-block in the sub-block wear count table by one in response to the sub-block erase operation; The physical page interference model table module includes: The programming unit is used to perform a programming operation on the first subpage location within a physical page and to detect the original bit error rate increments at each second subpage location within the same physical page caused by the programming operation. The first statistical unit is used to statistically analyze the original bit error rate increments corresponding to multiple programming operations, and to determine the average value of the original bit error rate increments corresponding to each second subpage position and the maximum value among the original bit error rate increments. The calculation unit is used to calculate the ratio of the average value of the bit error rate increment of each original bit to the maximum value, so as to obtain the programming interference weight of the first subpage position to each second subpage position; A construction unit is used to change the position of the first subpage and repeatedly determine the programming interference weight to obtain a physical page interference model table that characterizes the programming interference relationship between different subpage positions within a physical page. The recycling sub-block determination module includes: The count acquisition unit is used to acquire the number of programming / erasing operations for each candidate sub-block and determine the average number of programming / erasing operations based on the number of programming / erasing operations for each sub-block in the flash memory; The result determination unit is used to determine the value result between the space reclamation benefit and data migration overhead of each candidate sub-block based on the difference between the number of invalid sub-pages and the number of valid sub-pages of each candidate sub-block. The wear result confirmation unit is used to determine the wear result of each candidate sub-block based on the difference between the number of programming / wiping times of each candidate sub-block and the average number of programming / wiping times. The recycling sub-block determination unit is used to determine the lifespan of each candidate sub-block based on the value result and the wear result, and to determine the candidate sub-block with the best lifespan as the target recycling sub-block.

11. A flash memory waste recycling device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the flash memory garbage collection method as claimed in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the flash memory garbage collection method as described in any one of claims 1 to 9.

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