Electrostatic discharge protection device including a silicon controlled rectifier

Abstract

The static discharge protection device of the present application including thyristor rectifier comprises: a substrate of a first conductive type; a ring disposed in the substrate, belonging to a second conductive type different from the first conductive type, comprising a first part and a second part spaced apart from each other; a first well of the first conductive type disposed in the substrate and disposed between the first part of the ring and the second part of the ring, spaced apart from the first part of the ring and the second part of the ring; a second well of the first conductive type disposed in the substrate and disposed between the first part of the ring and the second part of the ring, spaced apart from the first well, the first part of the ring and the second part of the ring; a third well of the first conductive type disposed in the substrate and disposed between the first well and the second well, spaced apart from the first well and the second well; and a cathode electrode connected between the first well and the third well, connected to the third well, and connected between the second well and the third well.

Description

Technical Field

[0001] This invention relates to an electrostatic discharge (ESD) protection device including a silicon controlled rectifier. Background Technology

[0002] The content described in this section is merely to provide background information for this embodiment and does not constitute prior art.

[0003] To protect the device from malfunction and damage, it is necessary to prevent electrostatic discharge (ESD). To achieve ESD protection, a silicon controlled rectifier (SCR) capable of bidirectional current control can be used.

[0004] For electrostatic discharge (ESD) protection devices that include silicon controlled rectifiers (SCRs), there may be a problem of low gain when the p-type well operates as the NPN base. Therefore, there is a need for ESD protection devices that include the SCR structure used to increase gain. Summary of the Invention

[0005] The problem the invention aims to solve

[0006] The purpose of this invention is to provide an electrostatic discharge protection device including a silicon controlled rectifier that can prevent electrostatic discharge.

[0007] The objectives of this invention are not limited to those mentioned above. Other objectives and advantages of this invention not mentioned can be understood through the following description and will become more apparent through embodiments of this invention. Furthermore, it is obvious that the objectives and advantages of this invention can be achieved through methods and combinations thereof described within the scope of the claims.

[0008] means for solving problems

[0009] An electrostatic discharge protection device for a silicon controlled rectifier (SCR) according to an embodiment of the present invention includes: a substrate of a first conductivity type; a ring disposed within the substrate, belonging to a second conductivity type different from the first conductivity type, including a first portion and a second portion spaced apart from each other; a first well of the first conductivity type disposed within the substrate and between the first portion and the second portion of the ring, spaced apart from the first portion and the second portion of the ring; a second well of the first conductivity type disposed within the substrate and between the first portion and the second portion of the ring, spaced apart from the first well, the first portion and the second portion of the ring; a third well of the first conductivity type disposed within the substrate and between the first well and the second well, spaced apart from the first well and the second well; and a cathode electrode connected between the first well and the third well, connected to the third well, and connected between the second well and the third well.

[0010] Furthermore, the first separation distance between the first well and the third well, and the second separation distance between the second well and the third well, are respectively 0.6 μm or more and 1.4 μm or less.

[0011] Furthermore, a first region of the substrate is disposed between the first well and the third well, and a second region of the substrate is disposed between the second well and the third well.

[0012] Furthermore, a third region of the substrate is disposed between the first well and the first portion of the ring, and a fourth region of the substrate is disposed between the second well and the second portion of the ring.

[0013] Furthermore, the ring further includes: a third portion of the ring of the second conductivity type, disposed within the substrate and spaced apart from the first portion and the second portion of the ring; a fourth portion of the ring, disposed within the substrate and connecting the first end of the first portion of the ring, the first end of the second portion of the ring, and the first end of the third portion of the ring; and a fifth portion of the ring, disposed within the substrate and connecting the second end of the first portion of the ring, the second end of the second portion of the ring, and the second end of the third portion of the ring.

[0014] Furthermore, the present invention further includes: a fourth well of the first conductivity type, disposed within the substrate and between the second portion and the third portion of the ring, spaced apart from the second portion and the third portion of the ring; a fifth well of the first conductivity type, disposed within the substrate and between the second portion and the third portion of the ring, spaced apart from the fourth well, the second portion and the third portion of the ring; a sixth well of the first conductivity type, disposed within the substrate and between the fourth well and the fifth well, spaced apart from the fourth well and the fifth well; and an anode electrode, connected between the fourth well and the sixth well, connected to the sixth well, and connected between the fifth well and the sixth well.

[0015] Furthermore, the fifth region of the substrate is disposed between the fourth well and the sixth well, and the sixth region of the substrate is disposed between the fifth well and the sixth well.

[0016] Furthermore, the seventh region of the substrate is disposed between the fourth well and the second portion of the ring, and the eighth region of the substrate is disposed between the fifth well and the third portion of the ring.

[0017] Furthermore, the present invention also includes: a tenth well of the second conductivity type disposed between the fourth well and the sixth well; an eleventh well of the first conductivity type disposed within the sixth well; and a twelfth well of the second conductivity type disposed between the fifth well and the sixth well, wherein the anode electrode is connected to the tenth well, the eleventh well, and the twelfth well.

[0018] Furthermore, the present invention also includes a peripheral well of the first conductivity type, disposed within the substrate to surround the ring.

[0019] Furthermore, the peripheral well is connected to the cathode electrode.

[0020] Furthermore, the present invention also includes: a seventh well of the second conductivity type disposed between the first well and the third well; an eighth well of the first conductivity type disposed within the third well; and a ninth well of the second conductivity type disposed between the second well and the third well, wherein the cathode electrode is connected to the seventh well, the eighth well, and the ninth well.

[0021] Furthermore, the present invention also includes a first buried layer of the second conductivity type disposed within the substrate, and the ring is connected to the first buried layer.

[0022] Furthermore, the present invention also includes a second buried layer disposed within the substrate and on the first buried layer, and connected to the ring.

[0023] Furthermore, the ring includes a first concentration region, a second concentration region on the first concentration region, and a third concentration region within the second concentration region.

[0024] Furthermore, the present invention also includes a first buried layer of the second conductivity type disposed within the substrate, a first concentration region disposed on the first buried layer within the substrate, and a first well, a second well, and a third well disposed within the substrate, spaced apart from the first concentration region between the first concentration region and the upper surface of the substrate.

[0025] An electrostatic discharge protection device for a silicon controlled rectifier (SCR) according to an embodiment of the present invention includes: a substrate of a first conductivity type; a first well and a second well of the first conductivity type, extending apart from each other along one direction and disposed within the substrate; a third well of the first conductivity type, extending along the one direction and disposed apart between the first well and the second well, and disposed within the substrate; a fourth well and a fifth well of the first conductivity type, extending apart from each other along the one direction and disposed within the substrate; a sixth well of the first conductivity type, extending along the one direction and disposed apart between the fourth well and the fifth well, and disposed within the substrate; a ring of a second conductivity type different from the first conductivity type, disposed within the substrate, separating the second well and the fourth well, and surrounding the first well to the sixth well; and a peripheral well of the first conductivity type, disposed within the substrate in a manner surrounding the ring.

[0026] Furthermore, the first separation distance between the first well and the third well, and the second separation distance between the second well and the third well, are respectively 0.6 μm or more and 1.4 μm or less.

[0027] Furthermore, a first region of the substrate is disposed between the first well and the third well, and a second region of the substrate is disposed between the second well and the third well.

[0028] Furthermore, a third region of the substrate is disposed between the first well and the ring, and a fourth region of the substrate is disposed between the second well and the ring.

[0029] Furthermore, the fifth region of the substrate is disposed between the fourth well and the sixth well, and the sixth region of the substrate is disposed between the fifth well and the sixth well.

[0030] Furthermore, the seventh region of the substrate is disposed between the fourth well and the ring, and the eighth region of the substrate is disposed between the fifth well and the ring.

[0031] Invention Effects

[0032] The electrostatic discharge protection device of the present invention, which includes a silicon controlled rectifier, can prevent electrostatic discharge by providing multiple mutually spaced traps in the substrate, thereby increasing the gain of the device.

[0033] In addition to the above description, the specific effects of the present invention will be described in the following description of specific embodiments. Attached Figure Description

[0034] Figure 1 This is a top view of an electrostatic discharge protection device including a silicon controlled rectifier, used to illustrate some embodiments of the present invention.

[0035] Figure 2 For along Figure 1 A cross-sectional view cut off by line A-A'.

[0036] Figure 3 for Figure 2 A magnified view of region M in the image.

[0037] Figure 4 The figure illustrates the effect of an electrostatic discharge protection device including a silicon controlled rectifier in some embodiments of the present invention.

[0038] Figure 5 For along Figure 1 A cross-sectional view cut off by line A-A'. Detailed Implementation

[0039] The terms or words used in this specification and the claims should not be construed as limited to their common or dictionary meanings. Based on the principle that inventors may define the concepts of terms or words to best illustrate their invention, they should be interpreted in accordance with the meanings and concepts consistent with the technical concept of this invention. Furthermore, the embodiments described in this specification and the structures shown in the figures are merely one embodiment of the invention and do not represent all the technical ideas of the invention. Therefore, at the time of filing this application, there may be various equivalent technical solutions and examples that can be modified and applied.

[0040] The terms "first," "second," "A," and "B," as used in this specification and the claims of the invention, may be used to describe various structural elements, but the structural elements should not be limited to these terms. These terms are used only to distinguish one structural element from other structural elements. For example, without departing from the scope of this invention, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element. The term "and / or" may include a combination of multiple related description items or any one of multiple related description items.

[0041] The terminology used in this specification and the claims is for illustrative purposes only and does not limit the invention. Unless otherwise defined in the context, singular expressions include plural expressions. Terms such as "comprising" or "having" in this application should be understood as not precluding the presence or additional possibilities of features, numbers, steps, actions, structural elements, components, or combinations thereof described in the specification.

[0042] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0043] Terms defined in commonly used dictionaries should be interpreted as having the same meaning as the relevant technology in the context, and should not be interpreted in an idealized or overly formalized sense unless explicitly defined in this application. Furthermore, the various structures, processes, techniques, or methods included in the embodiments of this invention can be shared to the extent that they are not technically contradictory.

[0044] The following will refer to Figure 1 , Figure 2 , Figure 3 as well as Figure 4 The electrostatic discharge protection device including a silicon controlled rectifier in some embodiments of the present invention will be described.

[0045] Figure 1 This is a top view of an electrostatic discharge protection device including a silicon controlled rectifier, used to illustrate some embodiments of the present invention. Figure 2 For along Figure 1 A cross-sectional view cut off by line A-A'. Figure 3 for Figure 2 A magnified view of region M in the image. Figure 4 This diagram illustrates the effect of an electrostatic discharge protection device including a silicon controlled rectifier (SCR) according to some embodiments of the present invention. Figure 1 For clarity, the diagrams of several electrodes and the seventh to twelfth wells have been omitted.

[0046] Reference Figure 1 and Figure 2 The electrostatic discharge protection device including a silicon controlled rectifier in some embodiments of the present invention may include: a substrate 100, a ring IR, a peripheral well SDW, a first well W1, a second well W2, a third well W3, a fourth well W4, a fifth well W5, and a sixth well W6.

[0047] The substrate 100 can be of a first conductivity type. For example, the substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Conversely, the substrate 100 can be a silicon substrate, or other materials, such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 can be a structure in which an epitaxial layer is formed on a substrate.

[0048] A ring IR can be disposed within the substrate 100. The ring IR can be of a second conductivity type. The first conductivity type and the second conductivity type can be different from each other. The ring IR can include a first portion IR1, a second portion IR2, a third portion IR3, a fourth portion IR4, and a fifth portion IR5. The first portion IR1, the second portion IR2, and the third portion IR3 of the ring IR can be spaced apart from each other. The second portion IR2 of the ring IR can be disposed between the first portion IR1 and the third portion IR3.

[0049] The IR ring may not be electrically connected to other devices.

[0050] The fourth part IR4 can connect to the first end of the first part IR1, the first end of the second part IR2, and the first end of the third part IR3. The fifth part IR5 can connect to the second end of the first part IR1, the second end of the second part IR2, and the second end of the third part IR3. The first end of the first part IR1, the first end of the second part IR2, and the first end of the third part IR3 can be the end portion on one side of each of the first part IR1, the second part IR2, and the third part IR3, respectively. The second end of the first part IR1, the second end of the second part IR2, and the second end of the third part IR3 can be the end portion on the other side of each of the first part IR1, the second part IR2, and the third part IR3, respectively.

[0051] A ring IR can surround multiple wells W1, W2, ... For example, the first part IR1, the second part IR2, a portion of the fourth part IR4, and a portion of the fifth part IR5 of a ring IR can surround the first well W1, the second well W2, the third well W3, the seventh well W7, the eighth well W8, and the ninth well W9. For example, the second part IR2, the third part IR3, the remainder of the fourth part IR4, and the remainder of the fifth part IR5 of a ring IR can surround the fourth well W4, the fifth well W5, the sixth well W6, the tenth well W10, the eleventh well W11, and the twelfth well W12.

[0052] The ring IR can extend from the upper surface of the substrate 100 to the lower surface of the substrate 100. The ring IR can be connected to a first buried layer BL1 disposed within the substrate 100. The first buried layer BL1 can be of a second conductivity type.

[0053] For example, the ring IR can include multiple regions with different doping concentrations. For example, the closer the ring IR is to the upper surface from the lower surface of the substrate 100, the higher the doping concentration of the impurity of the second conductivity type may be. Or, for example, the closer the ring IR is to the upper surface from the lower surface of the substrate 100, the higher the doping concentration of the impurity of the second conductivity type may first decrease and then increase again.

[0054] For example, the ring IR may include a first concentration region IR11, a second concentration region IR12, and a third concentration region IR13. The first concentration region IR11 may be disposed within the substrate 100. The second concentration region IR12 may be disposed on the first concentration region IR11. The doping concentrations of the second conductivity type impurities in the first concentration region IR11, the second concentration region IR12, and the third concentration region IR13 may be different from each other. For example, the third concentration region IR13 may be disposed within the second concentration region IR12. The doping concentration of the second conductivity type impurities in the first concentration region IR11 may be higher than the doping concentrations of the second conductivity type impurities in the second concentration regions IR12 and the third concentration region IR13.

[0055] The first concentration region IR11 of the ring IR can be connected to the first buried layer BL1. The first concentration region IR11 can be disposed on the first buried layer BL1 within the substrate 100.

[0056] The first portion IR1 and the second portion IR2 of the ring IR may further include a fourth concentration region IR14. The fourth concentration region IR14 may be disposed within the third concentration region IR13 and exposed on the upper surface of the substrate 100.

[0057] A peripheral well SDW can be disposed within the substrate 100. The peripheral well SDW can be of a first conductivity type. For example, the peripheral well SDW can have the same conductivity type as the substrate 100. The peripheral well SDW can surround the ring IR. The peripheral well SDW can be disposed spaced apart from the ring IR. Within the substrate 100, the peripheral well SDW can extend from the upper surface to the lower surface portion of the substrate 100.

[0058] Multiple electrodes CE and AE can be disposed on the substrate 100. The multiple electrodes CE and AE may include a cathode electrode CE and an anode electrode AE ​​disposed separately from each other.

[0059] The peripheral well SDW can be connected to the cathode electrode CE. The peripheral well SDW is connected to the cathode electrode CE and to the ground terminal, thereby significantly reducing the amount of current flowing to the substrate 100 when the device is operating.

[0060] The first well W1, the second well W2, and the third well W3 can be disposed between the first portion IR1 and the second portion IR2 of the ring IR. The first well W1, the second well W2, and the third well W3 can be of a first conductivity type. The first well W1, the second well W2, and the third well W3 can be disposed within the substrate 100. The first well W1, the second well W2, and the third well W3 can each extend in one direction between the first portion IR1 and the second portion IR2 of the ring IR. The first well W1, the second well W2, and the third well W3 can be spaced apart from each other. The first well W1, the second well W2, and the third well W3 can each be spaced apart from the first portion IR1 and the second portion IR2 of the ring IR. Within the substrate 100, the first well W1, the second well W2, and the third well W3 can each extend from the upper surface to the lower surface portion of the substrate 100.

[0061] The first well W1 can be separated from the first portion IR1 and the second portion IR2 of the ring IR. The second well W2 can be separated from the first well W1, the first portion IR1 of the ring IR, and the second portion IR2. Between the first well W1 and the second well W2, the third well W3 can be separated from the first well W1 and the second well W2.

[0062] Since the first well W1 and the third well W3 are spaced apart from each other, the first region R1 of the substrate 100 can be disposed between the first well W1 and the third well W3. Between the first well W1 and the third well W3, a seventh well W7 can be disposed on the first region R1 of the substrate 100. The seventh well W7 can be disposed within the substrate 100. The seventh well W7 can be disposed on the upper surface side of the substrate 100. The seventh well W7 can be of a second conductivity type. The seventh well W7 can be connected to the first region R1 of the substrate 100.

[0063] The eighth well W8 can be disposed within the third well W3. The eighth well W8 can be of the first conductivity type. The eighth well W8 can be disposed within the substrate 100. The doping concentration of the eighth well W8 can be higher than that of the third well W3. The eighth well W8 can be disposed on the upper surface side of the substrate 100.

[0064] Since the second well W2 and the third well W3 are spaced apart from each other, the second region R2 of the substrate 100 can be disposed between the second well W2 and the third well W3. Between the second well W2 and the third well W3, a ninth well W9 can be disposed on the second region R2 of the substrate 100. The ninth well W9 can be of a second conductivity type. The ninth well W9 can be disposed within the substrate 100. The ninth well W9 can be disposed on the upper surface side of the substrate 100. The ninth well W9 can be of a second conductivity type. The ninth well W9 can be connected to the second region R2 of the substrate 100.

[0065] Since the first portion IR1 of the ring IR is spaced apart from the first well W1, the third region R3 of the substrate 100 can be disposed between the first portion IR1 of the ring IR and the first well W1. Since the second portion IR2 of the ring IR is spaced apart from the second well W2, the fourth region R4 of the substrate 100 can be disposed between the second portion IR2 of the ring IR and the second well W2.

[0066] The cathode electrode CE can be connected between the first well W1 and the third well W3. For example, between the first well W1 and the third well W3, the cathode electrode CE can be connected to the seventh well W7. The cathode electrode CE can be connected to the third well W3. For example, the cathode electrode CE can be connected to the third well W3 via the eighth well W8. The cathode electrode CE can be connected between the second well W2 and the third well W3. For example, between the second well W2 and the third well W3, the cathode electrode CE can be connected to the ninth well W9. The cathode electrode CE can be connected to the peripheral well SDW.

[0067] The fourth well W4, the fifth well W5, and the sixth well W6 can be disposed between the second portion IR2 and the third portion IR3 of the ring IR. The fourth well W4, the fifth well W5, and the sixth well W6 can be of a first conductivity type. The fourth well W4, the fifth well W5, and the sixth well W6 can be disposed within the substrate 100. The fourth well W4, the fifth well W5, and the sixth well W6 can each extend in one direction between the second portion IR2 and the third portion IR3 of the ring IR. The fourth well W4, the fifth well W5, and the sixth well W6 can be spaced apart from each other. The fourth well W4, the fifth well W5, and the sixth well W6 can each be spaced apart from the second portion IR2 and the third portion IR3 of the ring IR. Within the substrate 100, the fourth well W4, the fifth well W5, and the sixth well W6 can each extend from the upper surface to the lower surface portion of the substrate 100. The fourth well W4, the fifth well W5, and the sixth well W6 can extend in the same direction as the first well W1, the second well W2, and the third well W3.

[0068] The fourth well W4 can be separated from the second portion IR2 and the third portion IR3 of the ring IR. The fifth well W5 can be separated from the fourth well W4, the second portion IR2 of the ring IR, and the third portion IR3. Between the fourth well W4 and the fifth well W5, the sixth well W6 can be separated from the fourth well W4 and the fifth well W5.

[0069] Since the fourth well W4 and the sixth well W6 are spaced apart from each other, the fifth region R5 of the substrate 100 can be disposed between the fourth well W4 and the sixth well W6. Between the fourth well W4 and the sixth well W6, the tenth well W10 can be disposed on the fifth region R5 of the substrate 100. The tenth well W10 can be disposed within the substrate 100. The tenth well W10 can be disposed on the upper surface side of the substrate 100. The tenth well W10 can be of a second conductivity type. The tenth well W10 can be connected to the fifth region R5 of the substrate 100.

[0070] The eleventh well W11 can be disposed within the sixth well W6. The eleventh well W11 can be of the first conductivity type. The eleventh well W11 can be disposed within the substrate 100. The doping concentration of the eleventh well W11 can be higher than that of the sixth well W6. The eleventh well W11 can be disposed on the upper surface side of the substrate 100.

[0071] Since the fifth well W5 and the sixth well W6 are spaced apart from each other, the sixth region R6 of the substrate 100 can be disposed between the fifth well W5 and the sixth well W6. Between the fifth well W5 and the sixth well W6, the twelfth well W12 can be disposed on the sixth region R6 of the substrate 100. The twelfth well W12 can be of a second conductivity type. The twelfth well W12 can be disposed within the substrate 100. The twelfth well W12 can be disposed on the upper surface side of the substrate 100. The twelfth well W12 can be of a second conductivity type. The twelfth well W12 can be connected to the sixth region R6 of the substrate 100.

[0072] Since the second portion IR2 of the ring IR and the fourth well W4 are spaced apart, the seventh region R7 of the substrate 100 can be disposed between the second portion IR2 of the ring IR and the fourth well W4. Since the third portion IR3 of the ring IR and the fifth well W5 are spaced apart, the eighth region R8 of the substrate 100 can be disposed between the third portion IR3 of the ring IR and the fifth well W5.

[0073] The anode electrode AE ​​can be connected between the fourth well W4 and the sixth well W6. For example, between the fourth well W4 and the third well W3, the anode electrode AE ​​can be connected to the tenth well W10. The anode electrode AE ​​can be connected to the sixth well W6. For example, the anode electrode AE ​​can be connected to the sixth well W6 via the eleventh well W11. The anode electrode AE ​​can be connected between the fifth well W5 and the sixth well W6. For example, between the fifth well W5 and the sixth well W6, the anode electrode AE ​​can be connected to the twelfth well W12.

[0074] The second buried layer BL2 can be disposed within the substrate 100. The second buried layer BL2 can be disposed between the first buried layer BL1 and a plurality of wells W1, W2, W3, ... The second buried layer BL2 can be disposed within a ring IR. For example, the second buried layer BL2 can be disposed between a first portion IR1 and a second portion IR2 of the ring IR. For example, the second buried layer BL2 can be disposed between a second portion IR2 and a third portion IR3 of the ring IR. The second buried layer BL2 can be of a first conductivity type. The second buried layer BL2 can be connected to the ring IR.

[0075] Reference Figure 3 and Figure 4A first spacing D1 can be separated between the first well W1 and the third well W3, and a second spacing D2 can be separated between the second well W2 and the third well W3. The first spacing D1 and the second spacing D2 can be distances measured along a direction parallel to the upper surface of the substrate 100. The first spacing D1 can be the width of the first region R1 of the substrate 100. The second spacing D2 can be the width of the second region R2 of the substrate 100. Furthermore, the first spacing D1 can be the spacing between the fourth well W4 and the sixth well W6, and the second spacing D2 can be the spacing between the fifth well W5 and the sixth well W6.

[0076] The first spacing D1 and the second spacing D2 can be greater than 0.6 μm and less than 1.4 μm. For example, when the width of the seventh well W7 is 1 μm, the first spacing D1 and the second spacing D2 can be greater than 0.6 μm and less than 1.4 μm.

[0077] Figure 4 The first curve G1 represents the transmission line pulse (TLP) characteristics of an existing electrostatic discharge protection device including a silicon controlled rectifier (SCR) under a positive supply voltage. In existing SCR rectifier-based ESD protection devices, the spacing between the first well W1 and the third well W3 can be less than 0.6 μm, the spacing between the second well W2 and the third well W3 can be less than 0.6 μm, the spacing between the fourth well W4 and the sixth well W6 can be less than 0.6 μm, and the spacing between the fifth well W5 and the sixth well W6 can be less than 0.6 μm.

[0078] The second curve G2 represents the TLP characteristics of the electrostatic discharge protection device including a silicon controlled rectifier (SCR) according to an embodiment of the present invention under a positive supply voltage. The third curve G3 represents the TLP characteristics of a conventional electrostatic discharge protection device including a SCR under a negative supply voltage. The fourth curve G4 represents the TLP characteristics of the electrostatic discharge protection device including a SCR under an embodiment of the present invention under a negative supply voltage.

[0079] The first current curve LP1 can relate to the leakage current of an existing electrostatic discharge protection device including a silicon controlled rectifier (SCR) under a positive supply voltage. The second current curve LP2 can relate to the leakage current of an electrostatic discharge protection device including a SCR under an embodiment of the present invention under a positive supply voltage.

[0080] In the case of the first curve G1, when a positive supply voltage is supplied to an existing electrostatic discharge protection device including a silicon controlled rectifier (SCR), leakage current is observed, and breakdown occurs after the current (in A) on the first current curve LP1 is approximately 23 A. In the case of the second curve G2, when a positive supply voltage is supplied to the electrostatic discharge protection device including a SCR in this embodiment of the invention, leakage current is observed, and breakdown occurs after the current on the second current curve LP2 is approximately 30 A. That is, even if the current flowing through the electrostatic discharge protection device including a SCR in this embodiment of the invention reaches the breakdown current of an existing electrostatic discharge protection device including a SCR, it can still operate normally. In other words, it can be seen that when the first pitch D1 and the second pitch D2 are less than 0.6 μm, a lower breakdown current is achieved; conversely, when the first pitch D1 and the second pitch D2 are greater than 0.6 μm, a significantly higher breakdown current is achieved.

[0081] The third current curve LN3 can relate to the leakage current of existing electrostatic discharge protection devices including silicon controlled rectifiers under negative supply voltage. The fourth current curve LN4 can relate to the leakage current of the electrostatic discharge protection device including a silicon controlled rectifier in the embodiments of the present invention under negative supply voltage.

[0082] In the case of the third curve G3, when a negative supply voltage is supplied to an existing electrostatic discharge protection device including a silicon controlled rectifier (SCR), leakage current is observed, and breakdown occurs after the absolute value of the current (in A) on the third current curve LN3 is approximately 25 A. In the case of the fourth curve G4, when a negative supply voltage is supplied to the electrostatic discharge protection device including a SCR in this embodiment of the invention, leakage current is observed, and breakdown occurs after the absolute value of the current on the fourth current curve LN4 is approximately -30 A. That is, even if the current flowing through the electrostatic discharge protection device including a SCR in this embodiment of the invention reaches the breakdown current of an existing electrostatic discharge protection device including a SCR, it can still operate normally. In other words, it can be seen that when the first spacing D1 and the second spacing D2 are less than 0.6 μm, a lower breakdown current is achieved; conversely, when the first spacing D1 and the second spacing D2 are greater than 0.6 μm, a significantly higher breakdown current is achieved.

[0083] When the first spacing D1 and the second spacing D2 are greater than 1.4 μm, the breakdown voltage (BV) characteristics will be significantly reduced. When the first spacing D1 and the second spacing D2 are greater than 1.4 μm, the first part IR1 of the ring IR will approach the first well W1, the second part IR2 of the ring IR will approach the second well W2, the third part IR3 of the ring IR will approach the fifth well W5.

[0084] The following will refer to Figure 1 and Figure 5 The electrostatic discharge protection device including a silicon controlled rectifier (SCR) according to some embodiments of the present invention will be described. For clarity, descriptions that are repeated in the present description will be omitted.

[0085] Figure 5 For along Figure 1 A cross-sectional view cut off by line A-A'.

[0086] Reference Figure 1 and Figure 5 In some embodiments of the present invention, the electrostatic discharge protection device including the silicon controlled rectifier may not include the second buried layer BL2.

[0087] The first concentration region IR11 can be set on the first buried layer BL1 to cover the upper surface of the first buried layer BL1.

[0088] Multiple wells W1, W2, W3, ... can be disposed between the first concentration region IR11 and the upper surface of the substrate 100. The multiple wells W1, W2, W3, ... can be disposed separately from the first concentration region IR11.

[0089] The above description is merely an illustrative illustration of the technical concept of this embodiment. For those skilled in the art, various modifications and variations can be made without departing from the essential characteristics of this embodiment. Therefore, this embodiment is not intended to limit the technical concept of this embodiment, but rather to illustrate it. The scope of the technical concept of this embodiment is not limited to these embodiments. The scope of protection of this embodiment should be interpreted by the appended claims, and all technical concepts within their equivalent scope should be interpreted as being included within the scope of the claims of this embodiment.

Claims

1. An electrostatic discharge protection device including a silicon controlled rectifier (SCR), characterized in that, include: Substrate of the first conductivity type; A ring, disposed within the substrate, belongs to a second conductivity type different from the first conductivity type, and includes a first portion and a second portion that are spaced apart from each other; A first well of the first conductivity type is disposed within the substrate and between the first portion and the second portion of the ring, and is spaced apart from the first portion and the second portion of the ring. The second well of the first conductivity type is disposed within the substrate and between the first portion of the ring and the second portion of the ring, and is spaced apart from the first well, the first portion of the ring and the second portion of the ring; The third well of the first conductivity type is disposed within the substrate and between the first well and the second well, and is spaced apart from the first well and the second well; as well as A cathode electrode is connected between the first well and the third well, connected to the third well, and connected between the second well and the third well.

2. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 1, characterized in that, The first separation distance between the first well and the third well and the second separation distance between the second well and the third well are respectively greater than 0.6 μm and less than 1.4 μm.

3. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 1, characterized in that, The first region of the substrate is disposed between the first well and the third well, and the second region of the substrate is disposed between the second well and the third well.

4. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 3, characterized in that, The third region of the substrate is disposed between the first well and the first portion of the ring, and the fourth region of the substrate is disposed between the second well and the second portion of the ring.

5. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 1, characterized in that, The ring also includes: The third portion of the ring of the second conductivity type is disposed within the substrate and is spaced apart from the first portion and the second portion of the ring; The fourth portion of the ring is disposed within the substrate, connecting the first end of the first portion of the ring, the first end of the second portion of the ring, and the first end of the third portion of the ring; and The fifth portion of the ring is disposed within the substrate and connects the second end of the first portion of the ring, the second end of the second portion of the ring, and the second end of the third portion of the ring.

6. An electrostatic discharge protection device including a silicon controlled rectifier, characterized in that, include: Substrate of the first conductivity type; The first well and the second well of the first conductivity type extend apart from each other in one direction and are disposed in the substrate; The third well of the first conductivity type extends along the one direction, is disposed between the first well and the second well, and is disposed within the substrate; The fourth and fifth wells of the first conductivity type extend apart from each other along the one direction and are disposed within the substrate; The sixth well of the first conductivity type extends along the one direction, is disposed between the fourth well and the fifth well, and is disposed within the substrate; A ring of a second conductivity type, different from the first conductivity type, is disposed within the substrate, separating the second well from the fourth well and surrounding the first well to the sixth well; as well as The first type of conductive peripheral well is disposed within the substrate in a manner that surrounds the ring.

7. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 6, characterized in that, The first separation distance between the first well and the third well and the second separation distance between the second well and the third well are respectively greater than 0.6 μm and less than 1.4 μm.

8. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 6, characterized in that, The first region of the substrate is disposed between the first well and the third well, and the second region of the substrate is disposed between the second well and the third well.

9. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 7, characterized in that, The third region of the substrate is disposed between the first well and the ring, and the fourth region of the substrate is disposed between the second well and the ring.

10. The electrostatic discharge protection device including a silicon controlled rectifier according to claim 6, characterized in that, The fifth region of the substrate is disposed between the fourth well and the sixth well, and the sixth region of the substrate is disposed between the fifth well and the sixth well.

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