Method for manufacturing shallow trench isolation structure

Abstract

The application provides a preparation method of a shallow trench isolation structure, and belongs to the field of semiconductors. The preparation method of the shallow trench isolation structure comprises a large field area and an array area; a mask layer of the array area is subjected to a two-fold pitch patterning process; a second etching is performed on the exposed initial silicon column with the silicon oxide layer as a mask, a plurality of second trenches and a plurality of target silicon columns are formed, and the plurality of second trenches are arranged along a first direction; and a second isolation structure is formed by filling a second insulating material in the second trenches. The application performs a first etching on the silicon epitaxial layer of the array area by adopting a two-fold pitch, the pitch of a single etching is doubled, the difficulty of a photolithography process is reduced, a greater photolithography margin is obtained, the critical dimension of the formed initial silicon column is wider, the support width of the initial silicon column is wider, the mechanical rigidity of the initial silicon column is greatly improved, stable support is provided for a subsequent filling process, and bending deformation of the initial silicon column is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a shallow trench isolation structure. Background Technology

[0002] 4F 2 Vertical-channel transistors (VCTs) occupy a layout area four times the square of the feature size for a single transistor cell. To achieve electrical isolation between different individual transistor cells, shallow trench isolation (STI) structures are required between the transistors. However, during the fabrication of STI structures, the active silicon pillars formed have low hardness, causing them to bend and deform. This deformation not only makes subsequent bit line and word line processes difficult to carry out, but also causes defects such as wafer alignment misalignment, critical dimension offset of the STI structure, and wavy distortion of the etching trench profile. In particular, electrical defects such as short circuits between bit lines, short circuits between memory nodes, and short circuits between word lines ultimately lead to device malfunctions and decreased yield.

[0003] Furthermore, as design rules continue to shrink, the photolithography patterning process for etching epitaxial layers is rapidly shifting from traditional EUV-less equipment to technologies such as dual photolithography (DPT) and quadruple photolithography (QPT). While this shift expands the pitch margin of photolithographic patterns, it increases the difficulty of mask manufacturing, and the process deviations between multiple masks also worsen, resulting in inconsistent etch trench slopes and depths. This causes discrepancies in the critical dimensions of shallow trench isolation (STI) structures, further leading to deviations in the critical dimensions of active silicon pillars.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating shallow trench isolation structures, so as to solve the problem of bending deformation of silicon pillars during the fabrication of shallow trench isolation structures.

[0006] To solve the above technical problems, the present invention provides a method for preparing a shallow trench isolation structure, comprising:

[0007] A substrate is provided, the substrate including a large field region and an array region, and a silicon-germanium stop layer, a silicon epitaxial layer and a mask layer are sequentially deposited on the surface of the substrate;

[0008] The mask layer of the array region is patterned with a pitch of twice. Using the patterned mask layer as a mask, the silicon epitaxial layer is etched to form a plurality of first trenches and a plurality of initial silicon pillars. The plurality of first trenches are arranged along a first direction and the first trenches and the initial silicon pillars are spaced apart.

[0009] A first insulating material is filled into the first trench to form a first isolation structure;

[0010] The patterned mask layer is etched back so that the width of the mask pattern in the remaining mask layer along the first direction is equal to the width of the first trench along the first direction.

[0011] A silicon oxide layer is filled between adjacent mask patterns, and the remaining mask layer is removed to expose a portion of the top of the initial silicon pillar;

[0012] Using the silicon oxide layer as a mask, a second etching is performed on the exposed initial silicon pillar to form a plurality of second trenches and a plurality of target silicon pillars. The plurality of second trenches are arranged along a first direction, and the target silicon pillars are located between the second trenches and the first isolation structure.

[0013] A second insulating material is filled into the second trench to form a second isolation structure.

[0014] Preferably, while performing a first etching on the silicon epitaxial layer of the array region, the method further includes:

[0015] The silicon epitaxial layer in the large field region is etched to form a third trench.

[0016] Preferably, the first insulating material simultaneously covers the inner wall and bottom of the third trench, and after the first insulating structure is formed, the method further includes:

[0017] The third trench is filled with spin-coated dielectric material and cured to form an oxide filler layer, which fills the spaces between patterned mask layers.

[0018] Preferably, before etching back the patterned mask layer, the method further includes:

[0019] The oxide filler layer is etched to expose the sidewalls and top of the patterned mask layer.

[0020] Preferably, the filling of the first insulating material and the second insulating material is formed by at least two deposition processes.

[0021] Preferably, the first insulating material and the second insulating material are filled using at least two atomic layer deposition processes.

[0022] Preferably, the first insulating material and the second insulating material are filled sequentially using atomic layer deposition (ALD), in-situ water vapor oxidation (IPE), and ALD processes.

[0023] Preferably, when performing the first and second etching, the silicon-germanium stop layer is used as the etching stop layer, and the endpoint detection is performed simultaneously with the etching. Based on the endpoint detection, the first and second etching are controlled to be over-etching.

[0024] Preferably, the method further includes:

[0025] After forming the plurality of first trenches, the silicon-germanium stop layer at the bottom of the first trenches is laterally etched using atomic layer etching.

[0026] After forming the plurality of second trenches, the silicon-germanium stop layer at the bottom of the second trenches is laterally etched using atomic layer etching.

[0027] Preferably, within the array region, the longitudinal depth of the first trench closest to the large field region is less than or equal to the longitudinal depth of all the second trenches within the array region, and the longitudinal depth of all the other first trenches within the array region except for that first trench.

[0028] Compared with the prior art, the method for preparing the shallow trench isolation structure of the present invention has the following advantages:

[0029] This invention employs a double-pitch technique to perform the first etching on the silicon epitaxial layer of the array region. This doubles the pattern pitch in a single etching operation, reducing the difficulty of the photolithography process, achieving greater lithographic margin, and resulting in a wider critical dimension for the formed initial silicon pillars. The increased support width of the initial silicon pillars significantly improves their mechanical rigidity, providing stable support for subsequent filling processes and preventing bending deformation. Simultaneously, using a double-pitch technique for the first etching reduces the pattern density in the array region, narrowing the pattern density difference between the large field region and the array region. This prevents tilting of the sidewall morphology of the formed first trench, avoiding bending of the initial silicon pillars between the array region and the large field region, and even preventing edge collapse. Furthermore, when filling the first trench with the first insulating material, the stress superposition between the initial silicon pillars is reduced, further preventing bending of the initial silicon pillars towards one side of the first trench. During the second etching of the initial silicon pillars, since the first trench is already filled with the first insulating material, the position of the first trench can be fixed, and the target silicon pillar is encased and supported by the first insulating material, preventing bending deformation. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure after the epitaxial layer has been etched.

[0031] Figure 2This is a schematic diagram of the structure of an active silicon pillar.

[0032] Figure 3 This is a flowchart of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the structure after etching the silicon epitaxial layer in one embodiment of the present invention.

[0034] Figure 5 This is a schematic diagram of the formation of the first isolation structure in one embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the structure after the patterned mask layer has been etched back in one embodiment of the present invention.

[0036] Figure 7 This is a schematic diagram of the structure after the groove is filled with a silicon oxide layer in one embodiment of the present invention.

[0037] Figure 8 This is a schematic diagram of the structure after removing the remaining mask layer in one embodiment of the present invention.

[0038] Figure 9 This is a schematic diagram of a structure forming multiple second trenches and target silicon pillars in one embodiment of the present invention.

[0039] Figure 10 This is a schematic diagram of the structure after the second trench is filled with the second insulating material in one embodiment of the present invention.

[0040] In the picture,

[0041] 10. Epitaxial layer; 20. Active silicon pillar; 30. Mask material layer; 40. Etching trench; 50. Insulating material; 100. Substrate; 200. Silicon-germanium stop layer; 300. Initial silicon pillar; 400. Mask layer; 500. First trench; 600. First isolation structure; 700. Spin-coated dielectric material; 110. Third trench; 310. Groove; 320. Second mask pattern; 330. Second mask layer; 340. Second trench; 350. Second isolation structure; 360. Target silicon pillar; 410. Buffer layer. Detailed Implementation

[0042] To make the objectives, advantages, and features of the present invention clearer, the preparation method of the shallow trench isolation structure proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of the present invention. It should be understood that the drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the drawings are also drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0044] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0045] refer to Figure 1 and Figure 2 As shown, in order to form a shallow trench isolation structure between different active silicon pillars 20, the commonly used etching process is as follows: first, pattern the mask material layer 30, and then use the mask material layer 30 as a mask to perform an etching of the epitaxial layer 10, forming a structure as shown. Figure 1 The etching trench 40 shown; finally, the etching trench 40 is filled with an insulating material 50 (e.g., silicon oxide material), and after chemical mechanical polishing (CMP), it forms as shown. Figure 2The shallow trench isolation structure shown is used to form electrical isolation between different active silicon pillars 20, thereby enabling electrical isolation between different unit transistors and preventing leakage between adjacent unit transistors.

[0046] Continue to refer to Figure 1 As shown, the epitaxial layer 10 includes a core region 10B and a peripheral region 10A. The core region 10B is the pillar region of the device, responsible for realizing the core electrical functions and high-density integration of the device, with extremely high pattern density. The peripheral region 10A is the support region of the device, with low pattern density. In the core region 10B, due to the extremely small spacing between the active silicon pillars 20 (the critical dimensions of the active silicon pillars 20 and the etching trench 40 are close to the process limits), during the subsequent etching of the epitaxial layer 10, the sidewalls of the etching trench 40 will be subjected to asymmetric stress from plasma bombardment. During the filling of silicon oxide material, thermal stress and film stress will be generated when the silicon oxide material is deposited on the sidewalls of the active silicon pillars 20. When the density of the etching trench 40 is too high, the stress of adjacent active silicon pillars 20 will be superimposed and cannot be released, causing the active silicon pillars 20 to bend towards one side of the etching trench 40, and in severe cases, they may even collapse.

[0047] Continue to refer to Figure 1 As shown, the peripheral region 10A is a large-area flat structure, while the core region 10B is a high-density array of active silicon pillars 20. The pattern density of the two regions changes abruptly at the boundary. During subsequent etching, filling, and CMP processes, this density abrupt change leads to abrupt changes in process rate. During etching, the etching rate of the etching trenches 40 at the boundary is neither as slow as in the core region 10B nor as fast as in the peripheral region 10A, making the sidewall morphology more prone to tilting. During filling, the uneven deposition and reflow of silicon oxide material at the boundary applies additional lateral stress to the active silicon pillars 20 at the edge. During CMP, the uneven distribution of polishing pressure at the boundary generates drag and compressive stress on the active silicon pillars 20 at the edge. These additional stresses concentrate on the outermost silicon pillars of the core region 10B, causing the active silicon pillars 20 at the edge to bend more easily than the active silicon pillars 20 inside the core region 10B, and even edge collapse zones may appear. These deformations not only make it difficult to carry out subsequent bit line and word line processes, but also cause defects such as wafer alignment deviation, critical dimension offset of the etch trench 40, and contour wavy distortion. In particular, electrical defects such as short circuits between bit lines, short circuits between memory nodes, and short circuits between word lines ultimately lead to abnormal device function and a decline in yield.

[0048] Furthermore, the photolithographic patterning process for etching the epitaxial layer 10 has been switched from the traditional EUV-less equipment solution to technologies such as dual photolithography (DPT) and quadruple photolithography (QPT). While this expands the pitch margin of the photolithographic pattern, it increases the difficulty of mask manufacturing, and the process deviations between multiple masks also accumulate, resulting in inconsistencies in the slope and depth of the etched trenches 40. This causes the critical dimensions of the shallow trench isolation structure (STI) to become discrete, and the critical dimensions of different shallow trench isolation structures deviate, which in turn leads to deviations in the critical dimensions of the active silicon pillars 20, thus affecting the performance of the device.

[0049] The core idea of ​​this invention is to provide a method for fabricating a shallow trench isolation structure, which can avoid bending deformation of silicon pillars and also avoid deviations in the critical dimensions of silicon pillars and shallow trench isolation structures, thereby improving device performance.

[0050] To achieve the above-mentioned goals, this invention provides a method for preparing a shallow trench isolation structure, referring to... Figures 3 to 10 A specific embodiment of the method for preparing a shallow trench isolation structure is disclosed. The method for preparing the shallow trench isolation structure includes the following steps S1 to S7.

[0051] Step S1: Provide a substrate, the substrate including a large field region and an array region, and a silicon germanium stop layer, a silicon epitaxial layer and a mask layer are sequentially deposited on the surface of the substrate.

[0052] refer to Figure 4 As shown, the substrate 100 includes a large field region 100A and an array region 100B. The array region 100B is the main region of the device, responsible for realizing the core electrical functions and high-density integration of the device, exhibiting extremely high pattern density. The large field region 100A is the peripheral support region of the device; although it does not directly participate in the operation of the memory cells, it is crucial to the overall functionality and process stability of the device. Because the large field region 100A and the array region 100B have different pattern densities, it is also called a dual-pitch pattern region. Dual pitch refers to the inclusion of two different pattern spacings within the same process, a critical process condition related to loading effects.

[0053] Continue to refer to Figure 4As shown, a substrate 100 is provided. The material of the substrate 100 may include silicon (Si), such as single-crystal Si, polycrystalline Si, or amorphous Si. A silicon-germanium stop layer 200 is disposed on the surface of the substrate 100, which serves as an etching stop layer for subsequent etching. A silicon epitaxial layer is formed on the surface of the silicon-germanium stop layer 200, and a mask layer 400 is formed on the surface of the silicon epitaxial layer. To protect the underlying silicon epitaxial layer during subsequent etching, a buffer layer 410 may be disposed between the silicon epitaxial layer and the mask layer 400. The material of the mask layer 400 may include silicon nitride. The material of the buffer layer 410 may include silicon oxide.

[0054] Step S2: The mask layer of the array region is patterned with a pitch of twice. Using the patterned mask layer as a mask, the silicon epitaxial layer is etched to form a plurality of first trenches and initial silicon pillars. The plurality of first trenches are arranged along a first direction and the first trenches and the initial silicon pillars are spaced apart.

[0055] Continue to refer to Figure 4 As shown, the mask layer 400 of the array region 100B is patterned with a double pitch to form a first mask pattern. Using the first mask pattern as a mask, dry etching is performed on the silicon epitaxial layer of the array region 100B to form a plurality of first trenches 500 and initial silicon pillars 300. The plurality of first trenches 500 are along a first direction (i.e., Figure 4 The first trench 500 and the initial silicon pillar 300 are arranged in an X-direction, with the first direction also being the direction of the subsequent bit line extension. It should be noted that when patterning the mask layer 400, the buffer layer 410 is also patterned simultaneously; that is, the first mask pattern is a stacked structure of silicon nitride and silicon oxide materials. It should also be noted that the initial silicon pillar 300 formed in this step is not the final active region silicon pillar; further etching of the initial silicon pillar 300 is required to form the target active region silicon pillar.

[0056] The design pitch required for the final device product, i.e., the standard distance between the centers of two adjacent shallow trench isolation structures (or adjacent target silicon pillars) in array region 100B, is called the pitch. The mask layer 400 is patterned with twice the pitch to form the first mask pattern. That is, during the first etching, the first mask pattern extends along the direction of the bit line extension (i.e., ...). Figure 4 The width of the initial silicon pillar 300 in the X direction is twice the pitch, and the initial silicon pillar 300 is along the first direction (i.e., Figure 4The width of the first etching (in the X direction) is also twice that of the subsequent target silicon pillar. The first etching etches only one set of trenches (i.e., multiple first trenches 500). The multiple first trenches 500 can be even-numbered trenches (e.g., the 2nd, 4th, 6th, 8th, ...) of the array region 100B, or odd-numbered trenches (e.g., the 1st, 3rd, 5th, 7th, ...) of the array region 100B. In this embodiment, the explanation is based on the example of multiple first trenches 500 being even-numbered trenches of the array region 100B.

[0057] During the first etching operation, a photolithography process with a double-pitch design is first used on the array region 100B, exposing and developing only the even-numbered trenches. Next, using the first mask pattern after exposure and development as a mask, the even-numbered silicon epitaxial layers of the array region 100B are etched, completing the etching of the even-numbered trenches. Because the pattern pitch of a single etching operation is doubled, the difficulty of the photolithography process is reduced, a larger photolithographic margin is obtained, and the critical dimension of the resulting initial silicon pillar 300 is wider. The wider support width of the initial silicon pillar 300 significantly improves its mechanical rigidity, providing stable support for subsequent filling processes and preventing bending deformation of the initial silicon pillar 300. Simultaneously, performing the first etching with twice the pitch can reduce the pattern density of the array region 100B, narrowing the pattern density difference between the large field region 100A and the array region 100B. This prevents the sidewall morphology of the formed first trench 500 from tilting, and avoids bending of the initial silicon pillars 300 between the array region 100B and the large field region 100A, or even the formation of edge collapse zones. Furthermore, when the first trench 500 is subsequently filled with the first insulating material, the stress superposition between the initial silicon pillars 300 can be reduced, further preventing the initial silicon pillars 300 from bending to one side of the first trench 500.

[0058] Furthermore, during the first etching process, a silicon-germanium stop layer 200 is set. During the etching process, the silicon-germanium stop layer 200 is used as the etching stop layer. At the same time as etching, an End Point Detection (EPD) machine is used to detect and accurately identify that the first etching has reached the silicon-germanium stop layer 200, thereby locking the etching end point and stopping the etching. This allows for precise control of the etching depth and avoids over-etching.

[0059] Furthermore, in some embodiments, the first etching is controlled to be over-etched based on endpoint detection. In order to remove etching residues and make the morphology of the first trench 500 more stable, the etching method also includes over-etching the first trench 500, that is, delaying the dry etching for a set time. The specific delay time can be set according to process requirements.

[0060] Furthermore, in some embodiments, the method further includes, after forming the plurality of first trenches 500, performing lateral etching of the silicon-germanium stop layer 200 at the bottom of the first trenches 500 using atomic layer etching (ALE) to widen the critical dimension at the bottom of the first trenches 500, so that the critical dimensions at the top and bottom of the first trenches 500 are consistent, avoiding depth deviation in the subsequently formed first isolation structure 600, and also avoiding differences in the critical dimensions of the first trenches 500.

[0061] While performing a first etching on the silicon epitaxial layer of the array region 100B, the method further includes:

[0062] The silicon epitaxial layer of the large field region 100A is etched to form a third trench 110. The third trench 110 is then filled with insulating material through subsequent processes to form an isolation structure, thereby isolating the subsequently formed target silicon pillar from the large field region 100A.

[0063] It should be noted that before performing step S3, the method may also include processes such as cleaning and drying the first trench 500.

[0064] Step S3: Fill the first trench with the first insulating material to form the first isolation structure.

[0065] refer to Figure 5 As shown, a first insulating material is filled into the first trench 500 to form a first insulating structure 600. The first insulating material may include silicon oxide, silicon nitride, or any other 4F material. 2 The insulating material for this type of vertical channel transistor. Preferably, silicon oxide. In this embodiment, the plurality of first isolation structures 600 are even-numbered isolation structures of the array region 100B, from Figure 5 The positions indicated by the middle arrow 'a', along the X direction, are, in sequence, the 2nd, 4th, 6th, and 8th first isolation structures 600. Those skilled in the art should understand that the four isolation structures 600 shown in the figure are merely illustrative, and the actual number of isolation structures is not limited.

[0066] The filling of the first insulating material is formed by at least two deposition processes. In some embodiments, the first insulating material is filled using at least two atomic layer deposition (ALD) processes. In other embodiments, the first insulating material is filled using atomic layer deposition (ALD), in-situ water vapor oxidation (ISSG), and atomic layer deposition (ALD) processes sequentially. That is, the filled silicon oxide material is formed using a layered preparation method of atomic layer deposition, in-situ water vapor oxidation (ISSG), and atomic layer deposition (ALD). The bottom layer uses ALD to deposit a silicon oxide film, which ensures uniform film deposition. The middle layer uses ISSG to deposit a silicon oxide film, which undergoes thermal oxidation with the silicon substrate to grow a thick, high-quality native oxide layer and smooth trench corners. The top layer uses ALD to form a silicon oxide film, which can balance the film stress on the trench sidewalls and avoid bending deformation of the silicon pillars due to the stress difference during subsequent sacrificial layer filling and CMP polishing.

[0067] The first insulating material simultaneously covers the inner wall and bottom of the third trench 110, and the method further includes:

[0068] refer to Figure 5 As shown, spin-coated dielectric material (SOD) 700 is filled in the third trench 110 and cured to form an oxide filling layer as an isolation structure between the target silicon pillar and the large field region 100A. The oxide filling layer fills the spaces between the patterned mask layers 400. Simultaneously with the filling of the first insulating material in the first trench 500, a thin film of the first insulating material is also formed in the large field region 100A. After the first isolation structure 600 is fabricated, a spin-coated dielectric process is used in conjunction with fluid chemical vapor deposition (FCVD) to fill the large field region 100A with spin-coated dielectric material 700. By filling the large field region 100A with SOD and curing it to form an oxide filling layer, the already formed initial silicon pillar 300 is fixed, preventing the initial silicon pillar 300 from bending under stress in subsequent processes.

[0069] When filling SOD, since the height of the SOD filling is higher than the height of the mask layer 400, the mask layer 400 is used as the polishing stop layer, and the SOD is polished using CMP process. The height after polishing is consistent with the height of the mask layer 400.

[0070] Finally, the oxide filling layer formed between the mask layers 400 is etched to completely expose the periphery of the mask layers 400, forming a layer as shown in the image. Figure 5 The structure is shown. When etching the oxide filling layer, dry etching can be used, with gases including fluorine-based gases such as CF4 and CHF3. Alternatively, wet etching can be used, with reagents such as hydrofluoric acid solution. Etching the oxide filling layer completely exposes the top and sidewalls of the mask layer 400, preparing it for subsequent processes.

[0071] Step S4: Etch back the patterned mask layer so that the width of the mask pattern in the remaining mask layer along the first direction is equal to the width of the first trench along the first direction.

[0072] refer to Figure 6 As shown, the exposed mask layer 400 is etched back using a wet etching process, forming a groove 310 at the etched mask layer 400. The remaining mask layer forms multiple mask patterns, which are defined as second mask patterns 320. A single second mask pattern 320 is etched along a first direction (i.e., Figure 6 The width of the second mask pattern 320 extending in the X direction is equal to the width of the first trench 500 extending in the first direction. The wet etching reagent may include phosphoric acid (H3PO4). During wet etching, the width of the second mask pattern 320 extending in the first direction can be controlled by controlling the etching time. Due to the characteristics of the etch-back process, the second mask pattern 320 can be positioned substantially at the top center of the initial silicon pillar 300.

[0073] Step S5: Fill the space between adjacent mask patterns with a silicon oxide layer and remove the remaining mask layer to expose part of the top of the initial silicon pillar.

[0074] refer to Figure 7 As shown, after etching, a silicon oxide layer is filled into the groove 310 and the surface of the SOD. Then, using the remaining mask layer as a polishing stop layer, the filled silicon oxide layer is chemically mechanically polished to make the height of the silicon oxide layer consistent with the height of the remaining mask layer, forming... Figure 7 The structure shown uses the polished silicon oxide layer as the second mask layer 330.

[0075] refer to Figure 8 As shown, dry etching is used to remove the remaining mask layer and the buffer layer 410 below it, exposing part of the top of the initial silicon pillar 300 to facilitate subsequent processes. Since the remaining mask layer (i.e., the second mask pattern 320) is basically located at the top center of the initial silicon pillar 300, the area opened in step S5 is also the top center region of the initial silicon pillar 300.

[0076] Step S6: Using the silicon oxide layer as a mask, perform a second etching on the exposed initial silicon pillar to form a plurality of second trenches and a plurality of target silicon pillars. The plurality of second trenches are arranged along a first direction, and the target silicon pillars are located between the second trenches and the first isolation structure.

[0077] Continue to refer to Figure 9As shown, firstly, using the silicon oxide layer as a mask, that is, using the second mask layer 330 as a mask, dry etching is used to perform a second etching on the initial silicon pillar 300 to form a second trench 340 and a plurality of target silicon pillars 360. The plurality of second trenches 340 are along a first direction (i.e., Figure 9 The target silicon pillars 360 are arranged in the X direction of the array region 100B and are located between the second trench 340 and the first isolation structure 600. The second trench 340 is an odd-numbered trench (e.g., the 1st, 3rd, 5th, 7th, ...) of the array region 100B. HBr and Cl2 can be used as the main etching gas for dry etching, and auxiliary gases such as argon and oxygen can be added to the main etching gas to achieve anisotropic trench etching. Simultaneously with the formation of the second trench 340, the target silicon pillars 360 are also formed. These target silicon pillars 360 serve as the active region, and subsequent fabrication of the source and drain electrodes, and the formation of channels, etc., on the target silicon pillars 360 will not be elaborated further here. Since step S5 opens the top central region of the initial silicon pillars 300, the width of each target silicon pillar 360 formed in step S6 can be made uniform.

[0078] During the second etching process, a silicon-germanium stop layer 200 is set. During the etching process, the silicon-germanium stop layer 200 is used as the etching stop layer. At the same time, an end point detection (EPD) machine is used to detect and accurately identify when the second etching reaches the silicon-germanium stop layer 200, thereby locking the etching end point and stopping the etching to accurately control the etching depth and avoid over-etching.

[0079] Furthermore, in some embodiments, the second etching is controlled to be over-etched based on endpoint detection. In order to remove etching residues and make the morphology of the second trench 340 more stable, the etching method further includes over-etching the second trench 340, that is, stopping the etching after a delay of T seconds during dry etching, where T can be 10S to 60S.

[0080] Furthermore, in some embodiments, the method further includes, after forming the plurality of second trenches 340, performing lateral etching of the silicon-germanium stop layer 200 at the bottom of the second trenches 340 using atomic layer etching (ALE) to widen the critical dimension at the bottom of the second trenches 340, so that the critical dimensions at the top and bottom of the second trenches 340 are consistent, avoiding depth deviations in the shallow trench isolation formed subsequently, and also avoiding differences in the critical dimensions of the second trenches 340.

[0081] Furthermore, within the array region 100B, the longitudinal depth of the first trench 500 closest to the large field region 100A is less than or equal to the longitudinal depth of all the second trenches 340 within the array region 100B, and the longitudinal depth of all the other first trenches 500 within the array region 100B except for this first trench 500. (Reference) Figure 9 and Figure 10 As shown, in the array region 100B adjacent to the large field region 100A (i.e., the edge region of array region 100B), the first groove 500 located at the position of arrow m is in the vertical direction (i.e., Figure 9 The depth at arrow Z in the diagram is less than or equal to the longitudinal depth of all second trenches 340 within the array region 100B, and the longitudinal depth of all first trenches 500 within the array region 100B except for the first trench 500 therein. In other words, the longitudinal depth of the first trench 500 located at position m can be the minimum. In this embodiment, the first trench 500 is formed using a double-pitch patterning process, and the second trench 340 is formed using a self-aligned process. Because the edge of the array region 100B is adjacent to the large-size wide pattern of the large field region 100A, the first second trench 340 near the large field region 100A is prone to being too deep due to the etching load effect. At the same time, the first trench 500 and the second trench 340 inside the array region 100B, that is, the odd-numbered trenches and the even-numbered trenches, have a depth difference due to the difference in the supply of etching reactants. This embodiment utilizes the inherent etching characteristics of a double-pitch patterning process and a self-aligned process to cancel each other out, ensuring that the depth of the first trench 500 at the edge (i.e., position m) is less than or equal to that of all other trenches within the array region 100B. This depth distribution design increases the thickness of the isolation structure in the array region 100B, improving the voltage isolation capability of the transistors in the peripheral circuitry; the thicker filling oxide dielectric can buffer the film stress caused by the density abrupt change between the large field region 100A and the array region 100B, effectively suppressing the bending deformation of the silicon pillars at the boundary of the array region 100B.

[0082] Step S6: Fill the second trench with a second insulating material to form a second isolation structure.

[0083] refer to Figure 10 As shown, a second insulating material is filled into the second trench 340 to form a second insulating structure 350. The second insulating material may include silicon oxide, silicon nitride, or any other 4F material. 2 The insulating material for this type of vertical channel transistor. Preferably, silicon oxide. Multiple second isolation structures 350 are odd-bit isolation structures for the array region 100B, from... Figure 10 The positions indicated by the middle arrow b, along the X direction, are, in order, the 1st second isolation structure 350, the 3rd second isolation structure 350, the 5th second isolation structure 350, and the 7th second isolation structure 350.

[0084] The filling of the second insulating material is formed by at least two deposition processes. In some embodiments, the first insulating material is filled using at least two atomic layer deposition (ALD) processes. In other embodiments, the first insulating material is filled using atomic layer deposition (ALD), in-situ vapor oxidation (ISSG), and atomic layer deposition (ALD) processes sequentially. That is, the filled silicon oxide material is formed using a layered preparation method of atomic layer deposition, in-situ vapor oxidation (ISSG), and atomic layer deposition (ALD). The bottom layer uses ALD to deposit a silicon oxide film, which makes the film deposition uniform. The middle layer uses ISSG to deposit a silicon oxide film, which undergoes thermal oxidation with the silicon substrate to grow a thick, high-quality native oxide layer and smooth the trench corners. The top layer uses ALD to form a silicon oxide film, which can balance the film stress on the trench sidewalls and avoid bending deformation of the silicon pillar due to the film stress difference during subsequent sacrificial layer filling and CMP polishing.

[0085] The first isolation structure 600 and the second isolation structure 350 constitute a complete shallow trench isolation structure for isolation between different target silicon pillars 360, thereby achieving electrical isolation between different unit transistors. In this embodiment, the initial silicon pillar 300 of the active region is set to a double-pitch structure according to the original design rules, which increases the mechanical hardness of the initial silicon pillar 300 to at least three times the original level; the even-numbered (or odd-numbered) trenches (i.e., the first trench 500) are filled first, which can improve the ability of the active region to resist bending deformation caused by subsequent processes; then the central region of the double-pitch initial silicon pillar 300 is etched and defined by a step-by-step self-aligned etch-back process, and finally the odd-numbered (or even-numbered) trenches (i.e., the second trench 340) are filled, thereby obtaining a 4F transistor that can significantly suppress the bending of the target silicon pillar 360 in the active region. 2 Shallow trench isolation structure for vertical channel transistors.

[0086] Using a double-pitch etching process for the first etching step reduces the pattern density of the array region, narrows the pattern density difference between the large field region 100A and the array region 100B, avoids tilting of the sidewall morphology of the formed first trench 500, and prevents bending of the initial silicon pillar 300 between the array regions 100A and 100B. Double-pitch etching also avoids stress superposition during subsequent silicon oxide filling, thus preventing bending deformation of the initial silicon pillar 300 and the target silicon pillar 360. During the second etching step, since the first isolation structure has already been formed, the silicon oxide filling in the first trench 500 can encapsulate and support the target silicon pillar 360, preventing bending deformation.

[0087] In summary, the above embodiments have provided detailed descriptions of different configurations of the preparation method of the shallow trench isolation structure. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that, include: A substrate is provided, the substrate including a large field region and an array region, and a silicon-germanium stop layer, a silicon epitaxial layer and a mask layer are sequentially deposited on the surface of the substrate; The mask layer of the array region is patterned at twice the final target design pitch. Using the patterned mask layer as a mask, the silicon epitaxial layer is etched to form a plurality of first trenches and a plurality of initial silicon pillars. The plurality of first trenches are arranged along a first direction, and the first trenches and the initial silicon pillars are spaced apart. A first insulating material is filled into the first trench to form a first isolation structure; The patterned mask layer is etched back so that the width of the mask pattern in the remaining mask layer along the first direction is equal to the width of the first trench along the first direction. A silicon oxide layer is filled between adjacent mask patterns, and the remaining mask layer is removed to expose a portion of the top of the initial silicon pillar; Using the silicon oxide layer as a mask, a second etching is performed on the exposed initial silicon pillar to form a plurality of second trenches and a plurality of target silicon pillars. The plurality of second trenches are arranged along a first direction, and the target silicon pillars are located between the second trenches and the first isolation structure. A second insulating material is filled into the second trench to form a second isolation structure.

2. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, While performing a first etching on the silicon epitaxial layer of the array region, the method further includes: The silicon epitaxial layer in the large field region is etched to form a third trench.

3. The method for preparing the shallow trench isolation structure according to claim 2, characterized in that, The first insulating material simultaneously covers the inner wall and bottom of the third trench. After the first insulating structure is formed, the method further includes: The third trench is filled with spin-coated dielectric material and cured to form an oxide filler layer, which fills the spaces between patterned mask layers.

4. The method for preparing the shallow trench isolation structure according to claim 3, characterized in that, Before the patterned mask layer is etched back, the method further includes: The oxide filler layer is etched to expose the sidewalls and top of the patterned mask layer.

5. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, The filling of the first insulating material and the second insulating material is formed by at least two deposition processes.

6. The method for preparing the shallow trench isolation structure according to claim 5, characterized in that, The first insulating material and the second insulating material are filled using at least two atomic layer deposition processes.

7. The method for preparing the shallow trench isolation structure according to claim 5, characterized in that, The first insulating material and the second insulating material are filled sequentially using atomic layer deposition (ALD), in-situ water vapor oxidation (IFO), and ALD processes.

8. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, During the first and second etching processes, the silicon-germanium stop layer is used as the etching stop layer, and endpoint detection is performed simultaneously with etching. Based on the endpoint detection, the first and second etching processes are controlled to be over-etched.

9. The method for preparing the shallow trench isolation structure according to claim 8, characterized in that, The method also includes: After forming the plurality of first trenches, the silicon-germanium stop layer at the bottom of the first trenches is laterally etched using atomic layer etching. After forming the plurality of second trenches, the silicon-germanium stop layer at the bottom of the second trenches is laterally etched using atomic layer etching.

10. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, Within the array region, the longitudinal depth of the first trench closest to the large field region is less than or equal to the longitudinal depth of all the second trenches within the array region, and the longitudinal depth of all the other first trenches within the array region except for that first trench.

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