Processor configuration information synchronization system, method and electronic device

Abstract

The application discloses a processor configuration information synchronization system and method and electronic equipment, and relates to the technical field of server management, comprising: connecting two processors by a Type-C cable; performing bidirectional authentication between a slave device and a corresponding security authentication module, and performing subsequent operations according to the authentication result; a master device reads the configuration information of the master device, and transmits the configuration information to the slave device through the Type-C cable; and the slave device receives the configuration information and updates the configuration information of the slave device. The application can solve the problems of a centralized management network or complex preparation work required for configuration of a BMC, low configuration efficiency, insufficient security of security protection of the BMC, and easy cracking of permissions. The system does not need to preconfigure a management network, and can batch configure the BMC only by connecting the Type-C cable, thereby simplifying the configuration process. The system sets a corresponding security authentication module for the BMC and establishes a physical-level access control mechanism for critical operations, thereby realizing hardware-level security protection for out-of-band interaction.

Description

Technical Field

[0001] This invention relates to the field of server management technology, and more specifically to a processor configuration information synchronization system, method, and electronic device. Background Technology

[0002] The Board Management Controller (BMC) is an independent microprocessor on the server motherboard responsible for out-of-band management functions. Common methods for configuring the BMC include: configuring the BMC using operating system tools, configuring the BMC using scripts via out-of-band networks, and manually configuring the BMC per compute node. However, configuring the BMC using operating system tools is inefficient and depends on the normal operation of the operating system. Configuring the BMC using scripts via out-of-band networks requires setting up a complex network environment beforehand and consumes bandwidth from the business or management networks. Manually configuring the BMC per compute node is very time-consuming and prone to errors. Furthermore, current access control for the BMC mainly relies on traditional username / password authentication mechanisms or IPMI (Intelligent Platform Management Interface) account permission management. However, this purely software-level security protection has significant vulnerabilities; permissions are easily cracked, and once the BMC management interface or IPMI remote channel is compromised, attackers can gain complete control of the server. Summary of the Invention

[0003] In view of this, the present invention provides a processor configuration information synchronization system, method and electronic device to solve the problems of requiring a centralized management network or complicated preparation work to configure BMC, resulting in low configuration efficiency, insufficient security protection for BMC and easy access to cracked permissions.

[0004] In a first aspect, this application provides a processor configuration information synchronization system, the system comprising: a first processor, a second processor, and a Type-C cable; A Type-C cable is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor. The second processor, when it is a slave device and receives a configuration information synchronization request, performs bidirectional authentication with the security authentication module in the second Type-C interface module if the plug of the Type-C cable is inserted into the second Type-C interface module, and obtains the authentication result; The first processor, when acting as the main device, reads its own configuration information if the authentication result is successful, and transmits the configuration information to the second Type-C interface module via a Type-C cable according to a preset communication protocol. The second processor is also used to receive configuration information from the second Type-C interface module when the authentication result is successful, and to update its own configuration information according to the received configuration information.

[0005] Secondly, this application provides a processor configuration information synchronization method, which is applied to a processor configuration information synchronization system, and the method includes: Connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor using a Type-C cable; When the second processor is a slave device and receives a configuration information synchronization request, if the plug of the Type-C cable is inserted into the second Type-C interface module, the second processor and the security authentication module in the second Type-C interface module perform bidirectional authentication to obtain the authentication result. When the first processor is the master device, if the authentication result is successful, the configuration information of the first processor is read and transmitted to the second Type-C interface module via a Type-C cable according to the preset communication protocol. If the authentication result is successful, the second processor receives configuration information from the second Type-C interface module and updates the configuration information of the second processor according to the received configuration information.

[0006] Thirdly, this application provides a processor configuration information synchronization device, which is deployed in a processor configuration information synchronization system, and the device includes: A connection module is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor using a Type-C cable; The authentication module is used to perform bidirectional authentication between the second processor and the security authentication module in the second Type-C interface module when the second processor is a slave device and a configuration information synchronization request is received, and the plug of the Type-C cable is inserted into the second Type-C interface module, to obtain the authentication result. The configuration information transmission module is used to read the configuration information of the first processor when the first processor is the master device, and if the authentication result is successful, transmit the configuration information to the second Type-C interface module through a Type-C cable according to a preset communication protocol. The configuration information receiving module is used to receive configuration information from the second Type-C interface module using the second processor when the authentication result is successful, and to update the configuration information of the second processor according to the received configuration information.

[0007] Fourthly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the processor configuration information synchronization method of the second aspect or any corresponding embodiment described above.

[0008] Fifthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the processor configuration information synchronization method of the second aspect or any corresponding embodiment described above.

[0009] In a sixth aspect, this application provides a computer program product, including computer instructions for causing a computer to execute the processor configuration information synchronization method of the second aspect or any corresponding embodiment described above.

[0010] This application addresses the challenges of configuring a BMC (Browser Control Center) by utilizing a Type-C cable to connect two processors. The slave device performs bidirectional authentication with its corresponding security authentication module, and subsequent operations are based on the authentication result. The master device reads its own configuration information and transmits it to the slave device via the Type-C cable. The slave device receives the configuration information and updates its own. This solves the problems of low configuration efficiency, insufficient security protection for the BMC, and vulnerability to compromised permissions, which often require a centralized management network or complex preparation work. The system eliminates the need for pre-configured management networks; a simple Type-C cable connection is sufficient to begin batch configuration information synchronization. This simplifies the synchronization process, avoids complex cabling and bandwidth consumption on the business network, and improves the deployment and maintenance efficiency of the server cluster. The synchronized slave device can then be used as the master device for the next synchronization process, connecting and configuring other processors sequentially via Type-C cables to form a configuration synchronization chain. Furthermore, a corresponding security authentication module is set up for the BMC, and a physical-level access control mechanism for critical operations is established, achieving hardware-level security protection for out-of-band interactions. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the configuration information synchronization system for a processor according to an embodiment of this application; Figure 2 This is a timing diagram of the BMC configuration information synchronization process based on the Type-C interface according to an embodiment of this application; Figure 3 This is a structural diagram of a BMC hardware security authentication system based on a Type-C interface according to an embodiment of this application; Figure 4 This is a schematic diagram of the two-way authentication process between the second processor and the security authentication module according to an embodiment of this application; Figure 5 This is a flowchart of the BMC hardware security authentication method according to an embodiment of this application; Figure 6 This is a structural diagram of a baseboard management controller according to an embodiment of this application; Figure 7 This is a flowchart illustrating the configuration information synchronization method according to an embodiment of this application; Figure 8 This is a structural block diagram of a configuration information synchronization device according to an embodiment of this application; Figure 9 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The Baseboard Management Controller (BMC) is an independent microprocessor on the server motherboard responsible for remote out-of-band management of the server, including critical functions such as hardware monitoring, logging, firmware updates, and remote power on / off. In modern data centers, high-density multi-node servers are increasingly common. A single server chassis may house multiple compute nodes, each with its own independent BMC. When deploying or maintaining such servers, administrators need to perform initial configuration or configuration updates for the BMC of each compute node, such as setting the Internet Protocol Address (IP), administrator account, network security policies, and sensor alarm thresholds.

[0017] Common BMC configuration methods include: operating system-based tool configuration, out-of-band network-based script configuration, and manual per-compute-node configuration. Operating system-based tool configuration requires installing the operating system on each node and then configuring it individually using the vendor's command-line or graphical tools. This method is extremely inefficient and depends heavily on the operating system's proper functioning. Out-of-band network-based script configuration requires batch configuration via network boot or remote management ports using automated scripts. While highly automated, this method requires a complex pre-built network environment and consumes bandwidth from the business or management networks. Manual per-compute-node configuration requires direct connection to each node's management port, which is time-consuming and error-prone. Furthermore, all of these BMC configuration methods require a centralized management network or complex preparation work. In certain scenarios, such as initial server deployment, when network infrastructure is not yet ready, or in highly secure isolated environments, these methods are limited.

[0018] Currently, access control for the BMC primarily relies on traditional username / password authentication mechanisms or IPMI account permission management. However, this purely software-based security approach has significant vulnerabilities: on the one hand, weak passwords, password leaks, and brute-force attacks are common; on the other hand, once the BMC's web management interface or IPMI remote channel is compromised, attackers can gain complete control of the server, including high-risk operations such as modifying BIOS (Basic Input Output System) settings and resetting administrator passwords.

[0019] As a new type of universal physical interface, the Type-C interface not only supports high-speed data transmission but also multiple alternative modes, such as DisplayPort and Thunderbolt. More importantly, the USB PowerDelivery (PD) protocol provides powerful communication capabilities through a configuration channel, enabling the transmission of information far beyond power negotiation. However, there is currently no technical solution for directly synchronizing configuration information between server BMCs using the Type-C interface.

[0020] Based on the above, this application provides a processor configuration information synchronization system. This system integrates Type-C interfaces on at least two Server Management Consoles (BMCs) and connects the two BMCs using Type-C cables. The BMCs negotiate master-slave identities via the Type-C cable to confirm the master and slave BMCs. The master BMC can encapsulate its configuration information (such as IP address, user account, firmware parameters, etc.) into data packets and send them to the slave BMC through the configuration or data channel of the Type-C interface. After receiving and parsing the data packets, the slave BMC applies the configuration, thereby achieving fast, batch configuration synchronization between BMCs. By integrating an independent security authentication chip into the Type-C interface on the server front panel, a physical-level access control mechanism for critical operations is established, achieving hardware-level security protection for out-of-band interaction. This system utilizes the high versatility and flexible protocols of the Type-C interface to achieve BMC configuration synchronization without complex wiring or consuming service network bandwidth, significantly improving the deployment and maintenance efficiency of server clusters.

[0021] This embodiment provides a processor configuration information synchronization system. Figure 1 This is a schematic diagram of the configuration information synchronization system for a processor according to an embodiment of this application, as shown below. Figure 1 As shown, the system includes: a first processor, a second processor, and a Type-C cable; A Type-C cable is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor. The second processor, when it is a slave device and receives a configuration information synchronization request, performs bidirectional authentication with the security authentication module in the second Type-C interface module if the plug of the Type-C cable is inserted into the second Type-C interface module, and obtains the authentication result; The first processor, when acting as the main device, reads its own configuration information if the authentication result is successful, and transmits the configuration information to the second Type-C interface module via a Type-C cable according to a preset communication protocol. The second processor is also used to receive configuration information from the second Type-C interface module when the authentication result is successful, and to update its own configuration information according to the received configuration information.

[0022] Specifically, the processor is a BMC, a central processing unit, or another processor. The BMC is a separate microprocessor on the server motherboard. For example... Figure 1 As shown, server node A contains a first processor, and server node B contains a second processor. Each processor has one or more Type-C interface modules; for example, the first processor corresponds to the first Type-C interface module, and the second processor corresponds to the second Type-C interface module. A communication link is established by connecting the Type-C interface modules of any two processors using a Type-C cable. The Type-C interface modules can be mounted on the front panel of the server. In addition to providing a standard Type-C physical interface, each Type-C interface module integrates a separate security authentication chip as a security authentication module. This security authentication chip is soldered inside the Type-C interface module on the front panel of the server; it is part of the server hardware and not an external device plugged into the Type-C port.

[0023] Combination Figure 2 The configuration information synchronization process of the processor is explained using the processor as a BMC as an example. A physical communication link is established between the two BMCs using a Type-C cable. The first and second processors, connected via the Type-C cable, negotiate master-slave roles to determine the master and slave devices, i.e., the master BMC and the slave BMC. The Type-C cable is a standard or slightly modified Type-C to Type-C cable.

[0024] The second processor can intercept and identify high-risk operation requests initiated by users through the BMC web interface or IPMI commands. Examples include configuration information synchronization requests for the second processor, which require modification of its configuration information. Furthermore, the determination of high-risk operations is based on a pre-configured list. High-risk operations may also include modifying BIOS settings, resetting the BMC administrator password, updating BMC firmware, changing the boot order, clearing the system event log (SEL), and restoring factory settings.

[0025] When the second processor is a slave device and receives a configuration information synchronization request, it detects whether the Type-C cable plug is inserted into the second Type-C interface module. The Type-C interface module integrates a security authentication chip independent of the BMC. The security authentication chip is connected to the BMC module via a dedicated communication bus. The insertion of the Type-C cable plug only triggers the authentication process. Even if the inserted device is controlled by a hacker, it cannot bypass the authentication because the private key required for authentication is always in the security chip inside the server. The external device only acts as a trigger for the physical key insertion action. The authentication logic is entirely completed between the security chip inside the server and the BMC.

[0026] If the plug is detected to be inserted into the second Type-C interface module, the second processor and the security authentication module in the second Type-C interface module perform a handshake protocol for two-way authentication. Based on the authentication result, the second processor decides whether to allow the high-risk operation. If both authentications are successful, the BMC's execution control unit allows the high-risk operation, including the BMC configuration operation corresponding to the configuration information synchronization request. If authentication fails or times out, the BMC refuses to execute the high-risk operation and records it in the security log.

[0027] When the first processor is the master device (i.e., the master BMC), it reads configuration information from its non-volatile memory. This configuration information includes at least one of the following: network configuration information, user account information, security certificates, sensor thresholds, event log policies, and firmware update images. The master BMC encapsulates this configuration information into a configuration data packet conforming to a predefined format. According to a preset communication protocol, this configuration data packet, containing the configuration information, is transmitted via a Type-C cable to other processors connected to the first processor (i.e., slave BMCs). Preset communication protocols include, for example, USB PD and a dedicated communication protocol for Alternate Mode. The Alternate Mode protocol refers to a non-USB high-speed protocol multiplexed through the USB Type-C interface, relying on USB PD negotiation to enter this mode, but the data transmission itself is handled by the corresponding specialized protocol.

[0028] When the second processor is a slave device (i.e., a slave BMC), it receives configuration data packets transmitted via a Type-C cable from other processors connected to it. After parsing the configuration data packets and verifying their integrity and validity, it retrieves the configuration information from the packets and applies it to itself, updating its own configuration information based on the received data. Additionally, the slave BMC can send application results back to the master BMC.

[0029] It should be noted that after completing configuration information synchronization, the slave BMC can act as the master device for the next configuration information synchronization process. For example, after the master BMC connects to the first slave BMC through a Type-C interface, the first slave BMC, after completing its own configuration update, can switch to the role of master device and continue to connect to and configure the second slave BMC through its other Type-C interface, and so on, forming a chain or tree-like synchronization network. Furthermore, the configuration information synchronization process in this embodiment supports a one-to-many synchronization mode, meaning that one master BMC can simultaneously synchronize configuration information for multiple slave BMCs. USB has a complete device detection mechanism that can detect device insertion and removal in real time. This rapid response helps reduce the operation time of a single device and improves efficiency. USB's interrupt mechanism also helps reduce the load on the BMC.

[0030] The processor configuration information synchronization system provided in this embodiment utilizes a Type-C cable to connect a first Type-C interface module corresponding to a first processor and a second Type-C interface module corresponding to a second processor. When the second processor is a slave device and receives a configuration information synchronization request, if the Type-C cable plug is inserted into the second Type-C interface module, the second processor performs bidirectional authentication with the security authentication module in the second Type-C interface module to obtain an authentication result. When the second processor is a master device, if the authentication result is successful, the first processor reads its own configuration information and transmits the configuration information to the second Type-C interface module via the Type-C cable according to a preset communication protocol. If the authentication result is successful, the second processor receives the configuration information from the second Type-C interface module and updates its own configuration information accordingly. This system does not require pre-configuration of a management network; batch configuration information synchronization can begin simply by connecting a Type-C cable. It eliminates the need for complex cabling, does not occupy business network bandwidth, simplifies the synchronization process, and improves the deployment and maintenance efficiency of server clusters. The synchronized slave device can be used as the master device for the next synchronization process, and other processors can be connected and configured sequentially via Type-C cables to form a configuration synchronization chain. In addition, a corresponding security authentication module is set up for the BMC, and a physical-level access control mechanism is established for critical operations to achieve hardware-level security protection for out-of-band interactions. This solves the problems of requiring a centralized management network or complex preparation work to configure the BMC, resulting in low configuration efficiency, insufficient security protection for the BMC, and easy access to compromised permissions.

[0031] As an optional embodiment, the second processor includes a handshake protocol module and a verification module, and the security authentication module includes a computing unit and a secure storage area; the security authentication module is connected to the second processor through a preset communication bus; The handshake protocol module is used to generate a first random number and send the first random number to the security authentication module through a preset communication bus; The processing unit is used to perform a signature operation on the first random number based on the private key, generate signature data, read the digital certificate in the secure storage area, and send the signature data and digital certificate to the second processor through a preset communication bus. The verification module is used to verify the signature validity of the digital certificate using the root certificate public key. If the digital certificate verification is successful, the public key of the security authentication module is extracted from the digital certificate, and the signature data is verified based on the public key. The verification module is also used to generate a second random number if the signature data is verified, encrypt the second random number according to the public key to generate ciphertext data, and send the ciphertext data to the security authentication module through a preset communication bus. The processing unit is used to decrypt the ciphertext data according to the private key, obtain the decrypted data, and send the decrypted data to the second processor through a preset communication bus; The verification module compares the second random number with the decrypted data. If the second random number matches the decrypted data, the authentication result is confirmed as successful.

[0032] Specifically, Figure 3 A BMC hardware security authentication system based on a Type-C interface was demonstrated. The system comprises a server motherboard and a server front panel. The server motherboard has a second processor, and the server front panel has a second Type-C interface module. A security authentication chip is installed in the second Type-C interface module as the security authentication module. The second processor communicates with the security authentication chip via a pre-defined communication bus. Figure 3 As shown, the second processor includes a handshake protocol module, an execution control module, and a critical operation detection module. The second processor also includes a verification module. The second Type-C interface module includes a secure storage area, an encryption processing unit (referred to as the encryption unit), a physical interface detection circuit, and an anti-tampering protection circuit. The critical operation detection unit is used to intercept and identify high-risk operation requests initiated by users through the BMC Web interface, IPMI commands, etc. The determination of high-risk operations is based on a pre-configured list. Examples include modifying BIOS settings, resetting the BMC administrator password, updating BMC firmware, modifying the boot order, clearing system event logs, and restoring factory settings. The handshake protocol unit is used to implement a two-way authentication protocol with the security authentication chip. The execution control unit is used to determine whether to allow high-risk operations based on the authentication result returned by the handshake protocol unit. If authentication is successful, the operation is allowed to continue; if authentication fails or times out, the operation is rejected and an alarm is triggered.

[0033] The secure storage area is used to pre-store the chip's unique identifier (UID), public / private key pairs, and digital certificates (containing the chip's public key and chip ID). The encryption unit is used to perform cryptographic operations such as signing, verification, encryption, and decryption. It supports asymmetric algorithms such as RSA and ECC. The physical interface detection circuit is used to detect the insertion and removal of the Type-C interface. When the Type-C plug is inserted, a level change on the CC (Configuration Channel) pin triggers detection and generates an interrupt signal to notify the BMC module via a dedicated communication bus. This circuit also draws power from the VBUS (Voltage Bus) pin of the Type-C interface. The tamper protection circuit detects physical attack attempts against the chip, such as voltage / frequency glitches, temperature anomalies, and probe detection. Once an attack is detected, a secure erase or chip self-destruct mechanism can be triggered.

[0034] Figure 4 This is a flowchart illustrating the two-way authentication process between the second processor and the security authentication module, combined with... Figure 4 The bidirectional authentication process between the second processor and the security authentication module is described. The security authentication module is a security authentication chip.

[0035] After a user initiates a high-risk operation, such as sending a configuration information synchronization request to the second processor, the second processor prompts the user to insert a Type-C connector. The maintenance personnel then insert the Type-C cable into the second Type-C interface module on the server's front panel. The second processor is a slave BMC, and the security authentication module is a security authentication chip. Figure 4 As shown, when a user initiates a high-risk operation from the BMC, the BMC prompts the user to insert a Type-C connector. The user inserts the Type-C cable connector into the second Type-C interface module on the front panel of the server.

[0036] The security authentication chip detects the insertion event through the physical interface detection circuit, draws power from the VBUS pin to start, and sends an insertion interrupt signal to the second processor through a dedicated communication bus.

[0037] The handshake protocol module of the second processor generates a first random number, for example, a 128-bit random number R1. The security authentication module is connected to the second processor via a preset communication bus, such as an I2C (Inter-Integrated Circuit) bus or a UART (Universal Asynchronous Receiver / Transmitter) serial bus. The preferred dedicated communication bus is an I2C bus. The preset communication bus is in a high-impedance state during normal server operation, without any communication, to reduce power consumption and attack surface. When the Type-C interface is inserted and the security authentication chip is powered on, the bus is activated, and the second processor initiates communication as the host. The first random number is sent to the security authentication module via the preset communication bus. Figure 4 As shown, a 128-bit random number R1 is generated from the BMC and sent to the security authentication chip.

[0038] The processing unit of the security authentication chip uses its private key to perform a signature operation on R1, generating signature data S1, where S1 = Sign(PrivKey, R1). It reads the digital certificate Cert from the secure storage area and sends the signature data and digital certificate to the second processor via a preset communication bus. Figure 4 As shown, the security authentication chip signs R1 with its private key to obtain R1, reads the certificate Cert, and returns R1 and Cert from the BMC.

[0039] The verification module uses the pre-stored public key of the CA (Certificate Authority) root certificate to verify the signature validity of the Certificate, ensuring that the certificate has not been tampered with and was issued by a trusted CA. If the digital certificate verification passes, the public key PubKey of the security authentication chip is extracted from the digital certificate. The verification module uses the extracted public key PubKey to verify the signature data S1, i.e., Verify(PubKey, R1, S1). Additionally, the digital certificate includes an expiration field; the BMC checks whether the current time is within the validity period when verifying the certificate, and expired certificates will be rejected.

[0040] If the signature data verification passes, it proves that the other party possesses the private key corresponding to the certificate, i.e., their identity is genuine. The verification module generates a second random number R2, encrypts the second random number using the public key PubKey of the security authentication chip, and generates ciphertext data E2, where E2 = Encrypt(PubKey, R2). This ciphertext data is then sent to the security authentication module via a preset communication bus. Figure 4As shown, the BMC uses the CA root certificate to verify the validity of Cert, extracts the public key from Cert, verifies the signature, and if the verification is successful, the chip identity is genuine. A random number R2 is generated, encrypted with the public key, and the ciphertext is sent to the security authentication chip.

[0041] The processing unit of the security authentication chip uses its private key to decrypt the ciphertext data, obtaining decrypted data R2x, R2x=Decrypt(PrivKey, E2), and sends the decrypted data in plaintext form to the second processor through a preset communication bus.

[0042] The verification module of the second processor compares the second random number R2 with the decrypted data R2x. If the second random number matches the decrypted data, the authentication result is confirmed as successful. The execution control unit of the BMC module receives the authentication success notification and allows the previously intercepted high-risk operation to proceed.

[0043] In the above process, all cryptographic operations use either the 512-bit RSA algorithm or the 256-bit ECC (Elliptic Curve Cryptography) algorithm to ensure sufficient security strength. The RSA algorithm is an asymmetric encryption algorithm based on the problem of factoring large integers.

[0044] In this embodiment, the solution relies on Type-C hardware to achieve two-way security authentication, accurately controlling high-risk BMC operations on the server. The communication bus is in normal dormancy to reduce the attack surface, the security chip can resist physical tampering attacks, and combined with high-strength encryption algorithms, it effectively intercepts illegal operations, comprehensively improving server operation and maintenance and hardware protection security.

[0045] As an optional embodiment, the second processor includes an operation detection unit; An operation detection unit is used to acquire user operation requests and determine the risk level of user operation requests, wherein configuration information synchronization requests are included in user operation requests. The second processor is also used to determine whether a first interrupt signal is received when the risk level is a preset level. The first interrupt signal is used to indicate that the plug of the Type-C cable is inserted into the second Type-C interface module.

[0046] Specifically, the operation detection unit acquires user operation requests and determines the risk level of the user operation requests. For example, if the user operation request is to view logs, the risk level is low and no hardware authentication is required; if the user operation request is to restart the BMC, the risk level is medium and only simple authentication is required; if the user operation request is to flash firmware, change boot items, or restore factory settings, the risk level is high and full two-way authentication and in-situ authentication are required; if the user operation request is to destroy the key or force format, the risk level is extremely high and two consecutive plug-in / unplug confirmations are required.

[0047] Preset risk levels include, for example, high risk and very high risk. When the risk level is at the preset level, the second processor determines whether a first interrupt signal has been received. The first interrupt signal indicates that a Type-C cable plug has been inserted into the second Type-C interface module. The first interrupt signal is generated by the security authentication chip after detecting that a Type-C cable plug has been inserted into the second Type-C interface module. Additionally, the security authentication chip can also generate a first interrupt signal if any other Type-C plug is inserted into the second Type-C interface module.

[0048] Figure 5 This embodiment demonstrates a BMC hardware security authentication method based on the processor's configuration information synchronization system, such as... Figure 5 As shown, the method includes: a second processor monitoring a user's high-risk operation request; the second processor prompting the user to insert an authorized Type-C security key via a front panel indicator or the BMC management interface; when the Type-C interface is inserted, the security authentication chip powers on and starts, the physical interface detection circuit generates an insertion interrupt signal, and notifies the second processor via a dedicated communication bus; the second processor and the security authentication chip perform a handshake protocol for bidirectional authentication: if both bidirectional authentications are successful, the BMC's execution control unit allows the high-risk operation; if authentication fails or times out, the BMC refuses to execute the high-risk operation and records a security log.

[0049] In this embodiment, user operation requests are categorized into multiple risk levels, coupled with a differentiated authentication mechanism. Operations at the preset risk level must complete two-way authentication by inserting a Type-C connector. If authentication fails, the operation will be directly intercepted and a security log will be retained. This approach precisely controls high-risk operational behaviors, effectively avoids the risk of unauthorized operations, and significantly improves server operational security.

[0050] As an optional embodiment, the security authentication module includes a physical interface detection circuit; The physical interface detection circuit is used to activate the security authentication module by drawing power from a preset pin in the second Type-C interface module and generating a first interrupt signal when the plug of the Type-C cable is detected to be inserted into the second Type-C interface module. The physical interface detection circuit is also used to transmit the first interrupt signal to the second processor via a preset communication bus; The physical interface detection circuit is also used to generate a second interrupt signal when the plug of the Type-C cable is detected to be unplugged from the second Type-C interface module, and to transmit the second interrupt signal to the second processor through a preset communication bus. The second interrupt signal is used to instruct the second processor to terminate the current operation.

[0051] Specifically, the security authentication chip adopts an independent power supply design. When the physical interface detection circuit detects that the Type-C cable plug is inserted into the second Type-C interface module, the security authentication module draws power from a preset pin in the second Type-C interface module to start. The preset pin is, for example, the VBUS pin of the Type-C interface. When the Type-C interface is not inserted, the security authentication chip is in a completely powered-off state and does not consume server standby power.

[0052] A first interrupt signal is generated and transmitted to the second processor via a preset communication bus. The second processor is notified that the plug of the Type-C cable has been inserted into the second Type-C interface module and subsequent operations can be performed.

[0053] In addition, the physical interface detection circuit is also used to perform physical existence verification steps. The physical interface detection circuit of the security authentication chip continuously monitors the connection status of the Type-C interface. If the plug of the Type-C cable is detected to be pulled out of the second Type-C interface module during the execution of a critical operation, a second interrupt signal is generated and transmitted to the second processor through a preset communication bus, instructing the second processor to immediately trigger an interrupt. After receiving the second interrupt signal, the second processor forcibly terminates the current operation.

[0054] The security chip directly drives the LED or buzzer, preventing the BMC from forging authentication prompts. Unplugging the Type-C connector not only terminates the operation but also automatically triggers a security snapshot and log lock. Unplugging immediately freezes the BMC configuration, automatically generating an unalterable security snapshot, and putting the log into read-only protection. In addition, to prevent spoofing attacks, the physical interface detection circuit uses VBUS current detection and CC pin timing dual verification. The security chip has built-in current detection, which must detect a legitimate load current, while simultaneously verifying the timing characteristics of the CC pin. When the BMC malfunctions, the security chip can independently block high-risk operations. The security chip has independent operation interception capabilities. Even if the BMC crashes or is controlled by a hacker, the hardware directly pulls down critical control signals when the Type-C connector is not plugged in, preventing firmware flashing or boot item modification.

[0055] In this embodiment, the security chip is powered via a Type-C interface pin. When no cable is plugged in, the chip is completely powered off and consumes zero power, effectively saving device energy. The cable plugging / unplugging status can be detected in real time; plugging in triggers authentication, and unplugging immediately terminates high-risk operations, achieving full-process in-place verification and preventing unauthorized tampering during operation.

[0056] As an optional embodiment, the first processor is configured to, when connected to the second processor via a Type-C cable, negotiate master-slave identity with the second processor via the Type-C cable, determine whether the first processor is a master device or a slave device based on the negotiation result, and determine whether the second processor is a master device or a slave device.

[0057] Specifically, this embodiment adopts an alternate mode. When two processors are connected via a Type-C cable, such as when the first processor is connected to the second processor via a Type-C cable, the two processors will negotiate to enter the alternate mode and perform master-slave identity negotiation to determine which processor is the master device and the other is the slave device.

[0058] The first processor negotiates master-slave status with the second processor via a Type-C cable. Based on the negotiation result, the first processor is determined to be either the master or slave device, and the second processor is also determined to be either the master or slave device. This establishes a high-speed data channel (e.g., based on Type-C), through which configuration data packets are transmitted from the master device to the slave device. This method is suitable for transmitting large amounts of data, such as firmware images.

[0059] In addition, this embodiment designs a PC (personal computer) scenario. In the PC scenario, multiple BMCs can be directly connected using a USB hub to perform batch configuration information synchronization operations on multiple BMCs, improving efficiency. When interacting with the PC, the BMC acts only as a slave device. A mass storage gadget is added at both ends after negotiation, with the master BMC mounting the slave BMC device and treating the slave BMC as a USB flash drive for reading and writing. This embodiment also includes an error handling process to handle errors such as negotiation failure, both ends being master or slave, device mounting failure, and data processing failure.

[0060] In this embodiment, a high-speed data channel is established through a Type-C master-slave mode and master-slave identity negotiation, enabling efficient transmission of large-capacity configuration data such as firmware images. This simplifies the configuration synchronization process between BMCs and significantly improves transmission efficiency and adaptability. The point-to-point physical connection via Type-C cable avoids the risk of network attacks, making it particularly suitable for environments with extremely high network security requirements.

[0061] As an optional embodiment, the first processor includes: a first configuration trigger module; the second processor includes: a second configuration trigger module; The first configuration trigger module is used to determine that the first processor is the master device and the second processor is the slave device when the preset button of the first processor is triggered, or when the first processor receives a master device configuration instruction. The second configuration trigger module is used to determine that the second processor is the master device and the first processor is the slave device when the preset button of the second processor is triggered, or when the second processor receives a master device configuration instruction.

[0062] Specifically, in this embodiment, a first configuration trigger module is provided in the first processor, and a second configuration trigger module is provided in the second processor. The configuration trigger module is used to trigger the first BMC to start the configuration synchronization process in response to the user's physical operation or software command.

[0063] Preset buttons, for example: the "synchronization button" on the compute node.

[0064] The first configuration trigger module determines that the first processor is the master device and the second processor is the slave device when it detects that a preset button on the first processor has been triggered, or when the first processor receives a master device configuration command. A preset button being triggered, for example, is when an administrator presses the "synchronization button" on a node. A master device configuration command can be a specific IPMI command sent by the administrator to the first processor to specify the master BMC.

[0065] The second configuration trigger module determines that the second processor is the master device and the first processor is the slave device when it determines that the preset button of the second processor is triggered, or when the second processor receives a master device configuration instruction.

[0066] In this embodiment, two triggering methods are supported: physical button pressing or IPMI command. This allows for quick designation of master and slave devices, convenient and flexible operation, efficient startup of the BMC configuration synchronization process, lowering the threshold for master and slave setup, and improving the ease of use and efficiency of configuration synchronization.

[0067] As an optional embodiment, the default communication protocol is an extended communication protocol based on the USB Power Delivery Protocol; The first processor is used to transmit configuration information to the second processor via a Type-C cable using vendor-defined messages in the USB Power Delivery Protocol, provided that the preset communication protocol is an extended communication protocol based on the USB Power Delivery Protocol.

[0068] Specifically, the default communication protocol is an extended communication protocol based on the USB Power Delivery (PD) protocol.

[0069] When the preset communication protocol is an extended communication protocol based on the USB Power Delivery Protocol, the first processor uses the Vendor Defined Message (VDM) in the USB Power Delivery Protocol to transmit configuration information to the second processor via a Type-C cable.

[0070] Alternatively, the default communication protocol can be a proprietary protocol implemented using the Alternate Mode of the Type-C interface. In this case, the first processor transmits configuration data via an established USB or non-USB data link. The configuration synchronization process is entirely performed on the proprietary link between BMCs, without consuming bandwidth of the business network or out-of-band management network, and with zero interference to the normal operation of the server.

[0071] As an optional embodiment, the first processor includes: a mode confirmation module, a first inventory generation module, and a first configuration management module; the second processor includes: a second inventory generation module and a second configuration management module. The mode confirmation module is used to switch the first processor to bidirectional synchronization mode and notify the second processor to switch to bidirectional synchronization mode when a bidirectional synchronization instruction is received. The first list generation module is used to generate a first configuration list based on the configuration information of the first processor and send it to the second processor in bidirectional synchronization mode. The second list generation module is used to generate a second configuration list based on the configuration information of the second processor and send it to the first processor in bidirectional synchronization mode. The first configuration management module is used to determine the first configuration item to be synchronized according to the second configuration list and send it to the second processor, and when the second configuration item to be synchronized is received, send the configuration information corresponding to the second configuration item to be synchronized to the second processor. The second configuration management module is used to determine the second configuration item to be synchronized according to the first configuration list and send it to the first processor, and when the first configuration item to be synchronized is received, send the configuration information corresponding to the first configuration item to be synchronized to the first processor. The first configuration management module is further configured to, if it is determined that there is conflict information based on the comparison result of the first configuration list and the second configuration list, determine the target information corresponding to the conflict information in the configuration information of the first processor or the configuration information of the second processor, and synchronize the target information to the second processor.

[0072] Specifically, the first processor and the second processor establish a physical connection through a Type-C cable to complete power negotiation and basic data link setup (based on USB PD or Alternate Mode).

[0073] Two-way synchronization commands, for example, are commands sent by the administrator to IPMI to specify the two-way synchronization mode.

[0074] Upon receiving a bidirectional synchronization command, the mode confirmation module switches the first processor to bidirectional synchronization mode and notifies the second processor to switch to bidirectional synchronization mode.

[0075] In bidirectional synchronous mode, the first configuration list generation module reads the configuration information from its own non-volatile memory, generates a first configuration list (including configuration type: network configuration / security policy / hardware threshold, corresponding version number, data digest, etc.), and sends the first configuration list to the second processor.

[0076] In bidirectional synchronization mode, the second configuration list generation module reads its own configuration information, generates a second configuration list (including configuration type, version number, and data summary), and sends the second configuration list to the first processor.

[0077] Upon receiving the second configuration list, the first configuration management module verifies its integrity. If verification fails, it requests a retransmission. It parses the second configuration list, extracts the configuration types (such as security policies) that the second processor needs to synchronize, and marks them as the first configuration items to be synchronized. It then sends the identifier of the first configuration item to be synchronized (e.g., the protocol field marker "Security Policy V2.1") to the second processor. Upon receiving the second configuration item to be synchronized from the second processor, the first configuration management module sends the corresponding configuration information to the second processor.

[0078] After receiving the first configuration list, the second configuration management module verifies its completeness. If the verification passes, it parses out the configuration types (such as network configuration) that it needs to synchronize from the first processor, marks them as second configuration items to be synchronized, sends a confirmation message to the first processor to confirm the synchronization range, explicitly informing it that the first configuration item to be synchronized has been received, and then sends the second configuration item to be synchronized to the second processor. Upon receiving the first configuration item to be synchronized, the second configuration management module sends the configuration information corresponding to the first configuration item to the first processor.

[0079] The first configuration management module compares the first configuration list and the second configuration list to determine if there are any conflicting information. For example, if there are configuration items with the same name but conflicting versions in the lists (such as both lists having "Network Configuration V1.0" but with different content), then this is considered conflicting information. The first configuration management module determines the conflict information handling rules, such as: higher priority configurations override lower priority configurations, and higher version numbers take precedence.

[0080] If the processing rule is that high-priority configuration overrides low-priority configuration, then the target information corresponding to the conflicting information is determined in the configuration information of the master device.

[0081] If the processing rule prioritizes the higher version number, the first configuration management module compares the version numbers of the conflicting items. If its own version is higher, it determines the target information corresponding to the conflicting information in the master device's configuration information. If the other device's version is higher, it determines the target information corresponding to the conflicting information in the slave device's configuration information.

[0082] If the handling rule requires manual user confirmation, the conflict information is recorded in the system event log, synchronization is paused, the local alarm indicator light is illuminated, and the administrator is prompted to intervene. The administrator is then asked to confirm the handling plan via a physical button or IPMI command. Based on the user's instructions, the target information corresponding to the conflict information is determined from the configuration information of the first processor or the configuration information of the second processor.

[0083] The first configuration management module synchronizes the target information to the second processor. After the second processor completes the synchronization, it sends a conflict resolution signal to the first processor and initiates data transmission preparation.

[0084] In this embodiment, the bidirectional synchronization mode can be easily switched via commands. Configuration lists are transmitted via Type-C cables and their integrity is ensured through verification lists, accurately selecting complementary items to be synchronized. A built-in multi-rule conflict handling mechanism can automatically or manually resolve configuration conflicts, achieving bidirectional complementary configuration synchronization between BMCs without the need for a fixed master-slave configuration, improving synchronization flexibility, accuracy, and efficiency, and reducing operational complexity.

[0085] As an optional embodiment, the first processor includes: a first configuration management module, a communication protocol module, a first storage module, and a first log recording module; The first storage module is used to store the configuration information of the first processor; The communication protocol module is used to acquire preset communication protocols; The first configuration management module is used to read configuration information from the first storage module when the first processor is the master device, encapsulate the configuration information into a data packet according to the encapsulation structure corresponding to the preset communication protocol, and transmit the data packet to the second processor through a Type-C cable. The first logging module is used to obtain configuration information synchronization operation information and write the configuration information synchronization operation information into the system event log of the first processor.

[0086] Specifically, the communication protocol module runs in the BMC firmware and is responsible for implementing the preset communication protocol. This preset protocol can be extended based on the USB PD protocol: it utilizes Vendor Defined Messages (VDMs) defined in the USB PD protocol to carry configuration data. The BMC communicates through the configuration channel of the Type-C interface. This method eliminates the need to establish a high-speed data link, has low power consumption, and is relatively simple to implement. Figure 6As shown, the baseboard management controller includes a configuration management module, a communication protocol module, non-volatile memory, and a Type-C interface controller.

[0087] The first storage module is, for example, the non-volatile memory (such as SPI Flash) of the first processor. Configuration information can be stored in the first storage module, including network settings, user information, security keys, hardware monitoring parameters, etc.

[0088] In this embodiment, a first configuration management module is set in the first processor. The first configuration management module is responsible for reading, packaging, parsing, and applying configuration information. When the first processor is the master device, the first configuration management module reads the configuration information from the first storage module, encapsulates the configuration information into a data packet according to the encapsulation structure corresponding to the preset communication protocol, and transmits the data packet to the second processor through a Type-C cable.

[0089] The first logging module acquires configuration information synchronization operation information, such as sending a confirmation message from the BMC to the main BMC, reporting the success or failure status of the configuration application. Configuration information synchronization operation information includes, for example, time, peer identifier, and synchronization result. The first logging module writes the configuration information synchronization operation information to the system event log of the first processor for administrator querying. Figure 2 As shown, the master BMC and slave BMC record synchronization logs.

[0090] As an optional embodiment, the second processor includes: a second storage module, a second configuration management module, and a second log recording module; The second configuration management module is used to perform integrity verification on the received data packet, and if the data packet verification passes, to parse the data packet and obtain new configuration information. The second storage module is used to store the configuration information of the second processor; The second configuration management module is used to write the new configuration information into the second storage module, send synchronization result feedback information to the first processor, and restart the relevant services of the second processor when it is determined that the new configuration information is different from the configuration information of the second processor. The second logging module is used to obtain configuration information synchronization operation information and write the configuration information synchronization operation information into the system event log of the second processor.

[0091] Specifically, the second storage module may be, for example, the non-volatile memory (such as SPI Flash) of the second processor. The second storage module stores the configuration information of the second processor, such as network settings, user information, security keys, hardware monitoring parameters, etc.

[0092] The second configuration management module is responsible for reading, packaging, parsing, and applying configuration information. It compares the received new configuration information with the configuration information stored in the second processor within the second storage module. If a difference is found, the new configuration information is written to the second storage module, a synchronization result feedback message is sent to the first processor, and the relevant services of the second processor are restarted to make the new configuration effective. The synchronization result feedback message includes, for example, feedback on the application result of the new configuration information.

[0093] The second logging module is used to obtain configuration information synchronization operation information, such as key information of this synchronization operation, including time, peer identifier, and result. This configuration information synchronization operation information is written to the system event log of the second processor for administrator querying.

[0094] In this embodiment, a complete feedback and logging mechanism is designed to make the synchronization process monitorable and traceable, facilitating fault diagnosis and operation and maintenance management.

[0095] As an optional embodiment, the first configuration management module includes: a fragmentation unit and a fragmentation transmission unit; the second configuration management module includes a fragmentation receiving unit; The fragmentation unit is used to divide data packets into fragments of a preset size and generate fragment sequence numbers; The fragmentation transmission unit is used to transmit fragments sequentially to the second processor via a Type-C cable according to the sequence number, and to determine the transmission status of the fragments. The fragment receiving unit is used to receive fragments, generate a fragment receiving confirmation message according to the sequence number of the received fragment, and send the fragment receiving confirmation message to the first processor. The fragmentation transmission unit is also used to modify the transmission status of the fragment corresponding to the fragment reception confirmation message to transmission success, and to determine the transmitted fragments that have not received the corresponding fragment reception confirmation message and modify the transmission status of the transmitted fragments to transmission failure. The fragment receiving unit is also used to generate a transmission interruption alarm message and send it to the first processor if no fragment is received within a preset time period. The transmission interruption alarm message includes the sequence number of the received fragment. The fragmentation transmission unit is also used to determine the unsent fragments based on the sequence number of the received fragments, and to transmit the unsent fragments and the fragments that failed to be transmitted to the second processor according to the sequence number.

[0096] Specifically, the fragmentation unit divides the data packet into fragments of a preset size and generates a fragment sequence number. For example, the preset size of the complete data packet is 1KB / fragment, which can be adjusted through protocol configuration. Each fragment is assigned an identifier: fragment sequence number (incrementing from 001), total number of fragments, fragment checksum, and unique data packet ID (consistent with the header identifier of the original data packet).

[0097] The fragmented transmission unit initializes the "fragmented transmission status table" to record the status of each fragment (not transmitted / transmitting / acknowledged) and sets retry parameters (default 3 retries, each retrieval interval is 500ms, configurable).

[0098] The fragment transmission unit is used to transmit fragments sequentially to the second processor via a Type-C cable according to their sequence numbers, and to determine the transmission status of the fragments. For example, fragment data is sent sequentially via the Type-C communication link in ascending order of fragment sequence number. After each fragment is sent, the unit waits for the second processor to receive feedback (the default timeout is 1 second). The unit receives the "fragment reception confirmation" message from the second BMC, parses the "maximum received fragment sequence number" and "list of lost fragment sequence numbers" in the message, and updates the local "fragment transmission status table" (marking confirmed fragments as "confirmed" and lost fragments as "not transmitted").

[0099] The fragment receiving unit initializes the fragment receiving buffer and the received fragment sequence number table to store successfully received fragment data and their corresponding sequence numbers; it also sends an initialization completion response to the first processor to indicate that it is ready to receive fragments.

[0100] The fragment receiving unit receives fragments, generates a fragment receiving acknowledgment message based on the sequence number of the received fragment, and sends the fragment receiving acknowledgment message to the first processor. For example, the fragment receiving acknowledgment message indicates that the fragment with sequence number 001 has been successfully received.

[0101] The fragmentation transmission unit modifies the transmission status of the fragment corresponding to the fragment reception acknowledgment message to "transmission successful". If the fragmentation transmission unit determines that a sent fragment has not received the corresponding fragment reception acknowledgment message, it modifies the transmission status of the sent fragment to "transmission failed". For example, if no feedback is received within 1 second after sending a single sent fragment, or a fragment verification failure response is received, the sent fragment is determined to have failed to transmit.

[0102] If the fragmentation transmission unit detects a disconnection in the Type-C cable (e.g., a loose cable), it immediately stops transmitting, records the current "maximum confirmed fragment sequence number" and "list of untransmitted fragments", and initiates link reconnection detection (detecting once every 1 second for 5 seconds).

[0103] The preset time period is, for example, 5 seconds, 10 seconds, or other durations. If the fragment receiving unit does not receive a fragment within the preset time period, it generates a transmission interruption alarm message and sends it to the first processor. The transmission interruption alarm message includes the sequence number of the received fragment. Alternatively, the transmission interruption alarm message may only include the maximum sequence number of the received fragment.

[0104] The fragmentation transmission unit is also used to determine unsent fragments based on the sequence numbers of the received fragments. For example, if the sequence numbers of the received fragments are 001-008, then the unsent fragments are fragments with sequence numbers 009-020. Fragments with sequence numbers 003 and 006 are also identified as having failed transmission.

[0105] According to the sequence number, unsent fragments and fragments that failed to be transmitted are transmitted to the second processor. Fragments with sequence numbers 009-020, and fragments with sequence numbers 003 and 006 are retransmitted to the second processor. Fragments that failed to be transmitted can be retransmitted in order of increasing sequence number, and only unsuccessful fragments can be retransmitted without retransmitting confirmed fragments.

[0106] In this embodiment, data integrity is ensured through fragmentation, sequence number identification, and verification. A status table tracks fragment transmission status, and confirmation is received to accurately locate failed / untransmitted fragments. Resumption of interrupted transmission and retransmission of failed transmissions are supported, only missing fragments are retransmitted, avoiding redundant transmission.

[0107] As an optional embodiment, a refined permission hierarchy and operation authorization mechanism can be designed for the configuration information in the first processor and the second processor.

[0108] In this embodiment, a mechanism for role-based identity verification, configuration item permission isolation, and sensitive operation authorization is adopted. The process is executed in the order of permission initialization, identity authentication, permission negotiation, authorization verification, and synchronous execution to ensure that no unauthorized operations occur.

[0109] Specifically, the permission module initialization phase: After powering on, the first processor loads the built-in security permission module and initializes the preset roles and corresponding permission lists (stored in an encrypted partition). The first processor reads the configuration information and categorizes it by sensitivity (sensitive category: security key, administrator account; ordinary category: sensor threshold, log policy), marks the permission level for each type of configuration item, and listens for Type-C interface connection requests to prepare to receive operator identity information.

[0110] The second processor synchronously loads the security permission module, initializes the same role permission system and configuration item sensitivity classification standard as the first processor; initializes the authorization verification buffer to store subsequently received identity credentials, authorization results and other information; after completing the Type-C cable establishment, it sends a permission module ready signal to the first processor and waits for permission negotiation.

[0111] Operator authentication stage: The first processor receives the identity credentials input by the operator (such as the hash value of the username and password, and the hardware key identifier); verifies the validity of the identity credentials (by comparing them with the preset credentials in the non-volatile memory), confirms the role corresponding to the operator, generates the identity authentication result (including role type and permission scope), and sends it to the second processor through the Type-C encrypted channel, while caching the result locally.

[0112] The second processor receives the authentication result sent by the first processor and verifies the integrity of the result by encrypting it with a public key. If the authentication result is an invalid identity, it immediately sends an authentication failure response to the first processor, triggering a link disconnection. If the authentication is successful, it caches the operator's role and permission scope, sends feedback to the first processor that the authentication has been successful, and can initiate permission negotiation.

[0113] Scope of authority negotiation phase: The first processor, based on the operator's role and permissions, filters the configuration items it can synchronize (e.g., an operations and maintenance administrator only filters general configurations), and generates a list of synchronizable configurations (including configuration item type, sensitivity, and required permissions). It then sends this list of synchronizable configurations to the second processor, along with a list of configuration items requested for synchronization; and receives a permission matching confirmation message from the second processor, confirming that both parties have consistent permission requirements for the synchronized configuration items.

[0114] The second processor receives the list of syncable configurations from the first processor, compares it with the local permission system, and verifies whether the permission tags of the configuration items in the list are accurate (e.g., if the sensor threshold is confirmed to be of the ordinary class, the operation and maintenance administrator can operate it); if the list contains configuration items that exceed the operator's permissions, it sends a permission mismatch alarm to the first processor and lists the illegal configuration items; if the permissions match correctly, it sends a "permission match confirmation" message to clearly indicate that ordinary class configuration items can be received for synchronization.

[0115] Sensitive operation secondary authorization stage: If the first processor can synchronize the configuration list containing sensitive configuration items, it triggers a secondary authorization process: sending an authorization request to the mobile device / cloud platform bound to the operator; receiving the secondary authorization certificate from the operator and verifying its validity; if the secondary authorization is successful, generating a sensitive operation authorization certificate (including authorization time and a validity period of 10 minutes) and sending it to the second processor; if the authorization fails, terminating the synchronization process.

[0116] The second processor receives the sensitive operation authorization credential sent by the first processor and verifies the validity and integrity of the credential. If the authorization credential is not received or is invalid, it sends a secondary authorization failure response to the first processor and refuses to receive sensitive configuration items. If the authorization is successful, it caches the authorization credential, sends feedback to the first processor that the secondary authorization is successful, and the sensitive configuration can be transmitted.

[0117] Configure synchronous execution phase: The first processor extracts the corresponding configuration item data according to the syncable configuration list, and requires an authorization credential identifier to be added for sensitive configuration items; it encapsulates the configuration data packet, adds an authorization verification field (including operator role and configuration item sensitivity) to the packet header, and sends it to the second processor via a Type-C cable. The processor receives the configuration reception confirmation information from the second processor, and after confirming that there are no permission-related objections, waits for the synchronization result feedback.

[0118] The second processor receives the configuration data packet and first verifies the permission verification field (e.g., confirming that the configuration item is a sensitive class and has been granted secondary authorization). If the verification finds that the configuration item exceeds the operator's permissions (e.g., receiving sensitive data without authorization), the data packet is immediately discarded, a permission violation alarm is sent, the log is recorded, and the link is disconnected. After the verification passes, the data packet is parsed and the configuration is applied. A successful configuration application and permission compliance response is sent to the first processor.

[0119] In this embodiment, BMC configuration synchronization is managed throughout the entire process through role verification, configuration item permission isolation, and secondary authorization for sensitive operations. Permission verification is performed according to a standardized process to block unauthorized operations and protect the security of sensitive configurations. A unified permission system adapts to multi-role collaboration, encrypted transmission enhances compliance, balancing security and ease of use, and effectively reducing operational risks.

[0120] According to an embodiment of the present invention, a method for synchronizing processor configuration information is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0121] This embodiment provides a method for synchronizing processor configuration information. This method is applied to a processor. Figure 7 This is a flowchart of a processor configuration information synchronization method according to an embodiment of this application, such as... Figure 7 As shown, the process includes the following steps: Step S701: Connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor using a Type-C cable.

[0122] Specifically, a Type-C cable is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor, and a communication link is established. The first processor and the second processor negotiate master-slave roles through the Type-C cable to determine the master device and slave device, namely the master BMC and the slave BMC.

[0123] In step S702, if the second processor is a slave device and a configuration information synchronization request is received, and if the plug of the Type-C cable is inserted into the second Type-C interface module, the second processor and the security authentication module in the second Type-C interface module perform bidirectional authentication to obtain the authentication result.

[0124] Specifically, if a plug is detected to be inserted into the second Type-C interface module, the second processor and the security authentication module in the second Type-C interface module perform a handshake protocol for two-way authentication. Based on the authentication result, the second processor decides whether to allow the high-risk operation. If both authentications are successful, the BMC's execution control unit allows the high-risk operation, including the BMC configuration operation corresponding to the configuration information synchronization request. If authentication fails or times out, the BMC refuses to execute the high-risk operation and records it in the security log.

[0125] In step S703, if the first processor is the master device and the authentication result is successful, the configuration information of the first processor is read and the configuration information is transmitted to the second Type-C interface module via a Type-C cable according to the preset communication protocol.

[0126] Specifically, when the first processor is the master device (i.e., the first processor is the master BMC), the master BMC reads configuration information from its non-volatile memory. This configuration information includes at least one of the following: network configuration information, user account information, security certificates, sensor thresholds, event log policies, and firmware update images. The master BMC encapsulates the configuration information into a configuration data packet conforming to a predefined format. According to a preset communication protocol, the configuration data packet containing the configuration information is transmitted via a Type-C cable to other processors connected to the first processor, i.e., slave BMCs. Preset communication protocols include, for example, USB PD and dedicated communication protocols for Alternate Mode. The dedicated communication protocol for Alternate Mode refers to non-USB high-speed protocols multiplexed through the USB Type-C interface, such as DisplayPort, HDMI, and Thunderbolt. It relies on USB PD negotiation to enter this mode, but the data transmission itself is completed by the corresponding professional protocol.

[0127] In step S704, if the authentication result is successful, the second processor receives configuration information from the second Type-C interface module and updates the configuration information of the second processor according to the received configuration information.

[0128] Specifically, when the second processor is a slave device (i.e., a slave BMC), it receives configuration data packets transmitted via a Type-C cable from other processors connected to the second processor. After parsing the configuration data packets and verifying their integrity and validity, it retrieves the configuration information from the packets and applies it to itself, updating its own configuration information based on the received information. Additionally, the slave BMC can send application results back to the master BMC.

[0129] The processor configuration information synchronization method provided in this embodiment does not require pre-configuration of the management network; batch configuration information synchronization can begin simply by connecting a Type-C cable. It eliminates the need for complex cabling, does not consume service network bandwidth, simplifies the synchronization process, and improves the deployment and maintenance efficiency of the server cluster. The synchronized slave device can be used as the master device for the next synchronization process, and other processors can be connected and configured sequentially via a Type-C cable to form a configuration synchronization chain. Furthermore, a corresponding security authentication module is set up for the BMC, and a physical-level access control mechanism for critical operations is established to achieve hardware-level security protection for out-of-band interactions.

[0130] This embodiment also provides a processor configuration information synchronization device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0131] This embodiment provides a processor configuration information synchronization device, which is deployed in a processor configuration information synchronization system, such as... Figure 8 As shown, it includes: The connection module 801 is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor using a Type-C cable. The authentication module 802 is used to perform bidirectional authentication between the second processor and the security authentication module in the second Type-C interface module when the second processor is a slave device and a configuration information synchronization request is received, and the plug of the Type-C cable is inserted into the second Type-C interface module, to obtain the authentication result. The configuration information transmission module 803 is used to read the configuration information of the first processor when the first processor is the master device, and if the authentication result is successful, transmit the configuration information to the second Type-C interface module through a Type-C cable according to a preset communication protocol. The configuration information receiving module 804 is used to receive configuration information from the second Type-C interface module using the second processor when the authentication result is successful, and to update the configuration information of the second processor according to the received configuration information.

[0132] Further functional descriptions of the above modules are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0133] In this embodiment, the processor configuration information synchronization device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0134] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0135] The following is a detailed reference. Figure 9 This diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 901, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 902 or a program loaded from memory 908 into random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the electronic device. The processor 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0136] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 9 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0137] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a memory 908, or installed from a ROM 902. When the computer program is executed by a processor 901, it performs the functions defined in the processor configuration information synchronization method of the embodiments of the present invention.

[0138] Figure 9 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present invention.

[0139] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the configuration information synchronization method for any of the processors described above when running.

[0140] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0141] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the embodiments of the configuration information synchronization method for any of the processors described above.

[0142] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the processor configuration information synchronization method embodiments described above.

[0143] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0144] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0145] The foregoing has provided a detailed description of a processor configuration information synchronization system, method, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A processor configuration information synchronization system, characterized in that, The system includes: a first processor, a second processor, and a Type-C cable; The Type-C cable is used to connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor; The second processor, when it is a slave device and receives a configuration information synchronization request, performs bidirectional authentication with the security authentication module in the second Type-C interface module if the plug of the Type-C cable is inserted into the second Type-C interface module, and obtains the authentication result; The first processor, when acting as the main device, reads its own configuration information if the authentication result is successful, and transmits the configuration information to the second Type-C interface module via the Type-C cable according to a preset communication protocol. The second processor is further configured to receive the configuration information from the second Type-C interface module when the authentication result is successful, and update its own configuration information according to the received configuration information; The second processor includes an operation detection unit; the operation detection unit is used to acquire a user operation request and determine the risk level of the user operation request, wherein the configuration information synchronization request is included in the user operation request; the second processor is further used to determine whether a first interrupt signal is received when the risk level is a preset level, wherein the first interrupt signal is used to indicate that the plug of the Type-C cable is inserted into the second Type-C interface module; the security authentication module includes a physical interface detection circuit; the physical interface detection circuit is used to generate the first interrupt signal by drawing power from a preset pin in the second Type-C interface module when the plug of the Type-C cable is detected to be inserted into the second Type-C interface module; the preset pin is Ty When the Type-C interface is not inserted, the security authentication module is in a completely powered-off state via the VBUS pin of the Type-C interface. The physical interface detection circuit is also used to transmit the first interrupt signal to the second processor via a preset communication bus. Furthermore, the physical interface detection circuit generates a second interrupt signal when the plug of the Type-C cable is detected to be unplugged from the second Type-C interface module, and transmits the second interrupt signal to the second processor via the preset communication bus. The second interrupt signal is used to instruct the second processor to terminate the current operation. The physical interface detection circuit employs dual verification of VBUS current detection and CC pin timing. The security authentication module has built-in current detection to detect legitimate load current and simultaneously verifies the timing characteristics of the CC pin to determine whether a false insertion attack has occurred. The first processor includes a mode confirmation module, a first list generation module, and a first configuration management module; the second processor includes a second list generation module and a second configuration management module; the mode confirmation module is used to switch the first processor to bidirectional synchronization mode upon receiving a bidirectional synchronization instruction, and to notify the second processor to switch to bidirectional synchronization mode; the first list generation module is used to generate a first configuration list based on the configuration information of the first processor and send it to the second processor in bidirectional synchronization mode; the second list generation module is used to generate a second configuration list based on the configuration information of the second processor and send it to the first processor in bidirectional synchronization mode; the first configuration management module is used to determine a first configuration list to be generated based on the second configuration list. The first configuration management module is configured to synchronize configuration items and send them to the second processor, and upon receiving a second configuration item to be synchronized, send the configuration information corresponding to the second configuration item to the second processor; the second configuration management module is configured to determine a second configuration item to be synchronized based on the first configuration list and send it to the first processor, and upon receiving the first configuration item to be synchronized, send the configuration information corresponding to the first configuration item to the first processor; the first configuration management module is further configured to, if it is determined that there is conflict information based on the comparison result between the first configuration list and the second configuration list, determine the target information corresponding to the conflict information in the configuration information of the first processor or the configuration information of the second processor, and synchronize the target information to the second processor.

2. The system according to claim 1, characterized in that, The second processor includes a handshake protocol module and a verification module, and the security authentication module includes a computing unit and a secure storage area; the security authentication module is connected to the second processor through a preset communication bus; The handshake protocol module is used to generate a first random number and send the first random number to the security authentication module through the preset communication bus; The computing unit is used to perform a signature operation on the first random number according to the private key to generate signature data, read the digital certificate in the secure storage area, and send the signature data and the digital certificate to the second processor through the preset communication bus; The verification module is used to verify the signature validity of the digital certificate using the root certificate public key. If the digital certificate is verified, the public key of the security authentication module is extracted from the digital certificate, and the signature data is verified based on the public key. The verification module is further configured to, if the signature data is verified, generate a second random number, encrypt the second random number according to the public key to generate ciphertext data, and send the ciphertext data to the security authentication module through the preset communication bus; The computing unit is used to decrypt the ciphertext data according to the private key to obtain decrypted data, and send the decrypted data to the second processor through the preset communication bus; The verification module is used to compare the second random number with the decrypted data. If the second random number matches the decrypted data, the authentication result is confirmed as successful.

3. The system according to claim 1, characterized in that, The first processor includes: a first configuration management module, a communication protocol module, a first storage module, and a first log recording module; The first storage module is used to store the configuration information of the first processor; The communication protocol module is used to acquire the preset communication protocol; The first configuration management module is used to read the configuration information from the first storage module when the first processor is the master device, encapsulate the configuration information into a data packet according to the encapsulation structure corresponding to the preset communication protocol, and transmit the data packet to the second processor through the Type-C cable; The first log recording module is used to obtain the configuration information synchronization operation information and write the configuration information synchronization operation information into the system event log of the first processor.

4. The system according to claim 3, characterized in that, The second processor includes: a second storage module, a second configuration management module, and a second log recording module; The second configuration management module is used to perform integrity verification on the data packet upon receiving it, and to parse the data packet to obtain new configuration information if the data packet verification passes. The second storage module is used to store the configuration information of the second processor; The second configuration management module is used to write the new configuration information into the second storage module, send synchronization result feedback information to the first processor, and restart the relevant services of the second processor when it is determined that the new configuration information is different from the configuration information of the second processor. The second logging module is used to obtain the configuration information synchronization operation information and write the configuration information synchronization operation information into the system event log of the second processor.

5. The system according to claim 4, characterized in that, The first configuration management module includes a fragmentation unit and a fragmentation transmission unit; the second configuration management module includes a fragmentation receiving unit. The fragmentation unit is used to divide the data packet into fragments of a preset size and generate a sequence number for the fragment; The fragment transmission unit is used to transmit the fragments sequentially to the second processor via the Type-C cable according to the sequence number, and to determine the transmission status of the fragments; The fragment receiving unit is used to receive the fragment, generate a fragment receiving confirmation message according to the sequence number of the received fragment, and send the fragment receiving confirmation message to the first processor. The segmented transmission unit is further configured to modify the transmission status of the segment corresponding to the segment receiving confirmation message to transmission success, and to modify the transmission status of the sent segment that has not received the corresponding segment receiving confirmation message to transmission failure. The fragment receiving unit is further configured to generate a transmission interruption alarm message and send it to the first processor if the fragment is not received within a preset time period, wherein the transmission interruption alarm message includes the sequence number of the received fragment. The fragment transmission unit is further configured to determine the unsent fragments based on the sequence number of the received fragments, and transmit the unsent fragments and the fragments that failed to be transmitted to the second processor based on the sequence number.

6. A method for synchronizing processor configuration information, characterized in that, The method is applied to the configuration information synchronization system of the processor according to any one of claims 1 to 5, and the method includes: Connect the first Type-C interface module corresponding to the first processor and the second Type-C interface module corresponding to the second processor using a Type-C cable; When the second processor is a slave device and receives a configuration information synchronization request, if the plug of the Type-C cable is inserted into the second Type-C interface module, the second processor and the security authentication module in the second Type-C interface module perform bidirectional authentication to obtain an authentication result. When the first processor is the master device, if the authentication result is successful, the configuration information of the first processor is read, and the configuration information is transmitted to the second Type-C interface module through the Type-C cable according to the preset communication protocol; If the authentication result is successful, the second processor receives the configuration information from the second Type-C interface module and updates the configuration information of the second processor according to the received configuration information.

7. An electronic device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes these computer instructions to perform the processor configuration information synchronization method of claim 6.

Images