A multi-level memory lookup method based on hierarchical VMA tree

Abstract

The application relates to a multi-level memory lookup method based on a hierarchical VMA tree, and belongs to the technical field of memory management, and solves the problems of low VMA lookup cache hit rate and long lookup time. The method comprises the following steps: receiving a virtual address read-only request, and obtaining a target virtual address; querying a VMA cache according to the target virtual address; if the target VMA is found, the target VMA is returned; otherwise, the target VMA containing the target virtual address is found in a hierarchical VMA tree; the hierarchical VMA tree is composed of VMA sub-trees in a plurality of page table descriptors distributed according to page table levels; each VMA sub-tree stores VMA segments belonging to an address partition corresponding to each page table descriptor; the VMA cache is updated according to the found target VMA; and the parameters of the VMA cache are dynamically adjusted by monitoring the cache hit rate and the access mode. The memory lookup hit rate and speed are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of memory management technology, and in particular to a multi-level memory lookup method based on a hierarchical VMA tree. Background Technology

[0002] In the Linux kernel memory management subsystem, virtual memory area (VMA) lookup is one of the most frequent operations. Whenever a process experiences a page fault, executes a system call (such as mprotect), or performs a memory permission check, the kernel needs to quickly locate the corresponding virtual memory region based on the given virtual address. With the development of cloud computing and virtualized storage, applications such as containerization, databases, and high-performance computing place even higher demands on memory lookup efficiency.

[0003] The current Linux kernel uses red-black trees or Maple trees to organize all VMAs of a process, supplemented by a single-level cache mmap_cache to speed up lookups. The lookup process is as follows: first, check mmap_cache; if a match is found, return directly; otherwise, traverse the global VMA tree and update the cache with the result.

[0004] However, existing technologies have the following technical problems and drawbacks: First, single-level caches have low hit rates. For example, mmap_cache only caches the most recently accessed VMA entry. For applications with dispersed access patterns (such as large databases, web servers, and browsers), processes may frequently switch between multiple non-adjacent VMAs, causing the cache to be repeatedly overwritten, resulting in low hit rates. Many lookup requests still require traversing the global VMA tree. Second, the size of the global VMA tree is proportional to the number of process mappings (usually hundreds to tens of thousands of nodes). Traversing the global VMA tree is costly, and the tree nodes are not contiguous in memory. The traversal process involves a large number of pointer dereferences, resulting in long hit lookup times. Third, page tables have inherent hierarchical characteristics, while VMA information is stored in an independent, flat global tree, making it impossible to quickly locate the region corresponding to the address range using the hierarchical structure of the page table. Fourth, existing caches use simple single-entry replacement, lacking adaptive capabilities. They cannot adjust cache parameters according to dynamic changes in workload (such as switching from sequential scan to random access), leading to unstable performance. Summary of the Invention

[0005] Based on the above analysis, the embodiments of the present invention aim to provide a multi-level memory lookup method based on a hierarchical VMA tree to solve the problems of low cache hit rate and long lookup time in existing VMA lookup methods.

[0006] This invention provides a multi-level memory lookup method based on a hierarchical VMA tree, comprising the following steps: Receive a read-only request for a virtual address and obtain the target virtual address; The VMA cache is queried based on the target virtual address. If the target VMA is found, it is returned; otherwise, the target VMA containing the target virtual address is searched in the hierarchical VMA tree. The hierarchical VMA tree consists of VMA subtrees within multiple page table descriptors distributed according to the page table hierarchy. Each VMA subtree stores VMA fragments belonging to the address partition corresponding to each page table descriptor. Update the VMA cache based on the found target VMA; The parameters of the VMA cache can be dynamically adjusted by monitoring cache hit rate and access patterns.

[0007] Based on the further improvement of the above method, the virtual address read-only request includes: page fault handling request and VMA lookup request; when the read-only request is a page fault handling request, the target virtual address is the virtual address that triggered the page fault; when the read-only request is a VMA lookup request, the target virtual address is the virtual address passed in the calling parameters.

[0008] Based on further improvements to the above method, the VMA cache includes: an L1 cache for each CPU core and an L2 cache for each process; each VMA entry in the L1 cache stores the address range of the VMA, a pointer to the VMA, a memory descriptor pointer of the process, a process identifier, and an access count; each VMA entry in the L2 cache stores the address range of the VMA and a pointer to the VMA.

[0009] A further improvement to the above method involves querying the VMA cache based on the target virtual address. If the target VMA is found, it is returned, including: Access the L1 cache using the current CPU core number as the index, traverse the VMA entries in the L1 cache. If the process ID of the current process is inconsistent with the process ID in the VMA entry in the L1 cache, skip the VMA entry; otherwise, determine whether the target virtual address is within the address range of the VMA entry. If so, a hit is achieved, increment the access count of the VMA entry, and return the corresponding VMA pointer as the target VMA. If the L1 cache is not hit, the L2 cache is queried. If the L2 cache is hit, the VMA pointer corresponding to the hit VMA entry is returned as the target VMA; otherwise, the result of the L2 cache not being hit is returned.

[0010] Based on the further improvement of the above method, the L2 cache adopts an adaptive replacement cache algorithm to maintain T1 linked list, T2 linked list, B1 linked list and B2 linked list. Among them, T1 linked list and T2 linked list store the address range of VMA and pointers to the VMA; B1 linked list and B2 linked list store the address range hash signature of the evicted VMA entry.

[0011] Based on the above method, in the adaptive replacement cache algorithm, when the target VMA is hit in the B1 linked list, the target capacity of the T1 linked list is updated using the following formula: , When the target VMA is hit in the B2 linked list, the target capacity of the T1 linked list is updated using the following formula: , in, and These represent the target capacities of linked list T1 before and after the update, respectively. and Let B1 and B2 be the entry capacities of their respective linked lists. This represents the total capacity of the L2 cache.

[0012] Based on the further improvement of the above method, each page table descriptor corresponds to a non-overlapping address partition and belongs to a page table level; all page table descriptors are organized in the same global radix tree according to the address range they cover and the page table level they belong to; the key of the global radix tree is obtained by adding the offset of the page table level to which the page table descriptor belongs to the partition index, wherein the partition index is obtained by right-shifting the virtual address in the address partition corresponding to the page table descriptor by the number of bits corresponding to the page table level to which the page table descriptor belongs.

[0013] Based on the above method, a further improvement is made to the hierarchical VMA tree, which searches for the target VMA containing the target virtual address, including: Following the order from the bottom-level page table hierarchy to the top-level page table hierarchy, for each page table hierarchy, the lookup key value is obtained based on the query target and the current page table hierarchy. The corresponding page table descriptor is searched in the global radix tree. In the VMA subtree of the obtained page table descriptor, the starting address of the VMA segment's address range is used as the sort key to find the largest node where the starting address of the VMA segment is less than or equal to the target virtual address. If the target virtual address is less than the ending address of the node, the VMA segment of that node is found and returned; otherwise, the search continues in the next page table hierarchy.

[0014] A further improvement to the above method involves updating the VMA cache based on the found target VMA, including: Insert the target VMA into the L1 cache of the current CPU core. If the L1 cache is full, evict the entry with the smallest access count. At the same time, insert the target VMA into the head of the T1 linked list of the L2 cache. If the length of the T1 linked list exceeds its current target capacity, move the VMA entry at the tail of the T1 linked list to the B1 linked list. If the length of the B1 linked list exceeds the preset limit, evict the VMA entry at the tail of the B1 linked list. If the length of the T2 linked list exceeds its current target capacity, move the VMA entry at the tail of the T2 linked list to the B2 linked list and evict the VMA entry at the tail of the B2 linked list.

[0015] Based on further improvements to the above method, the parameters of the VMA cache include: the capacity of the L1 cache, the capacity of the L2 cache, the prefetch distance of the L2 cache, and the replacement algorithm strategy of the L2 cache.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. First, the VMA cache is queried, and most lookup requests are intercepted. Only when the cache is completely missed will the hierarchical VMA tree be entered for hierarchical backup lookup. This collaborative lookup through the cache and hierarchical VMA tree significantly improves the hit rate and speed of read-only VMA lookup.

[0017] 2. The two-level caching eliminates the overhead of multi-core cache consistency. The L1 cache is maintained independently for each CPU core, with process identifiers stored in the entries. Access does not require locking and the data exclusively occupies the CPU cache line. When processes switch, invalid entries are quickly invalidated by process identifiers, avoiding the frequent cache line synchronization and false sharing problems in traditional shared caches. The L2 cache adopts an adaptive replacement caching algorithm, dynamically balancing recently accessed and frequently accessed data through four linked lists: T1, T2, B1, and B2. It also uses hash signatures in the B1 / B2 ghost linked lists to achieve low-cost historical pattern awareness, which significantly improves cache hit rate and memory efficiency.

[0018] 3. All page table descriptors are organized in the same radix tree according to their address range and level. The key value is generated by right-shifting the address and adding the level offset, which ensures the uniqueness of the key value at different levels. During the search, the key value is calculated level by level from the bottom level and the corresponding page table descriptor is obtained. The search is performed in the VMA subtree with the starting address as the sorting key. Since most VMAs are no larger than 2MB, the search can be completed at the bottom page table level, avoiding the overhead of traversing high-level tree nodes and greatly shortening the search path.

[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Figure 1 This is a flowchart of a multi-level memory lookup method based on a hierarchical VMA tree in an embodiment of the present invention. Detailed Implementation

[0021] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0022] A specific embodiment of the present invention discloses a multi-level memory lookup method based on a hierarchical VMA tree, such as... Figure 1 As shown, it includes steps S1-S4.

[0023] S1. Receive a virtual address read-only request and obtain the target virtual address.

[0024] It should be noted that, in this embodiment, the virtual address read-only request includes: page fault handling request and VMA lookup request; when the read-only request is a page fault handling request, the target virtual address is the virtual address that triggered the page fault; when the read-only request is a VMA lookup request, the target virtual address is the virtual address passed in the calling parameters.

[0025] For example, a VMA lookup request includes: find_vma calls, find_vma_prev calls, find_vma_intersection calls, and other read-only operations in the kernel that require finding the corresponding VMA based on the virtual address.

[0026] S2. Query the VMA cache based on the target virtual address. If the target VMA is found, return the target VMA; otherwise, search for the target VMA containing the target virtual address in the hierarchical VMA tree. The hierarchical VMA tree consists of VMA subtrees within multiple page table descriptors distributed according to the page table hierarchy. Each VMA subtree stores VMA fragments belonging to the address partition corresponding to each page table descriptor.

[0027] In this embodiment, the VMA cache includes: an L1 cache for each CPU core and an L2 cache for each process. The L1 cache stores the most recently accessed VMA entries of the current CPU core and the process identifiers to which each entry belongs. The L2 cache is managed using an adaptive replacement caching algorithm and is used to store process-level VMA entries. This design balances lookup speed and hit rate: the L1 cache has lock-free access and extremely fast response, making it suitable for caching the most frequently accessed VMA entries; the L2 cache has a larger capacity and a more intelligent algorithm, used to accommodate the working set of a process.

[0028] It should be noted that the L1 cache of each CPU core refers to defining an independent data structure (such as per_cpu_vma_cache) as the L1 cache for each CPU core. No locking is required when accessing it, and the data occupies the CPU cache line exclusively, eliminating false sharing and cache consistency overhead.

[0029] The number of VMA entries in the L1 cache of each CPU core is relatively small, such as 4 or 8. Each VMA entry stores the address range of the VMA (including the start address vmstart and end address vmend), a pointer to the VMA, a memory descriptor pointer of the process, the process identifier, and the access count. The VMA address range [vmstart, vmend) is used as the key, and the pointer to the VMA is used as the value. During a search, the target virtual address addr is input; if addr is located within the [vmstart, vmend) range, it is considered a hit.

[0030] This key-value structure allows the L1 cache to quickly determine a hit by simply comparing address ranges, without requiring additional hash calculations or tree traversals.

[0031] Each process's L2 cache is stored in the process's memory structure. Each VMA entry in the L2 cache stores the address range of the VMA and a pointer to the VMA, also using the key-value format described above.

[0032] In this embodiment, the L2 cache is managed using the Adaptive Replacement Cache (ARC) algorithm. The ARC algorithm can dynamically adjust the preference for "Least Recently Used" (LRU) and "Least Frequently Used" (LFU) caches based on the runtime workload characteristics, thereby achieving an optimal balance between sequential scan and random revisit modes.

[0033] It should be noted that the ARC algorithm maintains four linked lists: T1 linked list stores VMA entries that have been accessed only once, sorted by the most recent access time; T2 linked list stores VMA entries that have been accessed at least twice, sorted by the most recent access time; B1 linked list stores the metadata of VMA entries evicted from T1, serving as a ghost list; B2 linked list stores the metadata of VMA entries evicted from T2. That is, B1 and B2 only store the hash signature of the key of the evicted VMA entry, without retaining the VMA pointer, serving as a ghost list.

[0034] set up This is the total capacity of the L2 cache (i.e., the upper limit of the sum of the number of VMA entries in T1 and T2). The target capacity of linked list T1 ( Then the capacity of linked list T2 is... .

[0035] This embodiment describes the parameters. The update method has been improved to better suit the characteristics of the VMA access mode.

[0036] Specifically, when the hit VMA entry is located in B1 (i.e., the entry most recently evicted from T1 is accessed again), the target capacity in the T1 linked list is updated using the following formula.

[0037] , in, and These represent the target capacities of linked list T1 before and after the update, respectively. and These represent the entry capacities of linked lists B1 and B2, respectively.

[0038] The meaning of this formula is: if there are many ghost entries in B1, it indicates that the capacity of T1 may be too small, causing a large number of entries that are only accessed once to be prematurely eliminated. Therefore, the target capacity of the T1 linked list needs to be increased. At the same time, ensure No more than the total capacity .

[0039] When a hit VMA entry is located in B2 (i.e., an entry recently evicted from T2 is accessed again), update the target capacity of the T1 linked list using the following formula.

[0040] .

[0041] The meaning of this formula is: if there are many ghost entries in B2, it means that frequently accessed entries (which should be stored in T2) have been evicted, and it may be necessary to reduce the target capacity of the T1 linked list. This frees up more space for T2; while ensuring Not less than 0.

[0042] When the hit VMA entry is located in T1 or T2: Leave it unchanged, only adjust the position of the entry in the linked list (move it to the head).

[0043] This dynamic adjustment mechanism allows the L2 cache to quickly detect changes in workload. For example, when an application switches from sequential scans (many VMAs accessed only once) to random revisits (few frequently accessed VMAs), the number of B2 hits will increase. The T2 capacity is automatically reduced and increased, thus keeping hot VMAs in the cache for a long time.

[0044] Further, query the VMA cache based on the target virtual address, including: Access the L1 cache (e.g., per_cpu_vma_cache) using the current CPU core number as the index, obtain the process ID of the current process, traverse the VMA entries in the L1 cache, if the process ID of the current process does not match the process ID in the VMA entry in the L1 cache, skip the VMA entry; otherwise, determine if the target virtual address is within the address range of the VMA entry, if so, a hit is found, increment the access count of the VMA entry, and return the corresponding VMA pointer as the target VMA; If the L1 cache misses, the L2 cache is queried. If the L2 cache hits, the VMA pointer corresponding to the hit VMA entry is returned as the target VMA and inserted into the L1 cache; otherwise, the result of the miss is returned.

[0045] The query L2 cache includes: Get the memory descriptor of the current process and retrieve the L2 cache structure from the memory descriptor; search for the VMA entry corresponding to the target virtual address in the L2 cache structure; if a match is found, return the corresponding VMA pointer and insert the VMA into the L1 cache; if the L1 cache is full, evict the entry with the least access count; if a miss is found, return a null pointer, indicating that the cache was not hit, and proceed to step S3.

[0046] The process of finding the VMA entry corresponding to the target virtual address in the L2 cache structure includes: based on the target virtual address, searching for a matching VMA entry in the T1 and T2 linked lists by comparing the address range (i.e., whether the target virtual address is located between the start and end addresses stored in the linked list node); if a match is found in T1 or T2, the matched VMA entry is moved to the head of the linked list and the VMA pointer is returned; if a match is found in B1 or B2 (a ghost hit), the parameters are updated according to the aforementioned formula. The system then removes the hit VMA entry from the ghost list and re-inserts it into T1 or T2 (specifically, inserting into T2 when B1 hits and into T1 when B2 hits), and then returns the VMA pointer obtained from the VMA entry as the target VMA.

[0047] Compared with the prior art, the VMA cache entries in this embodiment use a key-value structure, which makes the cache lookup logic unified and efficient, and easy to implement and maintain; the ARC parameter update formula is dynamically adjusted by using the capacity ratio of B1 and B2, which is more sensitive to sudden changes in workload and facilitates the improvement of hit rate.

[0048] If the target VMA is not found in the VMA cache, proceed to the backup lookup path: search for the target VMA containing the target virtual address in the hierarchical VMA tree.

[0049] It should be noted that this embodiment divides the entire virtual address space into multiple fixed-size address partitions. Each address partition corresponds to a Page Table Descriptor (PTD). The PTD is used not only to manage hardware page tables but also to manage VMA segments within the range of that address partition. Each page table descriptor corresponds to a fixed-size address partition, and the size of the address partition is determined by the page table level to which the page table descriptor belongs. The granularity of each page table level includes: PT level, with a range granularity of 2MB: Each page table descriptor (PTD) covers 2MB of virtual address space (corresponding to 512 4KB pages). In this embodiment, considering that most VMA management intervals are less than 2MB, the preset range granularity is 2MB, that is, the default page table level is the PT level. PMD level, with a granularity of 1GB: each page table descriptor (PTD) covers 1GB of virtual address space (corresponding to 512 2MB blocks); suitable for very large memory mapping, reducing the number of PTDs; PUD hierarchy with a granular range of 512GB: each page table descriptor (PTD) covers a 512GB virtual address space; suitable for large memory, low concurrency scenarios; PGD ​​level, with a granularity of 256TB: each page table descriptor (PTD) covers the entire process address space; only used in extreme cases.

[0050] In other words, each page table descriptor corresponds to a non-overlapping address partition and belongs to a page table level; within the same page table level, all address partitions are the same size; however, the address partition sizes differ between different levels.

[0051] Each page table descriptor contains the following key fields: `vma_tree`, the root node of the VMA subtree, storing all VMA segments belonging to the address partition corresponding to the current PTD, sorted by the starting virtual address of the VMA; `level`, used to record the page table level (PT / PMD / PUD / PGD) corresponding to the page table descriptor; `ptd_flags`, descriptor status flags, unsigned long integers, including: active status flag (the PTD is in use), dirty status flag (the VMA or page table within the PTD has been modified and may need to be written back or refreshed), or locked status flag (whether the PTD is currently locked by a range lock); `vma_list`, the head of a doubly linked list of VMA segments, used to link all VMA segments within the address partition for easy traversal operations (e.g., batch release of VMA when a process exits); `vma_count`, the number of VMA segments; and `access_count`, used to record the number of times the address partition has been accessed, which can be used for statistics or adaptive optimization.

[0052] All page table descriptors at different page table levels are organized in the same global radix tree according to the address range they cover and the page table level they belong to. The key of each page table descriptor in the radix tree is obtained by adding the offset of the page table level to which the page table descriptor belongs to the partition index. The partition index is obtained by right-shifting the virtual address within the address partition corresponding to the page table descriptor by the number of bits corresponding to the page table level to which the page table descriptor belongs, as shown in the formula below: , in, The key of the page table descriptor in the radix tree. It can be any virtual address of the address partition corresponding to the page table descriptor; and They are shift right and shift left, respectively; This is the offset at the page table level. The bit width of the virtual address, such as 48 bits or 57 bits actually used in a 64-bit system, is used to ensure that the page table identifiers of different page table levels have non-overlapping key ranges in the radix tree. The page table level to which the page table descriptor belongs. The corresponding bit widths are as follows: PT level has 21 bits, PMD level has 30 bits, PUD level has 39 bits, and PGD level is determined based on the virtual address width.

[0053] This embodiment uses a design that requires only one radix tree to index page table descriptors at all page table levels.

[0054] It should be noted that the hierarchical VMA tree consists of multiple VMA subtrees distributed according to the page table hierarchy, and is constructed in the following way: A red-black tree is allocated as the VMA subtree for each page table descriptor, with an average of only 10-20 nodes. The VMA subtree stores VMA segments belonging to the address partition corresponding to that page table descriptor; page table descriptors of different page table levels (PGD, PUD, PMD, PT) are organized into a hierarchical structure according to the address range they cover. Each VMA segment (vma_segment) embeds a standard VMA structure (vm_area_struct) as its first member, facilitating its transfer to other kernel modules without modifying existing interfaces. Through zero-overhead macro conversion, it is compatible with existing VMA operation interfaces. The VMA segment also includes a pointer to its parent page table descriptor, the node structure of the VMA segment in the VMA subtree, and its storage level.

[0055] VMA fragments automatically select their storage level based on the address range they cover: if the address range does not cross the 2MB boundary (i.e., the start and end addresses belong to the same 2MB block), the VMA fragment is stored in the VMA subtree of the page table descriptor in the PT layer; if it does not cross the 1GB boundary, it is stored in the PMD layer; if it does not cross the 512GB boundary, it is stored in the PUD layer; otherwise, it is stored in the PGD layer. This strategy of automatically selecting the storage level based on address range boundaries ensures that 90% of small VMAs (≤2MB) are stored in the VMA subtree of the PT layer, 8% of medium VMAs (2MB~1GB) are stored in the VMA subtree of the PMD layer, and 2% of large VMAs (above 1GB) are stored in higher-level VMA subtrees, forming a logically hierarchical VMA tree. This hierarchical storage allows for searching from the bottom up, leveraging the high proportion of small VMAs for rapid hits and extremely high search efficiency.

[0056] Specifically, first, the start address newstart and end address newend are obtained based on the address range of the VMA segment. Then, the start address (newstart) and end address are decremented by one (newend-1) and shifted right by 21 bits (because the number of bits corresponding to 2MB is 21), resulting in two indices at the PT level. If the two indices at the PT level are equal, it means that the VMA to be inserted does not cross the 2MB boundary, and the PT level is selected as the storage level. If the two indexes at the PT level are not equal, the start address (newstart) and end address (newend-1) are decremented by one and shifted right by 30 bits respectively to obtain the two indexes at the PMD level. If the two indexes at the PMD level are equal, it means that the VMA to be inserted has not crossed the 1GB boundary, and the PMD level is selected as the storage level. If the two indexes at the PMD level are not equal, the start address (newstart) and end address are decremented by one (newend-1) and shifted right by 39 bits respectively to obtain the two indexes at the PUD level. If the two indexes at the PUD level are equal, it means that the VMA to be inserted has not crossed the 512GB boundary, and the PUD level is selected as the storage level. Otherwise, select the PGD level as the storage level.

[0057] Further, the target VMA containing the target virtual address is located in the hierarchical VMA tree, including: Following the order from the lowest page table level to the highest (PT level → PMD level → PUD level → PGD level), for each page table level, the lookup key is obtained based on the query target and the current page table level. The corresponding page table descriptor is then searched in the global radix tree. In the VMA subtree of the obtained page table descriptor, the starting address of the VMA fragment's address range is used as the sort key to find the largest node whose starting address is less than or equal to the target virtual address. If the target virtual address is less than the ending address of this node, a match is found, and the VMA fragment of that node is returned; otherwise, the search continues to the next page table level. If the target virtual address is not found after traversing all page table levels, NULL is returned, triggering an error message.

[0058] Since the vast majority of VMAs are no larger than 2MB, lookup operations can usually return at the PT level. For example, in a typical scenario, 90% of VMAs are no larger than 2MB, and the average lookup level is only 1.12 levels (1.12 times = 1×90% + 2×8% + 3×2% + 4×0%), which significantly shortens the lookup path compared to the traditional global VMA tree.

[0059] It should be noted that read-only lookup operations can ensure the concurrency safety of the data structure through the RCU (Read-Copy-Update) mechanism, and the hierarchical VMA tree itself will not change during the lookup process (write operations are protected by other paths).

[0060] S3. Update the VMA cache based on the found target VMA.

[0061] It should be noted that after successfully finding the target VMA from the hierarchical VMA tree, the target VMA needs to be backfilled into the VMA cache to improve the hit rate of subsequent searches.

[0062] Specifically, the target VMA is inserted into the L1 cache of the current CPU core and the L2 cache of the current process; where: When inserting into the L1 cache, the LFU cache eviction policy is adopted, that is, if the L1 cache is full, the VMA entry with the fewest access counts is evicted; the key of the inserted VMA entry is the start virtual address and end virtual address of the target VMA, and the value is a VMA pointer. When inserting into the L2 cache, the operation is performed according to the ARC algorithm, including: inserting the target VMA at the head of the T1 linked list; if the length of the T1 linked list exceeds its current target capacity. If the length of the T1 linked list exceeds the preset limit, then the VMA entry at the end of the B1 linked list is discarded; if the length of the T2 linked list exceeds its current target capacity... If so, move the VMA entry at the end of T2 to the B2 linked list and discard the VMA entry at the end of B2.

[0063] After backfilling is completed, subsequent lookup requests for the same or adjacent addresses will have a high probability of hitting the cache directly, thus avoiding entering the hierarchical VMA tree.

[0064] S4. Dynamically adjust the parameters of the VMA cache by monitoring cache hit rate and access mode.

[0065] This embodiment dynamically adjusts various parameters of the VMA cache by monitoring cache hit rate and access patterns. This adaptive optimization mechanism is triggered as a background task or timer, independent of each lookup operation.

[0066] The parameters of the VMA cache include: L1 cache capacity, L2 cache capacity, L2 cache prefetch distance, and L2 cache replacement algorithm strategy (ARC / MRU).

[0067] Specifically, dynamically adjusting the L1 cache capacity includes: If the L1 cache hit rate remains below the preset minimum hit rate threshold, such as 30%, it indicates that the current L1 cache capacity is insufficient to accommodate hot VMAs. In this case, the L1 cache capacity is automatically increased, up to a maximum of 8 entries. Conversely, if the L2 cache hit rate is higher than the preset maximum hit rate threshold, such as 80%, and the L1 cache capacity has not yet reached its minimum value, it indicates that the L1 cache is redundant. The L1 cache capacity is appropriately reduced to save memory, down to a minimum of 4 entries. Increasing or decreasing the L1 cache capacity is achieved by reallocating the cache array for each CPU core and migrating the original entries to the new array.

[0068] Dynamically adjust the L2 cache size, including: If the L2 cache hit rate remains below the preset minimum hit rate threshold, and the VMA tree lookup latency after a miss is higher than the preset latency threshold (e.g., 500 nanoseconds, or more than 1.5 times the historical average latency), the L2 cache capacity will be automatically increased. This includes: reallocating a larger cache space, migrating existing cached VMA entries to the new space, and updating the total capacity parameter c (e.g., increasing by 50% or doubling it). At the same time, the target capacity of the parameter T1 linked list will be adjusted proportionally to maintain the relative ratio of T1 and T2.

[0069] The dynamic adjustment of the L2 cache prefetch distance is determined by analyzing the address sequence of memory access requests to identify the access patterns of the current workload, including: When the virtual addresses of multiple consecutive memory access requests increase linearly (e.g., each time by a page size of 4KB) without significant backswings, it is determined to be a sequential access pattern. This pattern is common in scenarios such as large file reading and array traversal. In sequential access mode, spatial locality is very pronounced; the address following the current accessed address is highly likely to be accessed later. In this case, increasing the prefetch distance (e.g., setting it to 4) means preloading the four VMA entries following the target VMA into the L2 cache. When multiple consecutive memory access requests exhibit jumps in virtual addresses, with large and unpredictable differences between adjacent accesses, and a persistently low cache hit rate, it is identified as random access mode. This mode is commonly seen in scenarios such as pointer chasing and hash table traversal. In random access mode, prefetching is often ineffective or even wastes cache space. In this case, the prefetch distance can be set to 0 (disable prefetching) or 1 (do not perform additional prefetching).

[0070] The dynamic adjustment of the L2 cache replacement algorithm strategy is determined by simultaneously monitoring access patterns and L2 cache efficiency indices, including: When the efficiency index of the L2 cache is below 0.5, it indicates that the current caching strategy is not effective. At this time, regardless of the access mode, the L2 cache replacement strategy should be forcibly switched to the ARC algorithm, and access mode-based strategy switching should be temporarily disabled until the efficiency index recovers to above 0.5. When the efficiency index of the L2 cache is within the normal range (≥0.5), the strategy is further dynamically adjusted based on the access pattern: if a sequential access pattern is detected (multiple consecutive virtual addresses linearly increasing), the replacement strategy is temporarily switched to MRU (Most Recently Used), because newer entries in a sequential scan are less likely to be accessed again, and MRU can more promptly evict older entries; if a random access pattern is detected (address jumping and low hit rate), the algorithm is switched back to ARC to balance recent and frequent accesses. When the access pattern changes again, the strategy switches accordingly, but once the efficiency index drops below the threshold, ARC intervenes first and overrides any pattern-driven switch. Through this hierarchical decision-making, the caching strategy is made adaptable to the workload, while avoiding the continuous use of suboptimal strategies due to pattern misjudgment when efficiency is low.

[0071] In this embodiment, the efficiency index = (L2 cache hit rate × average saved latency) / total overhead, where average saved latency refers to the average time saved by accessing the hierarchical VMA tree when the L2 cache hit is compared to when the L2 cache miss is missed, and total overhead refers to the average time for performing L2 cache lookups (including hits and misses).

[0072] Preferably, to ensure compatibility with different kernel versions, the method in this embodiment determines whether to enable multi-level memory lookup during Linux system startup using kernel startup parameters (such as vma_cache=on / off). When enabled, the VMA multi-level cache and hierarchical VMA tree of this embodiment are used for VMA lookup; when disabled, the Linux system falls back to the traditional kernel VMA lookup path (such as red-black tree or Maple tree).

[0073] Compared with existing technologies, this embodiment provides a multi-level memory lookup method based on a hierarchical VMA tree. First, it queries the VMA cache, intercepting most lookup requests. Only when the cache is completely missed does it enter the hierarchical VMA tree for layered backup lookup. This collaborative lookup using the cache and hierarchical VMA tree significantly improves the hit rate and speed of read-only VMA lookups. The two-level cache eliminates multi-core cache consistency overhead. The L1 cache is maintained independently for each CPU core, storing process identifiers in entries. Access requires no locking, and data exclusively occupies the CPU cache line. When processes switch, invalid entries are quickly invalidated using the process identifier, avoiding frequent cache line synchronization and false sharing problems found in traditional shared caches. The L2 cache employs an adaptive replacement cache algorithm, dynamically balancing recently accessed and frequently accessed data through four linked lists (T1, T2, B1, B2), and utilizing hash signatures in the B1 / B2 ghost lists to achieve low-cost historical pattern awareness, significantly improving cache hit rate and memory efficiency. All page table descriptors are organized in the same radix tree according to their address range and level. The key value is generated by right-shifting the address and adding the level offset, which ensures the uniqueness of the key value at different levels. During the search, the key value is calculated level by level from the bottom level and the corresponding page table descriptor is obtained. The search is performed in the VMA subtree with the starting address as the sorting key. Since most VMAs are no more than 2MB in size, the search can be completed at the bottom page table level, avoiding the overhead of traversing high-level tree nodes and greatly shortening the search path.

[0074] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0075] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-level memory lookup method based on hierarchical VMA tree, characterized in that, Includes the following steps: Receive a read-only request for a virtual address and obtain the target virtual address; The VMA cache is queried based on the target virtual address. If the target VMA is found, it is returned. Otherwise, the target VMA containing the target virtual address is searched in the hierarchical VMA tree. The hierarchical VMA tree consists of VMA subtrees in multiple page table descriptors distributed according to the page table hierarchy. Each VMA subtree stores VMA fragments belonging to the address partition corresponding to each page table descriptor. Update the VMA cache based on the found target VMA; The parameters of the VMA cache can be dynamically adjusted by monitoring cache hit rate and access patterns.

2. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 1, characterized in that, The virtual address read-only request includes: a page fault handling request and a VMA lookup request; when the read-only request is a page fault handling request, the target virtual address is the virtual address that triggered the page fault; when the read-only request is a VMA lookup request, the target virtual address is the virtual address passed in the calling parameters.

3. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 1, characterized in that, The VMA cache includes: an L1 cache for each CPU core and an L2 cache for each process; each VMA entry in the L1 cache stores the address range of the VMA, a pointer to the VMA, a memory descriptor pointer of the process, a process identifier, and an access count; each VMA entry in the L2 cache stores the address range of the VMA and a pointer to the VMA.

4. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 3, characterized in that, The step of querying the VMA cache based on the target virtual address, and returning the target VMA if it is found, includes: Access the L1 cache using the current CPU core number as the index, traverse the VMA entries in the L1 cache. If the process ID of the current process is inconsistent with the process ID in the VMA entry in the L1 cache, skip the VMA entry; otherwise, determine whether the target virtual address is within the address range of the VMA entry. If so, a hit is found, increment the access count of the VMA entry, and return the corresponding VMA pointer as the target VMA. If the L1 cache is not hit, the L2 cache is queried. If the L2 cache is hit, the VMA pointer corresponding to the hit VMA entry is returned as the target VMA; otherwise, the result of the L2 cache not being hit is returned.

5. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 3, characterized in that, The L2 cache employs an adaptive replacement cache algorithm, maintaining T1, T2, B1, and B2 linked lists. T1 and T2 linked lists store the address range of VMAs and pointers to those VMAs; B1 and B2 linked lists store the address range hash signatures of evicted VMA entries.

6. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 5, characterized in that, In the adaptive replacement cache algorithm, when the target VMA is hit in the B1 linked list, the target capacity of the T1 linked list is updated using the following formula: ， When the target VMA is hit in the B2 linked list, the target capacity of the T1 linked list is updated using the following formula: ， in, and These represent the target capacities of linked list T1 before and after the update, respectively. and Let B1 and B2 be the entry capacities of linked lists respectively. This represents the total capacity of the L2 cache.

7. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 1, characterized in that, Each page table descriptor corresponds to a non-overlapping address partition and belongs to a page table level; all page table descriptors are organized in the same global radix tree according to the address range they cover and the page table level they belong to. The key of the global radix tree is obtained by adding the offset of the page table level to which the page table descriptor belongs to the partition index. The partition index is obtained by right-shifting the virtual address within the address partition corresponding to the page table descriptor by the number of bits corresponding to the page table level to which the page table descriptor belongs.

8. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 7, characterized in that, The step of searching for the target VMA containing the target virtual address in the hierarchical VMA tree includes: Following the order from the bottom-level page table hierarchy to the top-level page table hierarchy, for each page table hierarchy, the lookup key value is obtained based on the query target and the current page table hierarchy. The corresponding page table descriptor is searched in the global radix tree. In the VMA subtree of the obtained page table descriptor, the starting address of the VMA segment's address range is used as the sort key to find the largest node where the starting address of the VMA segment is less than or equal to the target virtual address. If the target virtual address is less than the ending address of the node, the VMA segment of that node is found and returned; otherwise, the search continues in the next page table hierarchy.

9. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 5, characterized in that, The step of updating the VMA cache based on the found target VMA includes: Insert the target VMA into the L1 cache of the current CPU core. If the L1 cache is full, evict the entry with the smallest access count. At the same time, insert the target VMA into the head of the T1 linked list of the L2 cache. If the length of the T1 linked list exceeds its current target capacity, move the VMA entry at the tail of the T1 linked list to the B1 linked list. If the length of the B1 linked list exceeds the preset limit, evict the VMA entry at the tail of the B1 linked list. If the length of the T2 linked list exceeds its current target capacity, move the VMA entry at the tail of the T2 linked list to the B2 linked list and evict the VMA entry at the tail of the B2 linked list.

10. The multi-level memory lookup method based on a hierarchical VMA tree according to claim 5, characterized in that, The parameters of the VMA cache include: the capacity of the L1 cache, the capacity of the L2 cache, the prefetch distance of the L2 cache, and the replacement algorithm strategy of the L2 cache.

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