Wafer defect training-free detection method based on frozen dino multi-granularity hierarchical pca subspace

Abstract

The wafer defect training-free detection method based on the frozen DINO multi-granularity hierarchical PCA subspace of the application belongs to the field of image processing. First, the center coordinates of each single chip on the wafer are calculated, and the single-chip region of interest is cropped; the single-chip region of interest image is input into the pre-trained DINO self-supervised large model with completely frozen weights to extract deep features; a three-level multi-granularity sliding window mechanism is introduced to decouple the deep features into local feature vectors covering different spatial scales; relying on a small amount of normal single chips, the PCA normal subspace projection matrix of each local feature is hierarchically constructed, the reconstruction residual of the to-be-tested single-chip image is calculated and weighted fusion is performed to generate the comprehensive abnormal score of the single chip; based on the statistical 3σ threshold rule, the automatic defect determination is completed, and the online adaptive update of the subspace projection matrix is realized through the incremental PCA mechanism, without the need to stop and retrain to adapt to the process drift of the production line.

Description

Technical Field

[0001] This invention belongs to the field of image processing and computer vision technology, and relates to a training-free method for wafer defect detection based on frozen DINO multi-granularity hierarchical PCA subspace. Background Technology

[0002] Wafer chips are the core product of semiconductor manufacturing, and their quality directly determines the performance and reliability of integrated circuits. Wafer fabrication involves multiple complex processes such as photolithography, etching, deposition, and polishing. During production, various defects such as particle contamination, scratches, and pattern breakage are easily generated. Therefore, efficient and accurate defect detection of each chip unit on the wafer before chip packaging is crucial for improving yield, reducing costs, and ensuring product quality.

[0003] Currently, in the field of automated wafer defect detection, the following three methods are mainly used for defect detection: traditional image processing methods based on fixed thresholds, deep learning defect detection methods based on convolutional neural networks (CNNs), and machine learning defect detection methods based on deep forests.

[0004] Traditional image processing methods based on fixed thresholds rely on numerous manually set parameter thresholds to identify defects using techniques such as Sobel edge detection, Canny operators, and template matching. Under complex lighting conditions and varying surface textures, their detection accuracy is unstable, their robustness is poor, and their detection rate for minute and low-contrast defects is insufficient.

[0005] Deep learning-based defect detection methods using convolutional neural networks achieve defect classification and localization through end-to-end training. They have achieved good results in some scenarios. However, they have the following significant limitations: they require a large number of labeled samples (including various defect samples and normal samples) for training, while defect samples are scarce and their distribution is extremely uneven in actual semiconductor production lines; they rely on high-performance GPU computing hardware for model training and inference; and the model training cycle is long, making it unable to quickly adapt to changes in production line processes.

[0006] Machine learning-based defect detection methods based on Deep Forest do not rely on the backpropagation mechanism of traditional neural networks. Instead, they employ multi-granularity scanning and cascaded forest structures for feature learning and classification. Although the training sample size requirement is relatively lower than that of CNNs, supervised training still requires both normal (OK) and defective (NG) labeled samples for supervision. Furthermore, manually designed features (HOG, LBP, GLCM, etc.) have limited representation capabilities for complex defects, and the increased number of cascaded layers leads to longer inference times.

[0007] Given the shortcomings of the existing technologies, there is an urgent need for a wafer defect detection method that requires no large number of labeled samples, no GPU-intensive training, high computational efficiency, and high detection accuracy. Summary of the Invention

[0008] To address the aforementioned technical problems, the present invention aims to provide a wafer defect detection method without training based on a frozen DINO multi-granularity hierarchical PCA subspace. This method aims to solve the technical challenges of traditional wafer defect detection methods, such as heavy reliance on large-scale defect annotation samples, high computational resource consumption, poor characterization capability of small defects, and difficulty in adapting to production line process drift.

[0009] This invention provides a training-free wafer defect detection method based on frozen DINO multi-granularity hierarchical PCA subspace, comprising:

[0010] Step 1: Obtain the original wafer image to be inspected, calculate the center coordinates of each single chip on the wafer, crop out the region of interest image of each single chip, and uniformly scale it to the preset bilinear interpolation resolution.

[0011] Step 2: After completely freezing all network weights of the pre-trained DINO self-supervised large model, perform deep feature extraction on the scaled region of interest images of each single chip.

[0012] Step 3: Set a sliding window with three spatial scales for the extracted depth features to decouple the depth features into local feature vectors with multi-scale local perception capabilities;

[0013] Step 4: Acquire normal single-chip images, perform steps 2 and 3 to extract all local feature vectors at each spatial scale, and construct feature matrices at each spatial scale; perform principal component analysis to construct normal subspace projection matrices at each spatial scale.

[0014] Step 5: Project the local feature vectors of each spatial scale extracted in Step 3 onto the corresponding normal subspace, calculate the reconstruction residuals of all local feature vectors at each spatial scale and aggregate them within the scale to obtain three scale-independent defect scores. Perform weighted fusion of multi-scale defect scores to calculate the comprehensive anomaly score of each single chip.

[0015] Step 6: Using the same method as in Step 5, calculate the comprehensive anomaly score of each chip in the normal wafer image acquired in Step 4, and calculate its mathematical expectation and standard deviation. Based on the mathematical expectation and standard deviation, calculate the defect judgment threshold of each chip. Compare the comprehensive anomaly score of the chip in the wafer to be inspected with the defect judgment threshold to determine whether the chip has a defect.

[0016] Step 7: Summarize all single-chip judgment results. If the proportion of defective single chips exceeds 5%, the wafer is judged to be defective.

[0017] Step 8: For single chips that are determined to be normal online, use the incremental PCA algorithm to dynamically update their projection matrix at each spatial scale.

[0018] The wafer defect detection method without training based on frozen DINO multi-granularity hierarchical PCA subspace of the present invention has the following beneficial effects:

[0019] (1) Completely training-free. The DINO self-supervised large model remains frozen, and the PCA subspace can be constructed with only a small number of normal samples' feature matrix decomposition. There is no network training, no gradient backpropagation, and no loss function optimization throughout the process, which greatly reduces the deployment threshold and computational resource requirements. Compared with CNN methods that require GPU training, the deployment cost is reduced by more than 90%; compared with deep forest methods that require supervised training, no defective sample labeling is required.

[0020] (2) Small sample / single class learning. Only a small number of normal (OK) chip samples (50-200 samples recommended) are needed to build a complete detection system. There is no need to collect and label defect samples, which fundamentally solves the core pain point of scarce defect samples and extremely uneven distribution of categories in semiconductor production lines.

[0021] (3) High robustness and detection rate. DINO's self-supervised pre-trained features are inherently robust to illumination changes, texture differences, and imaging noise; the statistical properties of the PCA subspace effectively suppress random noise interference. Under the same test conditions, the F1 score and AUC of the method of this invention are superior to traditional handmade feature methods and single-class SVM methods.

[0022] (4) High interpretability. The residuals reconstructed from features can be back-mapped to the original image space, intuitively locating the defect area and providing process engineers with a clear basis for defect root cause analysis. The contribution of the residuals at each granularity can be displayed independently, realizing interpretable analysis of defects at multiple scales.

[0023] (5) Computationally efficient. The inference process consists of only a single DINO forward propagation and PCA matrix projection, with single-chip inference time in the millisecond range, making it suitable for real-time online detection. No GPU cluster training is required, and it can be deployed on edge computing devices.

[0024] (6) Incremental Adaptive. Through the incremental PCA mechanism, the system can continuously absorb new normal samples from the production line and automatically adapt to process drift, equipment aging and changes in raw material batches, so as to realize the online continuous evolution of the detection system and avoid the high cost of periodic retraining. Attached Figure Description

[0025] Figure 1This is a flowchart of the wafer defect detection method without training based on the frozen DINO multi-grained layered PCA subspace of the present invention. Detailed Implementation

[0026] like Figure 1 As shown, the wafer defect training-free detection method based on frozen DINO multi-granularity hierarchical PCA subspace of the present invention includes:

[0027] Step 1: Acquire the original wafer image to be inspected, calculate the center coordinates of each chip on the wafer, crop out the region of interest image of each chip, and uniformly scale it to a preset bilinear interpolation resolution, specifically:

[0028] Step 1.1: Obtain the original wafer image to be inspected, and calculate the theoretical center coordinates of each single chip on the wafer based on the wafer layout parameters; the wafer layout parameters include the number of rows and columns of the chip array, the chip spacing, and the size of a single chip.

[0029] Assuming a single chip on a wafer is... OK If the column array is distributed in a grid, then the first... line, number Theoretical center coordinates of a single chip for:

[0030]

[0031]

[0032] In the formula, The starting reference point is the center coordinate of the chip. and These represent the horizontal and vertical chip arrangement spacing, respectively. .

[0033] Step 1.2: Eliminate translation and rotation residuals caused by mechanical positioning through geometric correction and registration, and calculate the center coordinates after correction and registration, specifically as follows:

[0034] Step 1.2.1: Calculate the rotation deviation angle and translation correction amount using the phase correlation method or key point matching.

[0035] Step 1.2.2: Calculate the center coordinates of the single chip after calibration and registration according to the following formula. :

[0036]

[0037] In the formula, The rotation center point of the entire wafer image, The rotational deviation angle, This is the translation correction amount.

[0038] Step 1.3: Based on the corrected and registered center coordinates and the size of each chip, crop the region of interest image of each chip from the whole wafer image.

[0039] Step 1.4: Scale the region of interest images of all single chips to a preset bilinear interpolation resolution of 224×224 pixels.

[0040] Step 2: After completely freezing all network weights of the pre-trained DINO self-supervised large model, deep feature extraction is performed on the scaled region of interest images of each single chip, specifically:

[0041] Step 2.1: Introduce the pre-trained ViT architecture DINO self-supervised large model, freeze all network weights of the model, and do not perform backpropagation operations in the subsequent process.

[0042] In practical implementation, either the ViT-S / 16 architecture DINO self-supervised large model or the ViT-B / 16 architecture DINO self-supervised large model can be used.

[0043] Step 2.2: Input the scaled region of interest images of each single chip into the frozen DINO self-supervised large model, and divide it into multiple non-overlapping image blocks through forward propagation of the visual Transformer.

[0044] Step 2.3: Extract the depth feature matrix output from the last Transformer Block layer. , where N is the number of image patches and D is the feature dimension.

[0045] Step 3: Set a three-level spatial scale sliding window for the extracted depth features to decouple the depth features into local feature vectors with multi-scale local perception capabilities, specifically:

[0046] Step 3.1: Set a sliding window with three spatial scales (fine-grained, medium-grained, and coarse-grained) for the extracted depth feature matrix, as follows:

[0047] A fine-grained window with a size of 32×32px and a step size of 16px is used to detect tiny particle contamination, minor scratches, and pinhole defects.

[0048] A medium-grained window with a size of 64×64px and a step size of 32px is used to detect local breaks, pattern anomalies, and moderate scratches.

[0049] A coarse-grained window with a size of 128×128px and a step size of 64px is used to detect large-area defects, global deformations, and structural defects.

[0050] Step 3.2: Decouple the deep features into three sets of local feature vectors with multi-scale local perception capabilities through fine-grained windows, medium-grained windows, and coarse-grained windows:

[0051] , , ;

[0052] in, It is a set of fine-grained local feature vectors. This is the Mth fine-grained local feature vector; It is a set of medium-granularity local feature vectors. This is the Nth medium-granularity local feature vector; It is a set of coarse-grained local feature vectors. Let Q be the Qth coarse-grained local feature vector.

[0053] Step 4: Acquire normal single-chip images, perform steps 2 and 3 to extract all local feature vectors at each spatial scale, and construct feature matrices at each spatial scale; perform principal component analysis to construct normal subspace projection matrices at each spatial scale, specifically:

[0054] Step 4.1: Collect 50 to 200 known normal single-chip images.

[0055] Step 4.2: Extract depth features from normal single-chip images using a pre-trained DINO self-supervised large model with frozen weights.

[0056] Step 4.3: Using the same method as in Step 3, extract multiple local feature vectors at various spatial scales from the region of interest image of a normal single chip. The feature matrix at that spatial scale is constructed from multiple local feature vectors at the same spatial scale from multiple normal single chip images. :

[0057]

[0058] in, Represents all local feature vectors of the region of interest image of the h-th single chip at a certain spatial scale; H is the number of normal region of interest images of a single chip.

[0059]

[0060] in, Let d be the local feature vector of the h-th single-chip region of interest at a certain spatial scale; Mg is the total number of local feature vectors at that spatial scale.

[0061] Step 4.4: Calculate the global mean vector of all local feature vectors. :

[0062]

[0063] feature matrix Subtract the mean vector from each local feature vector in the equation. The centered feature matrix is ​​obtained. :

[0064]

[0065] in, It is a column vector whose elements are all 1s.

[0066] Step 4.5: Construct the covariance matrix :

[0067]

[0068] For covariance matrix Perform eigenvalue decomposition:

[0069]

[0070] in, It is a diagonal matrix of eigenvalues ​​sorted in descending order, and the eigenvalues ​​satisfy... ; For the corresponding orthogonal eigenvector matrix, each column vector It represents the direction of an orthogonal principal component in a high-dimensional space.

[0071] Step 4.6: Set the cumulative variance contribution rate threshold. Used to determine the retained principal component dimensions :

[0072]

[0073] Before truncation The eigenvector columns corresponding to the largest eigenvalues ​​are concatenated column by column to obtain the normal subspace projection matrix. Closed-form calculation formula:

[0074]

[0075] in, P1 represents the projection matrix at the fine-grained spatial scale, P2 represents the projection matrix at the medium-grained spatial scale, and P3 represents the projection matrix at the coarse-grained spatial scale.

[0076] Step 5: Project the local feature vectors extracted in Step 3 at each spatial scale onto the corresponding normal subspace, calculate the reconstruction residuals of all local feature vectors at each spatial scale, and aggregate them within the scale to obtain three scale-independent defect scores. Perform weighted fusion of the multi-scale defect scores to calculate the comprehensive anomaly score for each single chip, specifically:

[0077] Step 5.1: For the region of interest image of each single chip, calculate the reconstruction residuals of all local features at the three spatial scales:

[0078]

[0079]

[0080]

[0081] in, The residual of the reconstructed local feature vectors of the region of interest image of a single chip at a fine-grained scale; The reconstruction residual of the local feature vectors of the region of interest image of a single chip at a medium granularity; This represents the reconstruction residual of the local feature vectors of the region of interest image on a single chip at a coarse-grained scale.

[0082] Step 5.2: Employ the Top-K mean strategy to extract the top-K mean values ​​at each spatial scale. The mean of the maximum reconstruction residuals is used to aggregate the reconstruction residuals of the local feature vectors at this spatial scale, resulting in three scale-independent defect scores:

[0083]

[0084]

[0085]

[0086] in, This represents the defect score at a finer-grained scale. This represents the defect score at the medium-grained scale. This represents the defect score at the coarse-grained scale.

[0087] Step 5.3: Calculate the final comprehensive anomaly score for the single chip using a weighted fusion strategy based on the defect scores at each scale.

[0088]

[0089] in, For the adaptive adjustment of weighting coefficients, and By using multi-scale fusion, the feature scores of defects of different sizes can all obtain effective gains from a global perspective.

[0090] Step 6: Using the same method as in Step 5, calculate the comprehensive anomaly score of each chip in the normal wafer image acquired in Step 4, and calculate its expected value and standard deviation. Based on the expected value and standard deviation, calculate the defect judgment threshold for each chip. Compare the comprehensive anomaly score of the chip in the wafer to be inspected with the defect judgment threshold to determine whether the chip has a defect. Specifically:

[0091] Step 6.1: Calculate the comprehensive anomaly score of each single chip in the normal wafer image acquired in Step 4 using the same method as in Step 5, and calculate its expected value. and standard deviation .

[0092] Step 6.2: Calculate the defect decision threshold for each single chip based on mathematical expectation and standard deviation. :

[0093]

[0094] Step 6.3: Assess the overall anomaly score of the single chip in the wafer under inspection. Compare with the defect decision threshold T: If If so, then the single chip is considered to be normal; if If so, the single chip is determined to be defective.

[0095] Step 7: Summarize all single-chip judgment results. If the proportion of defective single chips exceeds 5%, the wafer is judged to be defective.

[0096] Step 8: For single chips that are determined to be normal online, the incremental PCA algorithm is used to dynamically update their projection matrix at each spatial scale, specifically as follows:

[0097] Step 8.1: Recursive update formula for the global mean vector.

[0098] Let the old global mean vector be... When the buffer is full When the online determination of the number of single chips is normal, the same method as in step 4.3 is used to construct... Feature matrix of a single chip , The mean vector is:

[0099]

[0100] in, The c-th image is a local feature vector of a single chip that is determined to be normal online. The total number of all local feature vectors added to the single chip; the updated global mean vector. for:

[0101]

[0102] Step 8.2: Assume the old feature subspace contains the previous one. There are principal components, and their projection matrices are: The corresponding eigenvalue diagonal matrix is .

[0103] The newly added Centering each normal chip using the old mean yields the centered feature matrix of the normal chips. :

[0104]

[0105] Will Projecting onto the existing subspace yields the coordinate matrix within the existing subspace. Residual matrix of orthogonal complement space :

[0106]

[0107]

[0108] For the residual matrix Perform QR decomposition to extract the new directional basis of the orthogonal complement space. :

[0109]

[0110] in, It is an orthogonal matrix. It is an upper triangular matrix; the updated total basis of the subspace is written in matrix concatenation form. .

[0111] Step 8.3: Low-order equivalent matrix of the core covariance evolution relation The structure is as follows:

[0112]

[0113]

[0114] in, It is a left singular vector matrix. It is a singular value diagonal matrix. The transpose of the right singular vector matrix; truncation Center front The column vector corresponding to the largest singular values Calculate the updated projection matrix:

[0115]

[0116] Update the eigenvalue diagonal matrix to the newly solved front One singular value: .

[0117] In practice, the incremental PCA update is triggered when 50 new single chips are added to the wafer and confirmed to be normal, or when a subspace update is triggered every 24 hours to adapt to the process drift scenario of the production line.

[0118] This invention relates to a wafer defect detection method without training based on frozen DINO multi-granularity hierarchical PCA subspace. Its core technologies are mainly reflected in the following aspects:

[0119] 1. A training-free architecture combining frozen DINO features and a single-class PCA subspace

[0120] This invention directly employs a fully frozen, non-weight-updated self-supervised DINO large model as the basic feature extractor, and independently constructs the PCA normal texture subspace using only a very small number of known normal (OK) chips' depth features during deployment. This solves the industry pain points of traditional deep learning methods, which heavily rely on large-scale normal and defective dual-class labeled samples, and where production line defect samples are extremely scarce and class imbalanced. It also avoids the enormous computational overhead caused by backpropagation when deploying traditional large models at industrial edge environments. It achieves a completely "training-free" and "one-class learning" paradigm, requiring only 50-200 normal samples for rapid deployment, with no network training or gradient optimization throughout the process, reducing hardware deployment costs by over 90%.

[0121] 2. A mechanism based on fine / medium / coarse three-level feature space decoupling and Top-K residual fusion

[0122] This invention introduces a three-level spatial sliding window partitioning mechanism (fine-grained, medium-grained, and coarse-grained) on the depth feature map output by DINO. Reconstruction residuals are independently calculated at different spatial scales, and a Top-K mean strategy is used to aggregate local errors at each scale into a comprehensive defect score for a single chip. This solves the shortcomings of traditional defect detection methods, which suffer from the problem of local defects such as tiny particles / shallow scratches being easily diluted and smoothed out in global features due to the single feature scale, and the lack of spatial correlation representation for global defects such as large-area deformation. It achieves comprehensive coverage of multi-scale defects on the wafer surface, maintaining extremely high sensitivity to microparticle contamination while accurately identifying large-area structural defects. The Top-K mean aggregation strategy effectively balances the relationship between random imaging noise and real micro-defects, significantly improving the system's detection rate under complex textures.

[0123] 3. Incremental PCA Subspace Online Evolution Mechanism Based on Dynamic Time-Varying Characteristics

[0124] This invention designs an incremental PCA update mechanism. When a new single chip, deemed normal (OK), is generated during continuous production line operation, the existing PCA mean vector and feature basis are dynamically corrected directly using an incremental algorithm, achieving synchronous adaptive updates of the subspace and anomaly detection threshold. This solves the technical shortcomings of traditional static models, which are prone to frequent false alarms and false negatives and have high maintenance costs due to "process drift" in chip surface texture caused by semiconductor process fine-tuning, light source attenuation, equipment natural aging, or raw material batch changes during long-term operation of industrial production lines. Without changing the frozen large model, the system can dynamically absorb new samples online with extremely low computational complexity, enabling the detection subspace to have smooth evolution and self-correction capabilities. It eliminates the need for downtime and full recalculation, significantly improving the system's long-term robustness in real industrial environments.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the ideas of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer defect detection method without training based on frozen DINO multi-grained hierarchical PCA subspace, characterized in that, include: Step 1: Obtain the original wafer image to be inspected, calculate the center coordinates of each single chip on the wafer, crop out the region of interest image of each single chip, and uniformly scale it to the preset bilinear interpolation resolution. Step 2: After completely freezing all network weights of the pre-trained DINO self-supervised large model, perform deep feature extraction on the scaled region of interest images of each single chip. Step 3: Set a sliding window with three spatial scales for the extracted depth features to decouple the depth features into local feature vectors with multi-scale local perception capabilities; Step 4: Acquire normal single-chip images, perform steps 2 and 3 to extract all local feature vectors at each spatial scale, and construct feature matrices at each spatial scale; perform principal component analysis to construct normal subspace projection matrices at each spatial scale. Step 5: Project the local feature vectors of each spatial scale extracted in Step 3 onto the corresponding normal subspace, calculate the reconstruction residuals of all local feature vectors at each spatial scale and aggregate them within the scale to obtain three scale-independent defect scores. Perform weighted fusion of multi-scale defect scores to calculate the comprehensive anomaly score of each single chip. Step 6: Using the same method as in Step 5, calculate the comprehensive anomaly score of each chip in the normal wafer image acquired in Step 4, and calculate its mathematical expectation and standard deviation. Based on the mathematical expectation and standard deviation, calculate the defect judgment threshold of each chip. Compare the comprehensive anomaly score of the chip in the wafer to be inspected with the defect judgment threshold to determine whether the chip has a defect. Step 7: Summarize all single-chip judgment results. If the proportion of defective single chips exceeds 5%, the wafer is judged to be defective. Step 8: For single chips that are determined to be normal online, use the incremental PCA algorithm to dynamically update their projection matrix at each spatial scale.

2. The wafer defect detection method without training based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, Step 1 specifically involves: Step 1.1: Obtain the original wafer image to be inspected, and calculate the theoretical center coordinates of each single chip on the wafer based on the wafer layout parameters; the wafer layout parameters include the number of rows and columns of the chip array, the chip spacing, and the size of a single chip; Assuming a single chip on a wafer is... OK If the column array is distributed in a grid, then the first... line, number Theoretical center coordinates of a single chip for: In the formula, The starting reference point is the center coordinate of the chip. and These represent the horizontal and vertical chip arrangement spacing, respectively. ; Step 1.2: Eliminate translation and rotation residuals caused by mechanical positioning through geometric correction and registration, and calculate the center coordinates after correction and registration; Step 1.3: Based on the corrected and registered center coordinates and single-chip size, crop the region of interest image of each single chip from the whole wafer image; Step 1.4: Scale the region of interest images of all single chips to a preset bilinear interpolation resolution of 224×224 pixels.

3. The wafer defect detection method without training based on frozen DINO multi-grained hierarchical PCA subspace according to claim 2, characterized in that, Step 1.2 specifically includes: Step 1.2.1: Calculate the rotation deviation angle and translation correction amount using the phase correlation method or key point matching; Step 1.2.2: Calculate the center coordinates of the single chip after calibration and registration according to the following formula. : In the formula, The rotation center point of the entire wafer image, The rotational deviation angle, This is the translation correction amount.

4. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, Step 2 specifically involves: Step 2.1: Introduce the pre-trained ViT architecture DINO self-supervised large model, freeze all network weights of the model, and do not perform backpropagation operations in the subsequent process; Step 2.2: Input the scaled region of interest images of each single chip into the frozen DINO self-supervised large model, and divide it into multiple non-overlapping image blocks through forward propagation of the visual Transformer; Step 2.3: Extract the depth feature matrix output from the last Transformer Block layer. , where N is the number of image patches and D is the feature dimension.

5. The wafer defect detection method without training based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, Step 3 specifically involves: Step 3.1: Set a sliding window with three spatial scales (fine-grained, medium-grained, and coarse-grained) for the extracted depth feature matrix, as follows: A fine-grained window with a size of 32×32px and a step size of 16px is used to detect tiny particle contamination, minor scratches, and pinhole defects. A medium-grained window with a size of 64×64px and a step size of 32px is used to detect local breaks, pattern anomalies, and moderate scratches. A coarse-grained window with a size of 128×128px and a step size of 64px is used to detect large-area defects, global deformations, and structural defects. Step 3.2: Decouple the deep features into three sets of local feature vectors with multi-scale local perception capabilities through fine-grained windows, medium-grained windows, and coarse-grained windows: ， ， ； in, It is a set of fine-grained local feature vectors. This is the Mth fine-grained local feature vector; It is a set of medium-granularity local feature vectors. This is the Nth medium-granularity local feature vector; It is a set of coarse-grained local feature vectors. Let Q be the Qth coarse-grained local feature vector.

6. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, Step 4 specifically involves: Step 4.1: Collect 50-200 known normal single-chip images; Step 4.2: Extract depth features from normal single-chip images using a pre-trained DINO self-supervised large model with frozen weights; Step 4.3: Using the same method as in Step 3, extract multiple local feature vectors at various spatial scales from the region of interest image of a normal single chip. The feature matrix at that spatial scale is constructed from multiple local feature vectors at the same spatial scale from multiple normal single chip images. : in, Represents all local feature vectors of the region of interest image of the h-th single chip at a certain spatial scale; H is the number of normal region of interest images of a single chip; in, Let be the d-th local feature vector of the h-th single-chip region of interest image at a certain spatial scale; Mg is the total number of local feature vectors at this spatial scale; Step 4.4: Calculate the global mean vector of all local feature vectors. : feature matrix Subtract the mean vector from each local feature vector in the equation. The centered feature matrix is ​​obtained. : in, It is a column vector whose elements are all 1s; Step 4.5: Construct the covariance matrix : For covariance matrix Perform eigenvalue decomposition: in, It is a diagonal matrix of eigenvalues ​​sorted in descending order, and the eigenvalues ​​satisfy... ; For the corresponding orthogonal eigenvector matrix, each column vector It represents an orthogonal principal component direction in a higher-dimensional space; Step 4.6: Set the cumulative variance contribution rate threshold. Used to determine the retained principal component dimensions : Before truncation The eigenvector columns corresponding to the largest eigenvalues ​​are concatenated column by column to obtain the normal subspace projection matrix. Closed-form calculation formula: in, P1 represents the projection matrix at the fine-grained spatial scale, P2 represents the projection matrix at the medium-grained spatial scale, and P3 represents the projection matrix at the coarse-grained spatial scale.

7. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 6, characterized in that, Step 5 specifically involves: Step 5.1: For the region of interest image of each single chip, calculate the reconstruction residuals of all local features at the three spatial scales: in, The residual of the reconstructed local feature vectors of the region of interest image of a single chip at a fine-grained scale; The reconstruction residual of the local feature vectors of the region of interest image of a single chip at a medium granularity; The residual of the reconstruction of local feature vectors in the region of interest image of a single chip at a coarse-grained level; Step 5.2: Employ the Top-K mean strategy to extract the top-K mean values ​​at each spatial scale. The mean of the maximum reconstruction residuals is used to aggregate the reconstruction residuals of the local feature vectors at this spatial scale, resulting in three scale-independent defect scores: in, This represents the defect score at a finer-grained scale. This represents the defect score at the medium-grained scale. Defect score at the coarse-grained scale; Step 5.3: Calculate the final comprehensive anomaly score for the single chip using a weighted fusion strategy based on the defect scores at each scale. in, For the adaptive adjustment of weighting coefficients, and By using multi-scale fusion, the feature scores of defects of different sizes can all obtain effective gains from a global perspective.

8. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, Step 6 specifically involves: Step 6.1: Calculate the comprehensive anomaly score of each single chip in the normal wafer image acquired in Step 4 using the same method as in Step 5, and calculate its expected value. and standard deviation ; Step 6.2: Calculate the defect decision threshold for each single chip based on mathematical expectation and standard deviation. : Step 6.3: Assess the overall anomaly score of the single chip in the wafer under inspection. Compare with the defect decision threshold T: If If so, then the single chip is determined to be normal; if If so, the single chip is determined to be defective.

9. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 6, characterized in that, Step 8 specifically involves: Step 8.1: Recursive update formula for the global mean vector: Let the old global mean vector be... When the buffer is full When the number of single chips determined to be normal online, the feature matrix of the single chips determined to be normal online is constructed using the same method as in step 4.

3. , The mean vector is: in, The c-th image is a local feature vector of a single chip that is determined to be normal online. The total number of all local feature vectors added to the single chip; the updated global mean vector. for: Step 8.2: Assume the old feature subspace contains the previous one. There are principal components, and their projection matrices are: The corresponding eigenvalue diagonal matrix is ; The newly added Centering each normal chip using the old mean yields the centered feature matrix of the normal chips. : Will Projecting onto the existing subspace yields the coordinate matrix within the existing subspace. Residual matrix of orthogonal complement space : For the residual matrix Perform QR decomposition to extract the new directional basis of the orthogonal complement space. : in, It is an orthogonal matrix. It is an upper triangular matrix; the updated total basis of the subspace is written in matrix concatenation form. ; Step 8.3: Low-order equivalent matrix of the core covariance evolution relation The structure is as follows: in, It is a left singular vector matrix. It is a singular value diagonal matrix. The transpose of the right singular vector matrix; truncation Center front The column vector corresponding to the largest singular values Calculate the updated projection matrix: Update the eigenvalue diagonal matrix to the newly solved front One singular value: .

10. The wafer defect training-free detection method based on frozen DINO multi-grained hierarchical PCA subspace according to claim 1, characterized in that, The incremental PCA update is triggered when 50 new single chips are added to the wafer and confirmed to be normal, or when a subspace update is triggered every 24 hours.

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