An adaptive polar code decoder and decoding method

Abstract

The application discloses a kind of self-adapting polar code decoder and decoding method, belong to wireless communication technical field, the present application will channel log likelihood ratio LLR be stored into memory, controller receives node distribution pattern after on-line identification R0, R1, REP, SPC four kinds of special nodes, pruning and generating 16 bit decoding instruction;Computing unit array PEA reads LLR from memory and executes operation, result is written back;When encountering special node, node processing unit NPU reads LLR from memory and calculates path metric PM, generates decision result and path screening result through 2L to L filter;Decision result sends part and computing unit PSU to carry out single-cycle cross-level part and calculation, and then the result is fed back to PEA;Path screening result sends path management module to adjust memory pointer;The present application supports arbitrary confidence order decoding, significantly reduces delay and system overhead, and is suitable for sensory auxiliary, AI auxiliary and physical layer security scene.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically relating to an adaptive polar code decoder and decoding method. Background Technology

[0002] Polar codes, as the first channel coding scheme theoretically proven to reach the Shannon limit, rely on the channel polarization effect for their core error correction mechanism. Traditional polar codes pre-calculate a fixed polarization order based on a static statistical channel model, mapping information bits to high-confidence sub-channels and frozen bits to low-confidence sub-channels.

[0003] With the increasing application of polar codes in cutting-edge scenarios such as integrated sensing, AI-assisted optimization, and physical layer security, their construction logic has evolved towards dynamic, customized, and multi-objective joint optimization, resulting in various non-standard sub-channel confidence orders. However, existing polar code decoder architectures are typically hardware-fixed for a single fixed polar order, lacking the flexibility to handle dynamic polar orders.

[0004] In existing technologies, patent CN120856163A uses the decoder as a RISC-V coprocessor, with instructions generated by software, resulting in low efficiency and high communication overhead. Patent CN116248132A employs an offline-generated custom instruction set, which cannot adapt to dynamic scenarios and can only complete a single layer of computation per cycle, exhibiting significant latency bottlenecks. Therefore, there is an urgent need for a polar code decoder with high flexibility and universality. Summary of the Invention

[0005] To address the problems mentioned in the background art, this invention provides an adaptive polar code decoder and decoding method to solve the problems that existing polar code decoders cannot support arbitrary confidence order decoding, have low instruction generation efficiency, high partial sum calculation latency, and are difficult to adapt to the needs of dynamic scenarios such as sensory assistance, AI assistance, and physical layer security.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An adaptive polar code decoder includes a controller, a computing unit array (PEA), a node processing unit (NPU), a partial computing unit (PSU), a memory, and a path management module.

[0008] The controller is connected to the computing unit array (PEA), node processing unit (NPU), partial computing unit (PSU), memory, and path management module. The controller is used to identify the node type based on the input node distribution pattern, generate corresponding decoding instructions, and issue them.

[0009] The computational unit array (PEA) is connected to the memory. The PEA is used to perform the f(・) and g(・) operations for the transfer of log-likelihood ratio (LLR) between nodes during the decoding process according to the controller instructions, as well as to obtain the LLR required for computation from the memory and store the computation results into the memory.

[0010] The Node Processing Unit (NPU) is communicatively connected to the memory, the path management module, and the Partial Computing Unit (PSU). The NPU is used to process the four special nodes identified by the controller (R0, R1, REP, and SPC) according to the controller instructions, generate node decision results and path filtering results, and send the node decision results to the Partial Computing Unit (PSU) and the path filtering results to the path management module.

[0011] The partial sum calculation unit (PSU) is communicatively connected to the memory. The PSU is used to perform partial sum calculation after decision based on the controller instructions and the node decision results output by the node processing unit (NPU), and store the calculation results in the memory.

[0012] The memory is communicatively connected to the path management module. The memory is used to store the channel LLR of the decoding input, the internal LLR of the intermediate calculation results, and the bit estimation results.

[0013] The path management module is used to adjust the data source of each path according to the path filtering results output by the node processing unit (NPU), and to inform the memory of the data portion that should be read from each path.

[0014] Preferably, the controller has a built-in online special node identification module and a decoding instruction generation module. The online special node identification module identifies four types of special nodes, R0, R1, REP and SPC, using a node merging method from bottom to top. The decoding instruction generation module generates 16-bit decoding instructions, including but not limited to opcodes, node levels, storage control, and left and right branch flags, based on the special node identification results.

[0015] Preferably, the partial sum calculation unit (PSU) includes an XOR calculation section, a switching network section, and a storage feedback section. The XOR calculation section uses combinational circuits to perform partial sum calculations of any length less than or equal to the maximum node length supported by the decoder. The storage feedback section directly connects the register storage result to the PSU input, enabling multi-level partial sum calculations of nodes to be completed across levels within a single cycle.

[0016] Preferably, the Node Processing Unit (NPU) categorizes special nodes into two types: non-iterative nodes and iterative nodes for processing. Non-iterative nodes include R0 nodes and REP nodes, while iterative nodes include R1 nodes and SPC nodes. The NPU is equipped with a 2L to L path filter to filter the split paths and retain the optimal L paths, where L is the size of the decoder list.

[0017] A decoding method includes the following steps:

[0018] A1: The controller identifies special node types based on the input node distribution pattern, prunes the decoding tree of the node distribution pattern according to the identification results, sets the corresponding flag of the pruned node to 0, and generates the corresponding decoding instruction.

[0019] A2: The computational unit array PEA traverses all nodes according to the decoding instructions, starting from the root node of the decoding tree in the node distribution pattern in a depth-first traversal order.

[0020] When traversing to a normal node, the internal LLR is passed down and calculated, the f(・) operation and g(・) operation between nodes are completed, and the child nodes of that node are traversed.

[0021] When a special node is encountered, traversal of its child nodes is stopped. The Node Processing Unit (NPU) processes the special node according to the decoding instructions, generating node decision results and path filtering results. Then, the Partial Summation Unit (PSU) performs partial sum calculations upwards according to the decoding instructions and node decision results, and feeds the calculation results back to the PEA (Power Array for Computing Units). After processing is complete, the traversal process of the decoding tree is returned to continue processing the next branch node of the parent node of the special node. This continues until all nodes of the decoding tree have been traversed, and the decoding result is output.

[0022] Preferably, in A1, the online identification of special node types specifically involves: adopting a bottom-up node merging method, starting from a leaf node of length 2, merging layer by layer upwards according to a preset node merging rule until the maximum node length supported by the decoder is reached, thereby identifying the types of all high-level nodes; the node merging rule corresponds to the distribution pattern characteristics of four special nodes: R0, R1, REP, and SPC, where the distribution pattern of R0 nodes is all 0s, the distribution pattern of R1 nodes is all 1s, the distribution pattern of REP nodes is all 0s except for the last bit which is 1, and the distribution pattern of SPC nodes is all 1s except for the first bit which is 0.

[0023] Preferably, in A1, the corresponding decoding instructions are generated as follows:

[0024] Visit all reserved special nodes in depth-first traversal order. When a non-special node is visited, generate f(・) or g(・) operation instructions. When a special node is visited, generate special node decoding instructions of the corresponding type. At the same time, use the lowest common ancestor algorithm to generate partial sum calculation instructions or g(・) operation instructions.

[0025] Preferably, in A2, the calculation formulas for the f(・) operation and the g(・) operation are as follows:

[0026] f(・) operation:

[0027] ;

[0028] g(・) operation:

[0029] ;

[0030] Where α is the LLR value, β is the bit value after the decision, j is the level of the node, and i is the index of the node at that level.

[0031] Preferably, in A2, when processing special nodes, the path metric PM value of each path is calculated and input into the 2LtoL path filter for path filtering. The path metric PM is calculated as follows:

[0032] For node R0, the decision is all 0s, and the path metric penalty value is:

[0033] ;

[0034] For a REP node, after one path split, the metric penalty values ​​for the two paths are as follows:

[0035] ;

[0036] Where s is the exponent of the node length, l is the path index, HD(x) is the decision function, which returns 0 when x≥0 and 1 otherwise, and m is the index of the bits within the node.

[0037] Preferably, in A2, the calculation formula for the partial sum is:

[0038] ;

[0039] By utilizing the XOR computation part and storage feedback part of the partial sum computation unit (PSU), the multi-level partial sum computation of the node is completed across levels within a single cycle, and the hard information of the decided bits is transmitted to the higher level of the decoding tree.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] 1. Significantly improved flexibility of polar code decoders: By integrating online special node identification and dynamic instruction generation modules into the decoder, it can support polar code decoding under arbitrary confidence order, perfectly adapting to dynamic scenarios such as synesthesia-assisted, AI-assisted, and physical layer security.

[0042] 2. Significantly reduced decoding latency: The newly designed component and computing architecture can complete multi-level component and computing of nodes across levels within a single cycle. Combined with special node pruning techniques, the number of computing cycles is significantly reduced.

[0043] 3. Effective reduction in system overhead: Implementing the instruction generation part in hardware avoids the processor resource consumption and communication overhead of software-generated instructions, thereby increasing the upper limit of system throughput. Attached Figure Description

[0044] Figure 1 This is an overall architecture diagram of the adaptive polar code decoder of the present invention;

[0045] Figure 2 This is an overall flowchart of the adaptive polar code decoding method of the present invention;

[0046] Figure 3 This is a schematic diagram of the polar code decoding tree and four types of special nodes of the present invention;

[0047] Figure 4 This is a schematic diagram of the decoding instruction generation process of the present invention;

[0048] Figure 5 This is a hardware structure diagram for generating decoding instructions in this invention;

[0049] Figure 6 This is a diagram of the 16-bit decoding instruction set format of the present invention;

[0050] Figure 7 This is a block diagram of the computing unit array PEA of the present invention;

[0051] Figure 8 This is a block diagram of the node processing unit (NPU) of the present invention;

[0052] Figure 9 This is a block diagram of the invention and the computing unit PSU. Detailed Implementation

[0053] To facilitate understanding of the technical content of this invention by those skilled in the art, the invention will be further described in detail below with reference to the accompanying drawings and specific examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the scope of the invention.

[0054] An adaptive polar code decoder, such as Figure 1 As shown, it includes the following core components:

[0055] Computational cell array (PEA):

[0056] Function: Used to implement the basic operations for LLR transmission between nodes during the decoding process.

[0057] Signal processing method: The left child node in the decoding tree performs the signal processing. Operation; right child node performs Calculation.

[0058] Connection relationships: Connect to the controller to select the computation scale; connect to the memory to obtain the LLR used for computation and store the results in the memory.

[0059] Node Processing Unit (NPU):

[0060] Function: Used for processing four special nodes: R0, R1, REP, and SPC.

[0061] Signal processing method: Nodes are divided into iterative nodes (R1, SPC) and non-iterative nodes (R0, REP) according to whether iterative decoding is required.

[0062] Connection relationships: Connect to the controller and select the node type; connect to the memory and obtain the LLR value used for calculation.

[0063] Controller:

[0064] Function: Identify node types online based on node distribution patterns and generate corresponding decoding instructions.

[0065] Connection relationships: Connects to PEA, NPU, memory, and some computing units, and issues instructions to each processing unit.

[0066] Parts and computing units (PSU):

[0067] Function: Used to perform partial sum calculations after bit decision.

[0068] Signal processing method: corresponding bit XOR calculation.

[0069] Connection relationships: Connect to the controller to select parts and computation scale; connect to the NPU to obtain node decision results; connect to the storage to cache parts and computation results.

[0070] Memory:

[0071] Function: Used to store the channel LLR of the decoding input, the internal LLR of the intermediate settlement result, and the bit estimation result.

[0072] Connection relationships: Connect to the controller to select output data; connect to PEA, NPU, and PSU to read and write LLR values ​​used for calculation; connect to the path management module to achieve low-cost path replication.

[0073] Path management module:

[0074] Function: Records the data source for each path.

[0075] Connection relationships: Connects to the NPU to adjust the data source for each path based on the path filtering results; connects to the memory to inform each path which part of the data should be read.

[0076] A decoding method, such as Figure 2 As shown, at the start of decoding, special nodes are first identified and corresponding instructions are generated based on the node distribution pattern. Then, the internal LLR is passed. When a special node is encountered, it is processed. After processing, a partial sum is calculated and the calculation result is fed back to the upper layer. That is, the internal LLR passing and calculation steps are returned until all special nodes are processed and the decoding ends.

[0077] The specific steps include:

[0078] S1. Special node identification and instruction generation; executed by the controller, sub-steps include:

[0079] S11, Special Node Identification;

[0080] S12, Instruction generation;

[0081] S2, Internal LLR Transfer and Calculation; Performed by PEA;

[0082] S3, Special Node Processing; Performed by the NPU;

[0083] S4, Partial and Calculation; Performed by PSU.

[0084] Polar code decoding tree such as Figure 3 As shown, This represents the j-th node in the i-th layer, with a node length of . .

[0085] This invention employs the Fast-SSCL-SPC decoding algorithm, which introduces four special nodes—R0, REP, SPC, and R1—to prune the original decoding tree. Here, we define... This represents the distribution pattern of the j-th node in the i-th layer, for example... This indicates that all leaf nodes are frozen bits. A node that satisfies the following condition is called a special node:

[0086] ;

[0087] In the traditional SCL decoding algorithm, a depth-first traversal of all nodes is required. By introducing special nodes, bit decisions are performed directly at these special nodes, without traversing their child nodes. Figure 3 The decoder tree shown, after pruning, retains only... , as well as With three nodes, the decoding process is simplified to a depth-first traversal of the three-node decoding tree.

[0088] The real-time decoding algorithm flow of this invention is as follows: Figure 2 As shown, specifically, step S1 involves online node identification and instruction generation based on the node distribution map, which is implemented in the controller module.

[0089] Specifically, step S11, node online identification, is implemented in a bottom-up manner, that is, lower-level nodes are continuously merged to form higher-level nodes. Here, we define... The length is indicated by The special node Type, where , , This represents the maximum node length supported by the decoder. Therefore, the node merging rule can be expressed as:

[0090] ;

[0091] ;

[0092] ;

[0093] ;

[0094] in, Indicates length is The left and right child node types of the node. The initial state of merging all nodes can be represented as:

[0095] ;

[0096] ;

[0097] ;

[0098] in, This represents a 2-bit information subsequence. It's important to note that since the feature maps of 2-bit REP nodes and SPC nodes are identical, they are treated as REP nodes during the decoding process to simplify the decoding procedure. Therefore, the initial state for SPC node merging is REP nodes, as shown below. Figure 3 As shown.

[0099] Specifically, step S12 generates instructions based on the recognition results of step S11, and the generation method is as follows: Figure 4 As shown. Taking a 4-bit polar code as an example, the decoding tree for a 4-bit polar code has 7 nodes. In the special node detection section, 7 sets of registers are set up to store the node type and special node flag bits, respectively. The diagram shows that the registers of each node are arranged in depth-first traversal order. After obtaining the special node flag bits, the decoding tree is pruned using the inheritance relationship of the nodes in the decoding tree. The flag bits of the pruned nodes are set to 0. Finally, the types of the retained special nodes are obtained according to the pruned flag bits, and then the corresponding decoding instructions are generated. The generation method is to complete the access of all retained special nodes from the root node in depth-first traversal order. When a non-special node is accessed, ... and Related instructions are generated; when a special node is accessed, the corresponding decoding instructions are generated; then, using the lowest common ancestor algorithm, the lowest common ancestor of the gons between the two special nodes is found, and while accessing that ancestor node, partial sum instructions or... instruction.

[0100] The hardware structure diagram for node identification and decoding instruction generation is as follows: Figure 5 As shown. The input leaf node distribution pattern is used. Based on the aforementioned node merging rules, a combinational circuit is used to determine the type of each node in a single cycle, generating corresponding flag bits and storing them in a register. Then, using node inheritance relationships, a combinational circuit is used to implement pruning, obtaining the flag bits of the retained nodes and caching them. Finally, a priority encoder is used to quickly obtain the non-zero element index in the retained node register, and the node type register is accessed using the index to obtain the node type. The corresponding index is masked after use. After obtaining the special node type, a lookup table is first used for format conversion, changing the depth-first storage order to a tree-like storage order. Then, the node access controller is used, which internally maintains a state machine to control access from the current node to the target special node, and uses instruction mapping to generate the corresponding decoding instructions.

[0101] Following the above-described node identification and decoding instruction generation process, this invention further designs as follows: Figure 6 The decoding instruction set shown is as follows:

[0102] The meanings of each field in the instruction set are as follows:

[0103] Bits 0-3 (4 bits): Operation type field. "0000" indicates execution. Calculation; "0001" execution Calculation; "0010" performs partial and calculation; "1000" performs fast decoding of R0 node; "1001" performs fast decoding of R1 node; "1010" performs fast decoding of REP node; "1011" performs fast decoding of SPC node.

[0104] Bits 4-7 (4 bits): Node-level resources. Used to indicate the level of the current operation, and this field is also used to automatically generate the read and write addresses required by the memory.

[0105] Bits 8-9 (2 bits): Storage control. Used to indicate the current data read / write direction. "00" indicates that all reads are in RAM, used for read / write operations in higher-level nodes; "01" indicates reading from RAM and writing to registers, used for data flow from higher-level nodes to lower-level nodes; "10" indicates reading from registers and writing to registers, used for read / write operations in lower-level nodes; "11" indicates reading from registers and writing to higher-level RAM, used for backtracking from lower-level bits after decision-making.

[0106] Bit 10 (1 bit): Left / Right Branch Flag. "0" indicates that the current node is on the left branch of its parent node, and "1" indicates that the current node is on the right branch of its parent node. This field is mainly used to assist in shift operations of lower-level nodes.

[0107] Bits 11-15 (5 bits): Other parameter field, providing auxiliary parameters under different instructions. In multi-level parts and calculations, it indicates the number of parts and calculation layers; when nodes are long and require segmentation, it indicates the number of segmentation steps.

[0108] Specifically, step S2 is the process of passing LLR between nodes. and The operation, when passing to the left child node, uses The specific calculation is as follows:

[0109] ;

[0110] When passing to the right child node, use The specific calculation is as follows:

[0111] ;

[0112] in, This is the LLR value, also known as soft information. The bits following the decision are also called hard information.

[0113] The structural diagram of the PEA module implemented in this invention is as follows: Figure 7 As shown, where .

[0114] For a single decoding path, this module contains... Each PE contains a... Calculation module and Calculation module. In calculation... At that time, PEA reads the LLR value used for calculation from the LLR memory, sends it to the corresponding calculation unit through the switching network, completes the calculation, and then writes it back to the corresponding storage space through the switching network. For The computation requires additional components and calculation results, which are also sent to the corresponding computing units through a switching network.

[0115] Specifically, step S3 involves handling special nodes. For the four types of special nodes—R0, REP, R1, and SPC—the handling methods are as follows:

[0116] 1. Node R0;

[0117] Node R0 consists only of frozen bits, so its corresponding root node is directly judged to be all 0s, that is, the judgment bits are returned upwards. At the same time, for A penalty is imposed on bits whose result is not 0:

[0118] ;

[0119] in, Represents a node The m-th bit corresponds to the value of LLR. Let be the decision function. Returns 0 if it is greater than or equal to 0, otherwise returns 1. This represents the path metric; the smaller the value, the higher the confidence level of the path.

[0120] 2. REP node;

[0121] In a REP node, only the last bit is an information bit. Therefore, when making a decision on this type of special node, its root node will only show... and In both cases, after performing a partial sum operation upwards, the node will only have two possible outcomes: all 0s or all 1s. Therefore, for a REP node, only one path split needs to be considered, and the corresponding path penalty value after the split can be calculated as follows:

[0122] ;

[0123] 3. Node R1;

[0124] For nodes in R1, all leaf nodes are information bits. Once a node is determined to be R1, it is first hard-determined as a candidate path. Then, the nodes are sorted by their LLR values ​​in ascending order, and the smallest LLR is selected. Each bit is used for path splitting (since the path after hard decision will always have the smallest path metric, it will definitely be included in the optimal L paths, so at most L-1 splits are needed), and a penalty value is added to the path metric:

[0125] ;

[0126] in, The first step of fast decoding for R1 node iteration Indicates the LLR node Small index. For the remaining bits, keep their path metric unchanged:

[0127] ;

[0128] in, .

[0129] 4. SPC node;

[0130] For length of For an SPC node, its root node corresponds to a frozen bit and Similar to the R1 node, the SPC node can also be simplified to perform path selection after each split, using one information bit. Furthermore, the SPC node utilizes a characteristic of recursive polar code construction:

[0131] ;

[0132] in, For nodes The parity check results For continuous XOR, For nodes The first bit, which is also the frozen bit, is always set to 0. Once the node is determined to be an SPC node, a hard decision is first made and the parity check result is calculated. ,like This indicates that the parity check passed, and the current decision result is the maximum likelihood decision result; if This indicates that the current decision contains errors. Only after flipping the bit with the lowest confidence level can the maximum likelihood result be obtained. In this case, a penalty term needs to be added to the path.

[0133] ;

[0134] After obtaining the maximum likelihood decision result, similar to node R1, the index is selected as... to The bits are path-split, where The corresponding path penalty value is:

[0135] ;

[0136] in, It's important to note that because only a single bit is flipped during path splitting, the final bit sequence may not meet parity check requirements. Therefore, a parity check process needs to be added at the end of SPC decoding to correct the value of the bit with the lowest confidence level.

[0137] ;

[0138] Based on the above signal processing methods, the NPU hardware architecture is as follows: Figure 8 As shown.

[0139] This invention implements an NPU module that categorizes special nodes into non-iterative and iterative nodes for processing. R0 nodes do not involve path splitting and their decision result is all zeros; therefore, path metric calculation is performed solely through an addition tree. R1 nodes involve path splitting between all zeros and all one values. Paths with all one values ​​use the same implementation approach as R0 paths, while paths with all zero values ​​reuse R0 paths to improve resource utilization. Iterative nodes require multiple path splitting and filtering; therefore, after path filtering within the NPU, there is a corresponding feedback path to support iterative node calculations. Both R1 nodes and SPC nodes need to continuously calculate the minimum LLR modulus; therefore, the part for calculating the minimum LLR modulus is reused to improve resource utilization. After calculation, on the one hand, the path decision result is sent to the PSC module for partial sum calculation and update; on the other hand, the path filtering result is sent to the path management module to manage the LLR read pointer, avoiding large-scale data copying.

[0140] Specifically, step S4 involves partial sum calculation, used to pass the decided bit hard information to higher levels of the decoding tree. The passing calculation is shown in the following formula:

[0141] ;

[0142] To reduce the latency of multi-layer components and computations, based on the aforementioned signal processing methods, this invention designs a component and architecture as follows: Figure 9As shown, the processing node length is 8. The design follows the characteristics of polar codes: partial sum calculation is required only after the right child node has been processed; the node length is a power of 2; and the length of the processed node decreases before completing a partial sum calculation. The PSU can be divided into three parts: an XOR calculation part, a switching network part, and a storage feedback part. The XOR calculation part performs the main calculation of the partial sum, and uses a combinational circuit to simultaneously add an XOR control part to achieve partial sum calculation for any node length less than 8. The switching network is used to shift and store the partial sum result. When decoding reaches the left branch node, no partial sum calculation is needed; instead, the partial sum calculation must wait for the corresponding right branch node decision before proceeding. Therefore, the decision result of the left branch node needs to be temporarily stored. The storage feedback part directly connects the register storage result to the input part of the PSU through a multiplexer to achieve multi-level partial sum calculation. Figure 9 For example, after the final node PSU_IN[1:0] completes the decision, the two-level estimation results cached in PSU participate in the calculation together. By using combinational circuits, the two-level partial sum calculation results can be obtained in a single cycle.

[0143] Specifically, after completing steps S1-S4, return to step S2 until all nodes have been processed.

[0144] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An adaptive polar code decoder, characterized in that, It includes a controller, a computing unit array (PEA), a node processing unit (NPU), a partial computing unit (PSU), memory, and a path management module; The controller is connected to the computing unit array (PEA), node processing unit (NPU), partial computing unit (PSU), memory, and path management module. The controller is used to identify the node type based on the input node distribution pattern, generate corresponding decoding instructions, and issue them. The computational unit array (PEA) is connected to the memory. The PEA is used to perform the f(・) and g(・) operations for the transfer of log-likelihood ratio (LLR) between nodes during the decoding process according to the controller instructions, as well as to obtain the LLR required for computation from the memory and store the computation results into the memory. The Node Processing Unit (NPU) is communicatively connected to the memory, the path management module, and the Partial Computing Unit (PSU). The NPU is used to process the four special nodes identified by the controller (R0, R1, REP, and SPC) according to the controller instructions, generate node decision results and path filtering results, and send the node decision results to the Partial Computing Unit (PSU) and the path filtering results to the path management module. The partial sum calculation unit (PSU) is communicatively connected to the memory. The PSU is used to perform partial sum calculation after decision based on the controller instructions and the node decision results output by the node processing unit (NPU), and store the calculation results in the memory. The memory is communicatively connected to the path management module. The memory is used to store the channel LLR of the decoding input, the internal LLR of the intermediate calculation results, and the bit estimation results. The path management module is used to adjust the data source of each path according to the path filtering results output by the node processing unit (NPU), and to inform the memory of the data portion that should be read from each path.

2. The adaptive polar code decoder according to claim 1, characterized in that, The controller has a built-in online special node identification module and a decoding instruction generation module; The online special node identification module uses a bottom-up node merging method to identify four types of special nodes: R0, R1, REP, and SPC. The decoding instruction generation module generates 16-bit decoding instructions based on the special node identification results, including but not limited to opcodes, node levels, storage control, and left and right branch flags.

3. An adaptive polar code decoder according to claim 1, characterized in that, The partial sum calculation unit (PSU) includes an XOR calculation section, a switching network section, and a storage feedback section. The XOR calculation section uses combinational circuits to perform partial sum calculations of any length less than or equal to the maximum node length supported by the decoder. The storage feedback section directly connects the register storage results to the PSU input, enabling multi-level partial sum calculations of nodes to be completed across levels within a single cycle.

4. An adaptive polar code decoder according to claim 1, characterized in that, The Node Processing Unit (NPU) categorizes special nodes into two types: non-iterative nodes and iterative nodes. Non-iterative nodes include R0 nodes and REP nodes, while iterative nodes include R1 nodes and SPC nodes. The NPU has an internal 2L to L path filter to filter the split paths and retain the optimal L paths, where L is the size of the decoder list.

5. A decoding method, applied to the decoder as described in any one of claims 1-4, characterized in that, Includes the following steps: A1: The controller identifies special node types based on the input node distribution pattern, prunes the decoding tree of the node distribution pattern according to the identification results, sets the corresponding flag of the pruned node to 0, and generates the corresponding decoding instruction. A2: The computational unit array PEA traverses all nodes according to the decoding instructions, starting from the root node of the decoding tree in the node distribution pattern in a depth-first traversal order. When traversing to a normal node, the internal LLR is passed down and calculated, the f(・) operation and g(・) operation between nodes are completed, and the child nodes of that node are traversed. When a special node is encountered, the traversal of its child nodes is stopped. The node processing unit (NPU) processes the special node according to the decoding instructions, generating node decision results and path filtering results. Then, the partial sum calculation unit (PSU) performs partial sum calculations upwards according to the decoding instructions and node decision results, and feeds the calculation results back to the calculation unit array (PEA). After processing is complete, return to the traversal process of the decoding tree and continue processing the next branch node of the parent node of the special node; until all nodes of the decoding tree have been traversed, output the decoding result.

6. The decoding method according to claim 5, characterized in that, In A1, the online identification of special node types specifically involves: adopting a bottom-up node merging method, starting from a leaf node of length 2, merging upwards layer by layer according to a preset node merging rule until the maximum node length supported by the decoder is reached, thereby identifying the types of all higher-level nodes; the node merging rule corresponds to the distribution pattern characteristics of four special nodes: R0, R1, REP, and SPC, where the distribution pattern of R0 nodes is all 0s, the distribution pattern of R1 nodes is all 1s, the distribution pattern of REP nodes is all 0s except for the last bit which is 1, and the distribution pattern of SPC nodes is all 1s except for the first bit which is 0.

7. The decoding method according to claim 5, characterized in that, In A1, the specific steps for generating the corresponding decoding instructions are as follows: Visit all reserved special nodes in depth-first traversal order. When a non-special node is visited, generate f(・) or g(・) operation instructions. When a special node is visited, generate special node decoding instructions of the corresponding type. At the same time, use the lowest common ancestor algorithm to generate partial sum calculation instructions or g(・) operation instructions.

8. The decoding method according to claim 5, characterized in that, In A2, the calculation formulas for the f(・) and g(・) operations are as follows: f(・) operation: ； g(・) operation: ； Where α is the LLR value, β is the bit value after the decision, j is the level of the node, and i is the index of the node at that level.

9. The decoding method according to claim 5, characterized in that, In A2, when processing special nodes, the path metric PM is calculated for each path and input into the 2L to L path filter for path filtering. The path metric PM is calculated as follows: For node R0, the decision is all 0s, and the path metric penalty value is: ； For a REP node, after one path split, the metric penalty values ​​for the two paths are as follows: ； Where s is the exponent of the node length, l is the path index, HD(x) is the decision function, which returns 0 when x≥0 and 1 otherwise, and m is the index of the bits within the node.

10. The decoding method according to claim 5, characterized in that, In A2, the formula for calculating the partial sum is: ； By utilizing the XOR computation part and storage feedback part of the partial sum computation unit (PSU), the multi-level partial sum computation of the node is completed across levels within a single cycle, and the hard information of the decided bits is transmitted to the higher level of the decoding tree.

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