Method for optimizing industrial ethernet protocol stack and related device

Abstract

The application is suitable for the technical field of industrial Ethernet, and provides an industrial Ethernet protocol stack optimization method and related equipment, the method comprising: loading frame header data of a plurality of first industrial Ethernet protocol frames to a vector register to perform parameter extraction and check calculation, and performing protocol feature classification on a second industrial Ethernet protocol frame with a passed check result to obtain a protocol classification result; determining a home protocol stack instance of the second industrial Ethernet protocol frame and generating a processing completion signal; determining a target protocol stack instance to be scheduled to run on an upper processor, selectively saving general registers occupied by a current protocol stack instance to a context saving area, and selectively restoring the general registers according to the target protocol stack instance to complete context switching. The application solves the technical problems of low communication processing efficiency and low switching certainty of the prior art.

Description

Technical Field

[0001] This invention relates to the field of industrial Ethernet technology, and in particular to an industrial Ethernet protocol stack optimization method and related equipment. Background Technology

[0002] Processors based on the LoongArch instruction set architecture have been applied to industrial automation equipment such as PLCs and industrial edge controllers. These devices often need to run multiple industrial real-time Ethernet protocol stacks simultaneously, such as EtherCAT master, Profinet device, and EPA slave, which places high demands on protocol frame processing efficiency and deterministic switching between multiple protocol stacks.

[0003] In existing industrial Ethernet protocol stack software solutions, the processing stages of protocol frame parsing, protocol type identification and distribution, target protocol stack code execution, and multi-protocol stack instance scheduling are typically completed independently. No direct data-level connection is established between these stages, and they are implemented using general scalar instructions or general operating system scheduling strategies, without specifically adapting to the vector processing, custom instructions, and binary translation features inherent in the LoongArch instruction set. Consequently, when multiple protocols run in parallel on this type of processor platform, the processing stages are fragmented and execute independently. The results of one stage cannot directly support the judgment and execution of the next stage, making it difficult to form a collaborative and optimized processing chain. Therefore, this leads to the technical problems of low processing efficiency and low switching determinism in multi-protocol industrial Ethernet communication on the Loongson platform. Summary of the Invention

[0004] This invention provides an industrial Ethernet protocol stack optimization method and related equipment, which solves the technical problems of low processing efficiency and low switching determinism in multi-protocol industrial Ethernet communication in the prior art.

[0005] In a first aspect, embodiments of this application provide an industrial Ethernet protocol stack optimization method, including: The header data of multiple first industrial Ethernet protocol frames are loaded into a vector register to perform parameter extraction and verification calculation. Then, the second industrial Ethernet protocol frames that pass the verification are classified according to their protocol features to obtain the protocol classification results. Based on the protocol classification results, the belonging protocol stack instance of the second industrial Ethernet protocol frame is determined, and binary translation is performed on the belonging protocol stack instance to generate a processing completion signal; Based on the processing completion signal, the target protocol stack instance to be scheduled to run on the processor is determined. The general-purpose registers occupied by the current protocol stack instance are selectively saved to the corresponding context storage area. The general-purpose registers are selectively restored according to the target protocol stack instance, thereby completing the context switch between the current protocol stack instance and the target protocol stack instance.

[0006] Optionally, in a first implementation of the first aspect of the present invention, the step of loading the frame header data of multiple first industrial Ethernet protocol frames into a vector register to perform parameter extraction and verification calculation, and classifying the second industrial Ethernet protocol frames whose verification results are passed to obtain a protocol classification result, includes: Call the LSX vector load instruction or LASX vector load instruction to load the frame header data of multiple first industrial Ethernet protocol frames into the vector register, and obtain the frame header data and the frame header data base address; The protocol type field and address field in the vector register are extracted by calling vector comparison instructions and vector bit manipulation instructions; the frame verification status corresponding to each first industrial Ethernet protocol frame is obtained, and the verification result is obtained; Based on the channel position of the frame header data in the vector register, the protocol type field, the address field, the verification result, and the frame header data base address corresponding to the first industrial Ethernet protocol frame at the same channel position are associated, and the first industrial Ethernet protocol frame with the verification result passed is used as the second industrial Ethernet protocol frame. The second industrial Ethernet protocol frame is classified according to its protocol features to obtain the protocol classification result.

[0007] Optionally, in a second implementation of the first aspect of the present invention, the step of classifying the protocol features of the second industrial Ethernet protocol frame to obtain a protocol classification result includes: Create a custom classification instruction for the second industrial Ethernet protocol frame, and read the protocol feature field in the frame header data according to the frame header data base address of the second industrial Ethernet protocol frame; The protocol feature fields are compared in parallel with each protocol feature template in the protocol feature template table. The first protocol feature template that is successfully matched is selected according to the order of the protocol feature templates in the protocol feature template table. If none of the protocol feature templates are successfully matched, the default protocol feature template in the protocol feature template table is selected as the first protocol feature template that is successfully matched. The protocol type encoding, matching priority, and protocol stack instance index corresponding to the first successfully matched protocol feature template are written into the destination register to obtain the protocol classification result.

[0008] Optionally, in a third implementation of the first aspect of the present invention, the step of determining the home protocol stack instance of the second industrial Ethernet protocol frame based on the protocol classification result and performing binary translation on the home protocol stack instance to generate a processing completion signal includes: The protocol stack instance to which the second industrial Ethernet protocol frame belongs is determined based on the protocol stack instance index in the protocol classification result, and the dynamic translation cache is queried based on the frame processing function binary code of the protocol stack instance to obtain the cache query result; The local instruction sequence is determined and executed based on the cache query result, and the execution result is obtained. Based on the execution result, a processing completion signal for the second industrial Ethernet protocol frame by the home protocol stack instance is generated.

[0009] Optionally, in a fourth implementation of the first aspect of the present invention, the step of determining and executing a local instruction sequence based on the cache query result to obtain an execution result, and generating a processing completion signal for the second industrial Ethernet protocol frame by the home protocol stack instance based on the execution result, includes: When the cache query result is a hit, the local instruction sequence is read from the dynamic translation cache and execution is initiated. When the cache query result is a miss, the dynamic binary translation module is called to translate the binary code of the frame processing function, and the translation is accelerated by combining the LoongArch binary translation extension to obtain the local instruction sequence and execute it; The execution result of the local instruction sequence is obtained and a processing completion signal for the second industrial Ethernet protocol frame by the home protocol stack instance is generated.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the step of determining the target protocol stack instance to be scheduled to run on the processor based on the processing completion signal, selectively saving the general-purpose registers occupied by the current protocol stack instance to the corresponding context storage area, and selectively restoring the general-purpose registers according to the target protocol stack instance to complete the context switch between the current protocol stack instance and the target protocol stack instance includes: During the compilation phase of each protocol stack instance, static analysis is performed on the general-purpose registers actually read and written by the frame processing function to generate a register usage bitmap corresponding to each protocol stack instance. When the processing completion signal indicates that the current protocol stack instance has been processed, the target protocol stack instance is determined according to the matching priority in the protocol classification result; The atomic register save instruction is invoked, using the register usage bitmap corresponding to the current protocol stack instance as a mask, to save only the general-purpose registers marked as used in the register usage bitmap to the context save area of ​​the current protocol stack instance; Using the register usage bitmap corresponding to the target protocol stack instance as a mask, the saved register data stored in the context save area when the target protocol stack instance was last switched out of the processor is selectively restored, thereby completing the context switch between the current protocol stack instance and the target protocol stack instance.

[0011] Secondly, embodiments of this application provide an industrial Ethernet protocol stack optimization device, comprising: The protocol classification module is used to load the frame header data of multiple first industrial Ethernet protocol frames into a vector register to perform parameter extraction and verification calculation, and to classify the protocol features of the second industrial Ethernet protocol frames that pass the verification to obtain the protocol classification result. The processing module is used to determine the home protocol stack instance of the second industrial Ethernet protocol frame based on the protocol classification result and perform binary translation on the home protocol stack instance to generate a processing completion signal; The context switching module is used to determine the target protocol stack instance to be scheduled to run on the processor based on the processing completion signal, selectively save the general-purpose registers occupied by the current protocol stack instance to the corresponding context saving area, and selectively restore the general-purpose registers according to the target protocol stack instance, thereby completing the context switching between the current protocol stack instance and the target protocol stack instance.

[0012] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described industrial Ethernet protocol stack optimization method.

[0013] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described industrial Ethernet protocol stack optimization method.

[0014] Fifthly, embodiments of this application provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the above-described industrial Ethernet protocol stack optimization method.

[0015] In one of the solutions provided by the aforementioned industrial Ethernet protocol stack optimization method and related equipment, the frame header data of multiple industrial Ethernet protocol frames are loaded into a vector register at once through a vector loading instruction. Then, the fields of multiple frames in the same vector register are extracted simultaneously through vector comparison instructions and vector bit operation instructions, and the frame check status corresponding to each industrial Ethernet protocol frame is obtained. This allows the parsing actions of multiple protocol frames to be carried out in parallel within the same processing cycle, which is different from the method of processing frame by frame by calling scalar instructions sequentially. This establishes a clear data transmission relationship between the parsing results and the classification stage, avoiding the problem that the parsing stage and the classification stage are independent of each other and the results are not mutually compatible. This invention inputs the frame header data base address and the protocol feature template table base address into a custom classification instruction for parallel matching. It consolidates the processing logic, which originally relied on software looping and comparing protocol feature fields one by one, into a single instruction executed by the processor hardware execution unit. This invention allows existing protocol stack key function binary code to run on Loongson processors without rewriting or recompiling. Furthermore, by judging hot paths of high-frequency call paths and dynamically translating cache queries, repeatedly called protocol stack key functions can directly execute the local instruction sequence that has already been translated in the cache, reducing the processing overhead caused by repeated translation of the same function. This invention determines the target protocol stack instance to be switched based on the matching priority and processing completion signal output from the preceding steps. Based on the pre-generated register usage bitmap for each protocol stack instance, it selectively saves and restores only a subset of the general-purpose registers actually used by that instance, instead of uniformly saving and restoring all general-purpose registers. This simplifies the context switching process between protocol stack instances, and the switching timing is directly bound to the priority information and execution status output from the preceding steps, no longer determined solely by a general scheduling strategy. This invention can better meet the application requirements of LoongArch instruction set characteristics in industrial Ethernet multi-protocol parallel processing scenarios. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an industrial Ethernet protocol stack optimization system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating an industrial Ethernet protocol stack optimization method according to an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S100; Figure 4 yes Figure 2 A schematic diagram of the implementation process of step S200; Figure 5 yes Figure 2 A schematic diagram of the implementation process of step S300; Figure 6 This is a timing interaction diagram of an industrial Ethernet protocol stack optimization system according to an embodiment of the present invention; Figure 7 This is a schematic diagram of an industrial Ethernet protocol stack optimization device according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0020] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0022] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0023] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0024] To address the problems mentioned above in the background art, this application proposes an industrial Ethernet protocol stack optimization method and related equipment. The industrial Ethernet protocol stack optimization method provided by this invention can be applied to applications such as... Figure 1 The industrial Ethernet protocol stack optimization system shown includes a vectorized protocol frame parsing device 1, a custom instruction protocol frame classification device 2, a binary translation compatibility acceleration device 3, and a fast context switching scheduling device 4.

[0025] In one embodiment, such as Figure 2 As shown, an industrial Ethernet protocol stack optimization method is provided, which is applied to... Figure 1 Taking the industrial Ethernet protocol stack optimization system as an example, the following steps are included: S100: Load the frame header data of multiple first industrial Ethernet protocol frames into the vector register to perform parameter extraction and verification calculation, and classify the protocol features of the second industrial Ethernet protocol frames that pass the verification to obtain the protocol classification result; S200: Determine the home protocol stack instance of the second industrial Ethernet protocol frame based on the protocol classification result, and perform binary translation on the home protocol stack instance to generate a processing completion signal; S300: Based on the processing completion signal, determine the target protocol stack instance to be scheduled to run on the processor, selectively save the general-purpose registers occupied by the current protocol stack instance to the corresponding context saving area, and selectively restore the general-purpose registers according to the target protocol stack instance to complete the context switch between the current protocol stack instance and the target protocol stack instance.

[0026] In this embodiment, the header data of multiple industrial Ethernet protocol frames are loaded into the vector register at once using a vector loading instruction. Then, the fields of multiple frames in the same vector register are extracted simultaneously using vector comparison instructions and vector bit manipulation instructions. The frame check status corresponding to each industrial Ethernet protocol frame is obtained, so that the parsing actions of multiple protocol frames are carried out in parallel within the same processing cycle. This is different from the method of calling scalar instructions frame by frame for sequential processing. This establishes a clear data transmission relationship between the parsing results and the classification stage, avoiding the problem that the parsing stage and the classification stage are independent of each other and the results are not mutually compatible. This invention inputs the frame header data base address and the protocol feature template table base address into a custom classification instruction for parallel matching. It consolidates the processing logic, which originally relied on software looping and comparing protocol feature fields one by one, into a single instruction executed by the processor hardware execution unit. This invention allows existing protocol stack key function binary code to run on Loongson processors without rewriting or recompiling. Furthermore, by judging hot paths of high-frequency call paths and dynamically translating cache queries, repeatedly called protocol stack key functions can directly execute the local instruction sequence that has already been translated in the cache, reducing the processing overhead caused by repeated translation of the same function. This invention determines the target protocol stack instance to be switched based on the matching priority and processing completion signal output from the preceding steps. Based on the pre-generated register usage bitmap for each protocol stack instance, it selectively saves and restores only a subset of the general-purpose registers actually used by that instance, instead of uniformly saving and restoring all general-purpose registers. This simplifies the context switching process between protocol stack instances, and the switching timing is directly bound to the priority information and execution status output from the preceding steps, no longer determined solely by a general scheduling strategy. This invention can better meet the application requirements of LoongArch instruction set characteristics in industrial Ethernet multi-protocol parallel processing scenarios.

[0027] In one embodiment, such as Figure 3 As shown, step S100 specifically includes the following steps: S101: Call the LSX vector loading instruction or LASX vector loading instruction to load the frame header data of multiple first industrial Ethernet protocol frames into the vector register, and obtain the frame header data and the frame header data base address; S102: Call the vector comparison instruction and vector bit operation instruction to extract the protocol type field and address field in the vector register; obtain the frame check status corresponding to each first industrial Ethernet protocol frame and obtain the check result; S103: Based on the channel position of the frame header data in the vector register, associate the protocol type field, address field, verification result and frame header data base address of the first industrial Ethernet protocol frame at the same channel position, and use the first industrial Ethernet protocol frame with the verification result of passing as the second industrial Ethernet protocol frame. S104: Perform protocol feature classification on the second industrial Ethernet protocol frame to obtain the protocol classification result.

[0028] In this embodiment, a batch frame receiving buffer is set up between the industrial Ethernet MAC receiving queue and the vectorized protocol frame parsing device. When the MAC controller continuously receives multiple first industrial Ethernet protocol frames, it records the starting storage address of each first industrial Ethernet protocol frame in the receiving buffer according to the receiving order, and uses the starting storage address as the corresponding frame header data base address. At the same time, a batch sequence number and vector channel position are assigned to each first industrial Ethernet protocol frame to maintain a one-to-one correspondence between the frame header data, the frame header data base address, and the vector channel. The processor selects the LSX vector loading instruction or the LASX vector loading instruction according to the data size of the current batch. When using the LSX vector loading instruction, the frame header data is read with a 128-bit vector width. When using the LASX vector loading instruction, the frame header data is read with a 256-bit vector width. The corresponding frame header area is obtained from the batch frame receiving buffer according to the base address of each frame header data, and the fields that need to be processed in parallel are organized into different channels of the vector register. The Ethernet basic frame header is 14 bytes long. Therefore, a 128-bit vector can hold a complete basic frame header and reserve some remaining space, while a 256-bit vector can carry more data to be processed in parallel. In the actual organization process, according to the fixed position of the protocol field in the frame header, the key fields from multiple first industrial Ethernet protocol frames can be mapped to the corresponding vector channels respectively, and the frame header data base address corresponding to each channel can be retained synchronously.

[0029] In this embodiment, the processor calls vector bit manipulation instructions based on the fixed byte positions of each field in the Ethernet frame header to perform shift, mask, and combination processing on the target byte in the vector register, and calls vector comparison instructions to identify fields in multiple channels in parallel, thereby obtaining the protocol type field and address field corresponding to each first industrial Ethernet protocol frame. The protocol type field may include the EtherType field, and the address field may include the destination MAC address and the source MAC address. At the same time, the processor reads the reception status generated by the MAC controller for multiple first industrial Ethernet protocol frames, extracts the frame verification status from the reception status corresponding to each first industrial Ethernet protocol frame, obtains the verification result corresponding to each vector channel, and records the verification result as a pass or fail status. For example, 1 can be used to indicate verification pass and 0 can be used to indicate verification fail.

[0030] After field extraction and verification, this embodiment uses the vector channel position as the association basis. The protocol type field, address field, and verification result output by the same channel are combined with the corresponding frame header data base address of that channel, thus forming the parsing record corresponding to each first industrial Ethernet protocol frame. For example, the protocol type field, address field, and verification result output by channel 0 are associated with the frame header data base address corresponding to channel 0; the corresponding data output by channel 1 is associated with the frame header data base address corresponding to channel 1, and so on. This ensures that multiple sets of parsing results obtained from batch parallel processing can still correspond to the original first industrial Ethernet protocol frames. For first industrial Ethernet protocol frames that fail verification, they are no longer passed to protocol feature classification processing. For first industrial Ethernet protocol frames that pass verification, they are identified as second industrial Ethernet protocol frames, and the corresponding frame header data base address, protocol type field, and address field are retained. The second industrial Ethernet protocol frame is sent to the protocol feature classification process. The protocol feature fields required for subsequent classification are read according to the corresponding frame header data base address. The protocol type, matching priority and corresponding protocol stack instance index are determined by combining the pre-set protocol feature template to obtain the protocol classification result. Thus, multiple first industrial Ethernet protocol frames enter the protocol feature classification stage after passing through batch vector loading, parallel field extraction, frame verification status acquisition, channel association and valid frame filtering in sequence.

[0031] In one embodiment, step S104 specifically includes the following steps: Create a custom classification instruction for the second industrial Ethernet protocol frame, and read the protocol feature field in the frame header data according to the base address of the frame header data of the second industrial Ethernet protocol frame; The protocol feature fields are compared in parallel with each protocol feature template in the protocol feature template table. The first protocol feature template that is successfully matched is selected according to the order of the protocol feature templates in the protocol feature template table. If none of the protocol feature templates are successfully matched, the default protocol feature template in the protocol feature template table is selected as the first protocol feature template that is successfully matched. Write the protocol type encoding, matching priority, and protocol stack instance index corresponding to the first successfully matched protocol feature template into the destination register to obtain the protocol classification result.

[0032] In this embodiment, a custom classification instruction `proto_classify` for industrial Ethernet protocol frame classification can be defined through the LoongArch custom instruction extension interface. This instruction is configured with two source operands and one destination operand. The first source operand stores the base address of the header data of the second industrial Ethernet protocol frame, the second source operand stores the base address of the protocol feature template table, and the destination operand carries the protocol classification result. After receiving the base address of the header data corresponding to the second industrial Ethernet protocol frame, the processor accesses the frame receive buffer based on this base address and reads the header data required for protocol classification according to the preset field offset positions. The `EtherType` field, destination MAC address, and VLAN-related fields are used as protocol feature fields. For frames that require further differentiation of upper-layer protocols, the protocol number field at the corresponding position can be read according to the frame type indicated by the `EtherType` field, and the read multiple protocol feature fields are sent to the matching execution unit of the custom classification instruction. Simultaneously, a protocol feature template table is pre-established in the resident memory area, and the protocol feature templates are arranged according to the order of matching processing. For example, the EtherCAT protocol feature template, Profinet RT protocol feature template, EPA protocol feature template, EtherNet / IP protocol feature template, and default protocol feature template can be configured sequentially. The EtherCAT protocol feature template has its EtherType set to 0x88A4, matching priority set to 0, and protocol stack instance index set to 0. The Profinet RT protocol feature template has its EtherType set to 0x88A4, matching priority set to 0, and protocol stack instance index set to 0. The RT protocol feature template sets EtherType to 0x8892 and configures a VLAN priority of at least 6 as the matching condition, and sets the protocol stack instance index to 1. The EPA protocol feature template configures the corresponding protocol feature fields according to the actual encapsulation method used by the EPA protocol frame, and configures the destination MAC address, protocol type related fields, and protocol stack instance index 2. The EtherNet / IP protocol feature template can set EtherType to 0x0800 and further match the IP protocol number and TCP or UDP source port and destination port. It further identifies the corresponding EtherNet / IP port based on the TCP protocol number 0x06 or the UDP protocol number 0x11, and sets the protocol stack instance index to 3. The default protocol feature template sets the protocol stack instance index to 4. The custom classification instruction simultaneously sends the read protocol feature fields into multiple template comparison paths, enabling each protocol feature template to complete field comparisons in parallel and form corresponding matching states. Then, the matching states are prioritized according to the order in the protocol feature template table. When one or more protocol feature templates match successfully, the matching template with the highest position in the table is selected as the first successfully matched protocol feature template. When all non-default protocol feature templates fail to match, the default protocol feature template is selected.After determining the target template, this embodiment reads the pre-configured protocol type code, matching priority, and protocol stack instance index of the protocol feature template and writes them into different bit fields of the destination register. For example, the protocol type code is written into bits 7 to 0 of the destination register, the matching priority is written into bits 15 to 8, and the protocol stack instance index is written into bits 31 to 16. Thus, a protocol classification result that simultaneously includes protocol type, scheduling priority, and target protocol stack instance position is formed in one classification operation.

[0033] In one embodiment, such as Figure 4 As shown, step S200 specifically includes the following steps: S201: Determine the belonging protocol stack instance of the second industrial Ethernet protocol frame based on the protocol stack instance index in the protocol classification result, and query the dynamic translation cache based on the frame processing function binary code of the belonging protocol stack instance to obtain the cache query result; S202: Determine the local instruction sequence based on the cache query results and execute it to obtain the execution result. Then, generate a processing completion signal for the second industrial Ethernet protocol frame of the home protocol stack instance based on the execution result.

[0034] In this embodiment, a protocol stack instance mapping table is pre-established for each industrial Ethernet protocol stack instance running in the device. The protocol stack instance index is associated with the corresponding protocol stack instance's runtime context, frame processing function entry address, and frame processing function binary code. For example, protocol stack instance index 0 corresponds to the EtherCAT master protocol stack, protocol stack instance index 1 corresponds to the Profinet protocol stack, protocol stack instance index 2 corresponds to the EPA protocol stack, and protocol stack instance index 3 corresponds to the EtherNet / IP protocol stack. Other protocol frames not matched to a dedicated protocol stack can be processed by the default protocol stack instance. After obtaining the protocol classification result of the second industrial Ethernet protocol frame, the protocol stack instance index is read from the protocol classification result, and the protocol stack instance mapping table is queried using the protocol stack instance index to obtain the corresponding home protocol stack instance. Simultaneously, the frame header data base address of the second industrial Ethernet protocol frame and the protocol type obtained from previous processing are passed to the home protocol stack instance, enabling the home protocol stack instance to locate the second industrial Ethernet protocol frame that needs to be processed. The entry address of the frame processing function corresponding to the protocol stack instance is read, and the binary code of the frame processing function is obtained based on the entry address. The frame processing function can be a key processing function in the protocol stack responsible for protocol frame parsing, state update and data distribution. For the existing protocol stack binary code originally formed for other processor architectures, it is not required to rewrite the entire protocol stack. Instead, the frame processing function binary code is converted into LoongArch native instruction sequence through the dynamic binary translation module, and LoongArch binary translation extension is combined with the translation or native instruction execution process to accelerate the process. The dynamic translation cache pre-sets several cache entries. Each cache entry records at least the entry address of the original frame processing function and the storage location of the corresponding translated LoongArch native instruction sequence. Therefore, the processor can access the dynamic translation cache using the entry address of the current frame processing function as the lookup key and compare the lookup key with the entry addresses recorded in each valid cache entry. If a valid cache entry with the same address exists, the cache lookup result is determined to be a hit, and the storage address of the native instruction sequence stored in that cache entry is read, indicating that the current frame processing function has already completed binary translation and can reuse the existing translation result. If no corresponding cache entry exists, the cache lookup result is determined to be a miss, indicating that the current frame processing function has not yet formed a directly reusable native instruction sequence and needs to enter binary translation processing. For frequently called frame processing functions, the translated LoongArch native instruction sequence can be continuously stored in the dynamic translation cache, and an index relationship can be established using the original frame processing function's entry address. This allows subsequent calls to the same frame processing function by the same protocol stack instance to prioritize querying and reusing the already formed translation result, reducing the processing overhead caused by repeated translations.Based on the obtained cache query results, the local instruction sequence used for this protocol frame processing is further determined. When the cache is hit, the local instruction sequence in the dynamic translation cache is directly read and executed. When the cache is not hit, the dynamic binary translation module is called to convert the binary code of the corresponding frame processing function into a local instruction sequence. After the translation is accelerated by combining the LoongArch binary translation extension, the execution is performed, so that the home protocol stack instance completes the processing of the second industrial Ethernet protocol frame according to the corresponding protocol processing logic and obtains the corresponding execution result. Based on the execution result, a processing completion signal that can characterize the current protocol frame processing status of the home protocol stack instance is generated.

[0035] In one embodiment, step S202 specifically includes the following steps: When the cache query result is a hit, the local instruction sequence is read from the dynamic translation cache and execution is initiated. When the cache lookup result is a miss, the dynamic binary translation module is called to translate the binary code of the frame processing function, and the translation is accelerated by combining the LoongArch binary translation extension to obtain the local instruction sequence and execute it. The execution results of the local instruction sequence are obtained and a processing completion signal for the second industrial Ethernet protocol frame of the home protocol stack instance is generated.

[0036] In this embodiment, the processor uses the frame processing function entry address corresponding to the home protocol stack instance as the query key for the dynamic translation cache, and reads the cache entry status corresponding to the frame processing function entry address. Each valid cache entry in the dynamic translation cache records the original frame processing function entry address, the storage address of the translated LoongArch local instruction sequence, and the cache validity identifier. When the original frame processing function entry address obtained by the query is consistent with the entry address in a valid cache entry, the cache query result is determined as a hit. Then, according to the local instruction sequence storage address recorded in the cache entry, the processor reads the generated LoongArch local instruction sequence from the dynamic translation cache, and directly jumps the processor execution entry to the local instruction sequence. This allows the home protocol stack instance to perform protocol field parsing, protocol status update, and corresponding data processing operations on the second industrial Ethernet protocol frame according to the processing logic of the corresponding frame processing function, thereby omitting the process of performing binary translation again for the same frame processing function.

[0037] In this embodiment, when there is no valid cache entry in the dynamic translation cache corresponding to the entry address of the current frame processing function, the cache lookup result is determined to be a miss, and the binary code of the frame processing function corresponding to the protocol stack instance is obtained. This binary code is submitted to the dynamic binary translation module for processing. The dynamic binary translation module decodes and converts the original binary code according to the instruction semantics, and performs relevant translation acceleration processing in conjunction with the LoongArch binary translation extension to generate a local instruction sequence that can be executed by the current LoongArch processor. After the translation is completed, the obtained local instruction sequence is written to the executable storage area. At the same time, a correspondence is established between the original frame processing function entry address and the local instruction sequence storage address and written to the dynamic translation cache so that when the same frame processing function is called again, the completed translation result can be directly reused. Then, the processor execution entry is transferred to the newly generated local instruction sequence and the processing of the second industrial Ethernet protocol frame is executed. Regardless of whether the local instruction sequence comes from the dynamic translation cache or is newly generated by the dynamic binary translation module, the frame data corresponding to the second industrial Ethernet protocol frame and the running context of the home protocol stack instance are used as processing inputs during execution. After the local instruction sequence is executed, the corresponding execution result is obtained. The execution result is used to indicate whether the current frame processing function has completed the processing of the current second industrial Ethernet protocol frame. When the execution result shows that the protocol processing flow of the current frame has ended normally, the processing completion status corresponding to the home protocol stack instance is set to completion, and a processing completion signal is generated. The processing completion signal is associated with the current home protocol stack instance. If the local instruction sequence has not yet finished executing, the incomplete state is maintained, and the completion notification for the next protocol stack instance is not triggered.

[0038] In one embodiment, such as Figure 5 As shown, step S300 specifically includes the following steps: S301: During the compilation phase of each protocol stack instance, static analysis is performed on the general-purpose registers actually read and written by the frame processing function to generate a register usage bitmap corresponding to each protocol stack instance; S302: When the processing completion signal indicates that the current protocol stack instance has been processed, determine the target protocol stack instance according to the matching priority in the protocol classification results; S303: Call atomic register save instruction, using the register usage bitmap corresponding to the current protocol stack instance as a mask, only saves the general-purpose registers marked as used in the register usage bitmap to the context save area of ​​the current protocol stack instance; S304: Using the register usage bitmap corresponding to the target protocol stack instance as a mask, selectively restore the saved register data stored in the context save area when the target protocol stack instance was last switched out of the processor, and complete the context switch between the current protocol stack instance and the target protocol stack instance.

[0039] In this embodiment, after each protocol stack instance completes compilation and register allocation, static register usage analysis is performed on the frame processing functions of protocol stack instances such as the EtherCAT master protocol stack, Profinet protocol stack, and EPA protocol stack. The control flow graph corresponding to the frame processing function and the local instructions of each basic block are traversed to identify the general-purpose registers involved in the instruction source operands and destination operands. General-purpose registers that may be read or written in different execution branches are merged, thereby obtaining the set of general-purpose registers corresponding to the frame processing process of that protocol stack instance. A 32-bit register usage bitmap is established according to the 32 general-purpose registers of the LoongArch architecture, so that each bit in the bitmap corresponds to the corresponding general-purpose register in a fixed order. When a general-purpose register appears in the register usage set of that protocol stack instance, the corresponding bit is set to 1; otherwise, it is set to 0. The generated register usage bitmap is associated with the protocol stack instance index and the corresponding context storage area, enabling the scheduler to directly obtain the corresponding register usage bitmap through the protocol stack instance index. The scheduler continuously receives processing completion signals from each associated protocol stack instance. When the processing completion signal indicates that the current protocol stack instance has completed processing the second industrial Ethernet protocol frame, the scheduler reads the protocol classification result corresponding to the current protocol frame to be processed and obtains the matching priority. The protocol stack instances in the waiting state are compared according to the matching priority. For example, the scheduling priority can be set from high to low according to the order of EtherCAT master protocol stack, Profinet protocol stack, EPA protocol stack and default Ethernet protocol stack. The scheduler selects the protocol stack instance with the highest matching priority from the protocol stack instances with the protocol frames to be processed as the target protocol stack instance. At the same time, the scheduler obtains the register usage bitmap of the current protocol stack instance, the register usage bitmap of the target protocol stack instance and the context storage area of ​​each of them.

[0040] After determining the switching target in this embodiment, the processor uses the register usage bitmap corresponding to the current protocol stack instance as a save mask to call the atomic register save instruction. It checks the register usage bitmap bit by bit, performs the save operation only for general-purpose registers marked as 1, and does not perform invalid data writing for general-purpose registers marked as 0. It writes the register contents that need to be saved into the context save area pre-allocated by the current protocol stack instance according to the fixed storage location corresponding to the register number. For example, if the bitmap of a certain protocol stack instance only marks 12 general-purpose registers, then this switch-out process only saves the data corresponding to these 12 registers, without having to save all 32 general-purpose registers at once. This reduces the register access and memory write operations required in the context save stage. After selectively saving the current protocol stack instance, the register usage bitmap corresponding to the target protocol stack instance is read. This bitmap is then used as a recovery mask to access the context save area of ​​the target protocol stack instance. The context save area retains the saved register data formed when the target protocol stack instance was last switched out of the processor. The processor retrieves the corresponding data according to the register positions marked as 1 in the bitmap and writes them back to the corresponding general-purpose registers. However, no recovery operation is performed on the positions marked as 0 in the bitmap, thus allowing the target protocol stack instance to regain the register state saved from its last stop operation. After the register recovery is complete, the processor's execution control is transferred to the target protocol stack instance, allowing the target protocol stack instance to continue executing the corresponding frame processing task and synchronously update it to the current protocol stack instance. This forms a continuous context switching process consisting of processing completion signal triggering, target protocol stack instance selection based on matching priority, selective saving of the current protocol stack instance, and selective recovery of the target protocol stack instance. This ensures that the scope of register saving and recovery is determined by the actual set of general-purpose registers used by each protocol stack instance, rather than performing a unified saving and recovery of all general-purpose registers with each switch.

[0041] like Figure 6 As shown, the vectorized protocol frame parsing device 1 transmits the frame header data base address set to the custom instruction protocol frame classification device 2; the custom instruction protocol frame classification device 2 transmits the protocol stack instance index to the binary translation compatibility acceleration device 3; the custom instruction protocol frame classification device 2 transmits the protocol matching priority to the fast context switching scheduling device 4; the binary translation compatibility acceleration device 3 transmits the processing completion status and time occupied data to the fast context switching scheduling device 4; and the fast context switching scheduling device 4 issues the next processing cycle scheduling instruction to the vectorized protocol frame parsing device 1.

[0042] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0043] In one embodiment, an industrial Ethernet protocol stack optimization device is provided, which corresponds one-to-one with the industrial Ethernet protocol stack optimization method described in the above embodiments. For example... Figure 7 As shown, the industrial Ethernet protocol stack optimization device includes: The protocol classification module 701 is used to load the frame header data of multiple first industrial Ethernet protocol frames into a vector register to perform parameter extraction and verification calculation, and to perform protocol feature classification on the second industrial Ethernet protocol frames that pass the verification to obtain the protocol classification result. Processing module 702 is used to determine the home protocol stack instance of the second industrial Ethernet protocol frame based on the protocol classification result and perform binary translation on the home protocol stack instance to generate a processing completion signal; The context switching module 703 is used to determine the target protocol stack instance to be scheduled to run on the processor based on the processing completion signal, selectively save the general-purpose registers occupied by the current protocol stack instance to the corresponding context saving area, and selectively restore the general-purpose registers according to the target protocol stack instance, thereby completing the context switching between the current protocol stack instance and the target protocol stack instance.

[0044] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0045] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0046] This application also provides a computer device, such as... Figure 8As shown, the computer device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0047] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0048] Those skilled in the art will understand that Figure 8 The computer device described is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0049] The aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0050] The memory can be an internal storage unit of the computer device, such as a hard drive or RAM. The memory can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory can include both internal and external storage units of the computer device.

[0051] This application also provides a readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above.

[0052] This application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the steps described in the various method embodiments above.

[0053] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0054] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0055] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0056] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0057] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0058] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An industrial Ethernet protocol stack optimization method, characterized in that, include: Call the LSX or LASX vector loading instruction to load the frame header data of multiple first industrial Ethernet protocol frames into the vector register to obtain the frame header data and frame header data base address; call the vector comparison instruction and vector bit operation instruction to extract the protocol type field and address field in the vector register; obtain the frame check status corresponding to each first industrial Ethernet protocol frame to obtain the check result; Based on the channel position of the frame header data in the vector register, the protocol type field, the address field, the verification result, and the frame header data base address corresponding to the first industrial Ethernet protocol frame at the same channel position are associated, and the first industrial Ethernet protocol frame with the verification result passed is used as the second industrial Ethernet protocol frame. The second industrial Ethernet protocol frame is classified by protocol features to obtain the protocol classification result; The protocol stack instance to which the second industrial Ethernet protocol frame belongs is determined based on the protocol stack instance index in the protocol classification result. The dynamic translation cache is queried based on the frame processing function binary code of the protocol stack instance to obtain the cache query result. The local instruction sequence is determined and executed based on the cache query result to obtain the execution result. The processing completion signal of the protocol stack instance for the second industrial Ethernet protocol frame is generated based on the execution result. Based on the processing completion signal, the target protocol stack instance to be scheduled to run on the processor is determined. The general-purpose registers occupied by the current protocol stack instance are selectively saved to the corresponding context storage area. The general-purpose registers are selectively restored according to the target protocol stack instance, thereby completing the context switch between the current protocol stack instance and the target protocol stack instance.

2. The industrial Ethernet protocol stack optimization method as described in claim 1, characterized in that, The process of classifying the protocol features of the second industrial Ethernet protocol frame to obtain the protocol classification result includes: Create a custom classification instruction for the second industrial Ethernet protocol frame, and read the protocol feature field in the frame header data according to the frame header data base address of the second industrial Ethernet protocol frame; The protocol feature fields are compared in parallel with each protocol feature template in the protocol feature template table. The first protocol feature template that is successfully matched is selected according to the order of the protocol feature templates in the protocol feature template table. If none of the protocol feature templates are successfully matched, the default protocol feature template in the protocol feature template table is selected as the first protocol feature template that is successfully matched. The protocol type encoding, matching priority, and protocol stack instance index corresponding to the first successfully matched protocol feature template are written into the destination register to obtain the protocol classification result.

3. The industrial Ethernet protocol stack optimization method as described in claim 2, characterized in that, The step of determining and executing the local instruction sequence based on the cache query result, obtaining the execution result, and generating a processing completion signal for the second industrial Ethernet protocol frame by the home protocol stack instance based on the execution result includes: When the cache query result is a hit, the local instruction sequence is read from the dynamic translation cache and execution is initiated. When the cache query result is a miss, the dynamic binary translation module is called to translate the binary code of the frame processing function, and the translation is accelerated by combining the LoongArch binary translation extension to obtain the local instruction sequence and execute it; The execution result of the local instruction sequence is obtained and a processing completion signal for the second industrial Ethernet protocol frame by the home protocol stack instance is generated.

4. The industrial Ethernet protocol stack optimization method as described in claim 3, characterized in that, The step of determining the target protocol stack instance to be scheduled to run on the processor based on the processing completion signal, selectively saving the general-purpose registers occupied by the current protocol stack instance to the corresponding context saving area, and selectively restoring the general-purpose registers according to the target protocol stack instance to complete the context switch between the current protocol stack instance and the target protocol stack instance includes: During the compilation phase of each protocol stack instance, static analysis is performed on the general-purpose registers actually read and written by the frame processing function to generate a register usage bitmap corresponding to each protocol stack instance. When the processing completion signal indicates that the current protocol stack instance has been processed, the target protocol stack instance is determined according to the matching priority in the protocol classification result; The atomic register save instruction is invoked, using the register usage bitmap corresponding to the current protocol stack instance as a mask, to save only the general-purpose registers marked as used in the register usage bitmap to the context save area of ​​the current protocol stack instance; Using the register usage bitmap corresponding to the target protocol stack instance as a mask, the saved register data stored in the context save area when the target protocol stack instance was last switched out of the processor is selectively restored, thereby completing the context switch between the current protocol stack instance and the target protocol stack instance.

5. An industrial Ethernet protocol stack optimization device, characterized in that, The steps for implementing the industrial Ethernet protocol stack optimization method as described in any one of claims 1 to 4 include: The protocol classification module is used to call the LSX or LASX vector loading instruction to load the frame header data of multiple first industrial Ethernet protocol frames into a vector register, obtaining the frame header data and the frame header data base address; call the vector comparison instruction and vector bit operation instruction to extract the protocol type field and address field from the vector register; obtain the frame verification status corresponding to each first industrial Ethernet protocol frame, and obtain the verification result; according to the channel position of the frame header data in the vector register, associate the protocol type field, the address field, the verification result, and the frame header data base address corresponding to the first industrial Ethernet protocol frames at the same channel position, and use the first industrial Ethernet protocol frames with the verification result of passing as second industrial Ethernet protocol frames; perform protocol feature classification on the second industrial Ethernet protocol frames to obtain the protocol classification result; The processing module is configured to determine the home protocol stack instance of the second industrial Ethernet protocol frame based on the protocol stack instance index in the protocol classification result, and query the dynamic translation cache based on the frame processing function binary code of the home protocol stack instance to obtain the cache query result; determine the local instruction sequence based on the cache query result and execute it to obtain the execution result, and generate a processing completion signal for the home protocol stack instance of the second industrial Ethernet protocol frame based on the execution result. The context switching module is used to determine the target protocol stack instance to be scheduled to run on the processor based on the processing completion signal, selectively save the general-purpose registers occupied by the current protocol stack instance to the corresponding context saving area, and selectively restore the general-purpose registers according to the target protocol stack instance, thereby completing the context switching between the current protocol stack instance and the target protocol stack instance.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the industrial Ethernet protocol stack optimization method as described in any one of claims 1 to 4.

7. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the industrial Ethernet protocol stack optimization method as described in any one of claims 1 to 4.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the industrial Ethernet protocol stack optimization method as described in any one of claims 1 to 4.

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