Red light LED epitaxial structure and manufacturing method thereof, and LED chip

Abstract

The application discloses a red light LED epitaxial structure and a manufacturing method thereof, and an LED chip. The reflection structure layer of the epitaxial structure comprises a reflection layer and a current expansion layer. The reflection layer comprises a first reflection layer and a second reflection layer which are oppositely located on two sides of the current expansion layer. The reflection layer comprises a plurality of reflection period layers and stress adjusting layers which are periodically arranged between the reflection period layers. The reflection period layer comprises a first sublayer and a second sublayer which are stacked and have different refractive indexes. The four functions of optical reflection, stress regulation, heat conduction and current expansion are realized. In the embodiment, the setting of the reflection structure layer not only considers the optical performance, but also considers the heat, electricity and mechanics, and the synergistic optimization of the optical, thermal, electrical and mechanical properties is realized. Compared with the traditional DBR, the single performance optimization is upgraded to multi-dimensional synergistic optimization, and the comprehensive requirements of heat dissipation, current uniformity and long-term reliability for high-end applications can be met simultaneously.

Description

Technical Field

[0001] This application relates to the field of LED technology, and in particular to a red LED epitaxial structure and its fabrication method, as well as an LED chip. Background Technology

[0002] The AlGaInP material system is currently the mainstream technology for fabricating high-brightness red LEDs. By controlling the composition ratio of Al, Ga, and In, it can achieve efficient light emission in the 620nm-660nm wavelength range, and is widely used in display backlighting, general lighting, and other fields. With the increasing demands for wavelength stability, antistatic properties, and heat dissipation performance from high-end applications such as Mini / Micro LED displays and automotive lighting, these requirements are becoming more stringent.

[0003] In the epitaxial structure of red LEDs, the Distributed Bragg Reflector (DBR) is a key functional layer located between the substrate and the active region. Its function is to reflect the light emitted from the active region toward the substrate back to the light-emitting surface, thereby significantly improving the external quantum efficiency and light output brightness of the device.

[0004] However, existing distributed Bragg reflector designs only focus on optimizing optical reflection performance, without considering the synergistic design of thermal, electrical, and mechanical properties, and cannot simultaneously meet the comprehensive requirements of high-end applications for heat dissipation, current uniformity, and long-term reliability. Summary of the Invention

[0005] In view of the above problems, this application provides a red LED epitaxial structure and its fabrication method, as well as an LED chip, to achieve synergistic design of optical, thermal, electrical, and mechanical properties, which is beneficial for simultaneously meeting the comprehensive requirements of high-end applications for heat dissipation, current uniformity, and long-term reliability. The specific solution is as follows:

[0006] A red LED epitaxial structure includes: a stacked substrate, a reflective structure layer, an N-type structure layer, an active layer, and a P-type structure layer, wherein the reflective structure layer includes a reflective layer and a current spreading layer, and the reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer;

[0007] The reflective layer includes: a plurality of periodic reflective layers and a stress-adjusting layer periodically located between the periodic reflective layers, wherein the periodic reflective layers include a first sub-layer and a second sub-layer with different refractive indices stacked together.

[0008] Optionally, the first sub-layer is an AlInP layer, the second sub-layer is an AlGaInP layer, and the stress-adjusting layer is an AlInP layer.

[0009] Optionally, the conduction band offset of the first sub-layer ranges from 118meV to 208meV, including the endpoint value, and the thickness ranges from 35nm to 50nm, including the endpoint value.

[0010] The conduction band offset of the second sublayer ranges from 162meV to 306meV, including the endpoint values; the band gap ranges from 1.599eV to 1.875eV, including the endpoint values; and the thickness ranges from 35nm to 50nm, including the endpoint values.

[0011] The thickness of the reflective periodic layer ranges from 70 to 100 nm, including the endpoint values. The doped ion is silicon ion. The Fermi level position of the reflective periodic layer ranges from -15 meV to 5 meV, including the endpoint values.

[0012] The conduction band offset of the stress adjustment layer ranges from 162meV to 256meV, including the endpoint value. Along the growth direction of the reflective structure layer, the conduction band offset of the stress adjustment layer increases.

[0013] The thickness of the stress-adjusting layer ranges from 8 nm to 15 nm, including the endpoint values, and the Fermi level position ranges from -15 meV to 5 meV, including the endpoint values.

[0014] The total thickness of the reflective structure layer ranges from 0.77 μm to 2.25 μm, including the endpoint values.

[0015] Optionally, in the reflective layer, a stress adjustment layer is inserted every N reflection period layers, where N ranges from 3 to 6, including the endpoint values.

[0016] Optionally, the current spreading layer is Al. 0.3 Ga 0.2 In 0.5 P layer.

[0017] Optionally, the current spreading layer includes an spreading layer and an auxiliary layer located at least on one side of the spreading layer; wherein the Fermi level position of the auxiliary layer is less than or equal to the Fermi level position of the spreading layer.

[0018] Optionally, the Fermi level position of the auxiliary layer ranges from -7.5 meV to 23.1 meV, including the endpoint value, and the thickness of the auxiliary layer ranges from 40 nm to 60 nm, including the endpoint value.

[0019] The Fermi level position of the extended layer ranges from 23.1 meV to 39.5 meV, including the endpoint value, and the thickness ranges from 100 nm to 140 nm, including the endpoint value.

[0020] Optionally, the current spreading layer includes a first auxiliary layer and a second auxiliary layer located opposite each other on both sides of the spreading layer.

[0021] Optionally, the Fermi level positions of both the first auxiliary layer and the second auxiliary layer are smaller than the Fermi level position of the extended layer;

[0022] The current spreading layer further includes a first intrinsic spacer layer located between the auxiliary layer and the spreading layer.

[0023] Optionally, the current spreading layer comprises alternating stacks of Al 0.1 Ga 0.9 P-layer and GaP layer.

[0024] Optionally, the GaP layer includes a first sub-GaP layer and a second sub-GaP layer stacked along a direction away from the substrate, wherein the Fermi level position of the first sub-GaP layer is smaller than the Fermi level position of the second sub-GaP layer.

[0025] Optionally, the active layer includes a first active layer, a tunnel junction, and a second active layer arranged in a direction away from the substrate; wherein the first active layer includes alternating stacked first barrier layers and first well layers, and the second active layer includes alternating stacked second barrier layers and second well layers.

[0026] The first barrier layer and the second barrier layer are AlGaInP layers, and the bandgap of the first barrier layer is greater than the bandgap of the second barrier layer.

[0027] Optionally, the bandgap width of the first barrier layer ranges from 1.91 eV to 2.01 eV, including the endpoint values;

[0028] The bandgap width of the second barrier layer ranges from 1.85eV to 1.92eV, including the endpoint values.

[0029] Optionally, the first active layer further includes: a first simple well layer located between the first barrier layer and the first well layer; the second active layer includes a second simple well layer located between the second barrier layer and the second well layer;

[0030] Wherein, the lattice constant of the first simple well layer is greater than the lattice constant of the first barrier layer and less than the lattice constant of the first well layer, and the conduction band of the first simple well layer is greater than the conduction band of the first well layer and less than the conduction band of the first barrier layer.

[0031] The lattice constant of the second simple well layer is greater than that of the second barrier layer and less than that of the second well layer. The conduction band of the second simple well layer is greater than that of the second well layer and less than that of the second barrier layer.

[0032] Optionally, the conduction band offset of the first barrier layer ranges from 58 meV to 143 meV, including the endpoint value, and the thickness ranges from 6 nm to 10 nm, including the endpoint value.

[0033] The conduction offset of the first simple well layer ranges from 143meV to 189meV, including the endpoint value, and the thickness ranges from 5nm to 10nm, including the endpoint value.

[0034] The conduction band offset of the first well layer ranges from 0 meV to 25 meV, including the endpoint value; the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint value; and the thickness ranges from 3 nm to 8 nm, including the endpoint value.

[0035] The number of periods of the first barrier layer, the first simple well layer and the first well layer in the first active layer ranges from 3 to 5, including the endpoint values;

[0036] The total thickness of the first active layer ranges from 42nm to 140nm, including the endpoint values;

[0037] The conduction band offset of the second barrier layer ranges from 100meV to 237meV, including the endpoint values, and the thickness ranges from 6nm to 10nm, including the endpoint values.

[0038] The conduction band offset of the second simple well layer ranges from 143meV to 189meV, including the endpoint value, and the thickness ranges from 5nm to 10nm, including the endpoint value.

[0039] The conduction band offset of the second well layer ranges from 0 meV to 25 meV, including the endpoint value; the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint value; and the thickness ranges from 3 nm to 8 nm, including the endpoint value.

[0040] The number of cycles of the second barrier layer, the second simple well layer, and the second well layer in the second active layer ranges from 4 to 6, including the endpoint values;

[0041] The total thickness of the second active layer ranges from 56nm to 168nm, including the endpoint values.

[0042] Optionally, along a direction away from the substrate, the conduction band offset of the first barrier layer increases, and the conduction band offset of the second barrier layer increases.

[0043] Optionally, the number of cycles in the second active layer is greater than the number of cycles in the first active layer.

[0044] Optionally, the number of cycles in the first active layer is the minimum value of its range, and the number of cycles in the second active layer is the maximum value of its range.

[0045] Optionally, the tunnel junction includes an N-type doped GaAs layer and a P-type doped GaAs layer arranged along a direction away from the substrate; wherein,

[0046] The thickness of the N-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoint values, and the Fermi level position ranges from 115 meV to 170 meV, including the endpoint values.

[0047] The thickness of the p-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoint values, and the Fermi level position ranges from 90 meV to 140 meV, including the endpoint values.

[0048] The total thickness of the tunnel junction ranges from 16nm to 24nm, including the endpoint values.

[0049] Optionally, it further includes: a second intrinsic spacer layer located between the first active layer and the tunnel junction, and a third intrinsic spacer layer located between the tunnel junction and the second active layer;

[0050] The second intrinsic spacer layer and the third intrinsic spacer layer are GaAs layers with a thickness of not less than 50 nm.

[0051] An LED chip comprising the red LED epitaxial structure described in any of the preceding claims.

[0052] A method for fabricating a red LED epitaxial structure, applicable to any of the red LED epitaxial structures described above, the method comprising:

[0053] Provide substrate;

[0054] A reflective structure layer, an N-type structure layer, an active layer, and a P-type structure layer are sequentially fabricated on a substrate. The reflective structure layer includes a reflective layer and a current spreading layer. The reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer.

[0055] The reflective layer includes: a plurality of periodic reflective layers and a stress-adjusting layer periodically located between the periodic reflective layers, wherein the periodic reflective layers include a first sub-layer and a second sub-layer with different refractive indices stacked together.

[0056] Optionally, the fabrication of the active layer includes:

[0057] A first active layer is fabricated on the side of the N-type structure layer away from the substrate;

[0058] A tunnel junction is fabricated on the side of the first active layer away from the N-type structural layer;

[0059] A second active layer is fabricated on the side of the tunnel junction away from the first active layer;

[0060] The process of fabricating the tunnel junction includes:

[0061] By introducing a Ga source, an As source, and an N-type doped source, an N-type doped GaAs layer is fabricated on the side of the first active layer away from the N-type structure layer.

[0062] After the N-type doped GaAs layer is grown, the N-type doping source is stopped, and the P-type doping source is introduced at the first time.

[0063] After pausing growth for a second time in the P-type doped atmosphere, a P-type doped GaAs layer is grown on the side of the N-type GaAs layer away from the first active layer.

[0064] The first time ranges from 0.05s to 1s, including the endpoint value, and the second time ranges from 10s to 20s, including the endpoint value.

[0065] Optionally, before introducing the Ga source, As source, and N-type doped source, and fabricating an N-type doped GaAs layer on the side of the first active layer away from the N-type structure layer, the method further includes:

[0066] Introducing Ga and As sources, an intrinsically doped GaAs layer with a predetermined thickness is formed on the side of the first active layer away from the N-type structure layer. The N-type doped GaAs layer is formed on the surface of the intrinsically doped GaAs layer, and the predetermined thickness is not less than 50 nm.

[0067] After growing a P-type doped GaAs layer on the side of the N-type GaAs layer away from the first active layer, the method further includes:

[0068] Stop introducing the P-type doped source, and continue to introduce the Ga source and As source to grow an intrinsically doped GaAs layer on the surface of the P-type doped GaAs layer.

[0069] In the red LED epitaxial structure provided in this application embodiment, the reflective structure layer adopts a three-segment structure of a first reflective layer, a current spreading layer, and a second reflective layer, realizing four functions: optical reflection, stress regulation, heat conduction, and current spreading. That is, in this embodiment, the setting of the reflective structure layer not only considers optical performance, but also thermal, electrical, and mechanical aspects, achieving synergistic optimization of optics, thermal, electrical, and mechanical aspects. Compared with the traditional DBR, it upgrades from single performance optimization to multi-dimensional synergistic optimization, which is beneficial to simultaneously meeting the comprehensive requirements of high-end applications for heat dissipation, current uniformity, and long-term reliability. Attached Figure Description

[0070] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0071] Figure 1 A schematic diagram of a red LED epitaxial structure provided in this application;

[0072] Figure 2 A schematic diagram of another red LED epitaxial structure provided in this application;

[0073] Figure 3 A schematic diagram of the energy band structure of an LED when the reflective structure layer consists only of stacked AlInP and AlGaInP layers;

[0074] Figure 4 A schematic diagram of the energy band structure of an LED when the reflective structure layer includes a first reflective layer, a current spreading layer, and a second reflective layer;

[0075] Figure 5 A schematic diagram of yet another red LED epitaxial structure provided in this application;

[0076] Figure 6 A schematic diagram of the energy band structure of an LED when the active layer adopts a single active region structure;

[0077] Figure 7 A schematic diagram of the energy band structure of an LED when the active layer adopts a dual active region structure consisting of a first active layer, a tunnel junction, and a second active layer;

[0078] Figure 8 A flowchart illustrating a method for fabricating a red LED epitaxial structure provided in this application. Detailed Implementation

[0079] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0080] The terminology used in the embodiments section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. Various modifications and variations can be made to this application without departing from its spirit or scope. Moreover, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems, which is obvious to those skilled in the art. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0081] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0082] As described in the background section, existing distributed Bragg reflector designs only focus on optimizing optical reflection performance, without considering the synergistic design of thermal, electrical, and mechanical properties. This makes it impossible to simultaneously meet the comprehensive requirements of high-end applications for heat dissipation, current uniformity, and long-term reliability.

[0083] Currently, the most commonly used DBR structure is a periodic stacked structure of AlAs / AlGaAs materials. By precisely controlling the refractive index difference and thickness ratio of the two materials, high reflectivity (typically >99%) for specific wavelengths of light can be achieved. However, the intrinsic thermal conductivity of AlAs is only about 2 W / m·K, far lower than that of GaAs substrates (46 W / m·K). Furthermore, phonon scattering at the multilayer interface further hinders heat conduction, making the DBR the main source of thermal resistance in the device. This results in the inability to dissipate heat generated in the active region in a timely manner, leading to a significant increase in the device junction temperature.

[0084] Furthermore, there is a difference in lattice constant between AlAs and AlGaAs. This lattice mismatch generates accumulated stress during the repeated stacking of dozens of periodic layers. When the accumulated stress exceeds the material's critical yield strength, it can induce defects such as dislocations and microcracks. Moreover, as the operating time increases, the stress will further concentrate and be released, accelerating the degradation of device performance and shortening its lifespan.

[0085] In addition, traditional DBR structures are made of high-resistivity materials and do not have current spreading capabilities. When injected current enters the active region from the electrode, due to the lack of a lateral current conduction path, the current mainly flows along the shortest longitudinal path, forming a "current congestion effect". This results in excessively high local current density in the active region, generating hot spots, accelerating local aging, and reducing the device's electrostatic discharge (ESD) immunity.

[0086] In view of this, embodiments of this application provide a red LED epitaxial structure, such as... Figure 1As shown, the epitaxial structure of the red LED includes: a stacked substrate 10, a reflective structure layer 20, an N-type structure layer 30, an active layer 40, and a P-type structure layer 50. The reflective structure layer 20 includes a reflective layer 21 and a current spreading layer 22. The reflective layer 21 includes a first reflective layer 211 and a second reflective layer 212 located opposite each other on both sides of the current spreading layer 22. For example, the first reflective layer 211 is located between the substrate 10 and the current spreading layer 22, and the second reflective layer 212 is located between the current spreading layer 22 and the N-type structure layer 30. Thus, the reflective layer 21 reflects the light emitted from the active layer 40 toward the substrate 10 back to the light-emitting surface of the LED, improving the luminous efficiency of the LED. The current spreading layer 22 improves the lateral current spreading capability of the reflective structure layer 20, alleviating the "current congestion effect". This helps reduce the probability of excessively high local current density in the active layer 40, which could lead to hot spots, thereby avoiding excessively high local temperatures in the LED, delaying local aging of the LED, and improving the LED's electrostatic discharge (ESD) resistance.

[0087] Specifically, in this embodiment, the reflective layer includes multiple periodic reflective layers and a stress-adjusting layer periodically located between the periodic reflective layers. The periodic reflective layer includes a first sub-layer and a second sub-layer with different refractive indices stacked together. That is, the reflective layer includes alternating stacked first sub-layers and second sub-layers with different refractive indices, and a stress-adjusting layer periodically located between the stack of the first sub-layers and the second sub-layers. This allows the light emitted from the active layer onto the substrate to be reflected back to the light-emitting surface of the LED by utilizing the refractive index difference between the first sub-layers and the second sub-layers. The periodically arranged stress-adjusting layer also enables periodic stress relaxation, alleviating stress accumulation in the reflective structure layer, reducing the occurrence of defects such as dislocations and microcracks, mitigating LED performance aging, and extending the LED's lifespan.

[0088] Therefore, in the red LED epitaxial structure provided in this application embodiment, the reflective structure layer adopts a three-segment structure of a first reflective layer, a current spreading layer, and a second reflective layer, realizing four functions: optical reflection, stress regulation, heat conduction, and current spreading. That is, in this embodiment, the setting of the reflective structure layer not only considers optical performance, but also thermal, electrical, and mechanical aspects, realizing the synergistic optimization of optics, thermal, electrical, and mechanical aspects. Compared with the traditional DBR, it upgrades from single performance optimization to multi-dimensional synergistic optimization, which is conducive to simultaneously meeting the comprehensive requirements of high-end applications for heat dissipation, current uniformity, and long-term reliability.

[0089] Optionally, in some embodiments of this application, the N-type structural layer includes an N-type confinement layer, and the P-type structural layer includes a P-type barrier layer, a P-type window layer, and a P-type contact layer. However, this application does not limit this, and the specific implementation depends on the circumstances. For example, the N-type confinement layer is an N-type AlInP confinement layer, and the P-type confinement layer is a P-type AlInP confinement layer. However, this application does not limit this, and the specific implementation depends on the circumstances.

[0090] Optionally, in some embodiments of this application, the red LED epitaxial structure further includes a buffer layer located between the substrate and the reflective structure layer. Exemplarily, the substrate is a GaAs substrate, and the buffer layer is an n-GaAs buffer layer. However, this application does not limit this, and the specific implementation depends on the circumstances.

[0091] Optionally, in some embodiments of this application, the first sub-layer is an AlInP layer, and the second sub-layer is an AlGaInP layer. Since there is a refractive index difference between AlInP and AlGaInP, alternating stacking of AlInP and AlGaInP layers can create a periodic refractive index change, achieving Bragg reflection of light at a specific wavelength and improving the luminous efficiency of the LED.

[0092] The inventors discovered that in the periodic structure of DBR, the phonon spectra (phonon dispersion relation) of adjacent layers are mismatched due to differences in composition and lattice constant. Specifically, high-frequency optical phonons (>10THz) are reflected and mode-switched at the interlayer interface, making them difficult to transmit effectively. This results in a significant reduction in the phonon mean free path, which macroscopically manifests as a decrease in thermal conductivity.

[0093] In the embodiments of this application, the AlInP layer / AlGaInP layer are both InP-based materials with similar bonding characteristics, a smaller degree of phonon spectrum mismatch, reduced interface phonon scattering rate, extended phonon mean free path, and correspondingly reduced interface thermal resistance. This can significantly reduce the operating temperature of the reflective structure layer, alleviate the problem of heat generated in the active region not being able to be dissipated in time, help reduce the LED junction temperature, suppress the exacerbation of the quantum confinement Stark effect (QCSE), and thus improve the wavelength stability and luminous efficiency of the device.

[0094] Optionally, in some embodiments of this application, the conduction band offset of the first sublayer ranges from 118 meV to 208 meV, including the endpoint values. For example, the proportion of Al component in the first sublayer ranges from 0.4 to 0.6, including the endpoint values, meaning the first sublayer is Al. x1 In 1-x1In the P layer, x1 ranges from 0.4 to 0.6, including the endpoints; the thickness of the first sublayer ranges from 35 nm to 50 nm, including the endpoints; the conduction band offset of the second sublayer ranges from 162 meV to 306 meV, including the endpoints, and the band gap ranges from 1.599 eV to 1.875 eV, including the endpoints. For example, the Al component in the second sublayer ranges from 0.5 to 0.8, including the endpoints, and the In component ranges from 0.3 to 0.5, including the endpoints. Therefore, the second sublayer is (Al... x2 Ga 1-x2 ) 1-y1 In y1 The P-layer has x2 ranging from 0.5 to 0.8, inclusive, and y1 ranging from 0.3 to 0.5, inclusive. The thickness of the second sub-layer ranges from 35 nm to 50 nm, inclusive. The thickness of a single stack consisting of the first and second sub-layers ranges from 70 to 100 nm, inclusive. The dopant is silicon. The Fermi level position of the reflective periodic layer ranges from -15 meV to 5 meV, inclusive. For example, the doping concentration of the reflective periodic layer ranges from 3 × 10⁻⁶. 17 ~5×10 17 atoms / cm³, including endpoint values, i.e., the thickness of a single reflective periodic layer ranges from 70 to 100 nm, including endpoint values. The doping ions in both the first and second sublayers are silicon ions, and the doping concentration ranges from 3 × 10⁻⁶. 17 ~5×10 17 atoms / cm³, including endpoint values; however, this application does not limit this, and it depends on the specific circumstances.

[0095] It should be noted that in a single stack, there is approximately 0.3% to 1.2% lattice mismatch between the first and second sublayers. While a single mismatch is small, the mismatch strain energy accumulates linearly with the number of periods. Once a certain thickness is reached, the strain increases, generating non-radiative recombination centers and scattering centers at the interface, which in turn impairs luminescence efficiency and reflectivity. For example, if the thickness of a single stack consisting of the first and second sublayers ranges from 70 to 100 nm, then the total thickness of a stack consisting of six first and second sublayers is 420 nm to 600 nm, which is close to the thickness of the AlGaInP system when the Si doping concentration is 3 × 10⁻⁶. 17 ~5×10 17 atoms / cm 3The critical cumulative thickness of strain energy within the specified range. If the total thickness of the stack consisting of multiple first and second sublayers is less than this thickness, the strain energy is stored elastically (without dislocations). Once it exceeds this thickness, it must be released; otherwise, nonradiative recombination centers and scattering centers will be generated at the interface, impairing luminescence efficiency and reflectivity.

[0096] Therefore, in some embodiments of this application, a stress adjustment layer is inserted every N reflection period layers in the reflective layer, where N ranges from 3 to 6, including the endpoint value. This is to proactively introduce a stress adjustment layer as a "strain buffer" before the stress accumulation in the reflective layer reaches a critical point, allowing the strain energy within each N reflection period layer segment to be managed independently, preventing dislocations from penetrating into the active layer. At the same time, it avoids setting too many stress adjustment layers, which would result in a large total thickness of the reflective structure layer and affect the overall thickness of the red LED epitaxial structure.

[0097] Optionally, in some embodiments of this application, the number of the periodic reflection layers in the reflective structure layer ranges from 30 to 60, including the endpoint values. That is, the total number of periodic reflection layers included in the first and second reflective layers ranges from 30 to 60, including the endpoint values, in order to achieve a high reflectivity of 96% to 97% for the light emitted from the active layer to the substrate. However, this application does not limit this, and it depends on the specific circumstances.

[0098] Optionally, in some embodiments of this application, the conduction band offset of the stress-adjusting layer increases along the growth direction of the reflective structure layer, such as when the stress-adjusting layer is an AlInP layer, i.e., Al x3 In 1-x3 In the P-layer, along the growth direction of the reflective structure layer, the Al composition in the stress-regulating layer increases while the In composition decreases. This periodic arrangement of the stress-regulating layer in the reflective layer achieves periodic stress relaxation, alleviating stress accumulation in the reflective structure layer and significantly improving the long-term stability and lifespan of the LED. Furthermore, by setting a gradual change in composition within the stress-regulating layer, active lattice matching is achieved, reducing the dislocation density of the reflective structure layer from 10... 5 cm -2 Reduced to 5×10 4 cm -2 This reduces the dislocation density of the reflective structure layer by 50%, improving the reliability of the LED.

[0099] Optionally, in one embodiment of this application, the conduction band offset of the stress-adjusting layer ranges from 162 meV to 256 meV, including the endpoint values. For example, the Al composition in the stress-adjusting layer ranges from 0.5 to 0.7, including the endpoint values, i.e., x3 ranges from 0.5 to 0.7, including the endpoint values. The thickness of the stress-adjusting layer ranges from 8 nm to 15 nm, including the endpoint values. The Fermi level position of the stress-adjusting layer ranges from -15 meV to 5 meV, including the endpoint values. For example, the doping concentration of the stress-adjusting layer ranges from 3 × 10⁻⁶. 17 ~5×10 17 atoms / cm³, including endpoint values; however, this application does not limit this, and it depends on the specific circumstances.

[0100] It should be noted that, in the embodiments of this application, the stress-adjusting layer serves as a transition layer between partially reflective periodic layers. Its Al composition transitions continuously along the growth direction, which can also distribute the phonon spectrum mismatch on both sides of the stress-adjusting layer to the thickness range of the stress-adjusting layer. This reduces the phonon mode mismatch rate of a single interface from a large mismatch (e.g., 100%) at abrupt interfaces to a partial mismatch (e.g., 20%–40%) at a gradual interface. The phonon reflectivity decreases significantly, allowing more high-frequency phonons to penetrate the interface, thereby reducing the interfacial thermal resistance between the first sublayer and the second sublayer.

[0101] Furthermore, inserting a stress-modulating layer every N reflection periodic layers significantly reduces the total number of heterostructure interfaces compared to inserting a stress-modulating layer between every pair of periodic layers. Within the N reflection periodic layers without stress-modulating layers, phonon spectral mismatch still exists at the AlInP / AlGaInP interface. However, due to the close proximity of the interfaces, the mismatch is periodically blocked in the longitudinal propagation direction by the subsequently inserted stress-modulating layers, thus preventing the mismatch from continuously accumulating and amplifying along the thickness direction. Therefore, the longitudinal scale of phonon cumulative scattering is limited to the thickness of N reflection periodic layers, rather than the entire thickness of the reflective structure. The shortened scattering path increases the phonon mean free path by 2 to 5 times compared to the reflective structure without stress-modulating layers.

[0102] Based on any of the above embodiments, in some embodiments of this application, the current spreading layer is Al. 0.3 Ga 0.2 In 0.5 The P-layer enhances the lateral diffusion capability of the reflective structure layer, alleviates the "current crowding effect," and helps reduce the probability of excessively high local current density in the active layer, thus preventing excessively high local temperatures of the LED, delaying local aging of the LED, and improving the LED's electrostatic discharge (ESD) resistance.

[0103] Optionally, in some embodiments of this application, the current spreading layer includes: an spreading layer and an auxiliary layer located at least on one side of the spreading layer; wherein the Fermi level position of the auxiliary layer is less than or equal to the Fermi level position of the spreading layer, such as the doping concentration of the auxiliary layer being less than or equal to the doping concentration of the spreading layer. For example, the doping concentration of the auxiliary layer is greater than the doping concentration of the stress-adjusting layer and less than the doping concentration of the spreading layer, so as to reduce the contact resistance between at least one side of the current spreading layer and the reflective layer while enabling the current spreading layer to have lateral current spreading capability.

[0104] Exemplary examples, in some embodiments of this application, such as Figure 2 As shown, the current spreading layer includes an spreading layer 222 and a first auxiliary layer 221 and a second auxiliary layer 223 located opposite each other on both sides of the spreading layer 222. The Fermi level positions of both the first and second auxiliary layers are smaller than the Fermi level position of the spreading layer, such as the doping concentrations of both the first and second auxiliary layers being smaller than the doping concentration of the spreading layer. Specifically, in this embodiment, the first auxiliary layer 221 is located between the spreading layer 222 and the first reflective layer 211, and the second auxiliary layer 223 is located between the spreading layer 222 and the second reflective layer 212, forming a three-segment structure of "auxiliary layer-spreading layer-auxiliary layer". The doping concentrations of both the first and second auxiliary layers 221 are smaller than the doping concentration of the spreading layer 222. Optionally, in some embodiments of this application, the doping concentrations of the first and second auxiliary layers are the same, thereby forming a symmetrical doping gradient of "low-high-low" inside the current spreading layer 22.

[0105] Based on the above structure, the first auxiliary layer can decompose the "high-intrinsic" abrupt interface between the extended layer and the top stress-adjusting layer in the first reflective layer into a two-stage transition: "extended layer / first auxiliary layer" and "first auxiliary layer / stress-adjusting layer". Similarly, the second auxiliary layer can decompose the "high-intrinsic" abrupt interface between the extended layer and the bottom stress-adjusting layer in the second reflective layer into a two-stage transition. As a result, the doping concentration difference at a single interface decreases, the interface electric field strength decreases, and the single-interface electric field strength is approximately half that without the auxiliary layer, leading to a corresponding decrease in contact resistance. Simultaneously, the extended layer is located at the center of the current-extending layer, and its doping concentration is symmetrically distributed on both sides, causing the electric field strength near the center of the extended layer to approach zero. This results in a symmetrical electric field distribution within the reflective structure layer, preventing unilateral concentration of the electric field.

[0106] In summary, the first and second auxiliary layers reduce the doping concentration difference and electric field intensity at a single interface by decomposing the abrupt "extension layer / stress-modulating layer" interface into a two-stage transition. This reduces the contact resistance between the extension layer and the two reflective layers, and improves the uniformity of carrier injection. The symmetric design of the doping concentration gradient and electric field distribution optimizes the current uniformity within the reflective structure layer from an electrical perspective, making the current distribution in the active layer more uniform and indirectly mitigating the quantum confinement Stark effect exacerbated by localized electric field concentration.

[0107] In other embodiments of this application, the current spreading layer may include only the first auxiliary layer and the diffusion layer, or only the second auxiliary layer and the spreading layer. This application does not limit this, and it depends on the specific circumstances.

[0108] Optionally, in some embodiments of this application, the Fermi level position of the auxiliary layer ranges from -7.5 meV to 23.1 meV, including the endpoint values, such as the doping concentration of the auxiliary layer ranging from 1 × 10⁻⁶. 18 ~2×10 18 The thickness of the auxiliary layer ranges from 40 nm to 60 nm, including endpoints, and the Fermi level position of the extended layer ranges from 23.1 meV to 39.5 meV, including endpoints. For example, the doping concentration of the extended layer ranges from 2 × 10⁻⁶. 18 ~3×10 18 The thickness is measured in atoms / cm³, including endpoint values, and ranges from 100nm to 140nm, including endpoint values. However, this application does not impose any limitations on this; the specific value depends on the circumstances.

[0109] Based on the above doping concentration configuration, and considering that the doping concentration range of the stress adjustment layer is 3×10⁻⁶, 17 ~5×10 17 The concentration of atoms / cm³ allows the doping concentration of the auxiliary layer to be between that of the extended layer and the stress-adjusting layers on both sides. This decomposes the single "extended layer / stress-adjusting layer" high-intrinsic abrupt interface into a two-stage transition between "extended layer / auxiliary layer" and "auxiliary layer / stress-adjusting layer", reducing the doping concentration difference at the single interface and making the band transition smoother. As a result, the contact resistance between the extended layer and the stress-adjusting layers on both sides is reduced by about 30% to 40%.

[0110] In addition, the extended layer uses a higher doping concentration (e.g., 2×10⁻⁶). 18 ~3×10 18(atoms / cm³), which can effectively reduce the lateral resistance of the current spreading layer. Compared with not setting the current spreading layer, the lateral resistance of the reflective structure layer can be reduced from 5Ω~10Ω to 2Ω~3Ω, and the variance of the current density distribution is reduced by 25%~35%. This allows the injected current to spread more fully in the lateral direction, avoids the current concentration in the active layer, and improves the uniformity of the current distribution by about 30%~50%.

[0111] Furthermore, according to the Joule heat formula Q=I²R, when the lateral resistance of the reflective structural layer decreases from 5Ω~10Ω to 2Ω~3Ω, the Joule heat decreases by approximately 60%~80%, and the overall operating temperature of the reflective structural layer decreases by 8~12℃. This reduction in operating temperature decreases phonon-phonon scattering, allowing the material's intrinsic thermal conductivity to be fully utilized, thus creating a positive cycle of "structural cooling → increased intrinsic thermal conductivity".

[0112] It should be noted that in the embodiments of this application, the reflective structure layer adopts a three-segment structure of a first reflective layer, a current spreading layer, and a second reflective layer. This reduces interface phonon scattering. Combined with the high-doping and low-resistivity characteristics of the current spreading layer, the thermal conductivity of the reflective structure layer can reach 6W / m·K~8W / m·K. Compared with the 1W / m·K~2W / m·K of the traditional AlAs / AlGaAs system, the overall thermal conductivity of the reflective structure layer is improved by about 300%~400%, effectively reducing the junction temperature by 8~12℃. This alleviates the problem of heat generated in the active region not being able to be dissipated in time, which is beneficial to reducing the LED junction temperature, suppressing the exacerbation of the quantum confinement Stark effect (QCSE), solving the heat dissipation bottleneck of the traditional DBR as the main source of thermal resistance, and improving the wavelength stability and luminous efficiency of the LED.

[0113] In summary, in the reflective structure layer provided in this application embodiment, the first auxiliary layer, the extension layer, and the second auxiliary layer in the current extension layer are all Al. 0.3 Ga 0.2 In 0.5 The P-material, with its identical composition, well-matched lattice constants, and lack of strain accumulation, forms a synergistic effect with the first and second reflective layers, which employ alternating stacking of multiple components and periodic stress release through a stress-regulating layer. This results in two strain management mechanisms: "component homogenization" and "periodic stress release." Furthermore, this current-spreading layer guides the lateral diffusion of current, avoiding localized light decay and reliability issues caused by current concentration. Combined with the four synergistic effects of low contact resistance, symmetrical electric field distribution within the reflective structure layer, uniform current spread, and lack of strain accumulation, it indirectly provides a structural foundation for the active layer to maintain wavelength stability, current equalization, resistance to efficiency degradation, and anti-electrostatic discharge during the switching process from 25°C to 85°C by improving the working environment of the reflective structure layer (reduced lateral resistance, improved reflectivity uniformity, and reduced internal Joule heating).

[0114] Optionally, in some embodiments of this application, the current spreading layer further includes a first intrinsic spacer layer located between the auxiliary layer and the spreading layer, so as to block the impurity diffusion path between the auxiliary layer and the spreading layer using the first intrinsic spacer layer. However, this application does not limit this and it depends on the specific circumstances.

[0115] Optionally, in some other embodiments of this application, the current spreading layer does not employ a combination design of auxiliary and spreading layers, but rather a superlattice structure design. Specifically, in this embodiment, the current spreading layer comprises alternately stacked Al... 0.1 Ga 0.9 The P-layer and GaP-layer are used to enhance the current spreading capability of the current spreading layer, making it suitable for high-power devices driven by high current.

[0116] Based on the above embodiments, in some embodiments of this application, the GaP layer includes a first sub-GaP layer and a second sub-GaP layer stacked along the direction away from the substrate. The Fermi level of the first sub-GaP layer is smaller than that of the second sub-GaP layer. For example, the doping concentration of the first sub-GaP layer is smaller than that of the second sub-GaP layer, so that the GaP layer adopts a low-doped sub-layer / high-doped sub-layer design. However, this application does not limit this and it depends on the specific circumstances.

[0117] Optionally, in some embodiments of this application, the total thickness of the reflective structure layer ranges from 0.77 μm to 2.25 μm, including the endpoint values, but this application does not limit it and it depends on the specific circumstances.

[0118] like Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of the band structure of an LED when the reflective structure layer consists only of stacked AlInP and AlGaInP layers. Figure 4 This is a schematic diagram of the energy band structure of an LED when the reflective structure includes a first reflective layer 211, a current spreading layer 22, and a second reflective layer 212. A stress-adjusting layer 23 is also provided in the first reflective layer 211 and the second reflective layer 212. It should be noted that... Figure 3 and Figure 4 In the diagram, curve a represents the conduction band bottom (Ec), curve b represents the valence band top (Ev), and the horizontal axis represents the distribution of each film layer along the growth direction Z. It should be noted that... Figure 4 In this context, the current spreading layer is an N-type heavily doped layer.

[0119] contrast Figure 3 and Figure 4It can be seen that the energy difference between the bottom of the conduction band (Ec) and the top of the valence band (Ev) of the current spread layer is relatively large. If the charge carrier needs to cross this layer, it needs high energy. That is, the current spread layer has a high carrier suppression capability, which can suppress the leakage of charge carriers towards the substrate and improve the radiative recombination efficiency of the active layer region.

[0120] Based on any of the above embodiments, in some embodiments of this application, such as Figure 5 As shown, the active layer 40 includes a first active layer 41, a tunnel junction 42, and a second active layer 43 arranged in a direction away from the substrate 10; wherein the tunnel junction 42 is used to realize the electrical series connection of the first active layer 41 and the second active layer 43.

[0121] In this embodiment, the first active layer comprises alternating stacked first barrier layers and first well layers, and the second active layer comprises alternating stacked second barrier layers and second well layers. It should be noted that in this embodiment, the first and second barrier layers are AlGaInP layers, and the bandgap of the first barrier layer is greater than the bandgap of the second barrier layer. For example, the proportion of In component in the first barrier layer is less than the proportion of In component in the second barrier layer, thereby constructing two quantum well regions with different bandgap widths in the active layer.

[0122] In practical operation, at low temperatures (e.g., 25°C), the barrier of the first active layer is low, resulting in high carrier injection efficiency. Carriers injected into the active layer preferentially emit light in the first active layer, making it the light-conducting region with an emission peak at 640nm~650nm. As the temperature rises to high temperatures (e.g., 85°C), the thermally excited carriers in the first active layer leak into the second active layer. The second active layer gradually replaces the first active layer as the main light-emitting region. Therefore, at high temperatures, the second active layer becomes the main light-emitting region.

[0123] Optionally, in some embodiments of this application, the bandgap width of the first barrier layer ranges from 1.91 eV to 2.01 eV, including the endpoint values, such as the In component ratio in the first barrier layer ranging from 0.3 to 0.4, including the endpoint values; the bandgap width of the second barrier layer ranges from 1.85 eV to 1.92 eV, including the endpoint values, such as the In component ratio in the second barrier layer ranging from 0.4 to 0.5, including the endpoint values.

[0124] The bandgap temperature coefficient (dEg / dT) of the AlGaInP system decreases with increasing In content. During the transition from low to high temperature, the emission peak positions of both the first and second active layers redshift with increasing temperature, but at different rates. For example, the first barrier layer has an In content of 0.30–0.40, constituting a shallow well, with an absolute dEg / dT value of approximately 0.45–0.55 meV / K; the second barrier layer has an In content of 0.40–0.50, constituting a deep well, with an absolute dEg / dT value of approximately 0.35–0.45 meV / K. At 25℃, the emission peak of the first active layer is 640nm, and the emission peak of the second active layer is 660nm, with a peak difference of approximately 20nm. During a 60K temperature rise to 85℃, the emission peak of the first active layer shifts from 640nm to 652nm (redshift of approximately 12nm), while the emission peak of the second active layer shifts from 660nm to 670nm (redshift of approximately 10nm). This shows that the emission peaks of both the first and second active layers shift towards longer wavelengths, but the redshift of the first active layer is greater. This causes the peak position difference between the first and second active layers to decrease from 20nm to 18nm, exhibiting a gradual convergence trend. This effect reduces the weighted center shift of the overall emission peak position of the dual-active region formed by the first and second active layers by about 50% compared to the traditional single active region (from 12nm to 6~10nm), and the wavelength temperature coefficient decreases from 0.20nm / ℃ to 0.17nm / ℃, achieving self-compensation for wavelength temperature drift with a compensation efficiency of 40%~50%, making it particularly suitable for high-reliability scenarios such as Mini / Micro LED displays and automotive lighting.

[0125] Based on any of the above embodiments, in some embodiments of this application, the tunnel junction includes an N-type doped GaAs layer and a P-type doped GaAs layer arranged along a direction away from the substrate; wherein, the thickness of the N-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoints, and the Fermi level position ranges from 115 meV to 170 meV, including the endpoints, such as a doping concentration of not less than 5 × 10⁻⁶. 19 The thickness of the p-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoints, and the Fermi level ranges from 90 meV to 140 meV, including the endpoints, with a doping concentration of not less than 5 × 10¹⁹ atoms / cm³. In this embodiment, when the tunnel junction operates in the forward bias state, tunneling is the dominant conduction mechanism in the active layer, resulting in extremely low equivalent series resistance. This enables efficient carrier transport between the two In-component-differentiated active regions, the first and second active layers, with a series resistance increase of less than 5%, which has a negligible impact on the overall device efficiency. However, this application does not impose any limitations on this; the specific determination depends on the circumstances.

[0126] Optionally, in some embodiments of this application, the total thickness of the tunnel junction ranges from 16 nm to 24 nm, including the endpoint values. However, this application does not limit this value and it depends on the specific circumstances.

[0127] It should be noted that, in the embodiments of this application, the tunnel junction can not only achieve low-resistance electrical connection between the first active layer and the second active layer, but also regulate the redistribution of charge carriers in the first active layer and the second active layer, and achieve forced current shunting in the first active layer and the second active layer.

[0128] Specifically, the mechanism by which the tunnel structure achieves forced diversion is as follows:

[0129] First, the tunnel junction operates in a forward bias state, with tunneling as the dominant conduction mechanism. Its equivalent series resistance is extremely low, allowing the first and second active layers to form a parallel structure electrically. According to the principle of current distribution in parallel circuits based on conductance, the total injected current of the active layers is evenly distributed between the two active layers, with each bearing approximately 50% of the current density. This prevents premature saturation of a single active region under high current injection conditions and significantly alleviates efficiency degradation under high current density.

[0130] Secondly, according to the Kane / Esaki tunneling model, the tunneling current is highly sensitive to bias voltage, with a steeper sensitivity than that described by the Shockley equation for the diffusion current. When an increase in the current in the active region on one side leads to an increase in its local voltage drop, the tunnel junction automatically reduces the tunneling transfer current on that side, maintaining a dynamic balance of carrier concentrations on both sides. This negative feedback mechanism ensures that the current distribution between the two active layers remains stable despite fluctuations in operating conditions.

[0131] Furthermore, when a large instantaneous ESD current is injected, the first active layer, the tunnel junction, and the second active layer form three parallel discharge channels, distributing the surge energy across multiple paths. The current density borne by a single active region (i.e., the active region in the first active layer or the active region in the second active layer) is halved. Simultaneously, the tunnel junction enters a breakdown state under overvoltage conditions, clamping the voltage across its terminals within a safe range, blocking any path to overvoltage burnout in any active region, improving the LED's anti-static capability, and significantly enhancing the LED's reliability.

[0132] Finally, the reduction in current density lowers the operating temperature of the active layer, which in turn slows down the defect proliferation rate and the aging rate of hot carriers, thereby suppressing optical decay during long-term operation and extending the device's lifespan.

[0133] When the tunnel junction achieves carrier redistribution regulation in the active layer, this carrier redistribution regulation is realized through a mechanism of "forward injection → tunneling transfer → inter-well dynamic balance", as follows:

[0134] First, current is injected forward along the path of "N-type confinement layer → first active layer → tunnel junction → second active layer → P-type confinement layer". At this time, the tunnel junction is in a positive bias state, and the LED operates in a low-resistance conduction mode, providing a continuous transport channel for charge carriers.

[0135] Secondly, at low temperatures (e.g., 25°C), the first active layer has a shallow-well structure with a low barrier. Injected carriers are preferentially captured and recombine in the first active layer, resulting in luminescence. At this temperature, the tunnel junction only needs to provide the basic tunneling current required to maintain current continuity. Carriers are mainly distributed in the first active layer, which is the primary luminescent region. It should be noted that at low temperatures, the second active layer can also receive approximately 50% of the current injection through the tunnel junction. That is, the first and second active layers share approximately 50% of the current density through the tunnel junction. However, because the second barrier layer in the second active layer has a higher In content and is a deep-well structure with a higher barrier, it has a strong binding force on carriers. Once carriers are captured in the deep well, they are difficult to escape, resulting in a high intrinsic recombination rate. Its luminescence only manifests as a shoulder peak on the long-wavelength side. When the ambient temperature rises to 85°C, some carriers in the shallow well of the first active layer gain sufficient thermal energy to overcome the barrier binding and undergo thermally excited escape. Escaped electrons and holes drift into the deep well of the second active layer under the influence of the electric field and are captured by its higher barrier. At this time, the carrier concentration in the first active layer decreases, while the carrier concentration in the second active layer increases, and the bias state at both ends of the tunnel junction changes accordingly. Since the tunneling current of the tunnel junction is highly sensitive to the bias voltage at both ends, even a small change in the bias voltage can trigger a significant response in the tunneling current. This allows the tunnel junction to automatically adjust the magnitude of the tunneling current according to the carrier concentration difference between the two active regions (i.e., the active regions in the first active layer and the active regions in the second active layer), achieving real-time adaptive redistribution of carriers between the two active regions. Thus, in the red LED epitaxial structure provided in this application embodiment, the active layer utilizes the differentiated In composition of the first and second barrier layers, combined with the current shunting effect of the tunnel junction, to enable the first active layer to dominate light emission at low temperatures and the second active layer to dominate light emission at high temperatures, thereby largely solving the problem of heat leakage.

[0136] It should be noted that the tunnel junction does not change the total number of charge carriers in the LED during the above process. Its role is to dynamically regulate the spatial distribution of charge carriers based on the state differences between the two active layers, ensuring that charge carriers at different temperatures always tend to be distributed in the quantum wells that are most conducive to recombination and luminescence at that temperature, thereby achieving self-compensation for wavelength temperature drift. Therefore, this tunnel junction can significantly improve the current management capability of the LED and, by forcibly equalizing the current through the tunnel junction, ensure that both active layers receive sufficient charge carrier injection in both hot and cold states, avoiding the problem of a sharp drop in current utilization efficiency caused by thermal leakage of charge carriers in a single active layer at high temperatures.

[0137] In summary, the red LED epitaxial structure provided in this application, with its active layer consisting of a first active layer, a tunnel junction, and a second active layer, achieves the following three functions: First, it acts as a carrier reservoir, catching the overflow carriers from the first active layer under high current and suppressing efficiency decay under high current; second, it forces current distribution, preventing excessive current concentration and local saturation in a single active layer under large injection; and third, it preheats for the 85°C role reversal—as the temperature rises, the escape of shallow-well hot carriers in the first active layer increases, and the deep-well in the second active layer takes over the dominant position, allowing the second active layer to assume the main light emission without a "cold start," thus improving wavelength temperature stability.

[0138] Because the first barrier layer has a high Al content and a low lattice constant, while the first well layer has a high In content and a high lattice constant, there is a lattice mismatch stress between the first barrier layer and the first well layer due to the difference in lattice constant. If there is a direct transition between the first barrier layer and the first well layer, nonradiative recombination centers such as dislocations and dangling bonds will easily form at the interface between the first barrier layer and the first well layer. This serious nonradiative recombination will affect the internal quantum efficiency of the LED.

[0139] Therefore, based on any of the above embodiments, in some optional embodiments of this application, the first active layer further includes a first simple well layer located between the first barrier layer and the first well layer. The lattice constant of the first simple well layer is greater than the lattice constant of the first barrier layer and less than the lattice constant of the first well layer. That is, the lattice constant of the first simple well layer is between the lattice constant of the first barrier layer and the lattice constant of the first well layer. Thus, by setting the first simple well layer between the interface of the first barrier layer and the first well layer, the lattice mismatch that was originally concentrated on the single interface of the barrier layer / well layer can be distributed to the two interfaces of the barrier layer / simple well layer and the simple well layer / well layer. Moreover, the difference in lattice constant on both sides of each interface is less than the difference in lattice constant between the barrier layer and the well layer, thereby playing a role in lattice transition, absorbing interface stress, and reducing interface state density. Simultaneously, the conduction band of the first simple well layer is larger than that of the first well layer but smaller than that of the first barrier layer. That is, the conduction band of the first simple well layer is located between the conduction bands of the first barrier layer and the first well layer, forming a small conduction band step. This step buffers and slows down the carriers transported from the first barrier layer to the first well layer, preventing high-speed collisions with the first well layer interface and thus preventing interface recombination. It also guides the carriers towards the center of the first well layer. Through the synergistic effect of these three actions, the first simple well layer effectively reduces nonradiative recombination at the interface between the first well layer and the first barrier layer, improving the internal quantum efficiency of the device.

[0140] Similarly, the second barrier layer has a higher Al content and a smaller lattice constant, while the second well layer has a higher In content and a larger lattice constant. Therefore, there is a lattice mismatch stress between the second barrier layer and the second well layer due to the difference in lattice constants. This makes it easy for nonradiative recombination centers such as dislocations and dangling bonds to form at the interface between the second barrier layer and the second well layer, which affects the internal quantum efficiency of the LED.

[0141] Therefore, based on any of the above embodiments, in some optional embodiments of this application, the second active layer further includes a second simple well layer located between the second barrier layer and the second well layer. The lattice constant of the second simple well layer is greater than the lattice constant of the second barrier layer and less than the lattice constant of the second well layer. That is, the lattice constant of the second simple well layer is between the lattice constant of the second barrier layer and the lattice constant of the second well layer. Thus, by setting the second simple well layer between the interface of the second barrier layer and the second well layer, the lattice mismatch that was originally concentrated at the single interface of the barrier layer / well layer can be distributed to the two interfaces of the barrier layer / simple well layer and the simple well layer / well layer. Moreover, the difference in lattice constant on both sides of each interface is less than the difference in lattice constant between the barrier layer and the well layer, thereby playing a lattice transition role, absorbing interface stress, and reducing interface state density. Simultaneously, the conduction band of the second simple well layer is larger than that of the second well layer but smaller than that of the second barrier layer. That is, the conduction band of the second simple well layer is located between the conduction bands of the second barrier layer and the second well layer, forming a small conduction band step. This step buffers and slows down the carriers transported from the second barrier layer to the second well layer, preventing high-speed collisions with the second well layer interface and thus preventing interface recombination. It also guides the carriers towards the center of the second well layer. Through the synergistic effect of these three actions, the second simple well layer effectively reduces nonradiative recombination at the interface between the second well layer and the second barrier layer, improving the internal quantum efficiency of the device.

[0142] Optionally, in some embodiments of this application, the conduction band offset of the first barrier layer ranges from 58 meV to 143 meV, including the endpoint values. For example, the Al component in the first barrier layer ranges from 0.3 to 0.5, including the endpoint values, i.e., the first barrier layer is (Al... x4 Ga 1—x4 ) 1-y2 In y2 In the P layer, x4 ranges from 0.3 to 0.5, including the endpoint values; y2 ranges from 0.3 to 0.4, including the endpoint values; and the thickness of the first barrier layer ranges from 6 nm to 10 nm, including the endpoint values.

[0143] The conduction band offset of the first simple well layer ranges from 143 meV to 189 meV, including the endpoint values. For example, the Al component in the first simple well layer ranges from 0.5 to 0.6, including the endpoint values, meaning the first simple well layer is Al. x5 In 1-x5In layer P, x5 ranges from 0.5 to 0.6, including the endpoint values, and the thickness of the first simple well layer ranges from 5 nm to 10 nm, including the endpoint values.

[0144] The conduction band offset of the first well layer ranges from 0 meV to 25 meV, including the endpoint values, and the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint values. For example, the Al component in the first well layer ranges from 0.1 to 0.2, including the endpoint values, and the In component ranges from 0.3 to 0.5, including the endpoint values. That is, the first well layer is (Al... x6 Ga 1—x6 ) y3 In 1-y3 In the P layer, x6 ranges from 0.1 to 0.2, including the endpoint values; y3 ranges from 0.5 to 0.7, including the endpoint values; the thickness of the first well layer ranges from 3 nm to 8 nm, including the endpoint values; and the number of periods of the first barrier layer, the first simple well layer, and the first well layer in the first active layer ranges from 3 to 5, including the endpoint values.

[0145] The conduction band offset of the second barrier layer ranges from 100 meV to 237 meV, including the endpoint values. For example, the Al component in the second barrier layer ranges from 0.4 to 0.7, including the endpoint values. That is, the second barrier layer is (Al... x7 Ga 1—x7 ) 1-y4 In y4 In the P layer, the value of x7 ranges from 0.4 to 0.7, including the endpoint value; the value of y4 ranges from 0.4 to 0.5, including the endpoint value; and the thickness of the second barrier layer ranges from 6 nm to 10 nm, including the endpoint value.

[0146] The conduction band offset of the second simple well layer ranges from 143 meV to 189 meV, including the endpoint values. This means the Al component in the second simple well layer ranges from 0.5 to 0.6, including the endpoint values. x8 In 1-x8 For the P layer, x8 ranges from 0.5 to 0.6, including the endpoint values; and the thickness of the second simple well layer ranges from 5 nm to 10 nm, including the endpoint values.

[0147] The conduction band offset of the second well layer ranges from 0 meV to 25 meV, including the endpoint values, and the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint values. For example, the Al component in the second well layer ranges from 0.1 to 0.2, including the endpoint values, and the In component ranges from 0.3 to 0.5. That is, the second well layer is (Al... x9 Ga 1—x9 ) y5 In1-y5 In the P layer, x9 ranges from 0.1 to 0.2, including the endpoint values; y5 ranges from 0.5 to 0.7, including the endpoint values; the thickness of the first well layer ranges from 3 nm to 8 nm, including the endpoint values; and the number of periods of the second barrier layer, the second simple well layer, and the second well layer in the second active layer ranges from 4 to 6, including the endpoint values.

[0148] It should be noted that by using the above parameter settings, the LED heat leakage rate can be reduced from 85% of a single active layer to below 7%, while the wavelength drift is reduced by about 50% through dual emission peaks. Moreover, the first and second well layers can simultaneously achieve the triple effects of lattice transition, carrier buffering and deceleration, and central aggregation, thereby improving the internal quantum efficiency (IQE) of the LED by 5-10% and the lateral current uniformity of the LED by 30-50%. However, this application does not limit these aspects; the specific implementation depends on the circumstances.

[0149] Optionally, in some embodiments of this application, the total thickness of the first active layer ranges from 42nm to 140nm, including the endpoint values; the total thickness of the second active layer ranges from 56nm to 168nm, including the endpoint values. However, this application does not limit this, and the specific thickness depends on the circumstances.

[0150] It should be noted that if the first and second barrier layers use a uniform and fixed Al composition distribution, a band dead zone at the N-type confinement layer-first barrier layer interface and a conduction band spike at the barrier layer-well layer interface are easily generated, resulting in low carrier injection efficiency. Specifically, if the Al composition in the well layer is approximately 0.10, while the Al composition in the barrier layer abruptly changes to 0.50 or 0.70, the band gap changes abruptly at the well-barrier interface, and the distribution of conduction band offset (ΔEc) and valence band offset (ΔEv) is uneven. ΔEc is much larger than the proportion that should be present according to the band order ratio, resulting in a sharp upward conduction band spike at the well-barrier interface. During operation, electrons injected from the N-type confinement layer must overcome this spike or tunnel through it to enter the well layer, encountering significant resistance and resulting in low carrier injection efficiency.

[0151] Optionally, in some embodiments of this application, the conduction band offset of the first barrier layer increases along the direction away from the substrate, and the conduction band offset of the second barrier layer increases. For example, the Al composition in the first barrier layer increases along the direction away from the substrate, and the Al composition in the second barrier layer increases, so that the first and second barrier layers adopt a stepped Al composition increasing design, distributing the ΔEc originally concentrated at a single interface to the entire barrier layer thickness range, forming a "funnel-shaped" band distribution, and eliminating the interface barrier peak.

[0152] Taking the aluminum composition in the first barrier layer as an example, with a value ranging from 0.3 to 0.5, the Al composition of the first barrier layer gradually changes from 0.30 to 0.50 within a single barrier layer thickness. Consequently, the conduction band bottom (Ec) forms a continuously tilted band distribution. Charge carriers, driven by the electric field and concentration gradient, are transported along the negative gradient direction of the conduction band bottom via drift-diffusion, allowing injection into the well layer without the need for tunneling or thermal emission. When the aluminum composition in the second barrier layer ranges from 0.4 to 0.7, the Al composition of the second barrier layer gradually changes from 0.40 to 0.70 within a single barrier layer thickness, with the same mechanism as the first barrier layer. In this embodiment, ΔEc is no longer concentrated at a single interface and crossed all at once, but rather distributed as a quasi-field throughout the entire gradient layer, thus lowering the injection barrier, reducing the operating voltage, and increasing the recombination rate. Simultaneously, the valence band peak (Ev) also smoothly transitions along the Al gradient direction, providing a symmetrical and unobstructed path for holes, thus forming a bidirectional gentle-slope band structure that is favorable to both electrons and holes. This stepped band structure eliminates the conduction band spikes generated at the well-barrier interface by the uniform barrier layer, providing a smooth downhill channel for carrier transport. This allows carriers to recombine and emit light from the N-type confinement layer through the barrier layer and the simple well layer, ultimately injecting into the well layer, significantly improving injection efficiency.

[0153] Specifically, in some embodiments of this application, the Al composition of the first barrier layer gradually changes from 0.30 to 0.50 within a single barrier layer thickness, forming a stepped conduction band edge and valence band edge with the first well layer (Al≈0.10), resulting in a continuous change in the conduction band bottom and valence band top inside the first barrier layer. From the first well layer (Al≈0.10) to the highest Al composition of the first barrier layer, the conduction band drop ΔE_c of the first active layer can reach 0.16 eV; the Al composition of the second barrier layer gradually changes from 0.40 to 0.70, forming a stepped conduction band edge and valence band edge with the second well layer (Al≈0.10), resulting in a continuous change in the conduction band bottom and valence band top inside the second barrier layer. From the second well layer (Al≈0.10) to the highest Al composition of the second barrier layer, the conduction band drop ΔEc of the second active layer can reach 0.25~0.34 eV.

[0154] like Figure 6 and Figure 7 As shown, Figure 6 The diagram shows the band structure of an LED when the active layer adopts a single active region structure. In this structure, the active layer includes alternating stacked barrier layers and well layers. The material is AlGaInP, and the aluminum composition in the well layer is fixed at 0.3 and the indium composition is fixed at 0.7. The aluminum composition in the barrier layer is fixed at 0.65 and the indium composition is fixed at 0.35. Figure 7The diagram shows the band structure of an LED when the active layer adopts a dual-active region structure consisting of a first active layer 41, a tunnel junction 42, and a second active layer 43. The tunnel junction includes stacked N-layer heavily doped GaAs layers 421 and P-type heavily doped GaAs layers 422. In the first active layer, the aluminum composition of the first barrier layer gradually changes from 0.3 to 0.5, and the indium composition of the first well layer is 0.3-0.4. In the second barrier layer, the aluminum composition gradually changes from 0.4 to 0.7, and the indium composition of the first well layer is 0.4-0.5. A first simple well layer 411 is disposed between the first barrier layer and the first well layer in the first active layer, and a second simple well layer 431 is disposed between the second barrier layer and the second well layer in the second active layer. It should be noted that... Figure 6 and Figure 7 In the diagram, curve a represents the bottom of the conduction band (Ec), curve b represents the top of the valence band (Ev), and the horizontal axis represents the material growth direction.

[0155] contrast Figure 6 and Figure 7 It can be seen that in a single active region, the conduction band bottom (Ec) and valence band top (Ev) at the well-to-barrier interface are abrupt square waves, and the band profile is a regular, steep, square-wave step shape. At the well-to-barrier interface, Ec exhibits a single-point vertical jump, i.e., a concentrated, peak-type band shift. In contrast, in the active layer structure provided in this application embodiment, Ec and Ev at the well-to-barrier interface are continuously and gradually changed in a slope-like manner, and the band profile is a jagged, serrated shape. At the well-to-barrier interface, Ec exhibits a diagonal gradual change, i.e., a distributed quasi-field-type band shift.

[0156] Moreover, since the Al composition variation range of the second active layer is greater than that of the first active layer, from Figure 7 As can be seen, the band slope of the second active layer region is steeper than that of the first active layer region. This difference in band slope steepness directly reflects that the conduction band order ΔEc of the second active layer is greater than that of the first active layer, thus enabling differentiated control of band shifts in different active regions.

[0157] In summary, in the red LED epitaxial structure provided in this application embodiment, the active layer optimizes the carrier transport path across the entire chain, thereby dispersing and smoothing the band spike effect concentrated at the heterojunction interface. Specifically, the barrier layers of the first and second active layers employ a stepped Al composition to transform the conduction band shift energy (ΔEc) concentrated at the interface, forming a spike barrier with a reflectivity of approximately 80%, into a quasi-electric field distribution pattern distributed throughout the entire barrier layer thickness, with a reflectivity of approximately 5% and a transmittance of approximately 95%. Furthermore, a first simple well layer is provided between the first barrier layer and the first well layer, and a second simple well layer is provided between the second barrier layer and the second well layer. This allows the lattice abrupt change at the heterojunction interface to be transformed into a gradual transition pattern using the first and second simple well layers. The deceleration effect before carrier injection into the well region reduces interface scattering losses, and the barrier confinement effect of the quantum well allows carriers to accumulate towards the center region of the well region.

[0158] Therefore, in the embodiments of this application, the active layer can improve the device performance simultaneously from three dimensions: band structure control (band engineering), heterogeneous interface optimization (interface engineering), and carrier dynamic behavior management (kinetic engineering) through the synergistic effect of the above two designs.

[0159] By way of example, the parameter configuration of the present application embodiment can reduce the interface scattering loss between the barrier layer and the well layer by about 60% to 80%, increase the degree of carrier aggregation to the center region of the well region by about 40%, improve the internal quantum efficiency (IQE) by about 5% to 10%, improve the transverse current uniformity by about 30% to 50%, and significantly alleviate the efficiency decay (droop) effect.

[0160] Based on any of the above embodiments, in some embodiments of this application, the number of periods in the second active layer is greater than the number of periods in the first active layer. Optionally, the number of periods in the first active layer is the minimum value of its range, and the number of periods in the second active layer is the maximum value of its range, so as to achieve the output of a specific spectrum through the asymmetric design of the first active layer and the second active layer. However, this application does not limit this, and it depends on the specific situation.

[0161] Based on any of the above embodiments, in some embodiments of this application, the active layer further includes: a second intrinsic spacer layer located between the first active layer and the tunnel junction, and a third intrinsic spacer layer located between the tunnel junction and the second active layer, to prevent high doping diffusion in the tunnel junction from contaminating the first and second active layers, disrupting the compositional uniformity of the first and second active layers, causing abnormal quantum confinement Stark effect, and affecting the wavelength stability and luminous efficiency of the LED.

[0162] Optionally, in some embodiments of this application, the second intrinsic spacer layer and the third intrinsic spacer layer are GaAs layers with a thickness of not less than 50 nm to ensure the spacing effect of the first intrinsic spacer layer and the second intrinsic spacer layer. However, this application does not limit this and it depends on the specific circumstances.

[0163] Accordingly, this application also provides an LED chip, which includes the red LED epitaxial structure described in any of the above claims.

[0164] The red LED epitaxial structure and LED chip provided in this application are described below with reference to specific embodiments.

[0165] Example 1:

[0166] This application provides a design combining a standard active layer and a standard reflective structure layer. In this embodiment, the first active layer adopts a 4-pair quantum well periodic structure, i.e., a stack consisting of 4 first barrier layers and first well layers. The Al composition of the first barrier layer is set to a linearly gradient range of 0.35 to 0.45, corresponding to a conduction band offset ΔEc range of 97 meV to 140 meV. The In composition of the first well layer is fixed at 0.35, corresponding to a band gap of Eg ≈ 1.85 eV. The thickness of a single well is 5 nm, and the total thickness of the first active layer is approximately 56 nm. The tunnel junction adopts an N++GaAs / P++GaAs homogeneous structure, wherein the thickness of N++GaAs is 10 nm, the thickness of P++GaAs is 10 nm, and the doping concentration of both is 6 × 10⁻⁶. 19 The atoms / cm³ corresponds to a Fermi level gradient Ef-Ec value in the range of 125~180meV to ensure a tunneling efficiency of over 99%. The second active layer adopts a period of 5 pairs of quantum wells, which includes a stack of 5 second barrier layers and second well layers. The Al composition of the second barrier layer is fixed at 0.55, and the corresponding conduction band shift ΔEc value is 185meV. The In composition of the second well layer is 0.10, and the corresponding band gap Eg value is in the range of 2.05~2.10eV. The thickness of a single well is 5nm, and the total thickness of the second active layer is about 70nm. The reflective structure layer adopts a three-segment architecture, consisting of a bottom segment with 30 pairs of reflection cycles (i.e., the first reflective layer includes 30 reflection cycle layers), a middle current extension layer, and a top segment with 30 pairs of reflection cycles (i.e., the second reflective layer includes 30 reflection cycle layers). Each reflection cycle layer is a stack of AlInP / AlGaInP layers, and a total of 5 stress adjustment layers are inserted into the reflective structure layer, that is, one stress adjustment layer is inserted every 6 reflection cycles, with a total thickness of approximately 1.5 μm.

[0167] It should be noted that, compared to traditional single-In composition or continuously graded In composition active layer settings, the structure provided in this application embodiment adopts an architecture of dual-In composition discrete differentiated active regions cascaded with a highly doped GaAs tunnel junction. Specifically, the active layer includes a first active layer, a tunnel junction, and a second active layer arranged sequentially along the direction away from the substrate. The bandgap of the first well layer in the first active layer is approximately 2.05 eV to 2.10 eV (corresponding to a wavelength of approximately 590 nm to 605 nm), and the potential well depth is approximately 185 meV; the bandgap of the second well layer in the second active layer is approximately 1.85 eV (corresponding to a wavelength of approximately 670 nm), and the potential well depth is approximately 97 meV to 140 meV. The first active layer and the second active layer are electrically connected in series through a highly doped GaAs tunnel junction. The Fermi level of the tunnel junction penetrates more than 100 meV into the conduction band or valence band, with a tunneling efficiency greater than 99% and a series resistance increase of less than 5%.

[0168] Based on the aforementioned dual-well discrete potential depth design, carriers are automatically redistributed at different temperatures. At low temperatures (25°C), the first active layer has a shallow well structure with a low barrier, and injected carriers preferentially recombine and emit light in the first active layer, making it the dominant light-emitting region. When the temperature rises to 85°C, some carriers in the first active layer are thermally excited and escape, are captured by the deep well of the second active layer, and recombine and emit light. The second active layer gradually replaces the first active layer as the dominant light-emitting region. Through this temperature-adaptive carrier redistribution mechanism, the heat leakage rate at 85°C is reduced from over 40% in traditional schemes to below 7%, the wavelength drift is reduced from 12nm to 6~10nm, the compensation efficiency can reach 40%~50%, the cold-to-hot ratio is increased from 0.63 to 0.75, the external quantum efficiency is increased from 22% to 30%, the antistatic capability is increased from 1kV to over 3kV, and the device lifetime is extended from 5000h to 8000~10000h. Therefore, it can be seen that the red LED structure provided in this application embodiment can significantly improve the wavelength stability, antistatic capability, heat dissipation performance and overall photoelectric efficiency of the device.

[0169] Example 2:

[0170] This embodiment addresses the customized wavelength requirement of using a second active layer as the main light-emitting unit. In this embodiment, the first active layer adopts a quantum well periodic structure with a minimum number of cycles allowed by the process -3 pairs. That is, the first active layer consists of a stack of three first barrier layers and first well layers. The first well layer has an In composition of 0.30, corresponding to a bandgap of Eg≈1.90eV and a corresponding emission wavelength of approximately 653nm. The total thickness of the first active layer is approximately 42nm to reduce its contribution to the overall light emission. The tunnel junction adopts an N++GaAs / P++GaAs structure, where the thickness of N++GaAs is 8nm and the thickness of P++GaAs is 10nm, with both having a doping concentration of 5×10⁻⁶. 19The atoms / cm³ corresponds to a Fermi level gradient Ef-Ec value in the range of 115~170meV. The second active layer adopts the maximum design period number - 6 pairs of quantum well periods, that is, the second active layer consists of a stack of 6 second barrier layers and second well layers. The In composition of the second well layer is 0.20, and the corresponding bandgap Eg is increased to 1.99eV, with a corresponding emission wavelength of approximately 623nm. The total thickness of the second active layer is approximately 84nm, serving as the dominant wavelength output in the core emission region. The reflective structure layer is configured as follows: the bottom section reflective layer (i.e., the first reflective layer) includes 20 pairs of reflection periods (one pair of reflection periods corresponds to one reflection period layer), and the top section reflective layer (i.e., the second reflective layer) also includes 20 pairs of reflection periods, combined with 6 stress-tuning layers, with a total thickness of approximately 1.8μm.

[0171] In this embodiment, the active layer employs an asymmetric dual-active-region design. Specifically, the first active layer has 3 pairs of periods, a total thickness of approximately 42 nm, and a well bandgap of approximately 1.90 eV (corresponding to a wavelength of approximately 653 nm). The second active layer has 6 pairs of periods, a total thickness of approximately 84 nm, and a well bandgap of approximately 1.99 eV (corresponding to a wavelength of approximately 623 nm). The number of periods in the second active layer is twice that of the first active layer. The first and second active layers are cascaded with low resistance via a highly doped GaAs tunnel junction. The Fermi level of the tunnel junction extends deep into the conduction or valence band by 115 meV to 170 meV, with a tunneling efficiency greater than 99% and a series resistance increase of less than 5%.

[0172] Based on the aforementioned asymmetric period configuration, the second active layer contributes approximately 67% of the light emission, with the dominant wavelength determined by the second active layer at approximately 623 nm. The first active layer contributes approximately 33% of the light emission, serving as an auxiliary spectral filler. The reflective structure layer is configured with 40 pairs of reflection periods, achieving a reflectivity greater than 99.5%, and is paired with 6 stress-tuning layers, with a total thickness of approximately 1.8 μm, to match the optical resonance requirements of the active layer.

[0173] Example 3

[0174] This embodiment is used in a Mini chip micro-pitch display scenario, with the core objective being to prioritize reflectivity and wafer warpage control. In this embodiment, the reflective structure layer adopts a three-segment architecture: a bottom reflective layer with 25 pairs of reflection cycles, a middle current extension layer, and a top reflective layer with 25 pairs of reflection cycles, for a total of 50 pairs of reflection cycles. The stress adjustment layer is configured to insert one layer every 5 pairs of reflection cycles, for a total of 8 Al layers. 0.5 In 0.5 P, with a single-layer thickness of 8 nm, is used to mitigate lattice mismatch through high-frequency stress modulation. The middle current-spreading layer has a thickness of 140 nm and a doping concentration of 2.8 × 10⁻⁶. 18The atoms / cm³ corresponding to the Fermi level positions Ef-Ec values ​​are in the range of 30~50meV to enhance the lateral current spread uniformity of the current spread layer under high current drive. The active layer adopts the standard parameter configuration, that is, the configuration method in Example 1. The first active layer includes 4 pairs of quantum well periods, and the tunnel junction adopts an N++GaAs / P++GaAs homogeneous structure, wherein the thickness of N++GaAs is 10nm and the thickness of P++GaAs is 10nm; the second active layer adopts 5 pairs of quantum well periods, that is, it includes a stack of 5 second barrier layers and second well layers. The total thickness of the reflective structure layer is about 2.0μm, the reflectivity is ≥99.2%, and the wafer warpage can be controlled within the range of ≤50μm, which is suitable for the optical performance and mechanical stability requirements of Mini display devices.

[0175] In this embodiment, the reflective structure layer adopts a three-segment architecture, including 25 pairs of reflection cycles in the bottom reflective layer, the middle current extension layer, and the top reflective layer, for a total of 50 pairs of cycles. The reflectivity can reach over 99.2%, meeting the optical performance requirements of Mini display devices. Furthermore, in this embodiment, the stress adjustment layer employs a high-density configuration. Specifically, a stress adjustment layer is inserted every 5 pairs of reflection cycles. This high-frequency periodic insertion of stress adjustment layers periodically resets the accumulated strain energy generated during the stacking of multiple reflective periodic layers, effectively releasing lattice mismatch stress and controlling wafer warpage within 50 μm, thus meeting the mechanical stability requirements of Mini display devices.

[0176] Example 4:

[0177] This solution targets high-humidity and high-temperature applications such as automotive and outdoor use, with a core design focus on enhancing stress relaxation capabilities and long-term thermal stability. The reflective structure employs an architecture consisting of a bottom reflective layer with 20 reflection cycles, a middle current extension layer, and a top reflective layer with 20 reflection cycles, for a total of 40 reflection cycles. The stress-regulating layer utilizes a graded In composition design, with the composition linearly increasing from 0.50 to 0.70 and the lattice constant gradually changing from 5.668 Å to 5.749 Å. Each layer is 12 nm thick, with one stress-regulating layer inserted every 8 reflection cycles, for a total of 5 stress-regulating layers, to further disperse stress accumulation through the compositional gradient. The middle current extension layer employs a low-high-low doping gradient design (e.g., 1.2 × 10⁻⁶). 18 →2.5×10 18 →1.2×10 18The Fermi level gradient Ef-Ec ranges from 20-30 meV to 35-50 meV and then to 115-170 meV, with a 15nm first intrinsic spacer layer inserted to block impurity diffusion paths; the total thickness of the reflective structure layer is approximately 1.7μm. The active layer is simplified and optimized as follows: the first active layer uses a 3-pair quantum well periodic structure, the tunnel junction uses an 8nm N++GaAs and a 10nm P++GaAs structure, and the second active layer uses a 5-pair quantum well periodic structure to reduce the complexity of the active layer and improve the overall device reliability.

[0178] In this embodiment, the reflective structure layer adopts an architecture of 20 pairs of reflection periods in the bottom reflective layer, 20 pairs of reflection periods in the middle current extension layer, and 20 pairs of reflection periods in the top reflective layer, for a total of 40 pairs of periods. The lattice constant of the stress-adjusting layer gradually changes from 5.668 Å to 5.749 Å along the 12 nm thickness direction, and the mismatch gradually changes from +0.27% to +1.70%, so that the strain energy is distributed and stored within a total thickness of 60 nm, avoiding the concentration of strain energy at a single interface, thereby enhancing the stress relaxation capability and meeting the requirements for long-term thermal stability in high humidity and high temperature applications such as automotive and outdoor applications.

[0179] Furthermore, in this embodiment, the central current extension layer adopts a "low-high-low" doping gradient design. The difference between the Fermi level and the conduction band bottom at both ends (first auxiliary layer and second auxiliary layer) of the central current extension microstructure layer is approximately 20meV~30meV; the difference between the Fermi level and the conduction band bottom in the middle (extension layer) is approximately 35meV~50meV, resulting in a U-shaped distribution of the Fermi level positions, achieving synergy between lateral current extension and stress management. In addition, a 15nm intrinsic AlInP spacer layer is inserted. This material has a lattice constant close to that of GaAs, which can block impurity diffusion paths and further improve the long-term thermal stability of the device. Under the above configuration, the red LED epitaxial structure and LED chip provided in this embodiment exhibit a light decay rate of ≤3% after 1000 hours under accelerated aging conditions at 85℃ / 85%RH, meeting the long-life requirements of high-reliability scenarios.

[0180] Example 5

[0181] This embodiment is applied to the development of flexible substrates and thin-film devices, with the core constraint being strict control over the total thickness and stress accumulation level. In this embodiment, the reflective structure layer adopts a simplified architecture with a bottom reflective layer including 15 pairs of reflection periods, a middle current extension layer, and a top reflective layer including 15 pairs of reflection periods, for a total of 30 pairs of periods. The stress adjustment layer is simplified to 3 layers, with one stress adjustment layer inserted every 10 pairs of reflection periods. The thickness of a single layer after stress adjustment is 8nm, and Al is selected as the material. 0.6 In 0.4P is used to balance lattice matching and stress relief effects. The total thickness of the central current extension layer is compressed to 180nm (composed of a 40nm lower auxiliary layer, a 100nm extension layer, and a 40nm upper auxiliary layer), and the doping concentration is uniformly 2×10⁻⁶. 18 The density of atoms / cm³ is reduced to decrease the complexity of the growth process. The active layer is simultaneously adapted to thinning requirements: the first active layer is a periodic structure with three pairs of quantum wells, and the tunnel junction uses an 8nm N++GaAs and a 10nm P++GaAs structure; the second active layer uses a periodic structure with four pairs of quantum wells. The total thickness of the reflective structure layer is approximately 0.85μm. Compared to Example 1, the total stress accumulation in this embodiment can be reduced by 40%, making it suitable for ultra-thin substrates with a thickness ≤100μm, providing a feasible path for the epitaxial growth of flexible LED devices.

[0182] Example 6:

[0183] This embodiment is adapted to high-power devices driven by high current. Its core innovation is the integration of an AlGaP / GaP superlattice structure to enhance current spread capability. In this embodiment, the reflective structure layer adopts an architecture with a bottom reflective layer comprising 30 pairs of reflection periods, a middle current spread layer using a superlattice current spread layer, and a top reflective layer comprising 30 pairs of reflection periods, for a total of 60 pairs of reflection periods. The stress adjustment layer adopts a standard configuration, consisting of 5 layers, with one stress adjustment layer inserted every 6 pairs of reflection periods. The material is Al. 0.5 In 0.5 P. The current spreading layer uses 15 cycles of Al. 0.1 Ga 0.9 The P / GaP superlattice layer, where the GaP layer employs an alternating design of low-doped and high-doped sublayers, achieves a lateral current spread uniformity of over 95%. The active layers are designed to meet high current injection requirements. The first active layer is a 5-pair quantum well periodic structure, with the tunnel junction utilizing 12nm N++GaAs and 12nm P++GaAs structures. The second active layer is a 6-pair quantum well periodic structure. The total thickness of the reflective structure layer is approximately 2.3μm. This structure achieves an efficiency drop rate of <7% under a high current condition of 200A / cm², effectively mitigating current congestion and efficiency degradation issues in high-power devices.

[0184] Furthermore, this application also provides a method for fabricating a red LED epitaxial structure, applicable to the red LED epitaxial structure provided in any of the above embodiments, such as... Figure 8 As shown, the manufacturing method includes:

[0185] S1: Provide a substrate, exemplarily, the substrate is a GaAs substrate.

[0186] Optionally, in some embodiments of this application, before fabricating the reflective structure layer on the substrate, the fabrication method further includes: fabricating a buffer layer on the substrate, wherein the reflective structure layer is formed on the side of the buffer layer away from the substrate. For example, the buffer layer is an n-GaAs buffer layer, but this application does not limit it and it depends on the specific circumstances.

[0187] S2: A reflective structure layer, an N-type structure layer, an active layer, and a P-type structure layer are sequentially fabricated on a substrate. The reflective structure layer includes a reflective layer and a current spreading layer. The reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer.

[0188] Specifically, in one embodiment of this application, the sequential fabrication of a reflective structure layer, an N-type structure layer, an active layer, and a P-type structure layer on a substrate includes:

[0189] A reflective structure layer is fabricated on a substrate. The reflective structure layer includes a reflective layer and a current spreading layer. The reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer.

[0190] An N-type structure layer is fabricated on the side of the reflective structure layer away from the substrate. Exemplarily, the N-type structure layer includes an N-type confinement layer.

[0191] Active layers are formed in some areas of the N-type structure layer that are far from the substrate;

[0192] A P-type structural layer is formed on the side of the active layer away from the N-type structural layer. For example, the P-type structural layer includes a P-type barrier layer, a P-type window layer, and a P-type contact layer, but this application does not limit this and it depends on the specific situation.

[0193] Optionally, in this embodiment, the first reflective layer is located between the substrate and the current spreading layer, and the second reflective layer is located between the current spreading layer and the N-type structure layer. This allows the reflective layer to reflect light from the active layer toward the substrate back to the light-emitting surface of the LED, thereby improving the luminous efficiency of the LED. The current spreading layer enhances the lateral current spreading capability of the reflective structure layer, alleviating the "current congestion effect." This helps reduce the probability of excessively high local current density in the active layer, which could lead to hot spots, thus preventing excessively high local temperatures in the LED, delaying local aging of the LED, and improving the LED's electrostatic discharge (ESD) resistance.

[0194] Specifically, in this embodiment, the reflective layer includes: alternatingly stacked first and second sub-layers with different refractive indices, and a stress-adjusting layer periodically located between the stack of the first and second sub-layers. This layer utilizes the refractive index difference between the first and second sub-layers to reflect light from the active layer directed onto the substrate back to the light-emitting surface of the LED. The periodically arranged stress-adjusting layer also enables periodic stress relaxation, alleviating stress accumulation in the reflective structure layer, reducing the occurrence of defects such as dislocations and microcracks, mitigating LED performance aging, and extending the LED's lifespan.

[0195] Optionally, in some embodiments of this application, the current spreading layer includes: an spreading layer and an auxiliary layer located at least on one side of the spreading layer; wherein the doping concentration of the auxiliary layer is less than or equal to the doping concentration of the spreading layer, so as to reduce the basic resistance between at least one side of the current spreading layer and the reflection layer while enabling the current spreading layer to have current spreading capability.

[0196] In other embodiments of this application, the current spreading layer comprises alternating stacks of Al 0.1 Ga 0.9 The P-layer and GaP layer enhance the current spreading capability of the current spreading layer, making it suitable for high-power devices driven by high current. Optionally, in some embodiments of this application, the GaP layer includes a first sub-GaP layer and a second sub-GaP layer stacked along a direction away from the substrate. The doping concentration of the first sub-GaP layer is lower than that of the second sub-GaP layer, so that the GaP layer adopts a low-doped sub-layer / high-doped sub-layer design. However, this application does not limit this and it depends on the specific circumstances.

[0197] Based on any of the above embodiments, in some embodiments of this application, the fabrication of the active layer includes:

[0198] A first active layer is fabricated on the side of the N-type structure layer away from the substrate;

[0199] A tunnel junction is fabricated on the side of the first active layer away from the N-type structural layer;

[0200] A second active layer is fabricated on the side of the tunnel junction away from the first active layer.

[0201] It should be noted that, in this embodiment, the tunnel junction is used to achieve electrical series connection between the first active layer and the second active layer. The first active layer includes alternating stacked first barrier layers and first well layers, and the second active layer includes alternating stacked second barrier layers and second well layers. The first and second barrier layers are AlGaInP layers, and the In composition percentage in the first barrier layer is less than that in the second barrier layer. The bandgap width of the first barrier layer is greater than that of the second barrier layer, thereby constructing two quantum well sub-regions with different bandgap widths in the active layer, forming a dual active region.

[0202] It should also be noted that, as the core connection structure of the dual active region, the process control of the tunnel junction directly affects the carrier transport efficiency, spectral stability, and reliability of the device. Optionally, in some embodiments of this application, the fabrication process of the tunnel junction includes:

[0203] By introducing a Ga source, an As source, and an N-type doped source, an N-type doped GaAs layer is fabricated on the side of the first active layer away from the N-type structure layer.

[0204] After the N-type doped GaAs layer is grown, the N-type doping source is stopped, and the P-type doping source is introduced at the first time.

[0205] After pausing growth for a second time in the P-type doped atmosphere, a P-type doped GaAs layer is grown on the side of the N-type GaAs layer away from the first active layer.

[0206] The first time ranges from 0.05s to 1s, including the endpoint value, and the second time ranges from 10s to 20s, including the endpoint value.

[0207] Optionally, in some embodiments of this application, the tunnel junction includes an N-type doped GaAs layer and a P-type doped GaAs layer arranged along a direction away from the substrate. Exemplarily, in some embodiments of this application, the tunnel junction employs a highly doped N / P homogeneous GaAs structure. After the N-type doped GaAs layer is grown, the flow from the N-type doping source is switched to the P-type doping source within 1 second to avoid doping compensation and ensure a steep doping interface between the N-type and P-type doped GaAs layers. It should be noted that if the switching is delayed, the remaining N-type doping source will undergo a compensation reaction with the subsequent P-type doping source, reducing the effective doping concentration, leading to a decrease in tunneling probability (requiring >99%) and an increase in series resistance.

[0208] In addition, after switching to the P-type doped source, growth is interrupted for 20 seconds at the interface between the N-type doped GaAs layer and the P-type doped GaAs layer. This pauses growth at the interface to allow the doped source gas in the reaction chamber to stabilize sufficiently, reducing impurity adsorption and lattice disorder at the interface, thereby reducing the interface defect density and thus reducing the impact of defects as non-radiative recombination centers on carrier tunneling efficiency and device lifetime.

[0209] Optionally, in some embodiments of this application, the active layer further includes a second intrinsic spacer layer located between the first active layer and the tunnel junction, to prevent high doping diffusion in the tunnel junction from contaminating the first active layer, disrupting the compositional uniformity of the first active layer, causing abnormal quantum confinement Stark effect, and affecting the wavelength stability and luminous efficiency of the LED. In this embodiment, before introducing the Ga source, As source, and N-type doped source, and fabricating an N-type doped GaAs layer on the side of the first active layer away from the N-type structure layer, the method further includes: introducing the Ga source and As source, and fabricating an intrinsically doped GaAs layer with a predetermined thickness on the side of the first active layer away from the N-type structure layer as the second intrinsic spacer layer, wherein the N-type doped GaAs layer is formed on the surface of the intrinsically doped GaAs layer, and the predetermined thickness is not less than 50 nm.

[0210] Similarly, the active layer further includes a third intrinsic spacer layer located between the tunnel junction and the second active layer to prevent high doping diffusion in the tunnel junction from contaminating the second active layer, disrupting the compositional uniformity of the second active layer, causing abnormal quantum confinement Stark effect, and affecting the wavelength stability and luminous efficiency of the LED. In this embodiment, after growing a P-type doped GaAs layer on the side of the N-type GaAs layer away from the first active layer, the method further includes: stopping the introduction of the P-type doped source, continuing to introduce Ga and As sources, and growing an intrinsically doped GaAs layer on the surface of the P-type doped GaAs layer as the third intrinsic spacer layer.

[0211] Exemplarily, in one embodiment of this application, the process of fabricating the tunnel knot includes:

[0212] After the first active layer is grown, TMAl, TMIn, PH3, and SiH4 are simultaneously turned off within 0.05s to 1s. Then, TMGa and AsH3 are turned on within 0.05s to 1s to begin the growth of the second intrinsic spacer layer (the thickness can be monitored using the growth curve to obtain the required thickness). After the second intrinsic spacer layer is grown, SiH3 is turned on within 0.05s to 1s to grow the N++GaAs layer.

[0213] After the N++GaAs layer is grown, the SiH3 source is turned off within 0.05s to 1s, the CCl4 source is turned on within 0.05s to 1s, the growth is paused for 10 to 20s, and then the growth of the P++GaAs layer begins.

[0214] After the P++GaAs layer is grown, CCl4 is turned off within 0.05s~1s (TMGa and AsH3 are not turned off), and the growth of the third intrinsic spacer layer GaAs (≥50nm) begins.

[0215] After the growth of the third intrinsic spacer layer is completed, AsH3 and CCl4 are simultaneously turned off within 0.05s to 1s, and then TMAl, TMIn, PH3 and SiH4 are simultaneously turned on within 0.05s to 1s to begin the growth of the second active layer.

[0216] In summary, the red LED epitaxial structure and its fabrication method provided in this application embodiment not only consider optical performance, but also thermal, electrical and mechanical properties, achieving synergistic optimization of optics, thermal, electrical and mechanical properties. This is beneficial for simultaneously meeting the stringent comprehensive requirements of high-end applications for wavelength stability, antistatic capability, heat dissipation performance and reliability.

[0217] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the apparatus disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0218] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

Claims

1. A red LED epitaxial structure, characterized in that, include: The stacked substrate, reflective structure layer, N-type structure layer, active layer and P-type structure layer, wherein the reflective structure layer includes a reflective layer and a current spreading layer, and the reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer; The reflective layer includes: a plurality of periodic reflective layers and a stress-adjusting layer periodically located between the periodic reflective layers, wherein the periodic reflective layers include a first sub-layer and a second sub-layer with different refractive indices stacked together.

2. The red LED epitaxial structure according to claim 1, characterized in that, The first sub-layer is an AlInP layer, the second sub-layer is an AlGaInP layer, and the stress-adjusting layer is an AlInP layer.

3. The red LED epitaxial structure according to claim 2, characterized in that, The conduction band offset of the first sublayer ranges from 118meV to 208meV, including the endpoint value, and the thickness ranges from 35nm to 50nm, including the endpoint value. The conduction band offset of the second sublayer ranges from 162meV to 306meV, including the endpoint values; the band gap ranges from 1.599eV to 1.875eV, including the endpoint values; and the thickness ranges from 35nm to 50nm, including the endpoint values. The thickness of the reflective periodic layer ranges from 70 to 100 nm, including the endpoint values. The doped ion is silicon ion. The Fermi level position of the reflective periodic layer ranges from -15 meV to 5 meV, including the endpoint values. The conduction band offset of the stress adjustment layer ranges from 162meV to 256meV, including the endpoint value. Along the growth direction of the reflective structure layer, the conduction band offset of the stress adjustment layer increases. The thickness of the stress-adjusting layer ranges from 8 nm to 15 nm, including the endpoint values, and the Fermi level position ranges from -15 meV to 5 meV, including the endpoint values. The total thickness of the reflective structure layer ranges from 0.77 μm to 2.25 μm, including the endpoint values.

4. The red LED epitaxial structure according to claim 1, characterized in that, In the reflective layer, a stress adjustment layer is inserted every N reflective periodic layers, where N ranges from 3 to 6, including the endpoint values.

5. The red LED epitaxial structure according to claim 1, characterized in that, The current spreading layer is Al 0.3 Ga 0.2 In 0.5 P layer.

6. The red LED epitaxial structure according to claim 4, characterized in that, The current spreading layer includes a spreading layer and an auxiliary layer located at least on one side of the spreading layer; wherein the Fermi level position of the auxiliary layer is less than or equal to the Fermi level position of the spreading layer.

7. The red LED epitaxial structure according to claim 6, characterized in that, The Fermi level position of the auxiliary layer ranges from -7.5 meV to 23.1 meV, including the endpoint value, and the thickness of the auxiliary layer ranges from 40 nm to 60 nm, including the endpoint value. The Fermi level position of the extended layer ranges from 23.1 meV to 39.5 meV, including the endpoint value, and the thickness ranges from 100 nm to 140 nm, including the endpoint value.

8. The red LED epitaxial structure according to claim 6, characterized in that, The current spreading layer includes a first auxiliary layer and a second auxiliary layer located opposite each other on both sides of the spreading layer.

9. The red LED epitaxial structure according to claim 8, characterized in that, The Fermi level positions of both the first auxiliary layer and the second auxiliary layer are smaller than the Fermi level position of the extended layer; The current spreading layer further includes a first intrinsic spacer layer located between the auxiliary layer and the spreading layer.

10. The red LED epitaxial structure according to claim 1, characterized in that, The current spreading layer comprises alternating stacks of Al 0.1 Ga 0.9 P-layer and GaP layer.

11. The red LED epitaxial structure according to claim 10, characterized in that, The GaP layer includes a first sub-GaP layer and a second sub-GaP layer stacked along a direction away from the substrate, wherein the Fermi level position of the first sub-GaP layer is smaller than the Fermi level position of the second sub-GaP layer.

12. The red LED epitaxial structure according to any one of claims 1-11, characterized in that, The active layer includes a first active layer, a tunnel junction, and a second active layer arranged in a direction away from the substrate; wherein the first active layer includes alternating stacked first barrier layers and first well layers, and the second active layer includes alternating stacked second barrier layers and second well layers. The first barrier layer and the second barrier layer are AlGaInP layers, and the bandgap of the first barrier layer is greater than the bandgap of the second barrier layer.

13. The red LED epitaxial structure according to claim 12, characterized in that, The bandgap width of the first barrier layer ranges from 1.91 eV to 2.01 eV, including the endpoint values; The bandgap width of the second barrier layer ranges from 1.85eV to 1.92eV, including the endpoint values.

14. The red LED epitaxial structure according to claim 12, characterized in that, The first active layer further includes: a first simple well layer located between the first barrier layer and the first well layer; the second active layer includes a second simple well layer located between the second barrier layer and the second well layer; Wherein, the lattice constant of the first simple well layer is greater than the lattice constant of the first barrier layer and less than the lattice constant of the first well layer, and the conduction band of the first simple well layer is greater than the conduction band of the first well layer and less than the conduction band of the first barrier layer. The lattice constant of the second simple well layer is greater than that of the second barrier layer and less than that of the second well layer. The conduction band of the second simple well layer is greater than that of the second well layer and less than that of the second barrier layer.

15. The red LED epitaxial structure according to claim 14, characterized in that, The conduction band offset of the first barrier layer ranges from 58 meV to 143 meV, including the endpoint value, and the thickness ranges from 6 nm to 10 nm, including the endpoint value. The conduction offset of the first simple well layer ranges from 143meV to 189meV, including the endpoint value, and the thickness ranges from 5nm to 10nm, including the endpoint value. The conduction band offset of the first well layer ranges from 0 meV to 25 meV, including the endpoint value; the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint value; and the thickness ranges from 3 nm to 8 nm, including the endpoint value. The number of periods of the first barrier layer, the first simple well layer and the first well layer in the first active layer ranges from 3 to 5, including the endpoint values; The total thickness of the first active layer ranges from 42nm to 140nm, including the endpoint values; The conduction band offset of the second barrier layer ranges from 100meV to 237meV, including the endpoint values, and the thickness ranges from 6nm to 10nm, including the endpoint values. The conduction band offset of the second simple well layer ranges from 143meV to 189meV, including the endpoint value, and the thickness ranges from 5nm to 10nm, including the endpoint value. The conduction band offset of the second well layer ranges from 0 meV to 25 meV, including the endpoint value; the band gap ranges from 1.81 eV to 1.99 eV, including the endpoint value; and the thickness ranges from 3 nm to 8 nm, including the endpoint value. The number of cycles of the second barrier layer, the second simple well layer, and the second well layer in the second active layer ranges from 4 to 6, including the endpoint values; The total thickness of the second active layer ranges from 56nm to 168nm, including the endpoint values.

16. The red LED epitaxial structure according to claim 15, characterized in that, Along the direction away from the substrate, the conduction band offset of the first barrier layer increases, and the conduction band offset of the second barrier layer also increases.

17. The red LED epitaxial structure according to claim 16, characterized in that, The number of cycles in the second active layer is greater than the number of cycles in the first active layer.

18. The red LED epitaxial structure according to claim 17, characterized in that, The number of cycles in the first active layer is the minimum value of its range, and the number of cycles in the second active layer is the maximum value of its range.

19. The red LED epitaxial structure according to claim 12, characterized in that, The tunnel junction includes an N-type doped GaAs layer and a P-type doped GaAs layer arranged in a direction away from the substrate; wherein... The thickness of the N-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoint values, and the Fermi level position ranges from 115 meV to 170 meV, including the endpoint values. The thickness of the p-type doped GaAs layer ranges from 8 nm to 12 nm, including the endpoint values, and the Fermi level position ranges from 90 meV to 140 meV, including the endpoint values. The total thickness of the tunnel junction ranges from 16nm to 24nm, including the endpoint values.

20. The red LED epitaxial structure according to claim 12, characterized in that, Also includes: A second intrinsic spacer layer located between the first active layer and the tunnel junction, and a third intrinsic spacer layer located between the tunnel junction and the second active layer; The second intrinsic spacer layer and the third intrinsic spacer layer are GaAs layers with a thickness of not less than 50 nm.

21. An LED chip, characterized in that, Includes the red LED epitaxial structure as described in any one of claims 1-20.

22. A method for fabricating a red LED epitaxial structure, characterized in that, The method of fabricating the red LED epitaxial structure according to any one of claims 1-20 includes: Provide substrate; A reflective structure layer, an N-type structure layer, an active layer, and a P-type structure layer are sequentially fabricated on a substrate. The reflective structure layer includes a reflective layer and a current spreading layer. The reflective layer includes a first reflective layer and a second reflective layer located opposite each other on both sides of the current spreading layer. The reflective layer includes: a plurality of periodic reflective layers and a stress-adjusting layer periodically located between the periodic reflective layers, wherein the periodic reflective layers include a first sub-layer and a second sub-layer with different refractive indices stacked together.

23. The manufacturing method according to claim 22, characterized in that, The fabrication of the active layer includes: A first active layer is fabricated on the side of the N-type structure layer away from the substrate; A tunnel junction is fabricated on the side of the first active layer away from the N-type structural layer; A second active layer is fabricated on the side of the tunnel junction away from the first active layer; The process of fabricating the tunnel junction includes: By introducing a Ga source, an As source, and an N-type doped source, an N-type doped GaAs layer is fabricated on the side of the first active layer away from the N-type structure layer. After the N-type doped GaAs layer is grown, the N-type doping source is stopped, and the P-type doping source is introduced at the first time. After pausing growth for a second time in the P-type doped atmosphere, a P-type doped GaAs layer is grown on the side of the N-type GaAs layer away from the first active layer. The first time ranges from 0.05s to 1s, including the endpoint value, and the second time ranges from 10s to 20s, including the endpoint value.

24. The manufacturing method according to claim 23, characterized in that, The method further includes, before introducing a Ga source, an As source, and an N-type doped source, and before fabricating an N-type doped GaAs layer on the side of the first active layer away from the N-type structure layer: Introducing Ga and As sources, an intrinsically doped GaAs layer with a predetermined thickness is formed on the side of the first active layer away from the N-type structure layer. The N-type doped GaAs layer is formed on the surface of the intrinsically doped GaAs layer, and the predetermined thickness is not less than 50 nm. After growing a P-type doped GaAs layer on the side of the N-type GaAs layer away from the first active layer, the method further includes: Stop introducing the P-type doped source, and continue to introduce the Ga source and As source to grow an intrinsically doped GaAs layer on the surface of the P-type doped GaAs layer.

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