Error acquisition method of workpiece table and wafer defect detection system

Abstract

The application discloses a workpiece table error acquisition method and a wafer defect detection system. The method comprises the following steps: selecting error monitoring points in a plurality of alignment marks; correcting the theoretical alignment positions of each alignment mark to obtain corresponding optimized alignment positions; based on the optimized alignment positions of each error monitoring point, acquiring the initial distortion variable of the corresponding error monitoring point, and performing interpolation to obtain a first mapping relationship between the initial distortion error of the alignment mark and the corresponding position; acquiring the original error of the alignment mark; acquiring the position drift variable of the error monitoring point at the corresponding time point of each temperature drift monitoring period, and performing interpolation to obtain a second mapping relationship between the temperature drift error of the alignment mark and the corresponding position and time; and calculating the system error of the workpiece table based on the original error, the first mapping relationship and the second mapping relationship. The application can guarantee the accuracy of system error compensation and improve the stability of the system under different time and temperature environments.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for obtaining errors in a workpiece stage and a wafer defect detection system. Background Technology

[0002] In semiconductor bright-field defect inspection equipment, fixed optical systems such as illumination and imaging are typically used. A moving stage carrying the wafer is used to image different dies on the wafer, thus enabling wafer defect detection. During inspection, ensuring that the actual position of the die in the imaging field of view matches the preset position guarantees accurate image positioning, effectively reducing false detection rates and improving defect detection rates. Since the die is moved into the imaging field of view by the stage, the accuracy of the stage's positional movement must be as high as possible.

[0003] However, there is currently an error between the actual movement position of the workpiece stage and the set movement position. Under the current workpiece stage manufacturing process and control technology, the aforementioned error is caused by the systematic error of the workpiece stage. For example, in a workpiece stage using a grating ruler and encoder for positioning, the systematic error mainly comes from the accuracy error of the grating ruler, the bending of the workpiece stage motion guide rail, and the non-orthogonality of the two-dimensional motion axes of the workpiece stage (the degree of deviation from the ideal state). If a workpiece stage without systematic error correction is used for wafer defect detection, the actual movement position of the workpiece stage will be inconsistent with the set position. This may result in the position of the die image captured after the workpiece stage moves being inconsistent with the preset position of the die image, thus leading to a decrease in the defect detection rate and an increase in the false detection rate. Therefore, obtaining the error of the workpiece stage has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a method for obtaining errors in a workpiece stage and a wafer defect detection system, which can compensate for errors caused by the expansion and distortion of the standard silicon wafer itself, as well as dynamically compensate for errors caused by temperature. This can ensure the accuracy of system error compensation and improve the stability of the wafer defect detection system under different time and temperature environments.

[0005] Firstly, this application provides a method for obtaining the error of a workpiece stage, the method comprising:

[0006] A standard silicon wafer is configured, the standard silicon wafer including a plurality of alignment marks, and a series of error monitoring points are selected from the plurality of alignment marks, the series of error monitoring points including at least three non-collinear alignment marks;

[0007] The theoretical alignment position of each alignment mark is obtained, wherein the theoretical alignment position is the theoretical position of the workpiece stage when the corresponding alignment mark is located at a preset alignment position;

[0008] The expansion coefficient of the standard silicon wafer is determined, and the theoretical alignment position of each alignment mark is corrected according to the expansion coefficient to obtain the optimized alignment position of the corresponding alignment mark;

[0009] Based on the optimized alignment position of each error monitoring point, the initial distortion of the corresponding error monitoring point is obtained;

[0010] Two-dimensional linear interpolation is performed based on the initial distortion of the error monitoring points to obtain the first mapping relationship between the initial distortion error of each alignment mark and the corresponding position;

[0011] The alignment marks are sampled along a preset path to obtain the original error of each alignment mark;

[0012] During the sampling, the position drift of the error monitoring point at the corresponding time point in each temperature drift monitoring cycle is obtained, and interpolation is performed to obtain a second mapping relationship between the temperature drift error of the alignment mark and the corresponding position and time.

[0013] The system error of the workpiece stage is calculated based on the original error, the first mapping relationship, and the second mapping relationship.

[0014] Secondly, this application provides a wafer defect detection system, which includes a motion controller, an illumination system, an imaging system, an image sensor, and a processor; the processor is connected to the motion controller, the illumination system, the imaging system, and the image sensor respectively.

[0015] After the processor executes the error acquisition method of the workpiece stage as described in any embodiment and obtains the system error of the workpiece stage, it controls the motion controller to drive the workpiece stage to move. During the movement of the workpiece stage, the position of the workpiece stage is calibrated based on the system error. The illumination system is used to output a light beam so that the light beam is focused onto the surface of the wafer under test through the objective lens. The imaging system is used to receive the reflected light from the wafer under test returned through the objective lens and transmit it to the image sensor. The image sensor is used to image the wafer under test and transmit the image of the wafer under test to the processor for wafer defect detection.

[0016] To address the shortcomings of existing technologies, this application provides a method for obtaining the error of a workpiece stage. This method offers the following advantages: It uses a standard silicon wafer as a reference to obtain the systematic error of the workpiece stage. During this process, the expansion coefficient is calculated and the theoretical alignment position is corrected. This compensates for changes in the physical dimensions of the standard silicon wafer caused by thermal expansion and contraction due to temperature variations, ensuring that the workpiece stage is not affected by the thermal expansion and contraction of the standard silicon wafer when moving according to the alignment marks on it. Furthermore, considering the initial distortion deviation of the standard silicon wafer, the initial distortion is obtained based on the optimized alignment position of the error monitoring point. Two-dimensional linear interpolation is used to obtain the first mapping relationship between the initial distortion error of each alignment mark and its corresponding position. This compensates for errors caused by the expansion or distortion of the standard silicon wafer due to the clamping method of the chuck on the workpiece stage when the standard silicon wafer is placed on it, ensuring the accuracy of the subsequently obtained systematic error and thus providing more accurate compensation for systematic errors. The original error is then obtained by sampling along the preset path and aligning with the alignment mark. Simultaneously, the positional drift of the error monitoring point at different time points is acquired and interpolated to obtain a second mapping relationship between temperature drift error and position / time. This allows for dynamic compensation for the expansion or contraction of the standard silicon wafer caused by changes in ambient temperature, further improving the accuracy of calculating and acquiring the systematic error of the workpiece stage using the standard silicon wafer. The systematic error obtained in this way improves the accuracy of systematic error compensation, thereby enhancing the positioning accuracy and stability of the workpiece stage during processing or measurement operations, ultimately improving the processing or measurement quality of the product.

[0017] It should be noted that the aforementioned computer instructions may be stored, in whole or in part, on a computer-readable storage medium. This computer-readable storage medium may be packaged together with the processor of the error acquisition device for the workpiece stage, or it may be packaged separately from the processor of the error acquisition device for the workpiece stage; this application does not impose any limitations on this.

[0018] The description of the second aspect in this application can be referred to the detailed description of the first aspect; and the beneficial effects of the description of the second aspect can be referred to the analysis of the beneficial effects of the first aspect, which will not be repeated here.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description.

[0020] It is understood that before using the technical solutions disclosed in the various embodiments of this application, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this application in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating a method for obtaining the error of a workpiece stage provided in an embodiment of this application;

[0023] Figure 2 A schematic diagram illustrating the correction of the theoretical alignment position of the error monitoring point provided in the embodiments of this application;

[0024] Figure 3 A schematic diagram of a sampling grid provided in an embodiment of this application;

[0025] Figure 4 A schematic diagram of a sampling path provided for an embodiment of this application;

[0026] Figure 5 A flowchart illustrating a method for obtaining the error of a workpiece stage, provided in an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of a wafer defect detection system provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0029] It should be noted that the terms "first," "second," "target," and "original," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprising," "having," and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] Figure 1 This is a flowchart illustrating a method for obtaining errors in a workpiece stage according to an embodiment of this application. This embodiment is applicable to scenarios involving the acquisition of errors in the positional movement of a workpiece stage. The method for obtaining errors in a workpiece stage provided in this embodiment can be executed by the error acquisition device for the workpiece stage provided in this application. This device can be implemented through software and / or hardware and integrated into the electronic device executing this method.

[0031] See Figure 1 The method in this embodiment includes, but is not limited to, the following steps:

[0032] S110. Configure a standard silicon wafer, which includes multiple alignment marks, and select a series of error monitoring points from the multiple alignment marks.

[0033] In this embodiment, the standard silicon wafer can be a specific silicon wafer that meets the specifications for dimensions, flatness, and other indicators. Multiple specific alignment marks can be set on the surface of the standard silicon wafer. These alignment marks can be used in various processes to achieve precise alignment and monitor wafer deformation. For example, in different process stages, alignment marks can be used as a reference to ensure the consistency of the coordinate system throughout the entire process, avoiding process failures due to accumulated deviations between equipment. Of course, changes in the parameters corresponding to the alignment marks are used to monitor wafer deformation, allowing for real-time correction of the corresponding system parameters. A series of error monitoring points are selected from the multiple alignment marks to monitor temperature drift and distortion errors.

[0034] The number of error monitoring points is at least three. That is, a series of error monitoring points includes at least three non-collinear alignment marks. Since it is necessary to perform two-dimensional linear interpolation in space on the initial distortion and positional drift obtained from the error monitoring points, at least three non-collinear alignment marks are selected to ensure the continuity and integrity of the interpolation results in two independent directions in space. In other words, it needs to cover the horizontal and vertical coordinate directions in the spatial coordinate system. Optionally, the alignment marks at the four corners of the standard silicon wafer can also be used as error monitoring points. That is, the error monitoring points are four alignment marks distributed diagonally. Because deformation is more likely to occur closer to the edge of the standard silicon wafer, and the four corners of the standard silicon wafer are far apart, they can represent different areas of the standard silicon wafer. This can more comprehensively characterize the influence of temperature changes on the standard silicon wafer. Therefore, selecting the alignment marks at the four corners of the standard silicon wafer can ensure that the relevant parameters characterizing deformation are obtained the largest, as well as the more comprehensive changes in relevant parameters caused by temperature changes, thereby ensuring that the systematic error of the workpiece obtained based on the standard silicon wafer is more comprehensive and accurate. Of course, error monitoring points such as 9 or 16 can also be selected to form a square dot matrix distribution. The more error monitoring points there are, the larger and more detailed the amount of data obtained during the error acquisition process of the workpiece stage will be. After a series of data processing steps, the system error of the workpiece stage will be more accurate.

[0035] Optionally, some preparatory work is required before obtaining the error of the workpiece stage. For example, after loading the standard silicon wafer into the workpiece stage, wafer centering, low-magnification alignment, and high-magnification alignment can be performed on the standard silicon wafer. Another example is to take an image of a certain alignment mark (such as the alignment mark located at the center of the standard silicon wafer) and use this image as a template image for subsequent image matching.

[0036] S120. Obtain the theoretical alignment position for each alignment mark.

[0037] The theoretical alignment position of the alignment mark can be the position of the alignment mark in the ideal coordinate system; or it can be the theoretical position of the workpiece stage when the alignment mark is located at the preset alignment position. The preset alignment position can be a preset position in the camera's field of view, such as the center position of the camera's field of view. In other words, theoretically, when the alignment mark acquired by the camera is located at the preset position in the camera's field of view, such as the center of the camera's field of view, this is the theoretical position of the workpiece stage.

[0038] In this embodiment, if the distribution of multiple alignment marks on the standard silicon wafer is uniform, the theoretical alignment position of the first alignment mark can be obtained first, and then the theoretical alignment position of the second alignment mark can be obtained based on the interval between the alignment marks, and so on, to obtain the theoretical alignment position of each alignment mark. If the distribution of multiple alignment marks on the standard silicon wafer is non-uniform, each alignment mark can be moved to a preset alignment position, the theoretical position of the workpiece stage can be recorded, and the theoretical alignment position corresponding to each alignment mark can be obtained.

[0039] Alternatively, the theoretical alignment position can be obtained directly from the pre-stored coordinates of each alignment mark. In this case, since there is a pre-stored coordinate mapping relationship between the coordinate system corresponding to the workpiece stage and the coordinate system corresponding to the wafer, the theoretical position of the workpiece stage can be obtained directly from the pre-stored coordinates of each alignment mark based on the coordinate mapping relationship.

[0040] S130. Determine the expansion coefficient of the standard silicon wafer, and based on the expansion coefficient, correct the theoretical alignment position of each alignment mark to obtain the optimized alignment position of the corresponding alignment mark.

[0041] The coefficient of thermal expansion is a physical quantity that characterizes the expansion or contraction of a silicon wafer when its size changes with temperature. Since a standard silicon wafer has a coefficient of thermal expansion, the alignment mark may not be in the preset alignment position when the workpiece stage is in the theoretical position. When the optimized alignment position of the alignment mark is obtained by using the coefficient of thermal expansion, it can be considered that the alignment mark is truly in the preset alignment position without the influence of other errors, such as the position of the workpiece stage when the alignment mark is truly in the preset position of the camera's field of view.

[0042] In one embodiment, the method for determining the coefficient of thermal expansion of a standard silicon wafer can be as follows: The standard silicon wafer is measured using a laser interferometer, including: installing the standard silicon wafer in a suitable position within a temperature control device to ensure that the laser beam of the laser interferometer can vertically and accurately irradiate a predetermined area on the surface of the silicon wafer. At an initial temperature (e.g., room temperature), the laser interferometer is turned on, and the initial state of the interference fringes is recorded as reference data. The temperature of the silicon wafer is slowly increased at a set heating rate (e.g., 1°C per minute). After the temperature stabilizes at certain intervals (e.g., 5°C), the movement of the interference fringes is recorded, and the change in the length of the silicon wafer is calculated. Using the same method, the change in length at different temperature points is recorded. The coefficient of thermal expansion for each temperature range is calculated based on a preset formula, and then the coefficient of thermal expansion of the silicon wafer over the entire temperature range is obtained through data fitting and other methods.

[0043] In another embodiment, determining the expansion coefficient of a standard silicon wafer includes: moving the workpiece stage to the theoretical alignment position of the error monitoring point, acquiring images of the corresponding error monitoring point to obtain the actual position of the error monitoring point, and calculating the expansion coefficient of the standard silicon wafer based on the theoretical alignment position and the actual position of the error monitoring point.

[0044] Specifically, the workpiece stage is moved to the theoretical alignment position of the error monitoring point, and the corresponding error monitoring point image is acquired. Then, based on the pre-stored template image, the image of the error monitoring point is matched to obtain the actual position of the error monitoring point. The expansion coefficient of the standard silicon wafer is calculated based on the theoretical alignment position and the actual position of the error monitoring point.

[0045] Furthermore, the expansion coefficient of the standard silicon wafer is calculated based on the theoretical alignment position and the actual position of the error monitoring point, including: calculating the actual distance between multiple adjacent error monitoring points based on the actual position of each error monitoring point; calculating the ideal distance between multiple adjacent error monitoring points based on the theoretical alignment position of each error monitoring point; and using the ratio between the sum of multiple actual distances and the sum of multiple ideal distances as the expansion coefficient.

[0046] Specifically, error monitoring points with adjacent relationships are identified from multiple error monitoring points; based on the actual position of each error monitoring point, the actual distance between multiple adjacent error monitoring points is calculated; based on the theoretical alignment position of each error monitoring point, the ideal distance between multiple adjacent error monitoring points is calculated; and the ratio between the sum of multiple actual distances and the sum of multiple ideal distances is used as the expansion coefficient.

[0047] For example, with Figure 2 For example, suppose the error monitoring points are four diagonally distributed alignment marks, namely points a, b, c, and d. The error monitoring points with adjacent relationships are: point a and point b, point b and point c, point c and point d, and point d and point a. The actual distance between points a and b is l1, the actual distance between points b and c is l2, the actual distance between points c and d is l3, and the actual distance between points d and a is l4. The ideal distance between adjacent error monitoring points is l0. Therefore, the expansion coefficient is...

[0048] Optionally, when acquiring images of error monitoring points, in order to reduce random errors caused by jitter, multiple images can be taken for each error monitoring point. The images obtained from the multiple acquisitions are matched with a template image to obtain multiple actual positions. The average of the multiple actual positions is used as the actual position corresponding to each error monitoring point.

[0049] In the embodiments of this application, after calculating the expansion coefficient, the theoretical alignment position of each alignment mark is multiplied by the expansion coefficient to obtain the corrected position corresponding to each alignment mark, which is denoted as the optimized alignment position.

[0050] like Figure 2 The diagram shows the correction of the theoretical alignment position of the error monitoring points. In the left diagram, the circular gray-filled dots represent the theoretical alignment positions of the error monitoring points, the circular black-filled dots represent the actual positions of the error monitoring points, and the dashed lines connect the uncorrected theoretical alignment positions of the error monitoring points. In the right diagram, the triangular black-filled dots represent the optimized alignment positions of the error monitoring points, and the solid lines connect the corrected optimized alignment positions of the error monitoring points.

[0051] S140. Based on the optimized alignment position of each error monitoring point, obtain the initial distortion of the corresponding error monitoring point.

[0052] The initial distortion can be the amount of deformation in the geometry or position of the standard silicon wafer caused by the workpiece stage clamping the standard silicon wafer (such as by vacuum adsorption) due to the error monitoring point being placed on the workpiece stage.

[0053] In one embodiment, obtaining the initial distortion of the error monitoring point using electronic speckle interferometry includes: placing a standard silicon wafer on a workpiece stage without activating the clamping device (or simulating an unclamped state), irradiating the silicon wafer surface with a laser, and recording the speckle pattern at this time as a reference image of the initial state. Activating the clamping device of the workpiece stage (e.g., vacuum adsorption) to place the silicon wafer in the clamped state used in actual operation. Irradiating the silicon wafer again with a laser and recording the speckle pattern again. Analyzing the changes in the two speckle patterns to calculate the displacement of the interference fringes. Based on the relationship between the displacement of the interference fringes and the displacement of the silicon wafer surface, the displacement information of each point on the silicon wafer surface is obtained. By analyzing and processing this displacement information, the initial distortion of the standard silicon wafer can be determined.

[0054] In another embodiment, the initial distortion of the corresponding error monitoring point is obtained based on the optimized alignment position of each error monitoring point, including: moving the workpiece stage to the optimized alignment position of each error monitoring point, acquiring the image of the corresponding error monitoring point to obtain the actual position of the corresponding error monitoring point; and obtaining the initial distortion of the corresponding error monitoring point based on the deviation between the actual position and the optimized alignment position of each error monitoring point.

[0055] Specifically, the workpiece stage is moved to the optimized alignment position of each error monitoring point, and images of the corresponding error monitoring points are acquired. Then, based on the pre-stored template images, template matching is performed on the images of the error monitoring points to obtain the actual positions of the error monitoring points. The deviation between the actual position and the optimized alignment position of each error monitoring point is calculated, and the deviation is used as the initial distortion variable of the corresponding error monitoring point.

[0056] S150. Perform two-dimensional linear interpolation based on the initial distortion of the error monitoring point to obtain the first mapping relationship between the initial distortion error of each alignment mark and the corresponding position.

[0057] The initial distortion error is the deviation between the deformation of the standard silicon wafer in terms of geometry or position caused by the clamping of the workpiece stage and the ideal state. The ideal state can be a state in which there is no geometric or positional deformation at the error monitoring point.

[0058] In this embodiment, based on the initial distortion of the error monitoring point, the distortion of other points on the standard silicon wafer under the same conditions can be calculated using a two-dimensional linear interpolation algorithm. This means the distortion of other alignment marks on the standard silicon wafer under the same conditions can also be calculated. After obtaining the initial distortion error of each alignment mark on the standard silicon wafer using two-dimensional linear interpolation, a correspondence can be established between the initial distortion error of each alignment mark and its corresponding position, i.e., a first mapping relationship.

[0059] S160. Sample the alignment marks along the preset path to obtain the original error of each alignment mark.

[0060] In this embodiment, the process of determining the preset path can be as follows: connect adjacent alignment marks in sequence to obtain the preset path; of course, the process of determining the preset path can also be as follows: select alignment marks as sampling grid points according to a certain density (the density can be two alignment marks, three alignment marks, or even more) on the standard silicon wafer, and connect the selected sampling grid points in sequence to obtain the optimal movement path for obtaining the error of the workpiece stage, that is, the preset path, which can also be called the sampling path.

[0061] like Figure 3 The diagram shows a schematic of the sampling grid. The hollow circles represent alignment marks, which are evenly distributed on the standard silicon wafer. The solid squares represent sampling grid points selected from these alignment marks. Figure 4 The diagram shows a sampling path. A square gray-filled box represents a grain, and alignment marks are evenly distributed between and within each grain. The arrows in the diagram indicate a sampling path. Understandably, the more sampling points, the better the effect on the stage system error and the smaller the residual.

[0062] In one embodiment, a laser interferometer is used to sample alignment marks along a preset path to obtain the original error of each alignment mark. This includes accurately measuring the displacement by measuring the optical path difference between the laser beam in the reference optical path and the measurement optical path. When the measuring head of the laser interferometer moves along the preset path and samples the alignment marks, the deviation of each alignment mark relative to the ideal position, i.e., the original error, can be calculated based on the measurement data of the measuring head at different alignment mark positions.

[0063] In another embodiment, sampling the alignment marks along a preset path to obtain the original error of each alignment mark includes: moving the workpiece stage along the preset path to the optimized alignment position of each alignment mark, acquiring an image of the corresponding alignment mark to obtain the actual position of the corresponding alignment mark, and determining the original error of the corresponding alignment mark based on the difference between the actual position and the optimized alignment position of each alignment mark.

[0064] Specifically, the workpiece stage is moved along a preset path to the optimized alignment position of each alignment mark, and an image of each alignment mark is acquired. Then, based on a pre-stored template image, template matching is performed on the image of each alignment mark to obtain the actual position of each alignment mark. The difference between the actual position and the corresponding optimized alignment position of each alignment mark is calculated, and this difference is used as the original error of the alignment mark. In this embodiment, the alignment marks can be all the alignment marks set on the wafer, or they can be a selection of alignment marks from all alignment marks. Figure 3 The sampling grid points shown are not restricted here.

[0065] S170. When sampling, the position drift of the error monitoring point at the corresponding time point in each temperature drift monitoring cycle is obtained, and interpolation is performed to obtain the second mapping relationship between the temperature drift error of the alignment mark and the corresponding position and time.

[0066] Temperature drift refers to the shift in physical quantities (such as dimensions and resistance) caused by temperature changes. By monitoring the positional changes of error monitoring points, the changes in a standard silicon wafer under different temperature conditions can be monitored in real-time or periodically. This allows for timely detection and correction of errors caused by temperature drift, ensuring product quality and process stability. The temperature drift monitoring cycle is the time interval for monitoring the positional changes of error monitoring points, which can be determined by a preset time interval or by the sampling time of a preset number of alignment marks. The positional drift amount refers to the change in position of the error monitoring point under the influence of temperature. Temperature drift error is the error caused by the positional drift of alignment marks due to temperature influence.

[0067] Since the entire error acquisition process spans a certain time period, and temperature drift error is unavoidable, it is necessary to periodically monitor temperature drift error. For example, during the image acquisition of the alignment mark in step S160, temperature drift error monitoring can be performed simultaneously. The shorter the period interval for temperature drift error monitoring, the more accurate the monitoring of temperature drift error will be.

[0068] In one embodiment, a displacement sensor can be used to obtain the positional drift of the error monitoring point at each time point corresponding to the temperature drift monitoring cycle. This includes: at each time point corresponding to the temperature drift monitoring cycle, collecting the displacement change of the error monitoring point using the displacement sensor; and calculating the positional drift of the error monitoring point at each time point corresponding to the temperature drift monitoring cycle by comparing the displacement change with the initial position. The initial position refers to the position of each error monitoring point at the first time point.

[0069] In another embodiment, obtaining the positional drift of the error monitoring point at each time point corresponding to each temperature drift monitoring cycle includes: during sampling, at each time point corresponding to each temperature drift monitoring cycle, moving the workpiece stage to the optimized alignment position of each error monitoring point, acquiring images of the corresponding error monitoring points to obtain the actual position of the corresponding error monitoring points, determining the original error of each error monitoring point at the corresponding time point based on the deviation between the actual position and the optimized alignment position of each error monitoring point, and determining the positional drift based on the deviation between the original error of each error monitoring point and the corresponding initial error, wherein the initial error is the original error of each error monitoring point at the first time point.

[0070] During the sampling of alignment marks, at each time point corresponding to the temperature drift monitoring cycle, the workpiece stage is moved to the optimized alignment position of each error monitoring point, and image sampling is performed on the error monitoring point to obtain its image. Based on the pre-stored template image, template matching is performed on the error monitoring point image to obtain the actual position of the drift monitoring point. Based on the deviation between the actual position and the optimized alignment position of each error monitoring point, the original error of each error monitoring point at the corresponding time point is determined. Based on the deviation between the original error and the corresponding initial error of each error monitoring point, the position drift is determined. The initial error is the original error of each error monitoring point at the first time point.

[0071] Specifically, interpolation is performed to obtain a second mapping relationship between the temperature drift error of the alignment mark and its corresponding position and time, including: performing one-dimensional linear interpolation of the position drift of the error monitoring point in the time dimension to obtain a first mathematical relationship between the position drift and time; and performing one-dimensional linear interpolation of the first mathematical relationship in the spatial dimension to obtain a second mapping relationship between the temperature drift error of the alignment mark and its corresponding position and time.

[0072] The position drift of the error monitoring point was measured at different time points, resulting in a series of discrete data points. By performing one-dimensional linear interpolation in the time dimension on these data points, the position drift at any intermediate time point was estimated, establishing the first mathematical relationship between position drift and time.

[0073] Because there are multiple error monitoring points on the silicon wafer, which are spatially distributed in different locations. Based on the locations of these error monitoring points and the first mathematical relationship between their respective positional drift and time, the relationship between temperature drift error and time at other locations on the silicon wafer (such as alignment marks) is calculated. After linear interpolation in the spatial dimension, the temperature drift error of the alignment marks is linked to the corresponding location and time to obtain the second mapping relationship.

[0074] S180. Based on the original error, the first mapping relationship, and the second mapping relationship, calculate the systematic error of the workpiece stage.

[0075] In one embodiment, the systematic error of the workpiece stage is calculated based on the original error, a first mapping relationship, and a second mapping relationship. This includes: for each alignment mark, recording the acquisition time when acquiring an image of the corresponding alignment mark; obtaining the initial distortion error from the first mapping relationship according to the corresponding position of each alignment mark; and obtaining the temperature drift error of the alignment mark from the second mapping relationship according to the corresponding position of each alignment mark and the acquisition time; removing the temperature drift error and the initial distortion error from the original error of each alignment mark to obtain the position error of each alignment mark; and using the position errors of all alignment marks as the systematic error of the workpiece stage. In this embodiment, when calculating the original error, the workpiece stage is moved along a preset path to the optimized alignment position of each alignment mark. While acquiring the image of the alignment mark, the acquisition time can be recorded simultaneously. Therefore, the initial distortion error can be obtained from the first mapping relationship according to the corresponding position of each alignment mark, and the temperature drift error of the alignment mark can be obtained from the second mapping relationship according to the corresponding position of each alignment mark and the acquisition time.

[0076] In this embodiment, the first mapping relationship is the relationship between the initial distortion error of each alignment mark and its corresponding position. Based on the position of the alignment mark in the currently acquired image, the initial distortion error of that alignment mark can be found or calculated from the first mapping relationship. The second mapping relationship is the relationship between the temperature drift error of the alignment mark and its corresponding position and time. Based on the position of the alignment mark in the currently acquired image and the time recorded during image acquisition, the temperature drift error of the alignment mark at that specific time and position can be obtained from the second mapping relationship.

[0077] In one embodiment, after calculating the systematic error of the workpiece stage, the method further includes: performing two-dimensional linear interpolation of the systematic error in the spatial dimension, which can obtain the position error of any point within the standard silicon wafer. This allows for a comprehensive understanding of the systematic deviation at different positions on the standard silicon wafer, resulting in a more accurate systematic error of the workpiece stage. In other words, it enables position compensation to be achieved whenever the motion stage moves to any position.

[0078] This application uses a standard silicon wafer as a reference to obtain the systematic error of the workpiece stage. However, the standard silicon wafer is subject to deformation due to expansion, distortion, and temperature drift. Therefore, these effects are removed when obtaining the systematic error of the workpiece stage to ensure the accuracy of the systematic error calculation. In the specific process of obtaining the systematic error, the expansion coefficient is first calculated and the theoretical alignment position is corrected. This compensates for the physical dimensional changes caused by the thermal expansion and contraction of the standard silicon wafer due to temperature variations, ensuring that the workpiece stage is not affected by the thermal expansion and contraction of the standard silicon wafer when moving according to the alignment marks on the standard silicon wafer. Next, considering the initial distortion deviation of the standard silicon wafer, the initial distortion value is obtained based on the optimized alignment position of the error monitoring point. Two-dimensional linear interpolation is used to obtain the first mapping relationship between the initial distortion error of each alignment mark and its corresponding position. This compensates for the error caused by the expansion or distortion of the standard silicon wafer due to the clamping method when the standard silicon wafer is placed on the workpiece stage, ensuring the accuracy of the subsequently obtained systematic error and thus ensuring more accurate compensation of the systematic error. The original error is then obtained by sampling along the preset path and aligning with the alignment mark. Simultaneously, the positional drift of the error monitoring point at different time points is acquired and interpolated to obtain a second mapping relationship between temperature drift error and position / time. This allows for dynamic compensation for the expansion or contraction of the standard silicon wafer caused by changes in ambient temperature, further improving the accuracy of calculating and acquiring the systematic error of the workpiece stage using the standard silicon wafer. The systematic error obtained in this way improves the accuracy of systematic error compensation, thereby enhancing the positioning accuracy and stability of the workpiece stage during processing or measurement operations, ultimately improving the processing or measurement quality of the product.

[0079] In a practical application, the original error obtained from measuring the alignment mark is generally considered to include systematic error, temperature drift error, distortion error, and random error. Random error can be effectively reduced by capturing multiple frames at once and averaging the positions of the alignment mark across those frames. Theoretically, the systematic error can be obtained by subtracting the temperature drift error and distortion error from the original error. The systematic error is calculated as follows:

[0080] Step 1: Sample the alignment marks in the standard silicon wafer along a preset path to obtain the original errors of each alignment mark in the x and y directions, denoted as Δx0 and Δy0. The original errors are related to the position of each alignment mark (assuming it is the i-th alignment mark) and the sampling time, and are therefore expressed as: Δx0(x i,y i ,t i ) and Δy0(x i ,y i ,t i ).

[0081] The second step assumes that the error monitoring points are four alignment marks distributed diagonally, or four alignment marks distributed in a square, namely DM1, DM2, DM3, and DM4. The position drift measured in the Tth temperature drift monitoring cycle is expressed as: Δx DM1 (x DM1 ,y DM1 ,t T ) and Δy DM1 (x DM1 ,y DM1 ,t T ), Δx DM2 (x DM2 ,y DM2 ,t T ) and Δy DM2 (x DM2 ,y DM2 ,t T ), Δx DM3 (x DM3 ,y DM3 ,t T ) and Δy DM3 (x DM3 ,y DM3 ,t T ), Δx DM4 (x DM4 ,y DM4 ,t T ) and Δy DM4 (x DM4 ,y DM4 ,t T ).

[0082] By performing one-dimensional linear interpolation over time, the relationship between temperature drift error and time at each error monitoring point can be obtained: Δx DM1 (x DM1 ,y DM1 ,t)=Δx DM1 (x DM1 ,y DM1 )f xDM1 (t) and Δy DM1 (x DM1 ,y DM1 ,t)=Δy DM1 (x DM1 ,y DM1 )f yDM1 (t), Δx DM2 (xDM2 ,y DM2 ,t)=Δx DM2 (x DM2 ,y DM2 )f xDM2 (t) and Δy DM2 (x DM2 ,y DM2 ,t)=Δy DM2 (x DM2 ,y DM2 )f yDM2 (t), Δx DM3 (x DM3 ,y DM3 ,t)=Δx DM3 (x DM3 ,y DM3 )f xDM3 (t) and Δy DM3 (x DM3 ,y DM3 ,t)=Δy DM3 (x DM3 ,y DM3 )f yDM3 (t), Δx DM4 (x DM4 ,y DM4 ,t)=Δx DM4 (x DM4 ,y DM4 )f xDM4 (t) and Δy DM4 (x DM4 ,y DM4 ,t)=Δy DM4 (x DM4 ,y DM4 )f yDM4 (t).

[0083] At a given time t i The temperature drift error at any location on the silicon wafer can be obtained by performing two-dimensional linear interpolation on the positions of these four error monitoring points: Δx drift1 =g x (x i ,y i )f x (t i ) and Δy drift1 =g y (x i ,y i )f y (t i ).

[0084] Thirdly, considering that the standard silicon wafer itself will have slight initial distortion, which will affect the systematic error of each alignment mark, the distortion error should be removed to obtain accurate systematic error. The distortion error of the four error monitoring points can be expressed as: Δx OD1 (x DM1 ,y DM1 ) and Δy OD1 (x DM1 ,y DM1 ), Δx OD2 (x DM2 ,y DM2 ) and Δy OD2 (x DM2 ,y DM2 ), Δx OD3 (x DM3 ,y DM3 ) and Δy OD3 (x DM3 ,y DM3 ), Δx OD4 (x DM4 ,y DM4 ) and Δy OD4 (x DM4 ,y DM4 Two-dimensional linear interpolation at a given location yields the distortion error at any location: Δx OD =h x (x i ,y i ),Δy OD =h y (x i ,y i )

[0085] Step 4: The result of the systematic error at any alignment mark at any given time is: Δx system =Δx0-Δx drift1 -Δx OD Δy system =Δy0-Δy drift1 -Δy OD .

[0086] Figure 5This application provides a flowchart of a method for acquiring errors in a workpiece stage, illustrating the implementation process. Specifically: S1. Select error monitoring points from alignment marks and plan a preset path (which can be called a sampling path) for sampling the alignment marks. S2. Obtain the theoretical alignment position of each error monitoring point, move the workpiece stage to the theoretical alignment position of the error monitoring point, acquire an image of the error monitoring point, perform template matching on the image using a template image, and calculate the expansion coefficient of the standard silicon wafer. S3. Multiply the theoretical alignment position of each alignment mark by the expansion coefficient to obtain the corrected optimized alignment position. S4. Based on the optimized alignment position of each error monitoring point, move the workpiece stage to the optimized alignment position of the error monitoring point, acquire an image of the error monitoring point, perform template matching on the image using a template image, and calculate the initial distortion of the error monitoring point. S5. Set a temperature drift monitoring period, the duration of which is less than the sampling time for all alignment marks in the sampling path. S6. Move the workpiece stage to the optimized alignment position of the alignment mark according to the preset path (i.e., the sampling path), and acquire an image of the alignment mark. S7. During the process of acquiring images of alignment marks, when the time point corresponding to the temperature drift monitoring cycle is reached, the workpiece stage is moved to the optimized alignment position of each error monitoring point, and image sampling is performed on the error monitoring point to obtain the image of the error monitoring point.

[0087] After sampling all alignment marks, the data processing section follows. S8: Template matching is performed on the images acquired for error monitoring points using template images. The positional drift at each time point corresponding to the temperature drift monitoring cycle is calculated, and interpolation is performed to obtain a second mapping relationship between the temperature drift error of the alignment mark and its corresponding position and time. S9: Two-dimensional linear interpolation is performed on the initial distortion to obtain a first mapping relationship between the initial distortion error of each alignment mark and its corresponding position. S10: Template matching is performed on the images acquired along a preset path for the alignment marks using template images, and the original error of each alignment mark is calculated. S11: Based on the original error, the first mapping relationship, and the second mapping relationship, the systematic error of the workpiece stage is calculated. S12: Two-dimensional linear interpolation of the systematic error in spatial dimension yields the positional error of any point within the standard silicon wafer. S13: During wafer inspection, the workpiece stage is calibrated based on the positional error. After completing the error calibration of the workpiece stage, it is necessary to determine whether the systematic error meets the target requirements. If not, the parameters of the current error acquisition strategy are evaluated and improved. If they meet the requirements, the error calibration ends.

[0088] Figure 6This is a schematic diagram of a wafer defect detection system provided in an embodiment of this application. The diagram illustrates that the defect detection system includes a motion controller, an illumination system, an imaging system, an image sensor, and a processor. The processor is connected to the motion controller, the illumination system, the imaging system, and the image sensor. After the processor executes the error acquisition method of the workpiece stage in any of the above embodiments and obtains the system error of the workpiece stage, it controls the motion controller to drive the workpiece stage to move. During the movement of the workpiece stage, the position of the workpiece stage is acquired based on the system error. The illumination system is used to output a light beam so that the light beam is focused onto the surface of the wafer under test through the objective lens. The imaging system is used to receive the reflected light from the wafer under test returned through the objective lens and transmit it to the image sensor. The image sensor is used to image the wafer under test and transmit the image of the wafer under test to the processor for wafer defect detection.

[0089] Note that the above are merely preferred embodiments and technical principles applied in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. For example, those skilled in the art can use the various forms of processes shown above to reorder, add, or delete steps; the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution of this application can be achieved, and no limitations are imposed herein.

[0090] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for obtaining the error of a workpiece stage, characterized in that, The method includes: A standard silicon wafer is configured, the standard silicon wafer including a plurality of alignment marks, and a series of error monitoring points are selected from the plurality of alignment marks, the series of error monitoring points including at least three non-collinear alignment marks; The theoretical alignment position of each alignment mark is obtained, wherein the theoretical alignment position is the theoretical position of the workpiece stage when the corresponding alignment mark is located at a preset alignment position; The expansion coefficient of the standard silicon wafer is determined, and the theoretical alignment position of each alignment mark is corrected according to the expansion coefficient to obtain the optimized alignment position of the corresponding alignment mark; Based on the optimized alignment position of each error monitoring point, the initial distortion of the corresponding error monitoring point is obtained; Two-dimensional linear interpolation is performed based on the initial distortion of the error monitoring points to obtain the first mapping relationship between the initial distortion error of each alignment mark and the corresponding position; The alignment marks are sampled along a preset path to obtain the original error of each alignment mark; During the sampling, the position drift of the error monitoring point at the corresponding time point in each temperature drift monitoring cycle is obtained, and interpolation is performed to obtain a second mapping relationship between the temperature drift error of the alignment mark and the corresponding position and time. The system error of the workpiece stage is calculated based on the original error, the first mapping relationship, and the second mapping relationship.

2. The method for obtaining the error of the workpiece stage according to claim 1, characterized in that, The step of obtaining the initial distortion of the corresponding error monitoring point based on the optimized alignment position of each error monitoring point includes: The workpiece stage is moved to the optimized alignment position of each error monitoring point, and images of the corresponding error monitoring points are acquired to obtain the actual position of the corresponding error monitoring points. Based on the deviation between the actual position and the optimized alignment position of each error monitoring point, the initial distortion of the corresponding error monitoring point is obtained.

3. The method for obtaining the error of the workpiece stage according to claim 1, characterized in that, The temperature drift monitoring cycle is a preset time interval or determined by the sampling time of a preset number of alignment marks; obtaining the position drift of the error monitoring point at the corresponding time point in each temperature drift monitoring cycle includes: During the sampling, at the time point corresponding to each temperature drift monitoring cycle, the workpiece stage is moved to the optimized alignment position of each error monitoring point, and the image of the corresponding error monitoring point is acquired to obtain the actual position of the corresponding error monitoring point. Based on the deviation between the actual position of each error monitoring point and the optimized alignment position, the original error of each error monitoring point at the corresponding time point is determined. The position drift is determined based on the deviation between the original error and the corresponding initial error at each error monitoring point, wherein the initial error is the original error at each error monitoring point at the first said time point.

4. The method for obtaining the error of the workpiece stage according to claim 3, characterized in that, The interpolation process to obtain a second mapping relationship between the temperature drift error of the alignment mark and its corresponding position and time includes: One-dimensional linear interpolation in the time dimension is performed on the position drift of the error monitoring point to obtain the first mathematical relationship between the position drift and time; By performing spatial linear interpolation on the first mathematical relationship, a second mapping relationship is obtained between the temperature drift error of the alignment mark and its corresponding position and time.

5. The method for obtaining the error of the workpiece stage according to claim 1, characterized in that, The step of sampling the alignment marks along a preset path to obtain the original error of each alignment mark includes: The workpiece stage is moved along a preset path to the optimized alignment position of each alignment mark, and images of the corresponding alignment marks are acquired to obtain the actual position of the corresponding alignment marks. Based on the difference between the actual position and the optimized alignment position of each alignment mark, the original error of the corresponding alignment mark is determined.

6. The method for obtaining the error of the workpiece stage according to claim 5, characterized in that, The calculation of the systematic error of the workpiece stage based on the original error, the first mapping relationship, and the second mapping relationship includes: For each alignment mark, when acquiring the image of the corresponding alignment mark, the acquisition time is recorded. According to the corresponding position of each alignment mark, the initial distortion error is obtained from the first mapping relationship. According to the corresponding position of each alignment mark and the acquisition time, the temperature drift error of the alignment mark is obtained from the second mapping relationship. The position error of each alignment mark is obtained by removing the temperature drift error and the initial distortion error from the original error of each alignment mark, and the position errors of all the alignment marks are taken as the systematic error of the workpiece stage.

7. The method for obtaining the error of the workpiece stage according to claim 1, characterized in that, Determining the coefficient of thermal expansion of the standard silicon wafer includes: The workpiece stage is moved to the theoretical alignment position of the error monitoring point, and the corresponding image of the error monitoring point is acquired to obtain the actual position of the error monitoring point. The expansion coefficient of the standard silicon wafer is calculated based on the theoretical alignment position and the actual position of the error monitoring point.

8. The method for obtaining the error of the workpiece stage according to claim 7, characterized in that, The error monitoring points are four alignment marks distributed diagonally; the calculation of the expansion coefficient of the standard silicon wafer based on the theoretical alignment position and the actual position of the error monitoring points includes: Based on the actual location of each error monitoring point, the actual distance between multiple adjacent error monitoring points is calculated. Based on the theoretical alignment position of each error monitoring point, the ideal distance between multiple adjacent error monitoring points is calculated. The ratio between the sum of multiple actual spacings and the sum of multiple ideal spacings is used as the expansion coefficient.

9. The method for obtaining the error of the workpiece stage according to claim 1, characterized in that, After calculating the systematic error of the workpiece stage, the following steps are included: The positional error of any point within the standard silicon wafer is obtained by performing two-dimensional linear interpolation in the spatial dimension on the system error.

10. A wafer defect detection system, characterized in that, The defect detection system includes a motion controller, an illumination system, an imaging system, an image sensor, and a processor; the processor is connected to the motion controller, the illumination system, the imaging system, and the image sensor, respectively. After the processor executes the error acquisition method of the workpiece stage as described in any one of claims 1 to 9 and obtains the system error of the workpiece stage, it controls the motion controller to drive the workpiece stage to move. During the movement of the workpiece stage, the position of the workpiece stage is calibrated based on the system error. The illumination system is used to output a light beam so that the light beam is focused onto the surface of the wafer under test through the objective lens. The imaging system is used to receive the reflected light from the wafer under test returned through the objective lens and transmit it to the image sensor. The image sensor is used to image the wafer under test and transmit the image of the wafer under test to the processor for wafer defect detection.

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