Phased array chip testing apparatus, method, system and tester

Abstract

The embodiment of the application provides a phased array chip testing device, method, system and testing machine. The device comprises: a closed light-tight limited space, a test phased array antenna, a testing machine, the testing machine is in communication connection with the test phased array antenna and the phased array chip to be tested respectively; the closed light-tight limited space comprises a first area and a second area, the first area is used for placing the phased array chip to be tested, and the second area is used for placing the test phased array antenna; the test phased array antenna and the phased array chip to be tested are oppositely arranged in the interior of the limited space; the testing machine is used for controlling the test phased array antenna to emit a plurality of test beam signals of test phases in turn, so that after any test beam signal emitted once reaches the phased array chip to be tested through the limited space, the phased array chip to be tested simultaneously receives the test beam signals from the plurality of test phases; and each test beam signal is used for determining whether the phased array chip to be tested is qualified. The method is used to improve the testing efficiency.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a phased array chip testing device, method, system and testing machine. Background Technology

[0002] Millimeter-wave phased array antenna testing typically employs a large anechoic chamber with a mechanical turntable, combined with standard test antennas and RF measuring instruments to complete the directional scanning and measurement process.

[0003] However, this solution relies on a mechanical turntable rotating point by point, and the scanning speed is limited by the accuracy and stroke of physical motion, resulting in a long testing cycle. At the same time, the anechoic chamber needs to meet a large testing distance, which leads to high space occupation and construction costs. Long-path transmission will also increase signal loss and system configuration complexity.

[0004] Therefore, improving the testing rate in millimeter-wave phased array chip testing has become a technical problem that needs to be solved. Summary of the Invention

[0005] This application provides phased array chip testing apparatus, method, system, and testing machine to improve testing efficiency.

[0006] In a first aspect, embodiments of this application provide a phased array chip testing apparatus, comprising:

[0007] A closed, opaque, limited space, a phased array antenna under test, and a test machine. The test machine is communicatively connected to both the phased array antenna under test and the phased array chip under test.

[0008] The enclosed, opaque, and limited space includes a first region and a second region. The first region is used to place the phased array chip under test, and the second region is used to place the accompanying phased array antenna. The accompanying phased array antenna and the phased array chip under test are arranged opposite to each other inside the limited space. The accompanying phased array antenna includes an antenna with a planar array structure.

[0009] The tester is used to control the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested. This allows the phased array chip under test to receive test beam signals from multiple phases simultaneously after any transmitted test beam signal reaches the phased array chip under test through a limited space. Each test beam signal is used to determine whether the phased array chip under test is qualified.

[0010] In one possible embodiment, it also includes:

[0011] The test carrier, test fixture, and gripping structure are connected to the test machine via communication.

[0012] The test fixture is located on the test carrier board and is used to pick up the phased array chip under test in response to the test command sent by the test machine and place the phased array chip under test in the first area of ​​the limited space.

[0013] The test carrier plate is located outside the first region of the confined space;

[0014] The gripping structure is located on the side of the test carrier away from the confined space. It is used to grip the phased array chip under test in response to the gripping command sent by the test machine and place the phased array chip under test on the test fixture of the test carrier.

[0015] In one possible embodiment, the first region is located in a region of a limited space near a first boundary, and the second region is located in a region of a limited space near a second boundary, with the first boundary and the second boundary being set opposite to each other.

[0016] Secondly, embodiments of this application provide a phased array chip testing method, applied to a phased array chip testing device including the above-mentioned one, the phased array chip testing method comprising:

[0017] The accompanying phased array antenna is controlled to sequentially transmit multiple test beam signals of the phase to be tested, so that any one of the transmitted test beam signals can reach the phased array chip under test through a closed, opaque, and limited space.

[0018] When the test beam signal of any phase under test arrives at the phased array chip under test, control the phased array chip under test to simultaneously receive test beam signals from multiple phases under test.

[0019] The test beam signal is used to determine whether the phased array chip under test is qualified.

[0020] In one possible embodiment, controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested includes:

[0021] The test beam signal is controlled to transmit through the phased array antenna under test in the direction of the normal. The direction of the normal indicates the direction perpendicular to the plane in which the phased array antenna under test is located.

[0022] The accompanying phased array antenna is controlled to sequentially transmit test beam signals in the direction of illegal lines.

[0023] In one possible embodiment, before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, the method further includes:

[0024] Obtain the phase range and step size to be measured;

[0025] Multiple phases to be measured are determined based on the range of the phase to be measured and the step size;

[0026] The transmit phase of the phased array antenna to be tested is configured to be the phase to be tested;

[0027] Configure the receiving phase of the phased array chip under test as the phase to be tested.

[0028] In one possible embodiment, determining whether the phased array chip under test is qualified based on the test beam signal includes:

[0029] Obtain the preset amplitude range corresponding to each phase to be measured;

[0030] If the beam amplitude of the test beam signal corresponding to any phase under test is within the corresponding preset amplitude range, the phased array chip under test is determined to be qualified.

[0031] If the beam amplitude corresponding to one or more phases under test is not included in the preset amplitude range, the phased array chip under test is determined to be unqualified.

[0032] In one possible embodiment, determining whether the phased array chip under test is qualified based on the test beam signal further includes:

[0033] A beam pattern is generated based on the phase to be measured and the beam amplitude of the test beam signal;

[0034] The beam pattern is analyzed by a target neural network model to determine whether the beam pattern is qualified. The target neural network model is obtained by training multiple sets of historical data. Each set of historical data includes: historical beam pattern and labels indicating whether the historical beam pattern is qualified.

[0035] If the beam pattern is acceptable, the phased array chip under test is deemed acceptable.

[0036] If the beam pattern is unqualified, the phased array chip under test is determined to be unqualified.

[0037] In one possible embodiment, after determining whether the phased array chip under test is qualified based on the test beam signal, the method further includes:

[0038] Once the phased array chip under test is determined to be qualified, the control test fixture will clamp the phased array chip under test into the qualified area;

[0039] If the phased array chip under test is determined to be defective, the control test fixture will clamp the phased array chip under test to the defective area.

[0040] In one possible embodiment, controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested further includes:

[0041] Upon receiving the transmission signal from the test unit, the accompanying phased array antenna is controlled to sequentially transmit test beam signals of multiple phases to be tested.

[0042] In one possible embodiment, before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, the method further includes:

[0043] Phase correction is performed on the accompanying phased array antenna and the phased array chip under test to make the transmission phase of the accompanying phased array antenna the same as the reception phase of the phased array chip under test.

[0044] The path loss of the test beam signal in the limited space is compensated to ensure that the test beam signal received by the phased array chip under test is the same as the test beam signal transmitted by the phased array antenna under test.

[0045] In one possible embodiment, phase correction is performed on the accompanying phased array antenna and the phased array chip under test, including:

[0046] Control the phased array antenna under test to transmit the test beam signal of the target phase;

[0047] The phased array chip under test is controlled to receive the test beam signal from the target phase to obtain the received phase.

[0048] Calculate the difference between the target phase and the received phase;

[0049] Phase correction is performed on the accompanying phased array antenna and the phased array chip under test based on the difference to minimize the difference.

[0050] In one possible embodiment, the phased array chip under test is a multi-mode chip, and the accompanying phased array antenna is controlled to sequentially transmit multiple test beam signals of the phases under test, including:

[0051] Multiple test frequencies of the phased array chip under test are determined, and any one of the test frequencies corresponds to a communication mode of the phased array chip under test.

[0052] For any given frequency to be tested, the accompanying phased array antenna is controlled to sequentially transmit multiple test beam signals of the phases to be tested according to the frequency to be tested.

[0053] In one possible embodiment, determining whether the phased array chip under test is qualified based on the test beam signal includes:

[0054] If the test beam signals of multiple frequencies under test are all qualified, the phased array chip under test is determined to be qualified.

[0055] If the test beam signal at any of the tested frequencies fails, the phased array chip under test is determined to be defective.

[0056] In one possible embodiment, before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested according to the frequency to be tested, the method further includes:

[0057] Perform Fourier transform on the preset beam signals corresponding to multiple frequencies to be measured to obtain the frequency domain signals corresponding to the preset beam signals;

[0058] Calculate the channel frequency response corresponding to any measured frequency in the frequency domain signal. The channel frequency response represents the change in the signal corresponding to the measured frequency after passing through the transmission channel.

[0059] The compensation signal is obtained by calculating the reciprocal of the frequency domain signal and the channel frequency response;

[0060] The inverse Fourier transform of the compensation signal is performed to obtain the frequency-domain compensated test beam signal, in order to compensate for the path loss differences of test beam signals at different frequencies.

[0061] Thirdly, embodiments of this application provide a phased array chip testing system, comprising:

[0062] The phased array chip under test;

[0063] The aforementioned phased array chip testing device is used to test the phased array chip under test.

[0064] Fourthly, embodiments of this application provide a testing machine, including:

[0065] Memory, processor;

[0066] Memory, used to store processor-executable instructions;

[0067] The processor executes the methods provided above.

[0068] The phased array chip testing apparatus, method, system, and testing machine provided in this application embodiment, by setting up a closed, opaque, limited space, and within this limited space, arranging the accompanying phased array antenna opposite to the phased array chip under test, and having the testing machine control the accompanying phased array antenna to sequentially transmit test beam signals of multiple test phases, enables the phased array chip under test to simultaneously receive test beam signals from multiple test phases within the limited space and complete the qualification judgment accordingly. This reduces the dependence on large anechoic chambers, mechanical turntables, and long-distance scanning testing conditions, improves directional scanning testing efficiency, and reduces testing space occupation, system complexity, and testing costs. Attached Figure Description

[0069] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0070] Figure 1 This is a schematic diagram of a phased array testing scenario in existing technologies;

[0071] Figure 2A schematic diagram of the phased array chip testing device provided in this application;

[0072] Figure 3 A flowchart illustrating the phased array chip testing method provided in this application;

[0073] Figure 4 A standard beam pattern is provided for this application;

[0074] Figure 5 This is a schematic diagram of the test machine provided in this application.

[0075] The above figures include the following reference numerals:

[0076] 10. Anechoic chamber; 11. Control room; 12. Mechanical turntable; 13. Chip under test; 14. Test antenna; 15. RF measuring instrument; 20. Confined space; 21. Accompanying phased array antenna; 22. Test machine; 23. Phased array chip under test; 24. First area; 25. Second area; 26. Test carrier board; 27. Test fixture; 28. Gripping structure; 401. Processor; 402. Memory; 403. Communication component; 404. Bus.

[0077] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0078] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0079] First, let me explain the terms used in this application:

[0080] A phased array antenna is an antenna system that achieves electronic beam steering by adjusting the phase and amplitude of the radiating elements in the antenna array. It consists of an antenna array, a feed network, and a beam controller. By adjusting the phase, a small time difference (phase difference) is set for the signals of different antenna elements in the array, allowing the electromagnetic waves to superimpose in space. The signal in the in-phase region is enhanced to form a directional beam, while the signal in the out-of-phase region is weakened, thus deflecting the beam in a specific direction.

[0081] Millimeter waves: generally refer to electromagnetic waves with a frequency range of 30 GHz to 300 GHz (corresponding to wavelengths of 1 to 10 millimeters); however, in the field of communication (such as 5G NR), 24.25 GHz to 52.6 GHz is often also referred to as millimeter waves.

[0082] Beamforming, also known as spatial filtering, is a signal processing technique that uses sensor arrays to send and receive signals in a directional manner.

[0083] Figure 1 This is a schematic diagram of a phased array testing scenario in existing technology, such as... Figure 1 As shown, it includes an anechoic chamber 10, a control room 11, a mechanical turntable 12, a chip under test 13, a test antenna 14, and an RF measuring instrument 15, which is communicatively connected to the test antenna 14.

[0084] In existing technologies, a large anechoic chamber 10 is typically used in conjunction with a mechanical turntable 12, along with a standard test antenna 14 and an RF measurement instrument 15, to complete directional scanning and parameter measurement. Specifically, the chip under test (DUT) 13 is fixed on the mechanical turntable 12, the test antenna 14 is positioned inside the anechoic chamber 10 opposite to the DUT 13, the RF measurement instrument 15 provides an excitation signal to the test antenna 14, and the DUT 13 receives the test signal under different spatial orientations. Subsequently, the RF measurement instrument 15 records the amplitude, phase, or power data at the corresponding angles.

[0085] In order to obtain a complete directional response, the mechanical turntable 12 needs to rotate point by point according to the preset angle range, so that the chip under test 13 is tested in multiple directions in sequence. Then, the radiation pattern is generated based on the acquisition results, and it is determined whether the main lobe, side lobe and beam pointing meet the requirements.

[0086] While this type of solution can accomplish routine testing tasks, its shortcomings are also quite prominent. First, directional scanning relies on mechanical rotation, the rotation speed of which is limited by motor response, positioning accuracy, stopping and settling time, and round-trip travel, resulting in a long test cycle time, making it difficult to meet the high throughput requirements of mass chip production. Second, large anechoic chambers are required to accommodate long test distances, resulting in large space requirements, high construction costs, and difficulties in relocating and expanding the test system. Third, millimeter-wave signals experience significant loss over long propagation paths, often requiring additional RF link compensation measures, increasing system complexity and maintenance burden. Simultaneously, the mechanical motion itself can introduce repetitive positioning errors, making consistency control between different test batches more difficult, ultimately impacting the balance between test efficiency, test accuracy, and test cost.

[0087] In view of this, how to improve testing efficiency in millimeter-wave phased array chip testing has become an urgent technical problem to be solved.

[0088] Based on the above scenarios, it is clear that the existing technology of using a mechanical turntable to test phased arrays suffers from low testing efficiency.

[0089] The phased array chip testing device provided in this application achieves testing through a collaborative architecture of a closed, opaque, limited space, a companion phased array antenna, and a testing machine. The limited space includes a first region for placing the phased array chip under test (DUT) and a second region for placing the companion phased array antenna. The companion phased array antenna and the DUT are positioned opposite each other within the limited space, and the companion phased array antenna employs a planar array structure. During testing, the testing machine communicates with both the companion phased array antenna and the DUT, controlling the companion phased array antenna to sequentially transmit test beam signals for multiple test phases. After any transmitted test beam signal reaches the DUT through the limited space, the DUT can simultaneously receive test beam signals from multiple test phases and use these signals to determine whether the DUT is qualified. This technical solution replaces the traditional testing method, which relies on large spaces and mechanical point-by-point scanning, with a relative arrangement within a limited space and a multi-test-phase test beam signal transmission mechanism, thus providing a foundation for more efficient phased array chip testing.

[0090] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0091] Figure 2 This is a schematic diagram of the phased array chip testing device provided in this application, as shown below. Figure 2 As shown, the device includes:

[0092] A closed, opaque, limited space 20, a phased array antenna 21 under test, and a test machine 22 are included. The test machine 22 is communicatively connected to the phased array antenna 21 under test and the phased array chip 23 under test, respectively.

[0093] Among them, the confined space 20 is a closed and opaque cavity used for electromagnetic isolation testing of the phased array chip 23 under test and the accompanying phased array antenna 21. Its function is to provide a controlled spatial environment for the testing process and limit external light and electromagnetic interference from entering the test path, thereby ensuring that the millimeter wave test signal propagates under controllable conditions and is stably acquired.

[0094] In one possible embodiment, the confined space 20 can be configured as a hexahedral box structure or a cylindrical cavity structure. The box wall can be made of a metal shielding layer, a wave-absorbing material layer or a composite layer of metal and wave-absorbing material. Specifically, it can be implemented by means of aluminum alloy frame with wave-absorbing coating, steel plate shell with foam wave absorber, and composite resin shell with multi-layer wave-absorbing lining.

[0095] The confined space 20 is usually used as the main supporting structure of the overall test device. Its internal space is divided into different functional areas for device placement and beam transmission. Doors, covers or maintenance openings can be configured on the outside to facilitate the clamping of the device under test and maintenance of internal components. During normal testing, it is kept closed to reduce environmental disturbance.

[0096] Its internal length, width, and height form a proportional relationship adapted to the propagation direction of the test beam, and necessary installation and electromagnetic isolation margins are reserved for the first region 24 and the second region 25, for example, it can be 300mm×300mm×500mm. It should be understood that the above example is only illustrative and not limiting. The enclosed, opaque, limited space 20 can also be replaced by a dark box, shielding cabinet, partial shielding cover, or isolation test chamber with electromagnetic shielding function.

[0097] The enclosed, opaque, limited space 20 includes a first region 24 and a second region 25. The first region 24 is used to place the phased array chip 23 under test, and the second region 25 is used to place the accompanying phased array antenna 21. The accompanying phased array antenna 21 and the phased array chip 23 under test are arranged opposite to each other inside the limited space. The accompanying phased array antenna 21 includes an antenna with a planar array structure.

[0098] The accompanying phased array antenna 21 refers to a planar array antenna set in a limited space for transmitting test beam signals. Its function is to form multiple test beams corresponding to the phase to be tested by adjusting the phase and amplitude of the array elements, thereby replacing the traditional mechanical scanning method to achieve electronic beam pointing switching.

[0099] In one possible embodiment, the accompanying phased array antenna 21 can be a rectangular planar array or a partitioned planar array. The accompanying phased array antenna 21 is installed in a second region 25 within a limited space and is spatially arranged opposite to the phased array chip 23 under test, with its transmission direction facing the first region 24, so that the test beam signal can directly propagate to the phased array chip 23 under test within the limited space. Under the control of the test machine 22, the accompanying phased array antenna 21 can sequentially execute different phase configurations to transmit test beam signals of multiple phases under test. In other embodiments, this antenna can also be replaced by a digital beamforming antenna, a hybrid beamforming antenna, or a multi-array combination antenna to adapt to different test architectures.

[0100] The phased array chip under test 23 refers to the phased array integrated circuit whose beamforming or receiving performance is to be tested. Its function is to receive the test beam signal and output the corresponding electrical performance data so that the test machine 22 can determine whether it meets the predetermined requirements.

[0101] The phased array chip under test (DUT) 23 is placed within a limited space in the first region 24 and fixed by a test carrier 26, a fixture, or other support structure to ensure its positional stability and attitude consistency during testing. Its dimensions are typically smaller than the support area of ​​the test carrier 26 and are adapted to the clamping structure, allowing it to remain in a controlled, stationary state when receiving test beam signals from different directions. During testing, the DUT 23 will output amplitude, phase, power, or other relevant response data based on the received test beam signals. The chip can also be replaced by a phased array module, an RF front-end chip, or an integrated antenna chip to accommodate different product forms.

[0102] The tester 22 is used to control the accompanying phased array antenna 21 to sequentially transmit test beam signals of multiple phases to be tested, so that after any one of the transmitted test beam signals reaches the phased array chip 23 under test through a limited space, the phased array chip 23 under test simultaneously receives test beam signals from multiple phases to be tested; each test beam signal is used to determine whether the phased array chip 23 under test is qualified.

[0103] The test machine 22 refers to the test control equipment used to control the phased array antenna 21 under test and communicate with the phased array chip 23 under test. Its function is to issue test commands, control beam parameters, collect test results, and determine whether the phased array chip 23 under test is qualified based on the results.

[0104] In one possible embodiment, the test unit 22 can be a rack-mounted instrument, an embedded control host, or a modular test platform. The test unit 22 is typically located outside a confined space or on the control side electrically connected to the confined space. It establishes control and data interaction relationships with the phased array antenna 21 under test and the phased array chip 23 under test via communication interfaces. The interface type can be configured as an RF interface, a digital control interface, or a high-speed data interface according to system requirements. Driven by a software program, the test unit 22 controls the transmission state of the phased array according to a preset sequence and analyzes and judges the received response signals, thereby completing the consistency test of the chip performance.

[0105] The test beam signal refers to the radio frequency test excitation signal emitted by the accompanying phased array antenna 21, used to characterize different phase configurations under test. Its function is to enable the phased array chip 23 under test to receive and output corresponding responses under different phase conditions, so that the tester 22 can make a pass / fail judgment. In one possible embodiment, the test beam signal can be a single-frequency continuous wave, a pulse beam, a swept beam, or a modulated beam. The specific carrier can be located in the millimeter-wave band, and the envelope, phase configuration, and dwell time of the signal are all preset by the tester 22. After the test beam signal is emitted from the second region 25 of the confined space, it propagates through space to the phased array chip 23 under test in the first region 24. During the beam pointing switching process, the tester 22 can change the array phase of the accompanying phased array antenna 21 according to a preset sequence, so that the beams corresponding to different phases under test are formed and radiated in sequence. Its beamwidth, transmission power, and signal duration can be set according to the test accuracy and path loss requirements, and form a matching relationship with the size of the confined space and the array aperture, so as to obtain stable signal coverage in the controlled space. The test beam signal can also be replaced by an coded beam, a phase-coded pulse, or a multi-carrier test waveform to adapt to different test criteria and signal processing methods.

[0106] The test carrier 26, the test fixture 27, and the gripping structure are connected to the test machine 22 for communication.

[0107] The test fixture 27, located on the test carrier board 26, is used to clamp the phased array chip 23 under test in response to the test command sent by the test machine 22, and place the phased array chip 23 under test in the first region 24 of the limited space.

[0108] Test carrier plate 26 is located outside the first region 24 of the confined space;

[0109] The gripping structure, located on the side of the test carrier board 26 away from the confined space, is used to grip the phased array chip 23 under test in response to the gripping command sent by the test machine 22, and place the phased array chip 23 under test on the test fixture 27 of the test carrier board 26.

[0110] In one possible embodiment, the test carrier 26 is a carrier structure used to carry the phased array chip 23 under test and communicate with the test machine 22. Its function is to provide a platform for the automated loading, unloading, positioning, and test transfer of the phased array chip 23 under test. The test carrier 26 is located outside the first region 24 of the confined space and forms a loading and unloading relationship with the test fixture 27 and the gripping structure, respectively. The test machine 22 uses the test carrier 26 to coordinate the control of the fixture and the gripping structure to ensure that the phased array chip 23 under test has completed attitude adjustment and initial positioning before entering the confined space.

[0111] The test fixture 27 is a clamping mechanism mounted on the test carrier 26 for gripping the phased array chip 23 under test and placing it in the first region 24 of the confined space. Its function is to achieve stable positioning and maintain the test attitude of the phased array chip 23 under test. The test fixture 27 is located on the test carrier 26 and is communicatively connected to the test machine 22. After receiving test commands from the test machine 22, it performs opening, clamping, releasing, or lifting actions to deliver the phased array chip 23 under test into a predetermined position within the first region 24 of the confined space, thus satisfying the relative test relationship with the accompanying phased array antenna 21. The test fixture 27 can be structurally a three-jaw clamp, etc.

[0112] The gripping structure is an automated mechanical structure located on the side of the test carrier 26 away from the confined space, used to grip the phased array chip 23 under test and place it onto the test fixture 27. Its function is to complete the loading, unloading, and sorting of the phased array chip 23 under test. The gripping structure is communicatively connected to the test machine 22. After receiving the gripping command sent by the test machine 22, it performs translation, lifting, extension, or rotational movements according to a predetermined trajectory to grip the phased array chip 23 under test from the outside and accurately place it into the test fixture 27 on the test carrier 26, so as to realize automatic loading before testing or transfer and sorting after testing.

[0113] When the system starts, the test machine 22 first sends a gripping command to the gripping structure according to the test task of the phased array chip 23 under test. The gripping structure picks up the chip on the side of the test carrier 26 away from the confined space and smoothly moves it to the test fixture 27 position on the test carrier 26. Then, the test fixture 27 responds to the test command sent by the test machine 22, clamps, aligns and locks the chip, and places the phased array chip 23 under test in the first region 24 of the confined space, so that it maintains a predetermined spatial correspondence with the accompanying phased array antenna 21 located in the second region 25.

[0114] The first region 24 is located in a confined space near the first boundary, and the second region 25 is located in a confined space near the second boundary. The first boundary and the second boundary are set opposite to each other.

[0115] The first region 24 refers to the test area set in a limited space to accommodate the phased array chip 23 under test. Its function is to arrange the phased array chip 23 under test in a position close to the first boundary, so as to form a stable opposing test relationship with the accompanying phased array antenna 21 located on the opposite side.

[0116] To facilitate testing and ensure the strength of the received test signal, the phased array chip 23 under test and the accompanying phased array antenna 21 maintain a predetermined spatial correspondence. Specifically, the phased array chip 23 under test and the accompanying phased array antenna 21 can be arranged opposite each other, such as... Figure 2As shown. This ensures that the main lobe of the chip under test (DUT) coincides with the main lobe axis of the antenna under test, maximizing signal strength and enabling accurate evaluation of key performance parameters such as beam phase and amplitude.

[0117] In one possible embodiment, the first area 24 can be implemented by ground marking partitions or frame-type isolation partitions. The isolation material can be a metal partition, a wave-absorbing partition, or a composite insulating partition to further reduce crosstalk between areas and improve the electromagnetic environment.

[0118] The first region 24 is positioned opposite the second region 25, located on the opposite side of the phased array antenna 21 under test, enabling the test beam signal to reach the phased array chip 23 under test along a predetermined propagation path within a limited space. Its area or volume must meet the installation margin requirements of the phased array chip 23 under test, the test fixture 27, and the gripping action, while also considering the signal incident direction and reflection control conditions. During operation, it typically remains static, only serving the functions of device placement and testing. The first region 24 can also be replaced by a front test area, a chip carrier area, or a near-field receiving area to adapt to different assembly and testing organization methods.

[0119] The second region 25 refers to the transmission area set within a limited space to accommodate the phased array antenna 21 under test. Its function is to provide spatial support for the generation, transmission, and array mounting of the test beam signal. In one possible embodiment, the second region 25 can be implemented through a partitioned housing, support frame area, or independent mounting position in a cavity. The support component can be a metal bracket, an insulating bracket, or a composite material bracket to meet the needs of antenna fixation, power supply wiring, and heat dissipation. The second region 25 is set opposite to the first region 24 and corresponds to the phased array chip 23 under test through the propagation path within the limited space, so that the test beam signal transmitted by the phased array antenna 21 under test can accurately cover the location of the device under test. Its spatial dimensions should meet the requirements of phased array antenna array mounting, power supply connection, and heat dissipation, and ensure relative positional accuracy with the first region 24 to reduce the impact of beam offset on the test results. This region is used to keep the antenna array fixed and bear the beam transmission process during operation, and can also be replaced by a rear test area, antenna support area, or transmission array area.

[0120] The phased array chip testing device provided in this application places the phased array chip under test and the accompanying phased array antenna in a closed, opaque, limited space. Within this limited space, a first region and a second region are set up opposite to each other. The test beam signal propagates and is received within this controlled cavity environment. The testing machine then controls the accompanying phased array antenna to sequentially form multiple test beams according to a preset phase sequence. This allows the phased array chip under test to obtain response information in multiple directions without relying on mechanical rotation or large-scale spatial scanning. When the system starts, the testing machine first initializes the device positions, connection states, and beam parameters within the limited space. It then drives the accompanying phased array antenna to generate test beam signals according to a predetermined phase combination. After the test beam signals are transmitted from the second region to the first region, they travel along a fixed propagation path within the limited space to reach the phased array chip under test. Upon receiving the beam corresponding to each phase, the phased array chip under test outputs corresponding response data. The testing machine then collects, compares, and judges this response data to determine whether the chip's beam receiving capability, phase consistency, and directional response meet preset standards.

[0121] Because the phased array antenna used in the test adopts a planar array structure and switches the phase to be tested electronically, the testing process can reduce the dependence on mechanical turntables and large-size anechoic chambers, thereby shortening the test cycle, reducing site occupation, and reducing repeatability deviations caused by mechanical positioning errors. At the same time, the enclosed and opaque limited space can isolate external electromagnetic interference and light interference, allowing millimeter-wave test signals to complete radiation and reception in a more stable environment, which is conducive to improving the consistency of test data and the reliability of judgment.

[0122] It should be understood that the above examples are for demonstration purposes only and are not limiting. Limited space, accompanying phased array antennas, and test equipment can all be replaced or structurally adjusted according to actual production and testing needs.

[0123] Figure 3 The flowchart of the phased array chip testing method provided in this application is shown below. Figure 3 As shown, the method includes:

[0124] S201, control the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phase to be tested, so that any one of the transmitted test beam signals can reach the phased array chip under test through a closed, opaque, and limited space.

[0125] In this embodiment of the application, the executing entity can be a test machine that is communicatively connected to the phased array antenna under test and the phased array chip under test. The test machine may include an industrial control computer, a radio frequency control unit, a timing control unit, and a data processing unit, or be implemented by an integrated test platform composed of the above functional units.

[0126] The accompanying phased array antenna is a planar array structure antenna set in the second region of a limited space. Its array elements form transmit beams with different directions through a controllable phase shifting and amplitude adjustment network.

[0127] The phase to be measured can be understood as a set of phase configurations used to characterize the pointing state of the test beam or a set of array phase combinations corresponding to a preset spatial direction, such as multiple phase angles in the range of -60° to 60°.

[0128] The test beam signal can be understood as a directional radio frequency signal formed and radiated by the accompanying phased array antenna in the millimeter wave band according to the corresponding array excitation method.

[0129] In practice, before the test begins, the tester can read the product model, target operating frequency band, preset test angle range, phase step parameters and pass / fail judgment template of the phase array chip under test, and generate the phase sequence under test accordingly.

[0130] Because the limited space utilizes a closed structure, the phased array antenna under test is positioned opposite the phased array chip under test, and the propagation distance can be controlled within a preset range. Therefore, it is not necessary to use a large anechoic chamber and a mechanical turntable to complete point-by-point spatial scanning. The test machine continuously switches the phase under test electronically, allowing the test beam to sequentially illuminate the phased array chip under test in different directions, forming a rapid transmission process oriented towards production testing schedules.

[0131] S202. When the test beam signal of any phase under test arrives at the phased array chip under test, control the phased array chip under test to simultaneously receive test beam signals from multiple phases under test.

[0132] In this embodiment, test beam signals are received simultaneously from multiple phases under test. This can be understood as the accompanying phased array antenna transmitting a test beam signal of one phase angle each time. The phased array chip under test simultaneously establishes a reception response record for the arriving signals from multiple phases under test. The purpose is to comprehensively receive the test beam signal, including the main lobe and side lobes. The reception results typically include amplitude and phase, and may also include parameters such as beam index, signal-to-noise ratio, or demodulated measurement code correlation value.

[0133] In practice, before the phased array antenna under test transmits the test beam signal for each phase under test, the tester first sends a receive configuration command to the phased array chip under test, causing the chip to enter a preset receive scan mode. This receive scan mode may include synchronously enabling multiple receive channels within the chip, sequentially calling multiple internal beam weight tables, locking the local oscillator and sampling clocks, and initializing the measurement buffer.

[0134] After receiving the test beam signal from the accompanying phased array antenna within a limited space, the phased array chip under test (DUT) can perform multiple sets of receive phase configurations on the current incident wavefront based on its internal phased array receive link, thereby obtaining response values ​​under multiple test phases. For example, the DUT can quickly sample the same arriving signal under multiple receive phase states within a single transmit test time window and store the received data corresponding to each phase in a buffer.

[0135] This step is crucial for achieving high-efficiency directional testing. Traditional solutions typically rely on a mechanical turntable to change the spatial orientation one by one before measuring the single-point response. However, the embodiments in this application control the phased array chip under test to form a response set for multiple phases under test, transforming the spatial scanning problem into an electronic beam configuration problem, significantly reducing point-by-point positioning and waiting time. Based on the above analysis, this step can acquire multi-directional receiving capability, phase consistency, and directional response distribution information without increasing large-scale mechanical structures, which is beneficial for achieving high-throughput, low-repetition-error testing processes in production line environments. It should be understood that the above examples are merely illustrative and not limiting.

[0136] S203. Determine whether the phased array chip under test is qualified based on the test beam signal.

[0137] In this embodiment, after obtaining the reception results corresponding to multiple phases under test, the test machine analyzes the test beam signal and its derived parameters to output a pass / fail determination for the phased array chip under test. This determination based on the test beam signal can be achieved either by directly using threshold judgments based on the received power, phase value, and amplitude-phase consistency of each phase under test, or by reconstructing the response characteristics of the phased array chip under test based on the reception results of multiple phases under test to complete a comprehensive evaluation. The pass / fail determination can include results such as pass, fail, and require retesting, and can further generate a test report corresponding to the chip serial number.

[0138] Based on the above analysis, this application provides a phased array chip testing method. It replaces the point-by-point scanning method of large anechoic chambers and mechanical turntables by using a closed, opaque, limited space, a phased array antenna under test, and a planar array electronic scanning mechanism. This allows the test beam to complete multi-directional transmission within a limited propagation path, and enables the phased array chip under test to form multiple sets of received responses for the tested phases within the same testing process. The testing machine then automatically analyzes and determines the pass / fail status of the amplitude, phase, and directional distribution characteristics. This improves the directional scanning efficiency of millimeter-wave phased array chips, reduces the complexity of the testing site and equipment, minimizes the impact of mechanical positioning errors on test consistency, and balances testing accuracy, testing cost, and production line throughput requirements.

[0139] Based on the aforementioned embodiments, further, step S201, which controls the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phases to be tested, can be achieved through the following steps:

[0140] Step S2011: Control the accompanying phased array antenna to transmit a test beam signal in the normal direction, where the normal direction represents the direction perpendicular to the plane where the accompanying phased array antenna is located.

[0141] Step S2012: Control the accompanying phased array antenna to sequentially transmit test beam signals in the direction of illegal lines.

[0142] The normal direction refers to the reference radiation direction perpendicular to the phased array antenna array surface, which facilitates the verification of the beamforming state directly in front of the array surface. The non-normal direction refers to multiple angular radiation directions deviating from this reference direction, used to cover different incident conditions such as sideways and oblique directions. The phased array antenna under test is the planar array structure antenna in this application, and the test machine can control each array element to form beams in different directions through the phase configuration table.

[0143] In its implementation, the test machine first calls the array control interface of the accompanying phased array antenna, using the normal direction as the initial value and 0° as the normal direction. It then loads the phase weight corresponding to the normal direction, causing the test beam to be emitted to the phased array chip under test along the vertical reference direction within a limited space. Subsequently, it switches the phase weight according to a preset angle sequence, sequentially switching from 0° to other phase angles, thus forming multiple non-normal direction test beams. The angle sequence can be unfolded around the normal direction at different azimuth and elevation angles to ensure the tested phase covers more directional responses. This test machine can be implemented using an industrial control host or an embedded controller. In practical applications, other models of this component can also be selected, and this embodiment does not limit this choice.

[0144] By first transmitting a test beam in the normal direction and then transmitting a test beam in the non-normal direction, the phased array chip under test can first acquire the reference response directly in front of the array surface, and then acquire the response in directions other than directly in front, thus completing multi-directional consistency testing within a limited space. This method reduces reliance on mechanical scanning and is beneficial for improving directional coverage integrity, test repeatability, and batch testing efficiency.

[0145] In one possible implementation, before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, the method further includes:

[0146] Step S204: Obtain the phase range and step size to be measured;

[0147] Step S205: Determine multiple phases to be measured based on the range of phases to be measured and the step size;

[0148] Step S206: Configure the transmit phase of the accompanying phased array antenna as the phase to be measured;

[0149] Step S207: Configure the receiving phase of the phased array chip under test as the phase to be tested.

[0150] The range of the phase to be tested is used to define the interval of the phase scan, and the step size is used to define the discrete interval between adjacent phases to be tested. Both are preset and stored by the test machine in conjunction with the chip test task.

[0151] After obtaining the range and step size of the phase to be tested, the tester can generate multiple phases to be tested according to the phase start value, end value, and phase interval. Each phase to be tested is then sequentially written into the transmit control register of the accompanying phased array antenna and simultaneously written into the receive control register of the phased array chip under test. The transmit phase of the accompanying phased array antenna is kept consistent with the receive phase of the phased array chip under test to ensure that the test beam signal stably forms the corresponding beam direction within a limited space.

[0152] In practical applications, the test equipment can use a preset phase table to generate and transmit the phase to be tested, facilitating multi-phase testing without relying on mechanical scanning. This method enables the accompanying phased array antenna and the phased array chip under test to work together under the same phase conditions, thereby improving the consistency and repeatability of beam testing and reducing errors caused by manual settings. The aforementioned test equipment, transmit control register, and receive control register can all adopt other equivalent structures; this application does not limit these embodiments.

[0153] This implementation method, through parameterized configuration of phase range and step size, enables multiple phases to be tested to be automatically determined and synchronously loaded onto the transmitting and receiving sides, thereby forming a controllable phase test sequence. This facilitates the test equipment to collect responses under different phase conditions one by one, and also improves the efficiency, stability, and batch adaptation capability of the testing process.

[0154] Based on the aforementioned embodiments, step S203 further includes determining whether the phased array chip under test is qualified based on the test beam signal, including:

[0155] Step S2031: Obtain the preset amplitude range corresponding to each phase to be measured;

[0156] Step S2032: If the beam amplitude of the test beam signal corresponding to any phase under test is within the corresponding preset amplitude range, determine that the phased array chip under test is qualified.

[0157] Step S2033: If the beam amplitude corresponding to one or more phases under test is not included in the preset amplitude range, the phased array chip under test is determined to be unqualified.

[0158] The preset amplitude range is used to limit the allowable range of beam amplitude under each phase to be tested. It can be pre-written into the storage module by the test machine and corresponds one-to-one with the phase to be tested.

[0159] The preset amplitude range can be determined by pre-testing the phase and amplitude of multiple array chips, constructing a mapping table or diagram of standard phase and standard amplitude, and then using this mapping relationship.

[0160] Specifically, Figure 4 A standard beam pattern provided for this application, such as Figure 4 As shown, each phase beam corresponds to an amplitude value. In practical applications, the amplitude value can be extended to a small range to accommodate amplitude errors caused by uncontrollable factors during chip testing.

[0161] exist Figure 4 In the beam, the main lobe has a phase of 0° and an amplitude of 18.3dB; the first pair of side lobes has a phase of 30° and an amplitude of about 3.3dB; the second pair of side lobes has a phase of 60° and an amplitude of less than 0.3dB; it also includes the back lobe. In practical applications, the smaller the amplitude of the back lobe, the better.

[0162] Therefore, the preset amplitude range for the main lobe with a phase of 0° can be set to 18dB~18.5dB. Since the side lobes experience significant attenuation, they can be excluded from the preset amplitude range for chip qualification evaluation. Other phases can have their preset amplitude ranges set in the same way as the 0° phase.

[0163] The beam amplitude is a parameter extracted by the test machine from the amplitude value of the test beam signal received by the phased array chip under test. It is used to reflect the received strength under the corresponding phase.

[0164] The preset amplitude range can be represented as the upper and lower limits of the amplitude threshold. The testing machine makes a judgment by comparing the measured amplitude with this range.

[0165] In practical implementation, after the phased array antenna under test transmits the test beam signals for each phase to be tested, the test equipment collects the response data of the phased array chip under test to obtain the beam amplitude corresponding to each phase to be tested. For example, the amplitude of the received signal with a phase of 30° is 3.3dB.

[0166] When the beam amplitude of any phase under test falls within the preset amplitude range corresponding to that phase, the tester outputs a qualified result and records the result; when the beam amplitude of any phase under test exceeds the corresponding range, the tester outputs a failed result. The above amplitude range can be set according to product specifications, calibration data, or historical test statistics. In practical applications, this parameter can also be set in other ways, which are not limited in this embodiment.

[0167] This method matches the measured beam amplitude of multiple phases under test with corresponding preset amplitude ranges, enabling the tester to quickly determine chip conformity within a limited space and reducing reliance on manual interpretation. Since the judgment criteria directly correspond to the amplitude tolerance of each phase, it improves the consistency and traceability of test results, while also shortening production line testing cycles and reducing the probability of misjudgment.

[0168] Based on the aforementioned embodiments, step S203, which determines whether the phased array chip under test is qualified based on the test beam signal, can also be achieved through the following steps:

[0169] Step S2034: Generate a beam pattern based on the phase to be measured and the beam amplitude of the test beam signal;

[0170] Step S2035: Analyze the beam pattern using the target neural network model to determine whether the beam pattern is qualified. The target neural network model is obtained through multiple sets of historical data training sets. Each set of historical data includes: historical beam pattern and labels indicating whether the historical beam pattern is qualified.

[0171] Step S2036: If the beam pattern is qualified, determine that the phased array chip under test is qualified;

[0172] Step S2037: If the beam pattern is unqualified, determine that the phased array chip under test is unqualified.

[0173] The beam pattern is used to characterize the correspondence between the phase under test and the amplitude of the test beam signal. The test machine collects and maps the beam amplitudes emitted by the accompanying phased array antenna at each phase under test into a beam pattern. The target neural network model is called by the data processing module in the test machine. Its input layer receives the beam pattern, and its output layer provides the pass / fail judgment result. The historical data training set can be composed of historical beam pattern samples with known judgment results from the production line to improve recognition consistency. In practical applications, the model can also be in the form of a convolutional neural network or a multilayer perceptron; this application embodiment does not limit this.

[0174] Specifically, it can be Figure 4 The standard beam pattern shown is used as a historical beam pattern for training the target neural network model. The historical beam pattern can include multiple standard beam patterns. Each standard beam pattern is the beam pattern corresponding to a phase to be measured, and the validity of the beam pattern is marked for training the target neural network model.

[0175] After measuring the actual beam amplitude, the actual beam pattern is plotted based on the measured phase and the corresponding actual beam amplitude. The actual beam pattern is then input into the target neural network model for analysis to determine whether the beam pattern is qualified.

[0176] In practice, after the accompanying phased array antenna transmits test beam signals of multiple phases to be tested, the test machine obtains the beam amplitude corresponding to the phased array chip under test, and forms a two-dimensional or polar coordinate beam pattern according to the phase order. Then, the beam pattern is input into the target neural network model to complete the analysis.

[0177] If the model outputs a qualified beam pattern, the tester, considering the state of the phased array chip under test carried by the test carrier, test fixture, and gripping structure, determines that the chip is qualified; if the model output is unqualified, the chip is determined to be unqualified. The training set can be continuously supplemented with new batches of historical beam patterns and labels to improve the model's adaptability to different batches of chips.

[0178] This method uses neural networks to automatically identify radiation patterns, reducing the reliance on main lobe, side lobe, and beam pointing for manual visual comparison. This allows the test machine to make rapid judgments within a limited space and works in conjunction with the electronic phase scanning of the accompanying phased array antenna to improve the cycle time and consistency of batch testing, while reducing errors and maintenance costs caused by mechanical scanning.

[0179] In one possible implementation, after determining whether the phased array chip under test is qualified based on the test beam signal, the method further includes the following steps:

[0180] Step S208: If the phased array chip under test is determined to be qualified, control the test fixture to clamp the phased array chip under test to the qualified area.

[0181] Step S209: If it is determined that the phased array chip under test is unqualified, control the test fixture to clamp the phased array chip under test to the unqualified area.

[0182] The test fixture is connected to the test machine and is set to correspond to the mounting position on the test carrier. The qualified area and the unqualified area can be different receiving positions located outside the limited space, which are used to distinguish the phased array chips under test with different test results.

[0183] The test fixture can be an electric gripper, a vacuum suction fixture, or a positioning and clamping fixture. An anti-static pad can be provided on its clamping end face to reduce mechanical damage and electrostatic risks to the chip package surface. In practical applications, other models of this component can also be selected, but this application embodiment does not limit this.

[0184] When the testing machine outputs a pass / fail judgment based on the test beam signal, it controls the test fixture to move the phased array chip under test from the first area and transfer it to the pass area; when it outputs a fail / fail judgment, it transfers the phased array chip under test to the fail area. This control can be achieved by driving the test fixture to move, lift, or flip along a preset trajectory, so that chips corresponding to different judgment results enter different receiving positions.

[0185] With the above settings, the phased array chips under test can be automatically sorted according to the judgment results after the test is completed, without the need for manual handling. This helps to shorten the sorting time and reduce the probability of missorting or omission. It also makes it easier to separate qualified and unqualified products into subsequent assembly or rework processes, thereby improving the automation level of the production line and the consistency of testing.

[0186] Based on the aforementioned embodiments, further, controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested also includes the following steps:

[0187] Step S2013: Upon receiving the transmission signal sent by the test machine, control the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested.

[0188] The transmission signal is a control trigger signal sent by the test machine to the accompanying phased array antenna, which drives the antenna to enter the test beam transmission state.

[0189] The test beam signals for multiple phases to be tested can be 0°, 30°, 60°, etc., in sequence, and the corresponding test beam signals can be received. The beam pattern corresponding to each phase to be tested can be determined sequentially through the above steps S2031 to S2037 to determine whether it is qualified, thereby determining whether the phased array chip under test is qualified.

[0190] The test machine can be a rack-mounted control host, an industrial computer, or an embedded controller, and it is connected to the phased array antenna under test via a communication interface.

[0191] The test unit first configures the phase to be tested, and writes the phase sequence, transmission timing, and trigger conditions into the control command before sending the transmission signal. Upon receiving this signal, the accompanying phased array antenna sequentially switches the feed phase of its array elements according to preset control logic, causing each radiating element to form a beam pointing to the phase to be tested, and outputs multiple test beam signals in sequence. The transmission signal can be a radio frequency signal, which, upon reception, triggers the accompanying phased array antenna to enter the transmission state, thereby preventing unauthorized transmission and improving test synchronization.

[0192] With the above settings, the test equipment can uniformly trigger and synchronously control the transmission process of the phased array antenna under test, enabling the test beam signals of multiple phases under test to be output stably in a predetermined order. This improves the consistency of beam transmission timing, reduces test deviations caused by control delays, and helps improve the repeatability, accuracy, and batch testing efficiency of phased array chip testing.

[0193] Based on the aforementioned embodiments, the method further includes the following steps before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested:

[0194] Step S210: Perform phase correction on the accompanying phased array antenna and the phased array chip under test so that the transmission phase of the accompanying phased array antenna is the same as the reception phase of the phased array chip under test.

[0195] Step S211: Compensate for the path loss of the test beam signal in the limited space so that the test beam signal received by the phased array chip under test is the same as the test beam signal transmitted by the phased array antenna under test.

[0196] Before the formal test, the phase alignment of the accompanying phased array antenna and the phased array chip under test is calibrated.

[0197] Phase correction refers to measuring and correcting the amplitude and phase parameters of the array elements of the phased array antenna under test using a tester, and aligning them with the receiving reference phase of the phased array chip under test so that they are on the same phase reference.

[0198] The tester can communicate with the accompanying phased array antenna and the phased array chip under test, obtain the phase deviation using the calibration signal, and then write the compensation parameters to reduce the offset caused by installation errors and link phase shift.

[0199] Path loss compensation refers to adjusting the transmit power or gain of the test beam signal based on the propagation distance within a limited space, cavity reflection characteristics, and millimeter-wave band attenuation characteristics, so that the signal amplitude reaching the phased array chip under test is consistent with the transmitter of the accompanying phased array antenna.

[0200] In practical applications, the test unit can first complete phase correction and then perform path loss compensation, or it can complete the process in conjunction with a control strategy. Both processes serve the stable transmission of subsequent multi-phase test beam signals. Through the above processing, the signal received by the phased array chip under test is closer to the original transmission state of the accompanying phased array antenna, which helps to improve the accuracy and repeatability of beam direction response determination and reduce the impact of propagation differences in confined space on the test results.

[0201] Based on the aforementioned embodiments, further phase correction is performed on the accompanying phased array antenna and the phased array chip under test, including:

[0202] Step S2101: Control the accompanying phased array antenna to transmit the test beam signal of the target phase;

[0203] Step S2102: Control the phased array chip under test to receive the test beam signal from the target phase to obtain the received phase;

[0204] Step S2103: Calculate the difference between the target phase and the received phase;

[0205] Step S2104: Perform phase correction on the phased array antenna under test and the phased array chip under test according to the difference to minimize the difference.

[0206] The target phase is the reference phase preset by the test machine and written into the transmission control parameters of the phased array antenna under test. The received phase is the phase parameter measured by the test machine after the phased array chip under test receives the test beam in a limited space. The difference is the phase deviation between the two.

[0207] Because the phased array chip under test has multiple receiving channels, each corresponding to an antenna element, variations in chip manufacturing processes can lead to different actual receiving phases for each channel, even if all channels are set to the same receiving phase. This phase inconsistency disrupts coherent superposition during beamforming, resulting in beam pointing deviation, increased sidelobes, and decreased gain. Therefore, by measuring the phase deviation of each receiving channel relative to a reference channel and calculating a compensation value for each channel, the receiving phases of all channels under the same control phase can be made consistent.

[0208] In practical applications, the tester first sends the target phase configuration, such as 0°, to the phased array antenna under test, so that it forms a corresponding beam by the planar array unit. Then, the phased array chip under test receives the beam in the first area and outputs the phase feedback data. For example, if the received phase is 0.1°, it indicates that there is a deviation of 0.1°.

[0209] The test equipment subtracts the target phase from the received phase to generate a phase compensation value. Based on this, it synchronously adjusts the transmit phase of the accompanying phased array antenna and the receive phase of the phased array chip under test until the difference meets a preset threshold. This phase alignment process reduces the impact of propagation errors and initial device deviations within a limited space on the test results.

[0210] Specifically, the target phase is uniformly set to 0°, and the accompanying phased array antenna is controlled to transmit a 0° modulated test signal. The accompanying phased array antenna is usually in a calibrated state, and the phase distribution of each element is known and stable.

[0211] The signal is received by the receiving channel of the phased array chip under test. The phased array chip under test usually has multiple receiving channels. The phase shifter controlling all receiving channels of the phased array chip under test is set to 0°, that is, the test beam signal is received from the target phase of 0°. Then the actual receiving phase of each channel is measured. For example, the phased array chip under test includes channel 1, channel 2, channel 3 and channel 4. The actual phase measured by channel 1 is 0°, channel 2 is +3.2°, channel 3 is +4.7° and channel 4 is +5.1°.

[0212] The differences between the target phase and the received phase are 0°, -3.2°, 4.7° and -2.1°, respectively. Therefore, channel 1 does not need to be corrected, channel 2 needs to be compensated by 3.2°, channel 3 needs to be compensated by 4.7° and channel 4 needs to be compensated by 5.1°.

[0213] Specifically, the aforementioned phase deviation can be compensated by setting the compensation code of the phase shift register. The phase shift register can be 6-bit or 8-bit, etc. Taking a higher-precision 8-bit register as an example, the step value of the phase shift register is 360° / 2. N =360° / 256=1.40625. For example, for channel 2, calculate the compensation code: k=3.2° / 1.40625°≈2. Therefore, set the compensation code of the phase shift register to 2.

[0214] After compensation, the phase difference can be measured again to confirm whether the phase deviation has decreased.

[0215] This scheme uses the target phase as a unified reference to establish the correspondence between transmission and reception, and drives dual-end collaborative correction through differential feedback to enable the accompanying phased array antenna and the phased array chip under test to form a stable phase synchronization state. This improves the uniformity of test beam incidence, enhances the reliability of subsequent amplitude and direction determination, and reduces measurement fluctuations caused by repeated clamping and environmental disturbances, thereby improving test accuracy and batch test stability.

[0216] Based on the aforementioned embodiments, the phased array chip under test is further defined as a multi-mode chip, controlling the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phases under test, including:

[0217] Step S2014: Determine multiple test frequencies of the phased array chip under test. Each test frequency corresponds to a communication mode of the phased array chip under test.

[0218] Step S2015: For any frequency to be tested, control the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phases to be tested according to the frequency to be tested.

[0219] Among them, multi-mode chip refers to phased array chip under test that can work in multiple communication modes, and each communication mode corresponds to a pre-set test frequency; the frequency under test represents the transmission frequency of different communication modes.

[0220] The communication mode refers to the operating mode of the phased array chip under test in the corresponding frequency band. The tester can pre-establish the correspondence between "communication mode and frequency under test" by combining the standard information of the chip under test, product specifications, or production line configuration parameters, so as to perform beam verification at different frequency points during testing.

[0221] In practical implementation, the test machine first calls the mode configuration parameters of the phased array chip under test (DUT) to determine the multiple communication modes it supports and assigns corresponding test frequencies to each communication mode. Then, when testing any test frequency, the test machine controls the accompanying phased array antenna to switch to the operating state at that frequency and sequentially configures multiple test phases, enabling the accompanying phased array antenna to transmit the corresponding test beam signal at that frequency within a limited space. In this way, the DUT can receive multi-phase beam signals at corresponding frequencies under different communication modes and output corresponding response data for the test machine to judge.

[0222] By adopting the above method, multi-frequency and multi-communication mode testing of multi-mode chips can be completed without changing the limited space test architecture, improving frequency domain coverage and test adaptability, reducing repeated clamping and system reconstruction caused by frequency switching, and improving batch testing efficiency and result consistency.

[0223] Based on the foregoing embodiments, further determining whether the phased array chip under test is qualified based on the test beam signal includes:

[0224] Step S2038: If the test beam signals of multiple frequencies under test are all qualified, determine that the phased array chip under test is qualified;

[0225] Step S2039: If the test beam signal at any of the frequencies to be tested is unqualified, determine that the phased array chip under test is unqualified.

[0226] In this embodiment, the frequency under test refers to the frequency point parameter used to distinguish the test results of the multimode chip under different communication modes, and it corresponds one-to-one with each operating mode of the phased array chip under test. The test beam signal is the radio frequency excitation signal emitted by the accompanying phased array antenna controlled by the test machine. The test machine obtains the corresponding beam response based on each frequency under test and uses the response results for qualification judgment.

[0227] Since multiple frequencies under test correspond to different operating states, the test results adopt a "pass only if all requirements are met, fail if any requirement is not met" judgment rule, which can avoid the situation where a single frequency point passes but the overall performance is insufficient. In this way, the tester can evaluate the consistency of the multi-band adaptability of the phased array chip under test, thereby improving the accuracy and reliability of factory screening and reducing the risk of rework caused by inconsistent frequency point performance after subsequent assembly.

[0228] In one possible implementation, before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested according to the frequency to be tested, the method further includes:

[0229] Step S212: Perform Fourier transform on the preset beam signals corresponding to multiple frequencies to be measured to obtain the frequency domain signals corresponding to the preset beam signals;

[0230] Step S213: Calculate the channel frequency response corresponding to any frequency to be measured in the frequency domain signal. The channel frequency response represents the change in the signal corresponding to the frequency to be measured after passing through the transmission channel.

[0231] Step S214: Calculate the reciprocal of the frequency domain signal and the channel frequency response to obtain the compensation signal;

[0232] Step S215: Perform an inverse Fourier transform on the compensation signal to obtain the frequency-domain compensated test beam signal, so as to compensate for the path loss difference of test beam signals at different frequencies.

[0233] Among them, the preset beam signal is a set of beam signals pre-set for multiple frequencies to be measured.

[0234] The frequency domain signal is the frequency domain representation of the preset beam signal after Fourier transform.

[0235] Channel frequency response is used to characterize the attenuation and phase change of a test beam signal after it passes through a transmission channel in a finite space.

[0236] The compensation signal is used to cancel out the change, and the inverse Fourier transform is used to restore the compensated frequency domain result to a transmittable test beam signal.

[0237] In practical applications, in order to compensate for the loss caused by the differences between different frequencies, the test machine first calls the control module that is connected to the phased array antenna under test, reads the preset beam signal corresponding to each frequency under test, and establishes a channel frequency response model based on the propagation characteristics from the second region to the first region in a limited space. Then, it performs amplitude and phase compensation on the frequency domain signal to keep the beam strength reaching the phased array chip under test consistent at different frequencies.

[0238] The channel frequency response can be obtained from historical test data, pre-calibrated data, or fitting results of measured channel characteristics within a limited space. In practical applications, other models of this component can also be selected, but this application embodiment does not limit this.

[0239] This method performs frequency domain compensation before controlling the phased array antenna under test to transmit, so that the test beam signal emitted by the phased array antenna under test in the second region can reach the phased array chip under test in the first region with an amplitude and phase closer to the expected after transmission through a limited space, thereby reducing the impact of path loss differences between different frequencies on the test results.

[0240] This approach improves the consistency of multi-frequency testing, reduces the interference of millimeter wave propagation loss on pass / fail determination, and reduces test deviations caused by frequency differences, thereby improving test accuracy and batch test stability.

[0241] This application uses a planar antenna array instead of a horn antenna, significantly reducing the antenna size and thus alleviating the limitations of far-field testing distance. This reduction in size within a limited space leads to a simultaneous decrease in electromagnetic wave signal loss path, with path loss reduced to below 50dB. This lowers the requirements for transmit power and receive noise floor at the test equipment end, eliminating the need for external pre-amplification equipment to meet testing requirements. This reduces the complexity of the testing system, lowers costs, and improves maintainability. Furthermore, by using an amplitude and phase control chip cascaded with an antenna array, beamforming can achieve angular coverage from -60° to +60°, replacing the mechanical turntable in traditional solutions. This transforms mechanical movement in antenna testing into electromagnetic wave shaping, greatly improving testing efficiency.

[0242] This application also provides a phased array chip testing system, including:

[0243] The phased array chip under test;

[0244] The phased array chip testing device provided above is used to test the phased array chip under test.

[0245] In this testing system, the phased array chip under test (PDT) is the object of test, and it is tested by the phased array chip testing device. Because the testing device can transmit multiple test beam signals of the phased array chip under test to the PDT in a closed space and obtain the corresponding receiving response of the PDT chip, directional correlation testing can be achieved without relying on a large anechoic chamber and mechanical turntable.

[0246] This results in a smaller overall system footprint, shorter test links, and easier control of millimeter-wave propagation loss, thereby improving test cycle time and adaptability to batch testing. Therefore, this testing system can reduce equipment complexity and construction costs while maintaining test accuracy, and it also helps improve the consistency of test results across different batches of phased array chips.

[0247] The phased array chip testing system provided in this embodiment can execute the methods provided in the above-described method embodiments. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0248] Figure 5 This is a schematic diagram of the testing machine provided in this application. Figure 5 As shown, the test machine 22 provided in this embodiment includes at least one processor 401 and a memory 402. Optionally, the test machine 22 also includes a communication component 403. The processor 401, memory 402, and communication component 403 are connected via a bus 404.

[0249] In a specific implementation, at least one processor 401 executes computer execution instructions stored in memory 402, causing at least one processor 401 to perform the above-described method.

[0250] The specific implementation process of processor 401 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0251] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0252] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0253] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0254] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0255] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0256] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0257] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0258] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0259] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0260] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0261] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0262] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0263] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A phased array chip testing device, characterized in that, include: The system includes a closed, opaque, limited space, a phased array antenna under test, and a testing machine, wherein the testing machine is communicatively connected to both the phased array antenna under test and the phased array chip under test. The enclosed, opaque, limited space includes a first region and a second region. The first region is used to place the phased array chip under test, and the second region is used to place the accompanying phased array antenna. The accompanying phased array antenna and the phased array chip under test are arranged opposite to each other inside the limited space. The accompanying phased array antenna includes an antenna with a planar array structure. The test machine is used to control the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, so that after any one of the transmitted test beam signals reaches the phased array chip under test through the limited space, the phased array chip under test simultaneously receives the test beam signals from multiple phases to be tested. The test beam signals are used to determine whether the phased array chip under test is qualified.

2. The apparatus according to claim 1, characterized in that, Also includes: The test carrier, test fixture, and gripping structure are provided, wherein the test carrier and the gripping structure are respectively communicatively connected to the test machine. The test fixture, located on the test carrier, is used to clamp the phased array chip under test in response to receiving a test command sent by the test machine, and place the phased array chip under test in the first region of the limited space; The test carrier plate is located outside the first region of the confined space; The gripping structure is located on the side of the test carrier away from the limited space, and is used to grip the phased array chip under test in response to the gripping command sent by the test machine, and place the phased array chip under test on the test fixture of the test carrier.

3. The apparatus according to claim 1, characterized in that, The first region is located in the region of the limited space near the first boundary, and the second region is located in the region of the limited space near the second boundary, with the first boundary and the second boundary being set opposite to each other.

4. A method for testing phased array chips, characterized in that, The phased array chip testing method, applied to the phased array chip testing apparatus according to any one of claims 1 to 3, comprises: The accompanying phased array antenna is controlled to sequentially transmit multiple test beam signals of the phase to be tested, so that any one of the transmitted test beam signals can reach the phased array chip under test through a closed, opaque, and limited space. When the test beam signal of any one of the phases under test arrives at the phased array chip under test, the phased array chip under test is controlled to simultaneously receive the test beam signals from multiple phases under test. The test beam signal is used to determine whether the phased array chip under test is qualified.

5. The method according to claim 4, characterized in that, The accompanying phased array antenna is controlled to sequentially transmit test beam signals for multiple phases to be tested, including: The test beam signal is controlled to transmit in the normal direction of the accompanying phased array antenna, where the normal direction represents the direction perpendicular to the plane where the accompanying phased array antenna is located; The accompanying phased array antenna is controlled to sequentially transmit the test beam signal in the direction of the illegal line.

6. The method according to claim 4, characterized in that, Before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, the method further includes: Obtain the phase range and step size to be measured; Multiple phases to be measured are determined based on the range of phases to be measured and the step size; Configure the transmission phase of the accompanying phased array antenna as the phase to be measured; Configure the receiving phase of the phased array chip under test as the phase under test.

7. The method according to claim 4, characterized in that, Determining whether the phased array chip under test is qualified based on the test beam signal includes: Obtain the preset amplitude range corresponding to each of the phases to be measured; If the beam amplitude of the test beam signal corresponding to any one of the phases under test is within the corresponding preset amplitude range, the phased array chip under test is determined to be qualified. If the beam amplitude corresponding to one or more of the phases under test is not included in the preset amplitude range, the phased array chip under test is determined to be unqualified.

8. The method according to claim 4, characterized in that, Determining whether the phased array chip under test is qualified based on the test beam signal also includes: A beam pattern is generated based on the phase to be measured and the beam amplitude of the test beam signal; The beam pattern is analyzed by a target neural network model to determine whether the beam pattern is qualified. The target neural network model is obtained by training multiple sets of historical data. Each set of historical data includes: historical beam patterns and labels indicating whether the historical beam patterns are qualified. If the beam pattern is qualified, the phased array chip under test is determined to be qualified. If the beam pattern is unqualified, the phased array chip under test is determined to be unqualified.

9. The method according to claim 4, characterized in that, After determining whether the phased array chip under test is qualified based on the test beam signal, the method further includes: If the phased array chip under test is determined to be qualified, the test fixture is controlled to clamp the phased array chip under test into the qualified area; If the phased array chip under test is determined to be defective, the test fixture is controlled to clamp the phased array chip under test to the defective area.

10. The method according to claim 4, characterized in that, Controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested also includes: Upon receiving the transmission signal sent by the test machine, the accompanying phased array antenna is controlled to sequentially transmit test beam signals of multiple phases to be tested.

11. The method according to claim 4, characterized in that, Before controlling the accompanying phased array antenna to sequentially transmit test beam signals of multiple phases to be tested, the method further includes: Phase correction is performed on the accompanying phased array antenna and the phased array chip under test so that the transmission phase of the accompanying phased array antenna is the same as the reception phase of the phased array chip under test. The path loss of the test beam signal transmitted within the limited space is compensated so that the test beam signal received by the phased array chip under test is the same as the test beam signal transmitted by the accompanying phased array antenna.

12. The method according to claim 11, characterized in that, Phase correction is performed on the accompanying phased array antenna and the phased array chip under test, including: The test beam signal that controls the phase of the target is transmitted by the accompanying phased array antenna; The phased array chip under test is controlled to receive the test beam signal from the target phase to obtain the received phase; Calculate the difference between the target phase and the received phase; Phase correction is performed on the accompanying phased array antenna and the phased array chip under test based on the difference, so that the difference is minimized.

13. The method according to claim 4, characterized in that, The phased array chip under test is a multi-mode chip, which controls the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phases under test, including: Multiple test frequencies of the phased array chip under test are determined, and any one of the test frequencies corresponds to a communication mode of the phased array chip under test. For any given frequency to be tested, the accompanying phased array antenna is controlled to sequentially transmit multiple test beam signals of the phases to be tested according to the frequency to be tested.

14. The method according to claim 13, characterized in that, The step of determining whether the phased array chip under test is qualified based on the test beam signal includes: If the test beam signals of multiple frequencies under test are all qualified, the phased array chip under test is determined to be qualified. If the test beam signal at any of the tested frequencies fails, the phased array chip under test is determined to be defective.

15. The method according to claim 13, characterized in that, Before controlling the accompanying phased array antenna to sequentially transmit multiple test beam signals of the phase to be tested according to the frequency to be tested, the method further includes: Perform Fourier transform on the preset beam signals corresponding to the multiple frequencies to be measured to obtain the frequency domain signals corresponding to the preset beam signals; Calculate the channel frequency response corresponding to any one of the measured frequencies in the frequency domain signal, where the channel frequency response represents the amount of change in the signal corresponding to the measured frequency after passing through the transmission channel; The compensation signal is obtained by calculating the reciprocal of the frequency domain signal and the channel frequency response. The inverse Fourier transform of the compensation signal is performed to obtain the frequency-domain compensated test beam signal, so as to compensate for the path loss difference of the test beam signal at different frequencies.

16. A phased array chip testing system, characterized in that, include: The phased array chip under test; The phased array chip testing apparatus according to any one of claims 1 to 3 is used to test the phased array chip under test.

17. A testing machine, characterized in that, include: Memory, processor; Memory, used to store the processor-executable instructions; The processor executes the method according to any one of claims 4 to 15.

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