A multi-channel acquisition synchronization system and method for phased array digital array antennas

Abstract

The application discloses a kind of multi-channel acquisition synchronization systems and methods for phased array digital array antenna, it is related to phased array antenna digital acquisition processing technical field.The system includes multiple independent parallel working standardized antenna modules, each standardized antenna module includes analog receiving module and digital acquisition module.Digital acquisition module is equipped with clock management module, ADC sampling module based on LVDS interface, FPGA module and optical communication transceiver module.Clock management module receives external reference clock and generates multiple LVPECL clocks, respectively for each ADC chip and FPGA use;The clock trace of each ADC chip and the LVDS data line interconnected with FPGA are all designed with equal length PCB, which ensures consistent transmission delay between channels from hardware.FPGA module generates SYNC trigger signal through optical fiber analysis system synchronization signal, uses the signal to clear zero digital mixing NCO phase, controls the reset of FIR filter module, and triggers the frame header of data upload, further ensures consistent data processing delay of each channel from signal processing level.The application can realize multi-channel acquisition synchronization without boot calibration, significantly improves the rapid response capability of radar and system phase performance.

Description

Technical Field

[0001] This invention relates to the field of digital acquisition and processing technology for phased array antennas, specifically to a multi-channel acquisition synchronization system and method for phased array digital array antennas. Background Technology

[0002] In phased array antennas, the digital acquisition circuit, acting as a bridge for analog-to-digital signal conversion, plays a crucial role in the system. It primarily performs functions such as digital sampling, digital mixing, digital filtering, and data transmission of the antenna echo signal. Key performance indicators of the data acquisition circuit, such as instantaneous bandwidth, signal-to-noise ratio, spurious-free dynamic range, in-band ripple, and phase nonlinearity, affect the radar pulse compression performance, thus limiting the effectiveness of radar target detection. Furthermore, the time delay uncertainty between multiple digital acquisition channels affects the accuracy of radar measurements. Especially in phased array digital arrays, the time delay uncertainty between multiple digital acquisition channels limits the radar's coherent performance, severely impacting radar detection effectiveness.

[0003] Currently, traditional phased array antennas typically employ a self-calibration method upon startup to compensate for channel transmission delays, thereby resolving the issue of inconsistent transmission delays between channels. However, relying on self-calibration every time the radar is powered on requires a calibration process before it can function properly. Calibration times range from hundreds of milliseconds to several seconds, severely limiting the radar's core capabilities for rapid startup, rapid response, rapid relocation, and emergency deployment. Phased array radar antennas are now evolving towards digital and multi-channel technologies, thus necessitating a solution to the problem of consistent digital acquisition delays across multiple channels. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a multi-channel acquisition synchronization system and method for phased array digital array antennas, which solves the technical problem of consistency of multi-channel digital acquisition delay.

[0005] To address this, the present invention proposes a multi-channel acquisition and synchronization system for phased array digital array antennas, applicable to phased array antennas comprising multiple independently operating standardized antenna modules. Each standardized antenna module includes an analog receiving module and a digital acquisition module. The digital acquisition module includes a clock management module, an ADC sampling module based on an LVDS interface, an FPGA module, and an optical communication transceiver module. The clock management module is used to receive an external reference clock (REFCLK) and generate multiple LVPECL level clock signals, which are respectively used as the working clock of each ADC chip in the ADC sampling module, the system clock (SYSCLK) of the FPGA module, and the MGT reference clock (MGTREFCLK). The clock traces of each ADC chip in the ADC sampling module, as well as the LVDS differential data lines interconnecting each ADC chip with the FPGA module, all adopt an equal-length PCB design. The FPGA module is used to receive and parse the radar system synchronization signal through the fiber optic interface and generate the synchronization trigger signal SYNC. The FPGA module includes a digital mixer module, a digital filter module, and a data upload module. The NCO phase of the digital mixer module is cleared to zero by the SYNC signal. The reset of the digital filter module is associated with the SYNC signal. The frame header start time of the data upload module is controlled by the SYNC signal.

[0006] Preferably, the FPGA module internally generates a serial data clock (4fs) for serial-to-parallel conversion and a parallel data clock (fs) for parallel data processing based on the SYSCLK through the MMCM clock management unit; the phase relationships between the SYSCLK, the fs, and the 4fs, as well as between the three and the REFCLK, are deterministic.

[0007] Preferably, the ADC sampling module includes multiple ADC acquisition chips based on the LVDS interface, and the clock management module uses a low-jitter clock driver chip to provide a sampling clock for each ADC chip.

[0008] Preferably, the standardized antenna module's external interfaces include only a power interface, a reference clock interface, and an optical fiber interface. The optical fiber interface is used to achieve integrated transmission of acquired data and radar system synchronization signals.

[0009] Preferably, the FPGA module further includes an ADC data parsing and processing module, which includes a serial-to-parallel conversion module and a data arrangement module; The serial-to-parallel conversion module uses the ISERDES primitive language in the FPGA to convert the serial data sampled by the ADC into 12-bit parallel data and a 1-bit frame synchronization signal FRAME. The data arrangement module arranges the data according to the frame synchronization signal FRAME and outputs the aligned parallel ADC sampling data.

[0010] Preferably, the digital filtering module uses an FIR IP core to implement decimation anti-aliasing filtering. The reset signal of the FIR IP core is associated with the SYNC synchronization signal to ensure that the initial conditions of each frame of data are consistent, achieve complete isolation between frames, and meet the requirements of coherent processing.

[0011] Preferably, the data upload module sends the digitally filtered IQ data to the server according to the agreed protocol format, and the start time of the protocol frame header is controlled by the SYNC synchronization signal to ensure that the start delay and group delay of each frame of data are completely consistent, thereby achieving distance unit alignment.

[0012] This invention also proposes a multi-channel acquisition synchronization method for phased array digital array antennas, applied to a phased array antenna comprising multiple independently operating standardized antenna modules, each of which is equipped with a digital acquisition module. The method includes the following steps: S1. Clock Allocation Steps: Receive the external reference clock (REFCLK) through the clock management module, generate multiple LVPECL level clock signals, which are used as the working clock of each ADC chip in the ADC sampling module, the FPGA system clock (SYSCLK), and the MGT reference clock (MGTREFCLK), respectively. Perform equal-length PCB design for the clock traces of each ADC chip and the LVDS differential data lines interconnecting the ADC chip and the FPGA. S2. Synchronization signal parsing steps: The FPGA module receives and parses the radar system synchronization signal through the fiber optic interface, and generates the synchronization trigger signal SYNC. S3. Data acquisition and processing steps: The ADC sampling module acquires multi-channel analog signals based on the working clock and converts them into digital signals. The FPGA module internally performs serial-to-parallel conversion and data alignment on the digital signals. S4. Synchronization Processing Steps: The SYNC signal is used to clear the NCO phase of the digital mixer module inside the FPGA, the digital filter module is reset and controlled, and the frame header start time of the data upload module is synchronously triggered to ensure that the data processing delay of each channel is consistent.

[0013] Preferably, in step S3, the FPGA module internally generates a serial data clock (4fs) for serial-to-parallel conversion and a parallel data clock (fs) for parallel data processing based on the SYSCLK through the MMCM clock management unit, and the phase relationship between the SYSCLK, the fs and the 4fs, as well as the phase relationship between the three and the REFCLK, are all deterministic.

[0014] Preferably, in step S4, the digital filtering module uses an FIR IP core to implement decimation anti-aliasing filtering, and its reset signal is associated with the SYNC synchronization signal to ensure that the initial conditions of each frame of data are consistent and to achieve complete isolation between frames.

[0015] Compared with the prior art, the multi-channel acquisition synchronization system and method for phased array digital array antennas provided by the present invention have the following advantages: 1) This invention distributes the external reference clock REFCLK into multiple clocks through a clock management module, enabling equal-length sampling clock traces for multiple ADC sampling chips, equal-length LVDS differential data lines between the ADC sampling chips and the FPGA module, and determining the phase relationship between the data processing clocks (SYSCLK, fs, 4fs) generated by the MMCM inside the FPGA and the external reference clock REFCLK. This fundamentally eliminates the transmission delay uncertainty caused by physical link differences between multiple channels at the hardware level, ensuring the time delay consistency of the multi-channel data acquisition circuit and significantly improving the coherent performance of the digital array antenna.

[0016] 2) This invention uses an FPGA module to analyze the system synchronization signal transmitted through the optical fiber and generate a synchronization trigger signal SYNC. This SYNC signal is used simultaneously for the phase clearing of the digital mixer module NCO, the reset of the digital filter module FIR IP core, and the frame header start time control of the data upload module. This ensures that the initial conditions of each frame of data are completely consistent and that there is strict isolation between frames, which meets the requirements of radar coherent processing and effectively improves the radar's ability to detect weak targets and the accuracy of interferometric angle / range measurement.

[0017] 3) This invention abandons the traditional technical approach of requiring software calibration for each power-on of a phased array antenna. Through deterministic hardware design and fiber optic synchronization signal transmission mechanism, the radar can enter normal working state without calibration after power-on, eliminating the time-consuming calibration process (ranging from hundreds of milliseconds to several seconds). This greatly improves the rapid response capability and core combat effectiveness of the phased array radar in emergency deployment and rapid relocation scenarios.

[0018] 4) The standardized antenna module of this invention has only a power interface, a reference clock interface, and an optical fiber interface. The optical fiber interface enables the integrated transmission of large-capacity sampling data and radar system timing control signals, which greatly reduces the complex radio frequency cables and synchronization control cables in traditional array antennas, simplifies the system interconnection architecture, reduces the overall weight and transmission loss, and supports plug-and-play stacking expansion of standardized modules, effectively reducing the complexity of large phased array surface design.

[0019] 5) This invention integrates multi-channel delay consistency into the hardware design (PCB equal-length traces) and basic logic (FPGA clock management and SYNC synchronization mechanism) of a single standardized antenna module, enabling each standardized antenna module to independently complete amplitude and phase consistency calibration before leaving the factory. After the whole system is integrated, no additional full-array channel compensation debugging is required, which greatly simplifies the integration and testing process of phased array antennas, significantly shortens the system integration and testing cycle, and improves the mass production and delivery efficiency of products.

[0020] In addition to the purposes, features, and advantages described above, this application has other purposes, features, and advantages. A further detailed description of this application will be provided below with reference to the figures. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the standardized antenna module of the present invention; Figure 2 This is a schematic diagram of the structure of the digital acquisition module of the present invention; Figure 3 This is a schematic diagram of the clock distribution network and ADC data acquisition link of the present invention; Figure 4 This is a schematic diagram of the circuit structure for the clock network, data processing, and SNYC synchronization within the FPGA module of this invention. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] like Figures 1-4 As shown, the phased array antenna system of this application includes multiple standardized antenna modules that operate independently in parallel. Each standardized antenna module adopts a unified design and only retains three external interfaces: power supply, reference clock, and optical fiber, which facilitates system expansion and rapid integration.

[0024] like Figure 1 As shown, the standardized antenna module includes an array antenna, two TR components (TR component one and TR component two), a receiving module, and a digital acquisition module. The two TR components, the receiving module, and the digital acquisition module are positioned on the radiating surface of the array antenna. The standardized antenna module has only three external interfaces: a power interface, a reference clock interface, and a fiber optic interface. The radar echo signal enters the receiving module via the TR components and is then sent to the digital acquisition module for processing.

[0025] It should be noted here that, although Figure 1 This description uses two TR components as an example. Those skilled in the art can set the specific number of TR components according to actual needs.

[0026] like Figure 2As shown, the digital receiver module includes a power management module, a clock management module, an ADC sampling module, an FPGA module, and a photoelectric / electro-optical conversion module. After the radar echo signal enters the digital acquisition module, it is converted into a digital signal by the ADC sampling module. The digital signal is further processed within the FPGA module and then output by the electro-optical conversion module. The circuit management module is responsible for converting the external power supply into the voltages required by the various chips inside the digital receiver. The clock management module is responsible for converting the external reference clock into the various clocks required by the digital receiver.

[0027] It should be understood that the specific modules of the ADC sampling module, the power management module, the clock management module, and the photoelectric / electro-optical conversion module can all be set according to actual needs, and the embodiments of this application are not limited thereto.

[0028] For example, the ADC sampling module uses an LVDS-based ADC acquisition chip (such as the LTM9011). Meanwhile, the clock management module matching the ADC uses a high-performance, low-jitter clock driver chip (such as the HMC987), which provides a high-performance, multi-channel LVPECL level standard clock buffer; used to distribute the external reference clock REFCLK as multiple LVPECL clock outputs. The component selection and circuit design of the digital acquisition module meet the hardware requirements for multi-channel synchronous acquisition.

[0029] like Figure 3 As shown, the external reference clock REFCLK outputs seven clock channels via the clock management module: five of these serve as the operating clocks for the five LTM9011 chips in the ADC sampling module, i.e., the sampling clocks. One channel serves as the FPGA system clock SYSCLK, and another serves as the reference clock MGTREFCLK for the FPGA's high-speed MGT interface. During PCB routing, the five clock channels of the ADC sampling module are designed with equal lengths, and the LVDS differential data lines interconnecting the five LTM9011 chips within the ADC sampling module with the FPGA are also designed with equal lengths.

[0030] It should be understood that the specific modules of all modules within this digital acquisition module can be configured according to actual needs, and the embodiments of this application are not limited thereto.

[0031] For example, the clock management module can be the clock distribution chip ADCLK946; another example is that the ADC chip can be the LTM9011 or GK9011 based on the LVDS interface.

[0032] like Figure 4As shown, the FPGA module is the core of the entire synchronization mechanism. The external reference clock REFCLK is output as a SYSCLK by the clock management module as the FPGA system clock. This clock enters the FPGA and is used by the MMCM to generate a fs clock and a 4fs clock. The phase relationship between the three clocks, SYSCLK, fs, and 4fs, is fixed. Among them, 4fs is used as the serial data processing clock of the serial-to-parallel conversion module, and fs is used as the parallel data processing clock after serial-to-parallel conversion, including the parallel data processing clocks of the data arrangement module, digital mixing module, digital filtering module, and data uploading module.

[0033] The parallel data output from the serial-to-parallel conversion module undergoes data alignment processing in the data arrangement module. Through PCB length equalization design of critical paths such as clock and data, the aligned multi-channel data output from the data arrangement module already possesses the necessary hardware conditions for time delay consistency, laying the foundation for subsequent data preprocessing (digital mixing, digital filtering, and data uploading) and achieving the goal of multi-channel acquisition synchronization design.

[0034] The FPGA module analyzes the system synchronization data transmitted through the optical fiber and generates an internal SYNC synchronization signal. This SYNC signal serves as the NCO phase reset for the digital mixer module, the FIR IP reset for the digital filter module, and the frame header start trigger for the data upload module, ensuring the synchronization of multi-channel data processing within the FPGA.

[0035] Therefore, by planning the clock network, designing the critical path of the PCB, and applying the SYNC signal generated by the FPGA internal parsing system to synchronize data, the time delay consistency of the multi-channel data acquisition circuit can be achieved.

[0036] Therefore, by means of the above technical solution, this application has the following technical effects: The system architecture is simple: the standardized antenna array realizes the integrated transmission of large-capacity data and radar timing signals through optical fiber, which simplifies the system interface and interconnection cables; High system coherence: The multi-channel acquisition has consistent delay and phase at each power-on, which guarantees the coherence of the circuit from the hardware. Compared with the software correction method, the coherence and delay consistency are better, which can improve the interferometric measurement performance of phased array radar. High system testing efficiency: The hardware design ensures the synchronization of multi-channel acquisition circuits, which greatly simplifies the testing time of phased array antenna integration. There is no need to integrate all standard antenna modules and then perform software calibration. After the amplitude and phase calibration is completed at the standardized antenna module level, the full array antenna system can be tested.

[0037] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-channel acquisition and synchronization system for a phased array digital array antenna, applied to a phased array antenna comprising multiple independently operating standardized antenna modules, each of the standardized antenna modules comprising an analog receiving module and a digital acquisition module, characterized in that: The digital acquisition module includes a clock management module, an ADC sampling module based on an LVDS interface, an FPGA module, and an optical communication transceiver module. The clock management module is used to receive an external reference clock (REFCLK) and generate multiple LVPECL level clock signals, which are respectively used as the working clock of each ADC chip in the ADC sampling module, the system clock (SYSCLK) of the FPGA module, and the MGT reference clock (MGTREFCLK). The clock traces of each ADC chip in the ADC sampling module, as well as the LVDS differential data lines interconnecting each ADC chip with the FPGA module, all adopt an equal-length PCB design. The FPGA module is used to receive and parse the radar system synchronization signal through the fiber optic interface and generate the synchronization trigger signal SYNC. The FPGA module includes a digital mixer module, a digital filter module, and a data upload module. The NCO phase of the digital mixer module is cleared to zero by the SYNC signal. The reset of the digital filter module is associated with the SYNC signal. The frame header start time of the data upload module is controlled by the SYNC signal.

2. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The FPGA module internally generates a serial data clock (4fs) for serial-to-parallel conversion and a parallel data clock (fs) for parallel data processing based on the SYSCLK through the MMCM clock management unit; the phase relationship between the SYSCLK, the fs and the 4fs, as well as the phase relationship between the three and the REFCLK, are all deterministic.

3. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The ADC sampling module includes multiple ADC acquisition chips based on the LVDS interface, and the clock management module uses a low-jitter clock driver chip to provide sampling clock for each ADC chip.

4. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The standardized antenna module's external interfaces include only a power interface, a reference clock interface, and an optical fiber interface. The optical fiber interface is used to achieve integrated transmission of acquired data and radar system synchronization signals.

5. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The FPGA module also includes an ADC data parsing and processing module, which includes a serial-to-parallel conversion module and a data arrangement module. The serial-to-parallel conversion module uses the ISERDES primitive language in the FPGA to convert the serial data sampled by the ADC into 12-bit parallel data and a 1-bit frame synchronization signal FRAME. The data arrangement module arranges the data according to the frame synchronization signal FRAME and outputs the aligned parallel ADC sampling data.

6. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The digital filtering module uses an FIR IP core to implement decimation anti-aliasing filtering. The reset signal of the FIR IP core is associated with the SYNC synchronization signal to ensure that the initial conditions of each frame of data are consistent, achieve complete inter-frame isolation, and meet the requirements of coherent processing.

7. The multi-channel acquisition and synchronization system for phased array digital array antennas according to claim 1, characterized in that, The data upload module sends the digitally filtered IQ data to the server according to the agreed protocol format, and the start time of the protocol frame header is controlled by the SYNC synchronization signal to ensure that the start delay and group delay of each frame of data are completely consistent, thereby achieving distance unit alignment.

8. A multi-channel acquisition synchronization method for a phased array digital array antenna, applied to a phased array antenna comprising multiple independently operating standardized antenna modules, each of which is equipped with a digital acquisition module, characterized in that... The method includes the following steps: S1. Clock Allocation Steps: Receive the external reference clock (REFCLK) through the clock management module, generate multiple LVPECL level clock signals, which are used as the working clock of each ADC chip in the ADC sampling module, the FPGA system clock (SYSCLK), and the MGT reference clock (MGTREFCLK), respectively. Perform equal-length PCB design for the clock traces of each ADC chip and the LVDS differential data lines interconnecting the ADC chip and the FPGA. S2. Synchronization signal parsing steps: The FPGA module receives and parses the radar system synchronization signal through the fiber optic interface, and generates the synchronization trigger signal SYNC. S3. Data acquisition and processing steps: The ADC sampling module acquires multi-channel analog signals based on the working clock and converts them into digital signals. The FPGA module internally performs serial-to-parallel conversion and data alignment on the digital signals. S4. Synchronization Processing Steps: The SYNC signal is used to clear the NCO phase of the digital mixer module inside the FPGA, the digital filter module is reset and controlled, and the frame header start time of the data upload module is synchronously triggered to ensure that the data processing delay of each channel is consistent.

9. The multi-channel acquisition synchronization method according to claim 8, characterized in that, In step S3, the FPGA module internally generates a serial data clock (4fs) for serial-to-parallel conversion and a parallel data clock (fs) for parallel data processing based on the SYSCLK through the MMCM clock management unit. The phase relationships between the SYSCLK, the fs, and the 4fs, as well as between the three and the REFCLK, are all deterministic.

10. The multi-channel acquisition synchronization method according to claim 8, characterized in that, In step S4, the digital filtering module uses an FIR IP core to implement decimation anti-aliasing filtering. Its reset signal is associated with the SYNC synchronization signal to ensure that the initial conditions of each frame of data are consistent and to achieve complete inter-frame isolation.

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